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decoder.cc
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1 /*
2  * Copyright (c) 2015-2021 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <vector>
33 
37 
38 namespace gem5
39 {
40 
41 namespace VegaISA
42 {
44  {
45  } // Decoder
46 
48  {
49  } // ~Decoder
50 
51  /*
52  * These will probably have to be updated according to the Vega ISA manual:
53  * https://developer.amd.com/wp-content/resources/
54  * Vega_Shader_ISA_28July2017.pdf
55  */
569  };
570 
1340  };
1341 
1599  };
1600 
1730  };
1731 
1861  };
1862 
1992  };
1993 
2011  };
2012 
2142  };
2143 
2273  };
2274 
2532  };
2533 
2791  };
2792 
2922  };
2923 
3053  };
3054 
3060  };
3061 
3319  };
3320 
3578  };
3579 
3709  };
3710 
3711  GPUStaticInst*
3713  {
3714  InFmt_SOP1 *enc = &mach_inst->iFmt_SOP1;
3716  return (this->*method)(mach_inst);
3717  } // decode
3718 
3719  GPUStaticInst*
3721  {
3722  InFmt_VOPC *enc = &iFmt->iFmt_VOPC;
3723  IsaDecodeMethod method = tableSubDecode_OP_VOPC[enc->OP];
3724  return (this->*method)(iFmt);
3725  } // subDecode_OP_VOPC
3726 
3727  GPUStaticInst*
3729  {
3730  InFmt_VOP3P *enc = &iFmt->iFmt_VOP3P;
3732  return (this->*method)(iFmt);
3733  } // subDecode_OP_VOP3P
3734 
3735  GPUStaticInst*
3737  {
3738  InFmt_VOP1 *enc = &iFmt->iFmt_VOP1;
3739  IsaDecodeMethod method = tableSubDecode_OP_VOP1[enc->OP];
3740  return (this->*method)(iFmt);
3741  } // subDecode_OP_VOP1
3742 
3743  GPUStaticInst*
3745  {
3746  InFmt_SOP1 *enc = &iFmt->iFmt_SOP1;
3747  IsaDecodeMethod method = tableSubDecode_OP_SOP1[enc->OP];
3748  return (this->*method)(iFmt);
3749  } // subDecode_OP_SOP1
3750 
3751  GPUStaticInst*
3753  {
3754  InFmt_SOPC *enc = &iFmt->iFmt_SOPC;
3755  IsaDecodeMethod method = tableSubDecode_OP_SOPC[enc->OP];
3756  return (this->*method)(iFmt);
3757  } // subDecode_OP_SOPC
3758 
3759  GPUStaticInst*
3761  {
3762  InFmt_SOPP *enc = &iFmt->iFmt_SOPP;
3763  IsaDecodeMethod method = tableSubDecode_OP_SOPP[enc->OP];
3764  return (this->*method)(iFmt);
3765  } // subDecode_OP_SOPP
3766 
3767  GPUStaticInst*
3769  {
3770  InFmt_SMEM *enc = &iFmt->iFmt_SMEM;
3771  IsaDecodeMethod method = tableSubDecode_OP_SMEM[enc->OP];
3772  return (this->*method)(iFmt);
3773  } // subDecode_OP_SMEM
3774 
3775  GPUStaticInst*
3777  {
3778  InFmt_VOP3A *enc = &iFmt->iFmt_VOP3A;
3780  return (this->*method)(iFmt);
3781  } // subDecode_OPU_VOP3
3782 
3783  GPUStaticInst*
3785  {
3786  InFmt_VINTRP *enc = &iFmt->iFmt_VINTRP;
3788  return (this->*method)(iFmt);
3789  } // subDecode_OP_VINTRP
3790 
3791  GPUStaticInst*
3793  {
3794  InFmt_DS *enc = &iFmt->iFmt_DS;
3795  IsaDecodeMethod method = tableSubDecode_OP_DS[enc->OP];
3796  return (this->*method)(iFmt);
3797  } // subDecode_OP_DS
3798 
3799  GPUStaticInst*
3801  {
3802  InFmt_FLAT *enc = &iFmt->iFmt_FLAT;
3803  IsaDecodeMethod method;
3804  switch (enc->SEG) {
3805  case 0:
3806  method = tableSubDecode_OP_FLAT[enc->OP];
3807  break;
3808  case 1:
3809  method = tableSubDecode_OP_SCRATCH[enc->OP];
3810  break;
3811  case 2:
3812  method = tableSubDecode_OP_GLOBAL[enc->OP];
3813  break;
3814  default:
3815  fatal("Invalid SEG for FLAT encoding: %d\n", enc->SEG);
3816  }
3817  return (this->*method)(iFmt);
3818  } // subDecode_OP_FLAT
3819 
3820  GPUStaticInst*
3822  {
3823  InFmt_MUBUF *enc = &iFmt->iFmt_MUBUF;
3825  return (this->*method)(iFmt);
3826  } // subDecode_OP_MUBUF
3827 
3828  GPUStaticInst*
3830  {
3831  InFmt_MTBUF *enc = &iFmt->iFmt_MTBUF;
3833  return (this->*method)(iFmt);
3834  } // subDecode_OP_MTBUF
3835 
3836  GPUStaticInst*
3838  {
3839  InFmt_MIMG *enc = &iFmt->iFmt_MIMG;
3840  IsaDecodeMethod method = tableSubDecode_OP_MIMG[enc->OP];
3841  return (this->*method)(iFmt);
3842  } // subDecode_OP_MIMG
3843 
3844  GPUStaticInst*
3846  {
3847  return new Inst_VOP2__V_CNDMASK_B32(&iFmt->iFmt_VOP2);
3848  } // decode_OP_VOP2__V_CNDMASK_B32
3849 
3850  GPUStaticInst*
3852  {
3853  return new Inst_VOP2__V_ADD_F32(&iFmt->iFmt_VOP2);
3854  } // decode_OP_VOP2__V_ADD_F32
3855 
3856  GPUStaticInst*
3858  {
3859  return new Inst_VOP2__V_SUB_F32(&iFmt->iFmt_VOP2);
3860  } // decode_OP_VOP2__V_SUB_F32
3861 
3862  GPUStaticInst*
3864  {
3865  return new Inst_VOP2__V_SUBREV_F32(&iFmt->iFmt_VOP2);
3866  } // decode_OP_VOP2__V_SUBREV_F32
3867 
3868  GPUStaticInst*
3870  {
3871  return new Inst_VOP2__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP2);
3872  } // decode_OP_VOP2__V_MUL_LEGACY_F32
3873 
3874  GPUStaticInst*
3876  {
3877  return new Inst_VOP2__V_MUL_F32(&iFmt->iFmt_VOP2);
3878  } // decode_OP_VOP2__V_MUL_F32
3879 
3880  GPUStaticInst*
3882  {
3883  return new Inst_VOP2__V_MUL_I32_I24(&iFmt->iFmt_VOP2);
3884  } // decode_OP_VOP2__V_MUL_I32_I24
3885 
3886  GPUStaticInst*
3888  {
3889  return new Inst_VOP2__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP2);
3890  } // decode_OP_VOP2__V_MUL_HI_I32_I24
3891 
3892  GPUStaticInst*
3894  {
3895  return new Inst_VOP2__V_MUL_U32_U24(&iFmt->iFmt_VOP2);
3896  } // decode_OP_VOP2__V_MUL_U32_U24
3897 
3898  GPUStaticInst*
3900  {
3901  return new Inst_VOP2__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP2);
3902  } // decode_OP_VOP2__V_MUL_HI_U32_U24
3903 
3904  GPUStaticInst*
3906  {
3907  return new Inst_VOP2__V_MIN_F32(&iFmt->iFmt_VOP2);
3908  } // decode_OP_VOP2__V_MIN_F32
3909 
3910  GPUStaticInst*
3912  {
3913  return new Inst_VOP2__V_MAX_F32(&iFmt->iFmt_VOP2);
3914  } // decode_OP_VOP2__V_MAX_F32
3915 
3916  GPUStaticInst*
3918  {
3919  return new Inst_VOP2__V_MIN_I32(&iFmt->iFmt_VOP2);
3920  } // decode_OP_VOP2__V_MIN_I32
3921 
3922  GPUStaticInst*
3924  {
3925  return new Inst_VOP2__V_MAX_I32(&iFmt->iFmt_VOP2);
3926  } // decode_OP_VOP2__V_MAX_I32
3927 
3928  GPUStaticInst*
3930  {
3931  return new Inst_VOP2__V_MIN_U32(&iFmt->iFmt_VOP2);
3932  } // decode_OP_VOP2__V_MIN_U32
3933 
3934  GPUStaticInst*
3936  {
3937  return new Inst_VOP2__V_MAX_U32(&iFmt->iFmt_VOP2);
3938  } // decode_OP_VOP2__V_MAX_U32
3939 
3940  GPUStaticInst*
3942  {
3943  return new Inst_VOP2__V_LSHRREV_B32(&iFmt->iFmt_VOP2);
3944  } // decode_OP_VOP2__V_LSHRREV_B32
3945 
3946  GPUStaticInst*
3948  {
3949  return new Inst_VOP2__V_ASHRREV_I32(&iFmt->iFmt_VOP2);
3950  } // decode_OP_VOP2__V_ASHRREV_I32
3951 
3952  GPUStaticInst*
3954  {
3955  return new Inst_VOP2__V_LSHLREV_B32(&iFmt->iFmt_VOP2);
3956  } // decode_OP_VOP2__V_LSHLREV_B32
3957 
3958  GPUStaticInst*
3960  {
3961  return new Inst_VOP2__V_AND_B32(&iFmt->iFmt_VOP2);
3962  } // decode_OP_VOP2__V_AND_B32
3963 
3964  GPUStaticInst*
3966  {
3967  return new Inst_VOP2__V_OR_B32(&iFmt->iFmt_VOP2);
3968  } // decode_OP_VOP2__V_OR_B32
3969 
3970  GPUStaticInst*
3972  {
3973  return new Inst_VOP2__V_XOR_B32(&iFmt->iFmt_VOP2);
3974  } // decode_OP_VOP2__V_XOR_B32
3975 
3976  GPUStaticInst*
3978  {
3979  return new Inst_VOP2__V_MAC_F32(&iFmt->iFmt_VOP2);
3980  } // decode_OP_VOP2__V_MAC_F32
3981 
3982  GPUStaticInst*
3984  {
3985  return new Inst_VOP2__V_MADMK_F32(&iFmt->iFmt_VOP2);
3986  } // decode_OP_VOP2__V_MADMK_F32
3987 
3988  GPUStaticInst*
3990  {
3991  return new Inst_VOP2__V_MADAK_F32(&iFmt->iFmt_VOP2);
3992  } // decode_OP_VOP2__V_MADAK_F32
3993 
3994  GPUStaticInst*
3996  {
3997  return new Inst_VOP2__V_ADD_CO_U32(&iFmt->iFmt_VOP2);
3998  } // decode_OP_VOP2__V_ADD_CO_U32
3999 
4000  GPUStaticInst*
4002  {
4003  return new Inst_VOP2__V_SUB_CO_U32(&iFmt->iFmt_VOP2);
4004  } // decode_OP_VOP2__V_SUB_CO_U32
4005 
4006  GPUStaticInst*
4008  {
4009  return new Inst_VOP2__V_SUBREV_CO_U32(&iFmt->iFmt_VOP2);
4010  } // decode_OP_VOP2__V_SUBREV_CO_U32
4011 
4012  GPUStaticInst*
4014  {
4015  return new Inst_VOP2__V_ADDC_CO_U32(&iFmt->iFmt_VOP2);
4016  } // decode_OP_VOP2__V_ADDC_CO_U32
4017 
4018  GPUStaticInst*
4020  {
4021  return new Inst_VOP2__V_SUBB_CO_U32(&iFmt->iFmt_VOP2);
4022  } // decode_OP_VOP2__V_SUBB_CO_U32
4023 
4024  GPUStaticInst*
4026  {
4027  return new Inst_VOP2__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP2);
4028  } // decode_OP_VOP2__V_SUBBREV_CO_U32
4029 
4030  GPUStaticInst*
4032  {
4033  return new Inst_VOP2__V_ADD_F16(&iFmt->iFmt_VOP2);
4034  } // decode_OP_VOP2__V_ADD_F16
4035 
4036  GPUStaticInst*
4038  {
4039  return new Inst_VOP2__V_SUB_F16(&iFmt->iFmt_VOP2);
4040  } // decode_OP_VOP2__V_SUB_F16
4041 
4042  GPUStaticInst*
4044  {
4045  return new Inst_VOP2__V_SUBREV_F16(&iFmt->iFmt_VOP2);
4046  } // decode_OP_VOP2__V_SUBREV_F16
4047 
4048  GPUStaticInst*
4050  {
4051  return new Inst_VOP2__V_MUL_F16(&iFmt->iFmt_VOP2);
4052  } // decode_OP_VOP2__V_MUL_F16
4053 
4054  GPUStaticInst*
4056  {
4057  return new Inst_VOP2__V_MAC_F16(&iFmt->iFmt_VOP2);
4058  } // decode_OP_VOP2__V_MAC_F16
4059 
4060  GPUStaticInst*
4062  {
4063  return new Inst_VOP2__V_MADMK_F16(&iFmt->iFmt_VOP2);
4064  } // decode_OP_VOP2__V_MADMK_F16
4065 
4066  GPUStaticInst*
4068  {
4069  return new Inst_VOP2__V_MADAK_F16(&iFmt->iFmt_VOP2);
4070  } // decode_OP_VOP2__V_MADAK_F16
4071 
4072  GPUStaticInst*
4074  {
4075  return new Inst_VOP2__V_ADD_U16(&iFmt->iFmt_VOP2);
4076  } // decode_OP_VOP2__V_ADD_U16
4077 
4078  GPUStaticInst*
4080  {
4081  return new Inst_VOP2__V_SUB_U16(&iFmt->iFmt_VOP2);
4082  } // decode_OP_VOP2__V_SUB_U16
4083 
4084  GPUStaticInst*
4086  {
4087  return new Inst_VOP2__V_SUBREV_U16(&iFmt->iFmt_VOP2);
4088  } // decode_OP_VOP2__V_SUBREV_U16
4089 
4090  GPUStaticInst*
4092  {
4093  return new Inst_VOP2__V_MUL_LO_U16(&iFmt->iFmt_VOP2);
4094  } // decode_OP_VOP2__V_MUL_LO_U16
4095 
4096  GPUStaticInst*
4098  {
4099  return new Inst_VOP2__V_LSHLREV_B16(&iFmt->iFmt_VOP2);
4100  } // decode_OP_VOP2__V_LSHLREV_B16
4101 
4102  GPUStaticInst*
4104  {
4105  return new Inst_VOP2__V_LSHRREV_B16(&iFmt->iFmt_VOP2);
4106  } // decode_OP_VOP2__V_LSHRREV_B16
4107 
4108  GPUStaticInst*
4110  {
4111  return new Inst_VOP2__V_ASHRREV_I16(&iFmt->iFmt_VOP2);
4112  } // decode_OP_VOP2__V_ASHRREV_I16
4113 
4114  GPUStaticInst*
4116  {
4117  return new Inst_VOP2__V_MAX_F16(&iFmt->iFmt_VOP2);
4118  } // decode_OP_VOP2__V_MAX_F16
4119 
4120  GPUStaticInst*
4122  {
4123  return new Inst_VOP2__V_MIN_F16(&iFmt->iFmt_VOP2);
4124  } // decode_OP_VOP2__V_MIN_F16
4125 
4126  GPUStaticInst*
4128  {
4129  return new Inst_VOP2__V_MAX_U16(&iFmt->iFmt_VOP2);
4130  } // decode_OP_VOP2__V_MAX_U16
4131 
4132  GPUStaticInst*
4134  {
4135  return new Inst_VOP2__V_MAX_I16(&iFmt->iFmt_VOP2);
4136  } // decode_OP_VOP2__V_MAX_I16
4137 
4138  GPUStaticInst*
4140  {
4141  return new Inst_VOP2__V_MIN_U16(&iFmt->iFmt_VOP2);
4142  } // decode_OP_VOP2__V_MIN_U16
4143 
4144  GPUStaticInst*
4146  {
4147  return new Inst_VOP2__V_MIN_I16(&iFmt->iFmt_VOP2);
4148  } // decode_OP_VOP2__V_MIN_I16
4149 
4150  GPUStaticInst*
4152  {
4153  return new Inst_VOP2__V_LDEXP_F16(&iFmt->iFmt_VOP2);
4154  } // decode_OP_VOP2__V_LDEXP_F16
4155 
4156  GPUStaticInst*
4158  {
4159  return new Inst_VOP2__V_ADD_U32(&iFmt->iFmt_VOP2);
4160  }
4161 
4162  GPUStaticInst*
4164  {
4165  return new Inst_VOP2__V_SUB_U32(&iFmt->iFmt_VOP2);
4166  }
4167 
4168  GPUStaticInst*
4170  {
4171  return new Inst_VOP2__V_SUBREV_U32(&iFmt->iFmt_VOP2);
4172  }
4173 
4174  GPUStaticInst*
4176  {
4177  fatal("Trying to decode instruction without a class\n");
4178  return nullptr;
4179  }
4180 
4181  GPUStaticInst*
4183  {
4184  fatal("Trying to decode instruction without a class\n");
4185  return nullptr;
4186  }
4187 
4188  GPUStaticInst*
4190  {
4191  fatal("Trying to decode instruction without a class\n");
4192  return nullptr;
4193  }
4194 
4195  GPUStaticInst*
4197  {
4198  fatal("Trying to decode instruction without a class\n");
4199  return nullptr;
4200  }
4201 
4202  GPUStaticInst*
4204  {
4205  fatal("Trying to decode instruction without a class\n");
4206  return nullptr;
4207  }
4208 
4209  GPUStaticInst*
4211  {
4212  fatal("Trying to decode instruction without a class\n");
4213  return nullptr;
4214  }
4215 
4216  GPUStaticInst*
4218  {
4219  fatal("Trying to decode instruction without a class\n");
4220  return nullptr;
4221  }
4222 
4223  GPUStaticInst*
4225  {
4226  return new Inst_SOP2__S_ADD_U32(&iFmt->iFmt_SOP2);
4227  } // decode_OP_SOP2__S_ADD_U32
4228 
4229  GPUStaticInst*
4231  {
4232  return new Inst_SOP2__S_SUB_U32(&iFmt->iFmt_SOP2);
4233  } // decode_OP_SOP2__S_SUB_U32
4234 
4235  GPUStaticInst*
4237  {
4238  return new Inst_SOP2__S_ADD_I32(&iFmt->iFmt_SOP2);
4239  } // decode_OP_SOP2__S_ADD_I32
4240 
4241  GPUStaticInst*
4243  {
4244  return new Inst_SOP2__S_SUB_I32(&iFmt->iFmt_SOP2);
4245  } // decode_OP_SOP2__S_SUB_I32
4246 
4247  GPUStaticInst*
4249  {
4250  return new Inst_SOP2__S_ADDC_U32(&iFmt->iFmt_SOP2);
4251  } // decode_OP_SOP2__S_ADDC_U32
4252 
4253  GPUStaticInst*
4255  {
4256  return new Inst_SOP2__S_SUBB_U32(&iFmt->iFmt_SOP2);
4257  } // decode_OP_SOP2__S_SUBB_U32
4258 
4259  GPUStaticInst*
4261  {
4262  return new Inst_SOP2__S_MIN_I32(&iFmt->iFmt_SOP2);
4263  } // decode_OP_SOP2__S_MIN_I32
4264 
4265  GPUStaticInst*
4267  {
4268  return new Inst_SOP2__S_MIN_U32(&iFmt->iFmt_SOP2);
4269  } // decode_OP_SOP2__S_MIN_U32
4270 
4271  GPUStaticInst*
4273  {
4274  return new Inst_SOP2__S_MAX_I32(&iFmt->iFmt_SOP2);
4275  } // decode_OP_SOP2__S_MAX_I32
4276 
4277  GPUStaticInst*
4279  {
4280  return new Inst_SOP2__S_MAX_U32(&iFmt->iFmt_SOP2);
4281  } // decode_OP_SOP2__S_MAX_U32
4282 
4283  GPUStaticInst*
4285  {
4286  return new Inst_SOP2__S_CSELECT_B32(&iFmt->iFmt_SOP2);
4287  } // decode_OP_SOP2__S_CSELECT_B32
4288 
4289  GPUStaticInst*
4291  {
4292  return new Inst_SOP2__S_CSELECT_B64(&iFmt->iFmt_SOP2);
4293  } // decode_OP_SOP2__S_CSELECT_B64
4294 
4295  GPUStaticInst*
4297  {
4298  return new Inst_SOP2__S_AND_B32(&iFmt->iFmt_SOP2);
4299  } // decode_OP_SOP2__S_AND_B32
4300 
4301  GPUStaticInst*
4303  {
4304  return new Inst_SOP2__S_AND_B64(&iFmt->iFmt_SOP2);
4305  } // decode_OP_SOP2__S_AND_B64
4306 
4307  GPUStaticInst*
4309  {
4310  return new Inst_SOP2__S_OR_B32(&iFmt->iFmt_SOP2);
4311  } // decode_OP_SOP2__S_OR_B32
4312 
4313  GPUStaticInst*
4315  {
4316  return new Inst_SOP2__S_OR_B64(&iFmt->iFmt_SOP2);
4317  } // decode_OP_SOP2__S_OR_B64
4318 
4319  GPUStaticInst*
4321  {
4322  return new Inst_SOP2__S_XOR_B32(&iFmt->iFmt_SOP2);
4323  } // decode_OP_SOP2__S_XOR_B32
4324 
4325  GPUStaticInst*
4327  {
4328  return new Inst_SOP2__S_XOR_B64(&iFmt->iFmt_SOP2);
4329  } // decode_OP_SOP2__S_XOR_B64
4330 
4331  GPUStaticInst*
4333  {
4334  return new Inst_SOP2__S_ANDN2_B32(&iFmt->iFmt_SOP2);
4335  } // decode_OP_SOP2__S_ANDN2_B32
4336 
4337  GPUStaticInst*
4339  {
4340  return new Inst_SOP2__S_ANDN2_B64(&iFmt->iFmt_SOP2);
4341  } // decode_OP_SOP2__S_ANDN2_B64
4342 
4343  GPUStaticInst*
4345  {
4346  return new Inst_SOP2__S_ORN2_B32(&iFmt->iFmt_SOP2);
4347  } // decode_OP_SOP2__S_ORN2_B32
4348 
4349  GPUStaticInst*
4351  {
4352  return new Inst_SOP2__S_ORN2_B64(&iFmt->iFmt_SOP2);
4353  } // decode_OP_SOP2__S_ORN2_B64
4354 
4355  GPUStaticInst*
4357  {
4358  return new Inst_SOP2__S_NAND_B32(&iFmt->iFmt_SOP2);
4359  } // decode_OP_SOP2__S_NAND_B32
4360 
4361  GPUStaticInst*
4363  {
4364  return new Inst_SOP2__S_NAND_B64(&iFmt->iFmt_SOP2);
4365  } // decode_OP_SOP2__S_NAND_B64
4366 
4367  GPUStaticInst*
4369  {
4370  return new Inst_SOP2__S_NOR_B32(&iFmt->iFmt_SOP2);
4371  } // decode_OP_SOP2__S_NOR_B32
4372 
4373  GPUStaticInst*
4375  {
4376  return new Inst_SOP2__S_NOR_B64(&iFmt->iFmt_SOP2);
4377  } // decode_OP_SOP2__S_NOR_B64
4378 
4379  GPUStaticInst*
4381  {
4382  return new Inst_SOP2__S_XNOR_B32(&iFmt->iFmt_SOP2);
4383  } // decode_OP_SOP2__S_XNOR_B32
4384 
4385  GPUStaticInst*
4387  {
4388  return new Inst_SOP2__S_XNOR_B64(&iFmt->iFmt_SOP2);
4389  } // decode_OP_SOP2__S_XNOR_B64
4390 
4391  GPUStaticInst*
4393  {
4394  return new Inst_SOP2__S_LSHL_B32(&iFmt->iFmt_SOP2);
4395  } // decode_OP_SOP2__S_LSHL_B32
4396 
4397  GPUStaticInst*
4399  {
4400  return new Inst_SOP2__S_LSHL_B64(&iFmt->iFmt_SOP2);
4401  } // decode_OP_SOP2__S_LSHL_B64
4402 
4403  GPUStaticInst*
4405  {
4406  return new Inst_SOP2__S_LSHR_B32(&iFmt->iFmt_SOP2);
4407  } // decode_OP_SOP2__S_LSHR_B32
4408 
4409  GPUStaticInst*
4411  {
4412  return new Inst_SOP2__S_LSHR_B64(&iFmt->iFmt_SOP2);
4413  } // decode_OP_SOP2__S_LSHR_B64
4414 
4415  GPUStaticInst*
4417  {
4418  return new Inst_SOP2__S_ASHR_I32(&iFmt->iFmt_SOP2);
4419  } // decode_OP_SOP2__S_ASHR_I32
4420 
4421  GPUStaticInst*
4423  {
4424  return new Inst_SOP2__S_ASHR_I64(&iFmt->iFmt_SOP2);
4425  } // decode_OP_SOP2__S_ASHR_I64
4426 
4427  GPUStaticInst*
4429  {
4430  return new Inst_SOP2__S_BFM_B32(&iFmt->iFmt_SOP2);
4431  } // decode_OP_SOP2__S_BFM_B32
4432 
4433  GPUStaticInst*
4435  {
4436  return new Inst_SOP2__S_BFM_B64(&iFmt->iFmt_SOP2);
4437  } // decode_OP_SOP2__S_BFM_B64
4438 
4439  GPUStaticInst*
4441  {
4442  return new Inst_SOP2__S_MUL_I32(&iFmt->iFmt_SOP2);
4443  } // decode_OP_SOP2__S_MUL_I32
4444 
4445  GPUStaticInst*
4447  {
4448  return new Inst_SOP2__S_BFE_U32(&iFmt->iFmt_SOP2);
4449  } // decode_OP_SOP2__S_BFE_U32
4450 
4451  GPUStaticInst*
4453  {
4454  return new Inst_SOP2__S_BFE_I32(&iFmt->iFmt_SOP2);
4455  } // decode_OP_SOP2__S_BFE_I32
4456 
4457  GPUStaticInst*
4459  {
4460  return new Inst_SOP2__S_BFE_U64(&iFmt->iFmt_SOP2);
4461  } // decode_OP_SOP2__S_BFE_U64
4462 
4463  GPUStaticInst*
4465  {
4466  return new Inst_SOP2__S_BFE_I64(&iFmt->iFmt_SOP2);
4467  } // decode_OP_SOP2__S_BFE_I64
4468 
4469  GPUStaticInst*
4471  {
4472  return new Inst_SOP2__S_CBRANCH_G_FORK(&iFmt->iFmt_SOP2);
4473  } // decode_OP_SOP2__S_CBRANCH_G_FORK
4474 
4475  GPUStaticInst*
4477  {
4478  return new Inst_SOP2__S_ABSDIFF_I32(&iFmt->iFmt_SOP2);
4479  } // decode_OP_SOP2__S_ABSDIFF_I32
4480 
4481  GPUStaticInst*
4483  {
4484  return new Inst_SOP2__S_RFE_RESTORE_B64(&iFmt->iFmt_SOP2);
4485  } // decode_OP_SOP2__S_RFE_RESTORE_B64
4486 
4487  GPUStaticInst*
4489  {
4490  return new Inst_SOP2__S_MUL_HI_U32(&iFmt->iFmt_SOP2);
4491  }
4492 
4493  GPUStaticInst*
4495  {
4496  return new Inst_SOP2__S_MUL_HI_I32(&iFmt->iFmt_SOP2);
4497  }
4498 
4499  GPUStaticInst*
4501  {
4502  fatal("Trying to decode instruction without a class\n");
4503  return nullptr;
4504  }
4505 
4506  GPUStaticInst*
4508  {
4509  fatal("Trying to decode instruction without a class\n");
4510  return nullptr;
4511  }
4512 
4513  GPUStaticInst*
4515  {
4516  fatal("Trying to decode instruction without a class\n");
4517  return nullptr;
4518  }
4519 
4520  GPUStaticInst*
4522  {
4523  fatal("Trying to decode instruction without a class\n");
4524  return nullptr;
4525  }
4526 
4527  GPUStaticInst*
4529  {
4530  fatal("Trying to decode instruction without a class\n");
4531  return nullptr;
4532  }
4533 
4534  GPUStaticInst*
4536  {
4537  fatal("Trying to decode instruction without a class\n");
4538  return nullptr;
4539  }
4540 
4541  GPUStaticInst*
4543  {
4544  fatal("Trying to decode instruction without a class\n");
4545  return nullptr;
4546  }
4547 
4548  GPUStaticInst*
4550  {
4551  return new Inst_SOPK__S_MOVK_I32(&iFmt->iFmt_SOPK);
4552  } // decode_OP_SOPK__S_MOVK_I32
4553 
4554  GPUStaticInst*
4556  {
4557  return new Inst_SOPK__S_CMOVK_I32(&iFmt->iFmt_SOPK);
4558  } // decode_OP_SOPK__S_CMOVK_I32
4559 
4560  GPUStaticInst*
4562  {
4563  return new Inst_SOPK__S_CMPK_EQ_I32(&iFmt->iFmt_SOPK);
4564  } // decode_OP_SOPK__S_CMPK_EQ_I32
4565 
4566  GPUStaticInst*
4568  {
4569  return new Inst_SOPK__S_CMPK_LG_I32(&iFmt->iFmt_SOPK);
4570  } // decode_OP_SOPK__S_CMPK_LG_I32
4571 
4572  GPUStaticInst*
4574  {
4575  return new Inst_SOPK__S_CMPK_GT_I32(&iFmt->iFmt_SOPK);
4576  } // decode_OP_SOPK__S_CMPK_GT_I32
4577 
4578  GPUStaticInst*
4580  {
4581  return new Inst_SOPK__S_CMPK_GE_I32(&iFmt->iFmt_SOPK);
4582  } // decode_OP_SOPK__S_CMPK_GE_I32
4583 
4584  GPUStaticInst*
4586  {
4587  return new Inst_SOPK__S_CMPK_LT_I32(&iFmt->iFmt_SOPK);
4588  } // decode_OP_SOPK__S_CMPK_LT_I32
4589 
4590  GPUStaticInst*
4592  {
4593  return new Inst_SOPK__S_CMPK_LE_I32(&iFmt->iFmt_SOPK);
4594  } // decode_OP_SOPK__S_CMPK_LE_I32
4595 
4596  GPUStaticInst*
4598  {
4599  return new Inst_SOPK__S_CMPK_EQ_U32(&iFmt->iFmt_SOPK);
4600  } // decode_OP_SOPK__S_CMPK_EQ_U32
4601 
4602  GPUStaticInst*
4604  {
4605  return new Inst_SOPK__S_CMPK_LG_U32(&iFmt->iFmt_SOPK);
4606  } // decode_OP_SOPK__S_CMPK_LG_U32
4607 
4608  GPUStaticInst*
4610  {
4611  return new Inst_SOPK__S_CMPK_GT_U32(&iFmt->iFmt_SOPK);
4612  } // decode_OP_SOPK__S_CMPK_GT_U32
4613 
4614  GPUStaticInst*
4616  {
4617  return new Inst_SOPK__S_CMPK_GE_U32(&iFmt->iFmt_SOPK);
4618  } // decode_OP_SOPK__S_CMPK_GE_U32
4619 
4620  GPUStaticInst*
4622  {
4623  return new Inst_SOPK__S_CMPK_LT_U32(&iFmt->iFmt_SOPK);
4624  } // decode_OP_SOPK__S_CMPK_LT_U32
4625 
4626  GPUStaticInst*
4628  {
4629  return new Inst_SOPK__S_CMPK_LE_U32(&iFmt->iFmt_SOPK);
4630  } // decode_OP_SOPK__S_CMPK_LE_U32
4631 
4632  GPUStaticInst*
4634  {
4635  return new Inst_SOPK__S_ADDK_I32(&iFmt->iFmt_SOPK);
4636  } // decode_OP_SOPK__S_ADDK_I32
4637 
4638  GPUStaticInst*
4640  {
4641  return new Inst_SOPK__S_MULK_I32(&iFmt->iFmt_SOPK);
4642  } // decode_OP_SOPK__S_MULK_I32
4643 
4644  GPUStaticInst*
4646  {
4647  return new Inst_SOPK__S_CBRANCH_I_FORK(&iFmt->iFmt_SOPK);
4648  } // decode_OP_SOPK__S_CBRANCH_I_FORK
4649 
4650  GPUStaticInst*
4652  {
4653  return new Inst_SOPK__S_GETREG_B32(&iFmt->iFmt_SOPK);
4654  } // decode_OP_SOPK__S_GETREG_B32
4655 
4656  GPUStaticInst*
4658  {
4659  return new Inst_SOPK__S_SETREG_B32(&iFmt->iFmt_SOPK);
4660  } // decode_OP_SOPK__S_SETREG_B32
4661 
4662  GPUStaticInst*
4664  {
4665  return new Inst_SOPK__S_SETREG_IMM32_B32(&iFmt->iFmt_SOPK);
4666  } // decode_OP_SOPK__S_SETREG_IMM32_B32
4667 
4668  GPUStaticInst*
4670  {
4671  fatal("Trying to decode instruction without a class\n");
4672  return nullptr;
4673  }
4674 
4675  GPUStaticInst*
4677  {
4678  return new Inst_EXP__EXP(&iFmt->iFmt_EXP);
4679  } // decode_OP_EXP
4680 
4681  GPUStaticInst*
4683  {
4684  return new Inst_VOP3__V_CMP_CLASS_F32(&iFmt->iFmt_VOP3A);
4685  } // decode_OPU_VOP3__V_CMP_CLASS_F32
4686 
4687  GPUStaticInst*
4689  {
4690  return new Inst_VOP3__V_CMPX_CLASS_F32(&iFmt->iFmt_VOP3A);
4691  } // decode_OPU_VOP3__V_CMPX_CLASS_F32
4692 
4693  GPUStaticInst*
4695  {
4696  return new Inst_VOP3__V_CMP_CLASS_F64(&iFmt->iFmt_VOP3A);
4697  } // decode_OPU_VOP3__V_CMP_CLASS_F64
4698 
4699  GPUStaticInst*
4701  {
4702  return new Inst_VOP3__V_CMPX_CLASS_F64(&iFmt->iFmt_VOP3A);
4703  } // decode_OPU_VOP3__V_CMPX_CLASS_F64
4704 
4705  GPUStaticInst*
4707  {
4708  return new Inst_VOP3__V_CMP_CLASS_F16(&iFmt->iFmt_VOP3A);
4709  } // decode_OPU_VOP3__V_CMP_CLASS_F16
4710 
4711  GPUStaticInst*
4713  {
4714  return new Inst_VOP3__V_CMPX_CLASS_F16(&iFmt->iFmt_VOP3A);
4715  } // decode_OPU_VOP3__V_CMPX_CLASS_F16
4716 
4717  GPUStaticInst*
4719  {
4720  return new Inst_VOP3__V_CMP_F_F16(&iFmt->iFmt_VOP3A);
4721  } // decode_OPU_VOP3__V_CMP_F_F16
4722 
4723  GPUStaticInst*
4725  {
4726  return new Inst_VOP3__V_CMP_LT_F16(&iFmt->iFmt_VOP3A);
4727  } // decode_OPU_VOP3__V_CMP_LT_F16
4728 
4729  GPUStaticInst*
4731  {
4732  return new Inst_VOP3__V_CMP_EQ_F16(&iFmt->iFmt_VOP3A);
4733  } // decode_OPU_VOP3__V_CMP_EQ_F16
4734 
4735  GPUStaticInst*
4737  {
4738  return new Inst_VOP3__V_CMP_LE_F16(&iFmt->iFmt_VOP3A);
4739  } // decode_OPU_VOP3__V_CMP_LE_F16
4740 
4741  GPUStaticInst*
4743  {
4744  return new Inst_VOP3__V_CMP_GT_F16(&iFmt->iFmt_VOP3A);
4745  } // decode_OPU_VOP3__V_CMP_GT_F16
4746 
4747  GPUStaticInst*
4749  {
4750  return new Inst_VOP3__V_CMP_LG_F16(&iFmt->iFmt_VOP3A);
4751  } // decode_OPU_VOP3__V_CMP_LG_F16
4752 
4753  GPUStaticInst*
4755  {
4756  return new Inst_VOP3__V_CMP_GE_F16(&iFmt->iFmt_VOP3A);
4757  } // decode_OPU_VOP3__V_CMP_GE_F16
4758 
4759  GPUStaticInst*
4761  {
4762  return new Inst_VOP3__V_CMP_O_F16(&iFmt->iFmt_VOP3A);
4763  } // decode_OPU_VOP3__V_CMP_O_F16
4764 
4765  GPUStaticInst*
4767  {
4768  return new Inst_VOP3__V_CMP_U_F16(&iFmt->iFmt_VOP3A);
4769  } // decode_OPU_VOP3__V_CMP_U_F16
4770 
4771  GPUStaticInst*
4773  {
4774  return new Inst_VOP3__V_CMP_NGE_F16(&iFmt->iFmt_VOP3A);
4775  } // decode_OPU_VOP3__V_CMP_NGE_F16
4776 
4777  GPUStaticInst*
4779  {
4780  return new Inst_VOP3__V_CMP_NLG_F16(&iFmt->iFmt_VOP3A);
4781  } // decode_OPU_VOP3__V_CMP_NLG_F16
4782 
4783  GPUStaticInst*
4785  {
4786  return new Inst_VOP3__V_CMP_NGT_F16(&iFmt->iFmt_VOP3A);
4787  } // decode_OPU_VOP3__V_CMP_NGT_F16
4788 
4789  GPUStaticInst*
4791  {
4792  return new Inst_VOP3__V_CMP_NLE_F16(&iFmt->iFmt_VOP3A);
4793  } // decode_OPU_VOP3__V_CMP_NLE_F16
4794 
4795  GPUStaticInst*
4797  {
4798  return new Inst_VOP3__V_CMP_NEQ_F16(&iFmt->iFmt_VOP3A);
4799  } // decode_OPU_VOP3__V_CMP_NEQ_F16
4800 
4801  GPUStaticInst*
4803  {
4804  return new Inst_VOP3__V_CMP_NLT_F16(&iFmt->iFmt_VOP3A);
4805  } // decode_OPU_VOP3__V_CMP_NLT_F16
4806 
4807  GPUStaticInst*
4809  {
4810  return new Inst_VOP3__V_CMP_TRU_F16(&iFmt->iFmt_VOP3A);
4811  } // decode_OPU_VOP3__V_CMP_TRU_F16
4812 
4813  GPUStaticInst*
4815  {
4816  return new Inst_VOP3__V_CMPX_F_F16(&iFmt->iFmt_VOP3A);
4817  } // decode_OPU_VOP3__V_CMPX_F_F16
4818 
4819  GPUStaticInst*
4821  {
4822  return new Inst_VOP3__V_CMPX_LT_F16(&iFmt->iFmt_VOP3A);
4823  } // decode_OPU_VOP3__V_CMPX_LT_F16
4824 
4825  GPUStaticInst*
4827  {
4828  return new Inst_VOP3__V_CMPX_EQ_F16(&iFmt->iFmt_VOP3A);
4829  } // decode_OPU_VOP3__V_CMPX_EQ_F16
4830 
4831  GPUStaticInst*
4833  {
4834  return new Inst_VOP3__V_CMPX_LE_F16(&iFmt->iFmt_VOP3A);
4835  } // decode_OPU_VOP3__V_CMPX_LE_F16
4836 
4837  GPUStaticInst*
4839  {
4840  return new Inst_VOP3__V_CMPX_GT_F16(&iFmt->iFmt_VOP3A);
4841  } // decode_OPU_VOP3__V_CMPX_GT_F16
4842 
4843  GPUStaticInst*
4845  {
4846  return new Inst_VOP3__V_CMPX_LG_F16(&iFmt->iFmt_VOP3A);
4847  } // decode_OPU_VOP3__V_CMPX_LG_F16
4848 
4849  GPUStaticInst*
4851  {
4852  return new Inst_VOP3__V_CMPX_GE_F16(&iFmt->iFmt_VOP3A);
4853  } // decode_OPU_VOP3__V_CMPX_GE_F16
4854 
4855  GPUStaticInst*
4857  {
4858  return new Inst_VOP3__V_CMPX_O_F16(&iFmt->iFmt_VOP3A);
4859  } // decode_OPU_VOP3__V_CMPX_O_F16
4860 
4861  GPUStaticInst*
4863  {
4864  return new Inst_VOP3__V_CMPX_U_F16(&iFmt->iFmt_VOP3A);
4865  } // decode_OPU_VOP3__V_CMPX_U_F16
4866 
4867  GPUStaticInst*
4869  {
4870  return new Inst_VOP3__V_CMPX_NGE_F16(&iFmt->iFmt_VOP3A);
4871  } // decode_OPU_VOP3__V_CMPX_NGE_F16
4872 
4873  GPUStaticInst*
4875  {
4876  return new Inst_VOP3__V_CMPX_NLG_F16(&iFmt->iFmt_VOP3A);
4877  } // decode_OPU_VOP3__V_CMPX_NLG_F16
4878 
4879  GPUStaticInst*
4881  {
4882  return new Inst_VOP3__V_CMPX_NGT_F16(&iFmt->iFmt_VOP3A);
4883  } // decode_OPU_VOP3__V_CMPX_NGT_F16
4884 
4885  GPUStaticInst*
4887  {
4888  return new Inst_VOP3__V_CMPX_NLE_F16(&iFmt->iFmt_VOP3A);
4889  } // decode_OPU_VOP3__V_CMPX_NLE_F16
4890 
4891  GPUStaticInst*
4893  {
4894  return new Inst_VOP3__V_CMPX_NEQ_F16(&iFmt->iFmt_VOP3A);
4895  } // decode_OPU_VOP3__V_CMPX_NEQ_F16
4896 
4897  GPUStaticInst*
4899  {
4900  return new Inst_VOP3__V_CMPX_NLT_F16(&iFmt->iFmt_VOP3A);
4901  } // decode_OPU_VOP3__V_CMPX_NLT_F16
4902 
4903  GPUStaticInst*
4905  {
4906  return new Inst_VOP3__V_CMPX_TRU_F16(&iFmt->iFmt_VOP3A);
4907  } // decode_OPU_VOP3__V_CMPX_TRU_F16
4908 
4909  GPUStaticInst*
4911  {
4912  return new Inst_VOP3__V_CMP_F_F32(&iFmt->iFmt_VOP3A);
4913  } // decode_OPU_VOP3__V_CMP_F_F32
4914 
4915  GPUStaticInst*
4917  {
4918  return new Inst_VOP3__V_CMP_LT_F32(&iFmt->iFmt_VOP3A);
4919  } // decode_OPU_VOP3__V_CMP_LT_F32
4920 
4921  GPUStaticInst*
4923  {
4924  return new Inst_VOP3__V_CMP_EQ_F32(&iFmt->iFmt_VOP3A);
4925  } // decode_OPU_VOP3__V_CMP_EQ_F32
4926 
4927  GPUStaticInst*
4929  {
4930  return new Inst_VOP3__V_CMP_LE_F32(&iFmt->iFmt_VOP3A);
4931  } // decode_OPU_VOP3__V_CMP_LE_F32
4932 
4933  GPUStaticInst*
4935  {
4936  return new Inst_VOP3__V_CMP_GT_F32(&iFmt->iFmt_VOP3A);
4937  } // decode_OPU_VOP3__V_CMP_GT_F32
4938 
4939  GPUStaticInst*
4941  {
4942  return new Inst_VOP3__V_CMP_LG_F32(&iFmt->iFmt_VOP3A);
4943  } // decode_OPU_VOP3__V_CMP_LG_F32
4944 
4945  GPUStaticInst*
4947  {
4948  return new Inst_VOP3__V_CMP_GE_F32(&iFmt->iFmt_VOP3A);
4949  } // decode_OPU_VOP3__V_CMP_GE_F32
4950 
4951  GPUStaticInst*
4953  {
4954  return new Inst_VOP3__V_CMP_O_F32(&iFmt->iFmt_VOP3A);
4955  } // decode_OPU_VOP3__V_CMP_O_F32
4956 
4957  GPUStaticInst*
4959  {
4960  return new Inst_VOP3__V_CMP_U_F32(&iFmt->iFmt_VOP3A);
4961  } // decode_OPU_VOP3__V_CMP_U_F32
4962 
4963  GPUStaticInst*
4965  {
4966  return new Inst_VOP3__V_CMP_NGE_F32(&iFmt->iFmt_VOP3A);
4967  } // decode_OPU_VOP3__V_CMP_NGE_F32
4968 
4969  GPUStaticInst*
4971  {
4972  return new Inst_VOP3__V_CMP_NLG_F32(&iFmt->iFmt_VOP3A);
4973  } // decode_OPU_VOP3__V_CMP_NLG_F32
4974 
4975  GPUStaticInst*
4977  {
4978  return new Inst_VOP3__V_CMP_NGT_F32(&iFmt->iFmt_VOP3A);
4979  } // decode_OPU_VOP3__V_CMP_NGT_F32
4980 
4981  GPUStaticInst*
4983  {
4984  return new Inst_VOP3__V_CMP_NLE_F32(&iFmt->iFmt_VOP3A);
4985  } // decode_OPU_VOP3__V_CMP_NLE_F32
4986 
4987  GPUStaticInst*
4989  {
4990  return new Inst_VOP3__V_CMP_NEQ_F32(&iFmt->iFmt_VOP3A);
4991  } // decode_OPU_VOP3__V_CMP_NEQ_F32
4992 
4993  GPUStaticInst*
4995  {
4996  return new Inst_VOP3__V_CMP_NLT_F32(&iFmt->iFmt_VOP3A);
4997  } // decode_OPU_VOP3__V_CMP_NLT_F32
4998 
4999  GPUStaticInst*
5001  {
5002  return new Inst_VOP3__V_CMP_TRU_F32(&iFmt->iFmt_VOP3A);
5003  } // decode_OPU_VOP3__V_CMP_TRU_F32
5004 
5005  GPUStaticInst*
5007  {
5008  return new Inst_VOP3__V_CMPX_F_F32(&iFmt->iFmt_VOP3A);
5009  } // decode_OPU_VOP3__V_CMPX_F_F32
5010 
5011  GPUStaticInst*
5013  {
5014  return new Inst_VOP3__V_CMPX_LT_F32(&iFmt->iFmt_VOP3A);
5015  } // decode_OPU_VOP3__V_CMPX_LT_F32
5016 
5017  GPUStaticInst*
5019  {
5020  return new Inst_VOP3__V_CMPX_EQ_F32(&iFmt->iFmt_VOP3A);
5021  } // decode_OPU_VOP3__V_CMPX_EQ_F32
5022 
5023  GPUStaticInst*
5025  {
5026  return new Inst_VOP3__V_CMPX_LE_F32(&iFmt->iFmt_VOP3A);
5027  } // decode_OPU_VOP3__V_CMPX_LE_F32
5028 
5029  GPUStaticInst*
5031  {
5032  return new Inst_VOP3__V_CMPX_GT_F32(&iFmt->iFmt_VOP3A);
5033  } // decode_OPU_VOP3__V_CMPX_GT_F32
5034 
5035  GPUStaticInst*
5037  {
5038  return new Inst_VOP3__V_CMPX_LG_F32(&iFmt->iFmt_VOP3A);
5039  } // decode_OPU_VOP3__V_CMPX_LG_F32
5040 
5041  GPUStaticInst*
5043  {
5044  return new Inst_VOP3__V_CMPX_GE_F32(&iFmt->iFmt_VOP3A);
5045  } // decode_OPU_VOP3__V_CMPX_GE_F32
5046 
5047  GPUStaticInst*
5049  {
5050  return new Inst_VOP3__V_CMPX_O_F32(&iFmt->iFmt_VOP3A);
5051  } // decode_OPU_VOP3__V_CMPX_O_F32
5052 
5053  GPUStaticInst*
5055  {
5056  return new Inst_VOP3__V_CMPX_U_F32(&iFmt->iFmt_VOP3A);
5057  } // decode_OPU_VOP3__V_CMPX_U_F32
5058 
5059  GPUStaticInst*
5061  {
5062  return new Inst_VOP3__V_CMPX_NGE_F32(&iFmt->iFmt_VOP3A);
5063  } // decode_OPU_VOP3__V_CMPX_NGE_F32
5064 
5065  GPUStaticInst*
5067  {
5068  return new Inst_VOP3__V_CMPX_NLG_F32(&iFmt->iFmt_VOP3A);
5069  } // decode_OPU_VOP3__V_CMPX_NLG_F32
5070 
5071  GPUStaticInst*
5073  {
5074  return new Inst_VOP3__V_CMPX_NGT_F32(&iFmt->iFmt_VOP3A);
5075  } // decode_OPU_VOP3__V_CMPX_NGT_F32
5076 
5077  GPUStaticInst*
5079  {
5080  return new Inst_VOP3__V_CMPX_NLE_F32(&iFmt->iFmt_VOP3A);
5081  } // decode_OPU_VOP3__V_CMPX_NLE_F32
5082 
5083  GPUStaticInst*
5085  {
5086  return new Inst_VOP3__V_CMPX_NEQ_F32(&iFmt->iFmt_VOP3A);
5087  } // decode_OPU_VOP3__V_CMPX_NEQ_F32
5088 
5089  GPUStaticInst*
5091  {
5092  return new Inst_VOP3__V_CMPX_NLT_F32(&iFmt->iFmt_VOP3A);
5093  } // decode_OPU_VOP3__V_CMPX_NLT_F32
5094 
5095  GPUStaticInst*
5097  {
5098  return new Inst_VOP3__V_CMPX_TRU_F32(&iFmt->iFmt_VOP3A);
5099  } // decode_OPU_VOP3__V_CMPX_TRU_F32
5100 
5101  GPUStaticInst*
5103  {
5104  return new Inst_VOP3__V_CMP_F_F64(&iFmt->iFmt_VOP3A);
5105  } // decode_OPU_VOP3__V_CMP_F_F64
5106 
5107  GPUStaticInst*
5109  {
5110  return new Inst_VOP3__V_CMP_LT_F64(&iFmt->iFmt_VOP3A);
5111  } // decode_OPU_VOP3__V_CMP_LT_F64
5112 
5113  GPUStaticInst*
5115  {
5116  return new Inst_VOP3__V_CMP_EQ_F64(&iFmt->iFmt_VOP3A);
5117  } // decode_OPU_VOP3__V_CMP_EQ_F64
5118 
5119  GPUStaticInst*
5121  {
5122  return new Inst_VOP3__V_CMP_LE_F64(&iFmt->iFmt_VOP3A);
5123  } // decode_OPU_VOP3__V_CMP_LE_F64
5124 
5125  GPUStaticInst*
5127  {
5128  return new Inst_VOP3__V_CMP_GT_F64(&iFmt->iFmt_VOP3A);
5129  } // decode_OPU_VOP3__V_CMP_GT_F64
5130 
5131  GPUStaticInst*
5133  {
5134  return new Inst_VOP3__V_CMP_LG_F64(&iFmt->iFmt_VOP3A);
5135  } // decode_OPU_VOP3__V_CMP_LG_F64
5136 
5137  GPUStaticInst*
5139  {
5140  return new Inst_VOP3__V_CMP_GE_F64(&iFmt->iFmt_VOP3A);
5141  } // decode_OPU_VOP3__V_CMP_GE_F64
5142 
5143  GPUStaticInst*
5145  {
5146  return new Inst_VOP3__V_CMP_O_F64(&iFmt->iFmt_VOP3A);
5147  } // decode_OPU_VOP3__V_CMP_O_F64
5148 
5149  GPUStaticInst*
5151  {
5152  return new Inst_VOP3__V_CMP_U_F64(&iFmt->iFmt_VOP3A);
5153  } // decode_OPU_VOP3__V_CMP_U_F64
5154 
5155  GPUStaticInst*
5157  {
5158  return new Inst_VOP3__V_CMP_NGE_F64(&iFmt->iFmt_VOP3A);
5159  } // decode_OPU_VOP3__V_CMP_NGE_F64
5160 
5161  GPUStaticInst*
5163  {
5164  return new Inst_VOP3__V_CMP_NLG_F64(&iFmt->iFmt_VOP3A);
5165  } // decode_OPU_VOP3__V_CMP_NLG_F64
5166 
5167  GPUStaticInst*
5169  {
5170  return new Inst_VOP3__V_CMP_NGT_F64(&iFmt->iFmt_VOP3A);
5171  } // decode_OPU_VOP3__V_CMP_NGT_F64
5172 
5173  GPUStaticInst*
5175  {
5176  return new Inst_VOP3__V_CMP_NLE_F64(&iFmt->iFmt_VOP3A);
5177  } // decode_OPU_VOP3__V_CMP_NLE_F64
5178 
5179  GPUStaticInst*
5181  {
5182  return new Inst_VOP3__V_CMP_NEQ_F64(&iFmt->iFmt_VOP3A);
5183  } // decode_OPU_VOP3__V_CMP_NEQ_F64
5184 
5185  GPUStaticInst*
5187  {
5188  return new Inst_VOP3__V_CMP_NLT_F64(&iFmt->iFmt_VOP3A);
5189  } // decode_OPU_VOP3__V_CMP_NLT_F64
5190 
5191  GPUStaticInst*
5193  {
5194  return new Inst_VOP3__V_CMP_TRU_F64(&iFmt->iFmt_VOP3A);
5195  } // decode_OPU_VOP3__V_CMP_TRU_F64
5196 
5197  GPUStaticInst*
5199  {
5200  return new Inst_VOP3__V_CMPX_F_F64(&iFmt->iFmt_VOP3A);
5201  } // decode_OPU_VOP3__V_CMPX_F_F64
5202 
5203  GPUStaticInst*
5205  {
5206  return new Inst_VOP3__V_CMPX_LT_F64(&iFmt->iFmt_VOP3A);
5207  } // decode_OPU_VOP3__V_CMPX_LT_F64
5208 
5209  GPUStaticInst*
5211  {
5212  return new Inst_VOP3__V_CMPX_EQ_F64(&iFmt->iFmt_VOP3A);
5213  } // decode_OPU_VOP3__V_CMPX_EQ_F64
5214 
5215  GPUStaticInst*
5217  {
5218  return new Inst_VOP3__V_CMPX_LE_F64(&iFmt->iFmt_VOP3A);
5219  } // decode_OPU_VOP3__V_CMPX_LE_F64
5220 
5221  GPUStaticInst*
5223  {
5224  return new Inst_VOP3__V_CMPX_GT_F64(&iFmt->iFmt_VOP3A);
5225  } // decode_OPU_VOP3__V_CMPX_GT_F64
5226 
5227  GPUStaticInst*
5229  {
5230  return new Inst_VOP3__V_CMPX_LG_F64(&iFmt->iFmt_VOP3A);
5231  } // decode_OPU_VOP3__V_CMPX_LG_F64
5232 
5233  GPUStaticInst*
5235  {
5236  return new Inst_VOP3__V_CMPX_GE_F64(&iFmt->iFmt_VOP3A);
5237  } // decode_OPU_VOP3__V_CMPX_GE_F64
5238 
5239  GPUStaticInst*
5241  {
5242  return new Inst_VOP3__V_CMPX_O_F64(&iFmt->iFmt_VOP3A);
5243  } // decode_OPU_VOP3__V_CMPX_O_F64
5244 
5245  GPUStaticInst*
5247  {
5248  return new Inst_VOP3__V_CMPX_U_F64(&iFmt->iFmt_VOP3A);
5249  } // decode_OPU_VOP3__V_CMPX_U_F64
5250 
5251  GPUStaticInst*
5253  {
5254  return new Inst_VOP3__V_CMPX_NGE_F64(&iFmt->iFmt_VOP3A);
5255  } // decode_OPU_VOP3__V_CMPX_NGE_F64
5256 
5257  GPUStaticInst*
5259  {
5260  return new Inst_VOP3__V_CMPX_NLG_F64(&iFmt->iFmt_VOP3A);
5261  } // decode_OPU_VOP3__V_CMPX_NLG_F64
5262 
5263  GPUStaticInst*
5265  {
5266  return new Inst_VOP3__V_CMPX_NGT_F64(&iFmt->iFmt_VOP3A);
5267  } // decode_OPU_VOP3__V_CMPX_NGT_F64
5268 
5269  GPUStaticInst*
5271  {
5272  return new Inst_VOP3__V_CMPX_NLE_F64(&iFmt->iFmt_VOP3A);
5273  } // decode_OPU_VOP3__V_CMPX_NLE_F64
5274 
5275  GPUStaticInst*
5277  {
5278  return new Inst_VOP3__V_CMPX_NEQ_F64(&iFmt->iFmt_VOP3A);
5279  } // decode_OPU_VOP3__V_CMPX_NEQ_F64
5280 
5281  GPUStaticInst*
5283  {
5284  return new Inst_VOP3__V_CMPX_NLT_F64(&iFmt->iFmt_VOP3A);
5285  } // decode_OPU_VOP3__V_CMPX_NLT_F64
5286 
5287  GPUStaticInst*
5289  {
5290  return new Inst_VOP3__V_CMPX_TRU_F64(&iFmt->iFmt_VOP3A);
5291  } // decode_OPU_VOP3__V_CMPX_TRU_F64
5292 
5293  GPUStaticInst*
5295  {
5296  return new Inst_VOP3__V_CMP_F_I16(&iFmt->iFmt_VOP3A);
5297  } // decode_OPU_VOP3__V_CMP_F_I16
5298 
5299  GPUStaticInst*
5301  {
5302  return new Inst_VOP3__V_CMP_LT_I16(&iFmt->iFmt_VOP3A);
5303  } // decode_OPU_VOP3__V_CMP_LT_I16
5304 
5305  GPUStaticInst*
5307  {
5308  return new Inst_VOP3__V_CMP_EQ_I16(&iFmt->iFmt_VOP3A);
5309  } // decode_OPU_VOP3__V_CMP_EQ_I16
5310 
5311  GPUStaticInst*
5313  {
5314  return new Inst_VOP3__V_CMP_LE_I16(&iFmt->iFmt_VOP3A);
5315  } // decode_OPU_VOP3__V_CMP_LE_I16
5316 
5317  GPUStaticInst*
5319  {
5320  return new Inst_VOP3__V_CMP_GT_I16(&iFmt->iFmt_VOP3A);
5321  } // decode_OPU_VOP3__V_CMP_GT_I16
5322 
5323  GPUStaticInst*
5325  {
5326  return new Inst_VOP3__V_CMP_NE_I16(&iFmt->iFmt_VOP3A);
5327  } // decode_OPU_VOP3__V_CMP_NE_I16
5328 
5329  GPUStaticInst*
5331  {
5332  return new Inst_VOP3__V_CMP_GE_I16(&iFmt->iFmt_VOP3A);
5333  } // decode_OPU_VOP3__V_CMP_GE_I16
5334 
5335  GPUStaticInst*
5337  {
5338  return new Inst_VOP3__V_CMP_T_I16(&iFmt->iFmt_VOP3A);
5339  } // decode_OPU_VOP3__V_CMP_T_I16
5340 
5341  GPUStaticInst*
5343  {
5344  return new Inst_VOP3__V_CMP_F_U16(&iFmt->iFmt_VOP3A);
5345  } // decode_OPU_VOP3__V_CMP_F_U16
5346 
5347  GPUStaticInst*
5349  {
5350  return new Inst_VOP3__V_CMP_LT_U16(&iFmt->iFmt_VOP3A);
5351  } // decode_OPU_VOP3__V_CMP_LT_U16
5352 
5353  GPUStaticInst*
5355  {
5356  return new Inst_VOP3__V_CMP_EQ_U16(&iFmt->iFmt_VOP3A);
5357  } // decode_OPU_VOP3__V_CMP_EQ_U16
5358 
5359  GPUStaticInst*
5361  {
5362  return new Inst_VOP3__V_CMP_LE_U16(&iFmt->iFmt_VOP3A);
5363  } // decode_OPU_VOP3__V_CMP_LE_U16
5364 
5365  GPUStaticInst*
5367  {
5368  return new Inst_VOP3__V_CMP_GT_U16(&iFmt->iFmt_VOP3A);
5369  } // decode_OPU_VOP3__V_CMP_GT_U16
5370 
5371  GPUStaticInst*
5373  {
5374  return new Inst_VOP3__V_CMP_NE_U16(&iFmt->iFmt_VOP3A);
5375  } // decode_OPU_VOP3__V_CMP_NE_U16
5376 
5377  GPUStaticInst*
5379  {
5380  return new Inst_VOP3__V_CMP_GE_U16(&iFmt->iFmt_VOP3A);
5381  } // decode_OPU_VOP3__V_CMP_GE_U16
5382 
5383  GPUStaticInst*
5385  {
5386  return new Inst_VOP3__V_CMP_T_U16(&iFmt->iFmt_VOP3A);
5387  } // decode_OPU_VOP3__V_CMP_T_U16
5388 
5389  GPUStaticInst*
5391  {
5392  return new Inst_VOP3__V_CMPX_F_I16(&iFmt->iFmt_VOP3A);
5393  } // decode_OPU_VOP3__V_CMPX_F_I16
5394 
5395  GPUStaticInst*
5397  {
5398  return new Inst_VOP3__V_CMPX_LT_I16(&iFmt->iFmt_VOP3A);
5399  } // decode_OPU_VOP3__V_CMPX_LT_I16
5400 
5401  GPUStaticInst*
5403  {
5404  return new Inst_VOP3__V_CMPX_EQ_I16(&iFmt->iFmt_VOP3A);
5405  } // decode_OPU_VOP3__V_CMPX_EQ_I16
5406 
5407  GPUStaticInst*
5409  {
5410  return new Inst_VOP3__V_CMPX_LE_I16(&iFmt->iFmt_VOP3A);
5411  } // decode_OPU_VOP3__V_CMPX_LE_I16
5412 
5413  GPUStaticInst*
5415  {
5416  return new Inst_VOP3__V_CMPX_GT_I16(&iFmt->iFmt_VOP3A);
5417  } // decode_OPU_VOP3__V_CMPX_GT_I16
5418 
5419  GPUStaticInst*
5421  {
5422  return new Inst_VOP3__V_CMPX_NE_I16(&iFmt->iFmt_VOP3A);
5423  } // decode_OPU_VOP3__V_CMPX_NE_I16
5424 
5425  GPUStaticInst*
5427  {
5428  return new Inst_VOP3__V_CMPX_GE_I16(&iFmt->iFmt_VOP3A);
5429  } // decode_OPU_VOP3__V_CMPX_GE_I16
5430 
5431  GPUStaticInst*
5433  {
5434  return new Inst_VOP3__V_CMPX_T_I16(&iFmt->iFmt_VOP3A);
5435  } // decode_OPU_VOP3__V_CMPX_T_I16
5436 
5437  GPUStaticInst*
5439  {
5440  return new Inst_VOP3__V_CMPX_F_U16(&iFmt->iFmt_VOP3A);
5441  } // decode_OPU_VOP3__V_CMPX_F_U16
5442 
5443  GPUStaticInst*
5445  {
5446  return new Inst_VOP3__V_CMPX_LT_U16(&iFmt->iFmt_VOP3A);
5447  } // decode_OPU_VOP3__V_CMPX_LT_U16
5448 
5449  GPUStaticInst*
5451  {
5452  return new Inst_VOP3__V_CMPX_EQ_U16(&iFmt->iFmt_VOP3A);
5453  } // decode_OPU_VOP3__V_CMPX_EQ_U16
5454 
5455  GPUStaticInst*
5457  {
5458  return new Inst_VOP3__V_CMPX_LE_U16(&iFmt->iFmt_VOP3A);
5459  } // decode_OPU_VOP3__V_CMPX_LE_U16
5460 
5461  GPUStaticInst*
5463  {
5464  return new Inst_VOP3__V_CMPX_GT_U16(&iFmt->iFmt_VOP3A);
5465  } // decode_OPU_VOP3__V_CMPX_GT_U16
5466 
5467  GPUStaticInst*
5469  {
5470  return new Inst_VOP3__V_CMPX_NE_U16(&iFmt->iFmt_VOP3A);
5471  } // decode_OPU_VOP3__V_CMPX_NE_U16
5472 
5473  GPUStaticInst*
5475  {
5476  return new Inst_VOP3__V_CMPX_GE_U16(&iFmt->iFmt_VOP3A);
5477  } // decode_OPU_VOP3__V_CMPX_GE_U16
5478 
5479  GPUStaticInst*
5481  {
5482  return new Inst_VOP3__V_CMPX_T_U16(&iFmt->iFmt_VOP3A);
5483  } // decode_OPU_VOP3__V_CMPX_T_U16
5484 
5485  GPUStaticInst*
5487  {
5488  return new Inst_VOP3__V_CMP_F_I32(&iFmt->iFmt_VOP3A);
5489  } // decode_OPU_VOP3__V_CMP_F_I32
5490 
5491  GPUStaticInst*
5493  {
5494  return new Inst_VOP3__V_CMP_LT_I32(&iFmt->iFmt_VOP3A);
5495  } // decode_OPU_VOP3__V_CMP_LT_I32
5496 
5497  GPUStaticInst*
5499  {
5500  return new Inst_VOP3__V_CMP_EQ_I32(&iFmt->iFmt_VOP3A);
5501  } // decode_OPU_VOP3__V_CMP_EQ_I32
5502 
5503  GPUStaticInst*
5505  {
5506  return new Inst_VOP3__V_CMP_LE_I32(&iFmt->iFmt_VOP3A);
5507  } // decode_OPU_VOP3__V_CMP_LE_I32
5508 
5509  GPUStaticInst*
5511  {
5512  return new Inst_VOP3__V_CMP_GT_I32(&iFmt->iFmt_VOP3A);
5513  } // decode_OPU_VOP3__V_CMP_GT_I32
5514 
5515  GPUStaticInst*
5517  {
5518  return new Inst_VOP3__V_CMP_NE_I32(&iFmt->iFmt_VOP3A);
5519  } // decode_OPU_VOP3__V_CMP_NE_I32
5520 
5521  GPUStaticInst*
5523  {
5524  return new Inst_VOP3__V_CMP_GE_I32(&iFmt->iFmt_VOP3A);
5525  } // decode_OPU_VOP3__V_CMP_GE_I32
5526 
5527  GPUStaticInst*
5529  {
5530  return new Inst_VOP3__V_CMP_T_I32(&iFmt->iFmt_VOP3A);
5531  } // decode_OPU_VOP3__V_CMP_T_I32
5532 
5533  GPUStaticInst*
5535  {
5536  return new Inst_VOP3__V_CMP_F_U32(&iFmt->iFmt_VOP3A);
5537  } // decode_OPU_VOP3__V_CMP_F_U32
5538 
5539  GPUStaticInst*
5541  {
5542  return new Inst_VOP3__V_CMP_LT_U32(&iFmt->iFmt_VOP3A);
5543  } // decode_OPU_VOP3__V_CMP_LT_U32
5544 
5545  GPUStaticInst*
5547  {
5548  return new Inst_VOP3__V_CMP_EQ_U32(&iFmt->iFmt_VOP3A);
5549  } // decode_OPU_VOP3__V_CMP_EQ_U32
5550 
5551  GPUStaticInst*
5553  {
5554  return new Inst_VOP3__V_CMP_LE_U32(&iFmt->iFmt_VOP3A);
5555  } // decode_OPU_VOP3__V_CMP_LE_U32
5556 
5557  GPUStaticInst*
5559  {
5560  return new Inst_VOP3__V_CMP_GT_U32(&iFmt->iFmt_VOP3A);
5561  } // decode_OPU_VOP3__V_CMP_GT_U32
5562 
5563  GPUStaticInst*
5565  {
5566  return new Inst_VOP3__V_CMP_NE_U32(&iFmt->iFmt_VOP3A);
5567  } // decode_OPU_VOP3__V_CMP_NE_U32
5568 
5569  GPUStaticInst*
5571  {
5572  return new Inst_VOP3__V_CMP_GE_U32(&iFmt->iFmt_VOP3A);
5573  } // decode_OPU_VOP3__V_CMP_GE_U32
5574 
5575  GPUStaticInst*
5577  {
5578  return new Inst_VOP3__V_CMP_T_U32(&iFmt->iFmt_VOP3A);
5579  } // decode_OPU_VOP3__V_CMP_T_U32
5580 
5581  GPUStaticInst*
5583  {
5584  return new Inst_VOP3__V_CMPX_F_I32(&iFmt->iFmt_VOP3A);
5585  } // decode_OPU_VOP3__V_CMPX_F_I32
5586 
5587  GPUStaticInst*
5589  {
5590  return new Inst_VOP3__V_CMPX_LT_I32(&iFmt->iFmt_VOP3A);
5591  } // decode_OPU_VOP3__V_CMPX_LT_I32
5592 
5593  GPUStaticInst*
5595  {
5596  return new Inst_VOP3__V_CMPX_EQ_I32(&iFmt->iFmt_VOP3A);
5597  } // decode_OPU_VOP3__V_CMPX_EQ_I32
5598 
5599  GPUStaticInst*
5601  {
5602  return new Inst_VOP3__V_CMPX_LE_I32(&iFmt->iFmt_VOP3A);
5603  } // decode_OPU_VOP3__V_CMPX_LE_I32
5604 
5605  GPUStaticInst*
5607  {
5608  return new Inst_VOP3__V_CMPX_GT_I32(&iFmt->iFmt_VOP3A);
5609  } // decode_OPU_VOP3__V_CMPX_GT_I32
5610 
5611  GPUStaticInst*
5613  {
5614  return new Inst_VOP3__V_CMPX_NE_I32(&iFmt->iFmt_VOP3A);
5615  } // decode_OPU_VOP3__V_CMPX_NE_I32
5616 
5617  GPUStaticInst*
5619  {
5620  return new Inst_VOP3__V_CMPX_GE_I32(&iFmt->iFmt_VOP3A);
5621  } // decode_OPU_VOP3__V_CMPX_GE_I32
5622 
5623  GPUStaticInst*
5625  {
5626  return new Inst_VOP3__V_CMPX_T_I32(&iFmt->iFmt_VOP3A);
5627  } // decode_OPU_VOP3__V_CMPX_T_I32
5628 
5629  GPUStaticInst*
5631  {
5632  return new Inst_VOP3__V_CMPX_F_U32(&iFmt->iFmt_VOP3A);
5633  } // decode_OPU_VOP3__V_CMPX_F_U32
5634 
5635  GPUStaticInst*
5637  {
5638  return new Inst_VOP3__V_CMPX_LT_U32(&iFmt->iFmt_VOP3A);
5639  } // decode_OPU_VOP3__V_CMPX_LT_U32
5640 
5641  GPUStaticInst*
5643  {
5644  return new Inst_VOP3__V_CMPX_EQ_U32(&iFmt->iFmt_VOP3A);
5645  } // decode_OPU_VOP3__V_CMPX_EQ_U32
5646 
5647  GPUStaticInst*
5649  {
5650  return new Inst_VOP3__V_CMPX_LE_U32(&iFmt->iFmt_VOP3A);
5651  } // decode_OPU_VOP3__V_CMPX_LE_U32
5652 
5653  GPUStaticInst*
5655  {
5656  return new Inst_VOP3__V_CMPX_GT_U32(&iFmt->iFmt_VOP3A);
5657  } // decode_OPU_VOP3__V_CMPX_GT_U32
5658 
5659  GPUStaticInst*
5661  {
5662  return new Inst_VOP3__V_CMPX_NE_U32(&iFmt->iFmt_VOP3A);
5663  } // decode_OPU_VOP3__V_CMPX_NE_U32
5664 
5665  GPUStaticInst*
5667  {
5668  return new Inst_VOP3__V_CMPX_GE_U32(&iFmt->iFmt_VOP3A);
5669  } // decode_OPU_VOP3__V_CMPX_GE_U32
5670 
5671  GPUStaticInst*
5673  {
5674  return new Inst_VOP3__V_CMPX_T_U32(&iFmt->iFmt_VOP3A);
5675  } // decode_OPU_VOP3__V_CMPX_T_U32
5676 
5677  GPUStaticInst*
5679  {
5680  return new Inst_VOP3__V_CMP_F_I64(&iFmt->iFmt_VOP3A);
5681  } // decode_OPU_VOP3__V_CMP_F_I64
5682 
5683  GPUStaticInst*
5685  {
5686  return new Inst_VOP3__V_CMP_LT_I64(&iFmt->iFmt_VOP3A);
5687  } // decode_OPU_VOP3__V_CMP_LT_I64
5688 
5689  GPUStaticInst*
5691  {
5692  return new Inst_VOP3__V_CMP_EQ_I64(&iFmt->iFmt_VOP3A);
5693  } // decode_OPU_VOP3__V_CMP_EQ_I64
5694 
5695  GPUStaticInst*
5697  {
5698  return new Inst_VOP3__V_CMP_LE_I64(&iFmt->iFmt_VOP3A);
5699  } // decode_OPU_VOP3__V_CMP_LE_I64
5700 
5701  GPUStaticInst*
5703  {
5704  return new Inst_VOP3__V_CMP_GT_I64(&iFmt->iFmt_VOP3A);
5705  } // decode_OPU_VOP3__V_CMP_GT_I64
5706 
5707  GPUStaticInst*
5709  {
5710  return new Inst_VOP3__V_CMP_NE_I64(&iFmt->iFmt_VOP3A);
5711  } // decode_OPU_VOP3__V_CMP_NE_I64
5712 
5713  GPUStaticInst*
5715  {
5716  return new Inst_VOP3__V_CMP_GE_I64(&iFmt->iFmt_VOP3A);
5717  } // decode_OPU_VOP3__V_CMP_GE_I64
5718 
5719  GPUStaticInst*
5721  {
5722  return new Inst_VOP3__V_CMP_T_I64(&iFmt->iFmt_VOP3A);
5723  } // decode_OPU_VOP3__V_CMP_T_I64
5724 
5725  GPUStaticInst*
5727  {
5728  return new Inst_VOP3__V_CMP_F_U64(&iFmt->iFmt_VOP3A);
5729  } // decode_OPU_VOP3__V_CMP_F_U64
5730 
5731  GPUStaticInst*
5733  {
5734  return new Inst_VOP3__V_CMP_LT_U64(&iFmt->iFmt_VOP3A);
5735  } // decode_OPU_VOP3__V_CMP_LT_U64
5736 
5737  GPUStaticInst*
5739  {
5740  return new Inst_VOP3__V_CMP_EQ_U64(&iFmt->iFmt_VOP3A);
5741  } // decode_OPU_VOP3__V_CMP_EQ_U64
5742 
5743  GPUStaticInst*
5745  {
5746  return new Inst_VOP3__V_CMP_LE_U64(&iFmt->iFmt_VOP3A);
5747  } // decode_OPU_VOP3__V_CMP_LE_U64
5748 
5749  GPUStaticInst*
5751  {
5752  return new Inst_VOP3__V_CMP_GT_U64(&iFmt->iFmt_VOP3A);
5753  } // decode_OPU_VOP3__V_CMP_GT_U64
5754 
5755  GPUStaticInst*
5757  {
5758  return new Inst_VOP3__V_CMP_NE_U64(&iFmt->iFmt_VOP3A);
5759  } // decode_OPU_VOP3__V_CMP_NE_U64
5760 
5761  GPUStaticInst*
5763  {
5764  return new Inst_VOP3__V_CMP_GE_U64(&iFmt->iFmt_VOP3A);
5765  } // decode_OPU_VOP3__V_CMP_GE_U64
5766 
5767  GPUStaticInst*
5769  {
5770  return new Inst_VOP3__V_CMP_T_U64(&iFmt->iFmt_VOP3A);
5771  } // decode_OPU_VOP3__V_CMP_T_U64
5772 
5773  GPUStaticInst*
5775  {
5776  return new Inst_VOP3__V_CMPX_F_I64(&iFmt->iFmt_VOP3A);
5777  } // decode_OPU_VOP3__V_CMPX_F_I64
5778 
5779  GPUStaticInst*
5781  {
5782  return new Inst_VOP3__V_CMPX_LT_I64(&iFmt->iFmt_VOP3A);
5783  } // decode_OPU_VOP3__V_CMPX_LT_I64
5784 
5785  GPUStaticInst*
5787  {
5788  return new Inst_VOP3__V_CMPX_EQ_I64(&iFmt->iFmt_VOP3A);
5789  } // decode_OPU_VOP3__V_CMPX_EQ_I64
5790 
5791  GPUStaticInst*
5793  {
5794  return new Inst_VOP3__V_CMPX_LE_I64(&iFmt->iFmt_VOP3A);
5795  } // decode_OPU_VOP3__V_CMPX_LE_I64
5796 
5797  GPUStaticInst*
5799  {
5800  return new Inst_VOP3__V_CMPX_GT_I64(&iFmt->iFmt_VOP3A);
5801  } // decode_OPU_VOP3__V_CMPX_GT_I64
5802 
5803  GPUStaticInst*
5805  {
5806  return new Inst_VOP3__V_CMPX_NE_I64(&iFmt->iFmt_VOP3A);
5807  } // decode_OPU_VOP3__V_CMPX_NE_I64
5808 
5809  GPUStaticInst*
5811  {
5812  return new Inst_VOP3__V_CMPX_GE_I64(&iFmt->iFmt_VOP3A);
5813  } // decode_OPU_VOP3__V_CMPX_GE_I64
5814 
5815  GPUStaticInst*
5817  {
5818  return new Inst_VOP3__V_CMPX_T_I64(&iFmt->iFmt_VOP3A);
5819  } // decode_OPU_VOP3__V_CMPX_T_I64
5820 
5821  GPUStaticInst*
5823  {
5824  return new Inst_VOP3__V_CMPX_F_U64(&iFmt->iFmt_VOP3A);
5825  } // decode_OPU_VOP3__V_CMPX_F_U64
5826 
5827  GPUStaticInst*
5829  {
5830  return new Inst_VOP3__V_CMPX_LT_U64(&iFmt->iFmt_VOP3A);
5831  } // decode_OPU_VOP3__V_CMPX_LT_U64
5832 
5833  GPUStaticInst*
5835  {
5836  return new Inst_VOP3__V_CMPX_EQ_U64(&iFmt->iFmt_VOP3A);
5837  } // decode_OPU_VOP3__V_CMPX_EQ_U64
5838 
5839  GPUStaticInst*
5841  {
5842  return new Inst_VOP3__V_CMPX_LE_U64(&iFmt->iFmt_VOP3A);
5843  } // decode_OPU_VOP3__V_CMPX_LE_U64
5844 
5845  GPUStaticInst*
5847  {
5848  return new Inst_VOP3__V_CMPX_GT_U64(&iFmt->iFmt_VOP3A);
5849  } // decode_OPU_VOP3__V_CMPX_GT_U64
5850 
5851  GPUStaticInst*
5853  {
5854  return new Inst_VOP3__V_CMPX_NE_U64(&iFmt->iFmt_VOP3A);
5855  } // decode_OPU_VOP3__V_CMPX_NE_U64
5856 
5857  GPUStaticInst*
5859  {
5860  return new Inst_VOP3__V_CMPX_GE_U64(&iFmt->iFmt_VOP3A);
5861  } // decode_OPU_VOP3__V_CMPX_GE_U64
5862 
5863  GPUStaticInst*
5865  {
5866  return new Inst_VOP3__V_CMPX_T_U64(&iFmt->iFmt_VOP3A);
5867  } // decode_OPU_VOP3__V_CMPX_T_U64
5868 
5869  GPUStaticInst*
5871  {
5872  return new Inst_VOP3__V_CNDMASK_B32(&iFmt->iFmt_VOP3A);
5873  } // decode_OPU_VOP3__V_CNDMASK_B32
5874 
5875  GPUStaticInst*
5877  {
5878  return new Inst_VOP3__V_ADD_F32(&iFmt->iFmt_VOP3A);
5879  } // decode_OPU_VOP3__V_ADD_F32
5880 
5881  GPUStaticInst*
5883  {
5884  return new Inst_VOP3__V_SUB_F32(&iFmt->iFmt_VOP3A);
5885  } // decode_OPU_VOP3__V_SUB_F32
5886 
5887  GPUStaticInst*
5889  {
5890  return new Inst_VOP3__V_SUBREV_F32(&iFmt->iFmt_VOP3A);
5891  } // decode_OPU_VOP3__V_SUBREV_F32
5892 
5893  GPUStaticInst*
5895  {
5896  return new Inst_VOP3__V_MUL_LEGACY_F32(&iFmt->iFmt_VOP3A);
5897  } // decode_OPU_VOP3__V_MUL_LEGACY_F32
5898 
5899  GPUStaticInst*
5901  {
5902  return new Inst_VOP3__V_MUL_F32(&iFmt->iFmt_VOP3A);
5903  } // decode_OPU_VOP3__V_MUL_F32
5904 
5905  GPUStaticInst*
5907  {
5908  return new Inst_VOP3__V_MUL_I32_I24(&iFmt->iFmt_VOP3A);
5909  } // decode_OPU_VOP3__V_MUL_I32_I24
5910 
5911  GPUStaticInst*
5913  {
5914  return new Inst_VOP3__V_MUL_HI_I32_I24(&iFmt->iFmt_VOP3A);
5915  } // decode_OPU_VOP3__V_MUL_HI_I32_I24
5916 
5917  GPUStaticInst*
5919  {
5920  return new Inst_VOP3__V_MUL_U32_U24(&iFmt->iFmt_VOP3A);
5921  } // decode_OPU_VOP3__V_MUL_U32_U24
5922 
5923  GPUStaticInst*
5925  {
5926  return new Inst_VOP3__V_MUL_HI_U32_U24(&iFmt->iFmt_VOP3A);
5927  } // decode_OPU_VOP3__V_MUL_HI_U32_U24
5928 
5929  GPUStaticInst*
5931  {
5932  return new Inst_VOP3__V_MIN_F32(&iFmt->iFmt_VOP3A);
5933  } // decode_OPU_VOP3__V_MIN_F32
5934 
5935  GPUStaticInst*
5937  {
5938  return new Inst_VOP3__V_MAX_F32(&iFmt->iFmt_VOP3A);
5939  } // decode_OPU_VOP3__V_MAX_F32
5940 
5941  GPUStaticInst*
5943  {
5944  return new Inst_VOP3__V_MIN_I32(&iFmt->iFmt_VOP3A);
5945  } // decode_OPU_VOP3__V_MIN_I32
5946 
5947  GPUStaticInst*
5949  {
5950  return new Inst_VOP3__V_MAX_I32(&iFmt->iFmt_VOP3A);
5951  } // decode_OPU_VOP3__V_MAX_I32
5952 
5953  GPUStaticInst*
5955  {
5956  return new Inst_VOP3__V_MIN_U32(&iFmt->iFmt_VOP3A);
5957  } // decode_OPU_VOP3__V_MIN_U32
5958 
5959  GPUStaticInst*
5961  {
5962  return new Inst_VOP3__V_MAX_U32(&iFmt->iFmt_VOP3A);
5963  } // decode_OPU_VOP3__V_MAX_U32
5964 
5965  GPUStaticInst*
5967  {
5968  return new Inst_VOP3__V_LSHRREV_B32(&iFmt->iFmt_VOP3A);
5969  } // decode_OPU_VOP3__V_LSHRREV_B32
5970 
5971  GPUStaticInst*
5973  {
5974  return new Inst_VOP3__V_ASHRREV_I32(&iFmt->iFmt_VOP3A);
5975  } // decode_OPU_VOP3__V_ASHRREV_I32
5976 
5977  GPUStaticInst*
5979  {
5980  return new Inst_VOP3__V_LSHLREV_B32(&iFmt->iFmt_VOP3A);
5981  } // decode_OPU_VOP3__V_LSHLREV_B32
5982 
5983  GPUStaticInst*
5985  {
5986  return new Inst_VOP3__V_AND_B32(&iFmt->iFmt_VOP3A);
5987  } // decode_OPU_VOP3__V_AND_B32
5988 
5989  GPUStaticInst*
5991  {
5992  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
5993  } // decode_OPU_VOP3__V_OR_B32
5994 
5995  GPUStaticInst*
5997  {
5998  return new Inst_VOP3__V_XOR_B32(&iFmt->iFmt_VOP3A);
5999  } // decode_OPU_VOP3__V_XOR_B32
6000 
6001  GPUStaticInst*
6003  {
6004  return new Inst_VOP3__V_MAC_F32(&iFmt->iFmt_VOP3A);
6005  } // decode_OPU_VOP3__V_MAC_F32
6006 
6007  GPUStaticInst*
6009  {
6010  return new Inst_VOP3__V_ADD_CO_U32(&iFmt->iFmt_VOP3B);
6011  } // decode_OPU_VOP3__V_ADD_CO_U32
6012 
6013  GPUStaticInst*
6015  {
6016  return new Inst_VOP3__V_SUB_CO_U32(&iFmt->iFmt_VOP3B);
6017  } // decode_OPU_VOP3__V_SUB_CO_U32
6018 
6019  GPUStaticInst*
6021  {
6022  return new Inst_VOP3__V_SUBREV_CO_U32(&iFmt->iFmt_VOP3B);
6023  } // decode_OPU_VOP3__V_SUBREV_CO_U32
6024 
6025  GPUStaticInst*
6027  {
6028  return new Inst_VOP3__V_ADDC_CO_U32(&iFmt->iFmt_VOP3B);
6029  } // decode_OPU_VOP3__V_ADDC_CO_U32
6030 
6031  GPUStaticInst*
6033  {
6034  return new Inst_VOP3__V_SUBB_CO_U32(&iFmt->iFmt_VOP3B);
6035  } // decode_OPU_VOP3__V_SUBB_CO_U32
6036 
6037  GPUStaticInst*
6039  {
6040  return new Inst_VOP3__V_SUBBREV_CO_U32(&iFmt->iFmt_VOP3B);
6041  } // decode_OPU_VOP3__V_SUBBREV_CO_U32
6042 
6043  GPUStaticInst*
6045  {
6046  return new Inst_VOP3__V_ADD_F16(&iFmt->iFmt_VOP3A);
6047  } // decode_OPU_VOP3__V_ADD_F16
6048 
6049  GPUStaticInst*
6051  {
6052  return new Inst_VOP3__V_SUB_F16(&iFmt->iFmt_VOP3A);
6053  } // decode_OPU_VOP3__V_SUB_F16
6054 
6055  GPUStaticInst*
6057  {
6058  return new Inst_VOP3__V_SUBREV_F16(&iFmt->iFmt_VOP3A);
6059  } // decode_OPU_VOP3__V_SUBREV_F16
6060 
6061  GPUStaticInst*
6063  {
6064  return new Inst_VOP3__V_MUL_F16(&iFmt->iFmt_VOP3A);
6065  } // decode_OPU_VOP3__V_MUL_F16
6066 
6067  GPUStaticInst*
6069  {
6070  return new Inst_VOP3__V_MAC_F16(&iFmt->iFmt_VOP3A);
6071  } // decode_OPU_VOP3__V_MAC_F16
6072 
6073  GPUStaticInst*
6075  {
6076  return new Inst_VOP3__V_ADD_U16(&iFmt->iFmt_VOP3A);
6077  } // decode_OPU_VOP3__V_ADD_U16
6078 
6079  GPUStaticInst*
6081  {
6082  return new Inst_VOP3__V_SUB_U16(&iFmt->iFmt_VOP3A);
6083  } // decode_OPU_VOP3__V_SUB_U16
6084 
6085  GPUStaticInst*
6087  {
6088  return new Inst_VOP3__V_SUBREV_U16(&iFmt->iFmt_VOP3A);
6089  } // decode_OPU_VOP3__V_SUBREV_U16
6090 
6091  GPUStaticInst*
6093  {
6094  return new Inst_VOP3__V_MUL_LO_U16(&iFmt->iFmt_VOP3A);
6095  } // decode_OPU_VOP3__V_MUL_LO_U16
6096 
6097  GPUStaticInst*
6099  {
6100  return new Inst_VOP3__V_LSHLREV_B16(&iFmt->iFmt_VOP3A);
6101  } // decode_OPU_VOP3__V_LSHLREV_B16
6102 
6103  GPUStaticInst*
6105  {
6106  return new Inst_VOP3__V_LSHRREV_B16(&iFmt->iFmt_VOP3A);
6107  } // decode_OPU_VOP3__V_LSHRREV_B16
6108 
6109  GPUStaticInst*
6111  {
6112  return new Inst_VOP3__V_ASHRREV_I16(&iFmt->iFmt_VOP3A);
6113  } // decode_OPU_VOP3__V_ASHRREV_I16
6114 
6115  GPUStaticInst*
6117  {
6118  return new Inst_VOP3__V_MAX_F16(&iFmt->iFmt_VOP3A);
6119  } // decode_OPU_VOP3__V_MAX_F16
6120 
6121  GPUStaticInst*
6123  {
6124  return new Inst_VOP3__V_MIN_F16(&iFmt->iFmt_VOP3A);
6125  } // decode_OPU_VOP3__V_MIN_F16
6126 
6127  GPUStaticInst*
6129  {
6130  return new Inst_VOP3__V_MAX_U16(&iFmt->iFmt_VOP3A);
6131  } // decode_OPU_VOP3__V_MAX_U16
6132 
6133  GPUStaticInst*
6135  {
6136  return new Inst_VOP3__V_MAX_I16(&iFmt->iFmt_VOP3A);
6137  } // decode_OPU_VOP3__V_MAX_I16
6138 
6139  GPUStaticInst*
6141  {
6142  return new Inst_VOP3__V_MIN_U16(&iFmt->iFmt_VOP3A);
6143  } // decode_OPU_VOP3__V_MIN_U16
6144 
6145  GPUStaticInst*
6147  {
6148  return new Inst_VOP3__V_MIN_I16(&iFmt->iFmt_VOP3A);
6149  } // decode_OPU_VOP3__V_MIN_I16
6150 
6151  GPUStaticInst*
6153  {
6154  return new Inst_VOP3__V_LDEXP_F16(&iFmt->iFmt_VOP3A);
6155  } // decode_OPU_VOP3__V_LDEXP_F16
6156 
6157  GPUStaticInst*
6159  {
6160  return new Inst_VOP3__V_ADD_U32(&iFmt->iFmt_VOP3A);
6161  } // decode_OPU_VOP3__V_ADD_U32
6162 
6163  GPUStaticInst*
6165  {
6166  return new Inst_VOP3__V_SUB_U32(&iFmt->iFmt_VOP3A);
6167  } // decode_OPU_VOP3__V_SUB_U32
6168 
6169  GPUStaticInst*
6171  {
6172  return new Inst_VOP3__V_SUBREV_U32(&iFmt->iFmt_VOP3A);
6173  } // decode_OPU_VOP3__V_SUBREV_U32
6174 
6175  GPUStaticInst*
6177  {
6178  return new Inst_VOP3__V_NOP(&iFmt->iFmt_VOP3A);
6179  } // decode_OPU_VOP3__V_NOP
6180 
6181  GPUStaticInst*
6183  {
6184  return new Inst_VOP3__V_MOV_B32(&iFmt->iFmt_VOP3A);
6185  } // decode_OPU_VOP3__V_MOV_B32
6186 
6187  GPUStaticInst*
6189  {
6190  return new Inst_VOP3__V_CVT_I32_F64(&iFmt->iFmt_VOP3A);
6191  } // decode_OPU_VOP3__V_CVT_I32_F64
6192 
6193  GPUStaticInst*
6195  {
6196  return new Inst_VOP3__V_CVT_F64_I32(&iFmt->iFmt_VOP3A);
6197  } // decode_OPU_VOP3__V_CVT_F64_I32
6198 
6199  GPUStaticInst*
6201  {
6202  return new Inst_VOP3__V_CVT_F32_I32(&iFmt->iFmt_VOP3A);
6203  } // decode_OPU_VOP3__V_CVT_F32_I32
6204 
6205  GPUStaticInst*
6207  {
6208  return new Inst_VOP3__V_CVT_F32_U32(&iFmt->iFmt_VOP3A);
6209  } // decode_OPU_VOP3__V_CVT_F32_U32
6210 
6211  GPUStaticInst*
6213  {
6214  return new Inst_VOP3__V_CVT_U32_F32(&iFmt->iFmt_VOP3A);
6215  } // decode_OPU_VOP3__V_CVT_U32_F32
6216 
6217  GPUStaticInst*
6219  {
6220  return new Inst_VOP3__V_CVT_I32_F32(&iFmt->iFmt_VOP3A);
6221  } // decode_OPU_VOP3__V_CVT_I32_F32
6222 
6223  GPUStaticInst*
6225  {
6226  return new Inst_VOP3__V_MOV_FED_B32(&iFmt->iFmt_VOP3A);
6227  } // decode_OPU_VOP3__V_MOV_FED_B32
6228 
6229  GPUStaticInst*
6231  {
6232  return new Inst_VOP3__V_CVT_F16_F32(&iFmt->iFmt_VOP3A);
6233  } // decode_OPU_VOP3__V_CVT_F16_F32
6234 
6235  GPUStaticInst*
6237  {
6238  return new Inst_VOP3__V_CVT_F32_F16(&iFmt->iFmt_VOP3A);
6239  } // decode_OPU_VOP3__V_CVT_F32_F16
6240 
6241  GPUStaticInst*
6243  {
6244  return new Inst_VOP3__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP3A);
6245  } // decode_OPU_VOP3__V_CVT_RPI_I32_F32
6246 
6247  GPUStaticInst*
6249  {
6250  return new Inst_VOP3__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP3A);
6251  } // decode_OPU_VOP3__V_CVT_FLR_I32_F32
6252 
6253  GPUStaticInst*
6255  {
6256  return new Inst_VOP3__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP3A);
6257  } // decode_OPU_VOP3__V_CVT_OFF_F32_I4
6258 
6259  GPUStaticInst*
6261  {
6262  return new Inst_VOP3__V_CVT_F32_F64(&iFmt->iFmt_VOP3A);
6263  } // decode_OPU_VOP3__V_CVT_F32_F64
6264 
6265  GPUStaticInst*
6267  {
6268  return new Inst_VOP3__V_CVT_F64_F32(&iFmt->iFmt_VOP3A);
6269  } // decode_OPU_VOP3__V_CVT_F64_F32
6270 
6271  GPUStaticInst*
6273  {
6274  return new Inst_VOP3__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP3A);
6275  } // decode_OPU_VOP3__V_CVT_F32_UBYTE0
6276 
6277  GPUStaticInst*
6279  {
6280  return new Inst_VOP3__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP3A);
6281  } // decode_OPU_VOP3__V_CVT_F32_UBYTE1
6282 
6283  GPUStaticInst*
6285  {
6286  return new Inst_VOP3__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP3A);
6287  } // decode_OPU_VOP3__V_CVT_F32_UBYTE2
6288 
6289  GPUStaticInst*
6291  {
6292  return new Inst_VOP3__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP3A);
6293  } // decode_OPU_VOP3__V_CVT_F32_UBYTE3
6294 
6295  GPUStaticInst*
6297  {
6298  return new Inst_VOP3__V_CVT_U32_F64(&iFmt->iFmt_VOP3A);
6299  } // decode_OPU_VOP3__V_CVT_U32_F64
6300 
6301  GPUStaticInst*
6303  {
6304  return new Inst_VOP3__V_CVT_F64_U32(&iFmt->iFmt_VOP3A);
6305  } // decode_OPU_VOP3__V_CVT_F64_U32
6306 
6307  GPUStaticInst*
6309  {
6310  return new Inst_VOP3__V_TRUNC_F64(&iFmt->iFmt_VOP3A);
6311  } // decode_OPU_VOP3__V_TRUNC_F64
6312 
6313  GPUStaticInst*
6315  {
6316  return new Inst_VOP3__V_CEIL_F64(&iFmt->iFmt_VOP3A);
6317  } // decode_OPU_VOP3__V_CEIL_F64
6318 
6319  GPUStaticInst*
6321  {
6322  return new Inst_VOP3__V_RNDNE_F64(&iFmt->iFmt_VOP3A);
6323  } // decode_OPU_VOP3__V_RNDNE_F64
6324 
6325  GPUStaticInst*
6327  {
6328  return new Inst_VOP3__V_FLOOR_F64(&iFmt->iFmt_VOP3A);
6329  } // decode_OPU_VOP3__V_FLOOR_F64
6330 
6331  GPUStaticInst*
6333  {
6334  return new Inst_VOP3__V_FRACT_F32(&iFmt->iFmt_VOP3A);
6335  } // decode_OPU_VOP3__V_FRACT_F32
6336 
6337  GPUStaticInst*
6339  {
6340  return new Inst_VOP3__V_TRUNC_F32(&iFmt->iFmt_VOP3A);
6341  } // decode_OPU_VOP3__V_TRUNC_F32
6342 
6343  GPUStaticInst*
6345  {
6346  return new Inst_VOP3__V_CEIL_F32(&iFmt->iFmt_VOP3A);
6347  } // decode_OPU_VOP3__V_CEIL_F32
6348 
6349  GPUStaticInst*
6351  {
6352  return new Inst_VOP3__V_RNDNE_F32(&iFmt->iFmt_VOP3A);
6353  } // decode_OPU_VOP3__V_RNDNE_F32
6354 
6355  GPUStaticInst*
6357  {
6358  return new Inst_VOP3__V_FLOOR_F32(&iFmt->iFmt_VOP3A);
6359  } // decode_OPU_VOP3__V_FLOOR_F32
6360 
6361  GPUStaticInst*
6363  {
6364  return new Inst_VOP3__V_EXP_F32(&iFmt->iFmt_VOP3A);
6365  } // decode_OPU_VOP3__V_EXP_F32
6366 
6367  GPUStaticInst*
6369  {
6370  return new Inst_VOP3__V_LOG_F32(&iFmt->iFmt_VOP3A);
6371  } // decode_OPU_VOP3__V_LOG_F32
6372 
6373  GPUStaticInst*
6375  {
6376  return new Inst_VOP3__V_RCP_F32(&iFmt->iFmt_VOP3A);
6377  } // decode_OPU_VOP3__V_RCP_F32
6378 
6379  GPUStaticInst*
6381  {
6382  return new Inst_VOP3__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP3A);
6383  } // decode_OPU_VOP3__V_RCP_IFLAG_F32
6384 
6385  GPUStaticInst*
6387  {
6388  return new Inst_VOP3__V_RSQ_F32(&iFmt->iFmt_VOP3A);
6389  } // decode_OPU_VOP3__V_RSQ_F32
6390 
6391  GPUStaticInst*
6393  {
6394  return new Inst_VOP3__V_RCP_F64(&iFmt->iFmt_VOP3A);
6395  } // decode_OPU_VOP3__V_RCP_F64
6396 
6397  GPUStaticInst*
6399  {
6400  return new Inst_VOP3__V_RSQ_F64(&iFmt->iFmt_VOP3A);
6401  } // decode_OPU_VOP3__V_RSQ_F64
6402 
6403  GPUStaticInst*
6405  {
6406  return new Inst_VOP3__V_SQRT_F32(&iFmt->iFmt_VOP3A);
6407  } // decode_OPU_VOP3__V_SQRT_F32
6408 
6409  GPUStaticInst*
6411  {
6412  return new Inst_VOP3__V_SQRT_F64(&iFmt->iFmt_VOP3A);
6413  } // decode_OPU_VOP3__V_SQRT_F64
6414 
6415  GPUStaticInst*
6417  {
6418  return new Inst_VOP3__V_SIN_F32(&iFmt->iFmt_VOP3A);
6419  } // decode_OPU_VOP3__V_SIN_F32
6420 
6421  GPUStaticInst*
6423  {
6424  return new Inst_VOP3__V_COS_F32(&iFmt->iFmt_VOP3A);
6425  } // decode_OPU_VOP3__V_COS_F32
6426 
6427  GPUStaticInst*
6429  {
6430  return new Inst_VOP3__V_NOT_B32(&iFmt->iFmt_VOP3A);
6431  } // decode_OPU_VOP3__V_NOT_B32
6432 
6433  GPUStaticInst*
6435  {
6436  return new Inst_VOP3__V_BFREV_B32(&iFmt->iFmt_VOP3A);
6437  } // decode_OPU_VOP3__V_BFREV_B32
6438 
6439  GPUStaticInst*
6441  {
6442  return new Inst_VOP3__V_FFBH_U32(&iFmt->iFmt_VOP3A);
6443  } // decode_OPU_VOP3__V_FFBH_U32
6444 
6445  GPUStaticInst*
6447  {
6448  return new Inst_VOP3__V_FFBL_B32(&iFmt->iFmt_VOP3A);
6449  } // decode_OPU_VOP3__V_FFBL_B32
6450 
6451  GPUStaticInst*
6453  {
6454  return new Inst_VOP3__V_FFBH_I32(&iFmt->iFmt_VOP3A);
6455  } // decode_OPU_VOP3__V_FFBH_I32
6456 
6457  GPUStaticInst*
6459  {
6460  return new Inst_VOP3__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP3A);
6461  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F64
6462 
6463  GPUStaticInst*
6465  {
6466  return new Inst_VOP3__V_FREXP_MANT_F64(&iFmt->iFmt_VOP3A);
6467  } // decode_OPU_VOP3__V_FREXP_MANT_F64
6468 
6469  GPUStaticInst*
6471  {
6472  return new Inst_VOP3__V_FRACT_F64(&iFmt->iFmt_VOP3A);
6473  } // decode_OPU_VOP3__V_FRACT_F64
6474 
6475  GPUStaticInst*
6477  {
6478  return new Inst_VOP3__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP3A);
6479  } // decode_OPU_VOP3__V_FREXP_EXP_I32_F32
6480 
6481  GPUStaticInst*
6483  {
6484  return new Inst_VOP3__V_FREXP_MANT_F32(&iFmt->iFmt_VOP3A);
6485  } // decode_OPU_VOP3__V_FREXP_MANT_F32
6486 
6487  GPUStaticInst*
6489  {
6490  return new Inst_VOP3__V_CLREXCP(&iFmt->iFmt_VOP3A);
6491  } // decode_OPU_VOP3__V_CLREXCP
6492 
6493  GPUStaticInst*
6495  {
6496  return new Inst_VOP3__V_CVT_F16_U16(&iFmt->iFmt_VOP3A);
6497  } // decode_OPU_VOP3__V_CVT_F16_U16
6498 
6499  GPUStaticInst*
6501  {
6502  return new Inst_VOP3__V_CVT_F16_I16(&iFmt->iFmt_VOP3A);
6503  } // decode_OPU_VOP3__V_CVT_F16_I16
6504 
6505  GPUStaticInst*
6507  {
6508  return new Inst_VOP3__V_CVT_U16_F16(&iFmt->iFmt_VOP3A);
6509  } // decode_OPU_VOP3__V_CVT_U16_F16
6510 
6511  GPUStaticInst*
6513  {
6514  return new Inst_VOP3__V_CVT_I16_F16(&iFmt->iFmt_VOP3A);
6515  } // decode_OPU_VOP3__V_CVT_I16_F16
6516 
6517  GPUStaticInst*
6519  {
6520  return new Inst_VOP3__V_RCP_F16(&iFmt->iFmt_VOP3A);
6521  } // decode_OPU_VOP3__V_RCP_F16
6522 
6523  GPUStaticInst*
6525  {
6526  return new Inst_VOP3__V_SQRT_F16(&iFmt->iFmt_VOP3A);
6527  } // decode_OPU_VOP3__V_SQRT_F16
6528 
6529  GPUStaticInst*
6531  {
6532  return new Inst_VOP3__V_RSQ_F16(&iFmt->iFmt_VOP3A);
6533  } // decode_OPU_VOP3__V_RSQ_F16
6534 
6535  GPUStaticInst*
6537  {
6538  return new Inst_VOP3__V_LOG_F16(&iFmt->iFmt_VOP3A);
6539  } // decode_OPU_VOP3__V_LOG_F16
6540 
6541  GPUStaticInst*
6543  {
6544  return new Inst_VOP3__V_EXP_F16(&iFmt->iFmt_VOP3A);
6545  } // decode_OPU_VOP3__V_EXP_F16
6546 
6547  GPUStaticInst*
6549  {
6550  return new Inst_VOP3__V_FREXP_MANT_F16(&iFmt->iFmt_VOP3A);
6551  } // decode_OPU_VOP3__V_FREXP_MANT_F16
6552 
6553  GPUStaticInst*
6555  {
6556  return new Inst_VOP3__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP3A);
6557  } // decode_OPU_VOP3__V_FREXP_EXP_I16_F16
6558 
6559  GPUStaticInst*
6561  {
6562  return new Inst_VOP3__V_FLOOR_F16(&iFmt->iFmt_VOP3A);
6563  } // decode_OPU_VOP3__V_FLOOR_F16
6564 
6565  GPUStaticInst*
6567  {
6568  return new Inst_VOP3__V_CEIL_F16(&iFmt->iFmt_VOP3A);
6569  } // decode_OPU_VOP3__V_CEIL_F16
6570 
6571  GPUStaticInst*
6573  {
6574  return new Inst_VOP3__V_TRUNC_F16(&iFmt->iFmt_VOP3A);
6575  } // decode_OPU_VOP3__V_TRUNC_F16
6576 
6577  GPUStaticInst*
6579  {
6580  return new Inst_VOP3__V_RNDNE_F16(&iFmt->iFmt_VOP3A);
6581  } // decode_OPU_VOP3__V_RNDNE_F16
6582 
6583  GPUStaticInst*
6585  {
6586  return new Inst_VOP3__V_FRACT_F16(&iFmt->iFmt_VOP3A);
6587  } // decode_OPU_VOP3__V_FRACT_F16
6588 
6589  GPUStaticInst*
6591  {
6592  return new Inst_VOP3__V_SIN_F16(&iFmt->iFmt_VOP3A);
6593  } // decode_OPU_VOP3__V_SIN_F16
6594 
6595  GPUStaticInst*
6597  {
6598  return new Inst_VOP3__V_COS_F16(&iFmt->iFmt_VOP3A);
6599  } // decode_OPU_VOP3__V_COS_F16
6600 
6601  GPUStaticInst*
6603  {
6604  return new Inst_VOP3__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP3A);
6605  } // decode_OPU_VOP3__V_EXP_LEGACY_F32
6606 
6607  GPUStaticInst*
6609  {
6610  return new Inst_VOP3__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP3A);
6611  } // decode_OPU_VOP3__V_LOG_LEGACY_F32
6612 
6613  GPUStaticInst*
6615  {
6616  return new Inst_VOP3__V_MAD_LEGACY_F32(&iFmt->iFmt_VOP3A);
6617  } // decode_OPU_VOP3__V_MAD_LEGACY_F32
6618 
6619  GPUStaticInst*
6621  {
6622  return new Inst_VOP3__V_MAD_F32(&iFmt->iFmt_VOP3A);
6623  } // decode_OPU_VOP3__V_MAD_F32
6624 
6625  GPUStaticInst*
6627  {
6628  return new Inst_VOP3__V_MAD_I32_I24(&iFmt->iFmt_VOP3A);
6629  } // decode_OPU_VOP3__V_MAD_I32_I24
6630 
6631  GPUStaticInst*
6633  {
6634  return new Inst_VOP3__V_MAD_U32_U24(&iFmt->iFmt_VOP3A);
6635  } // decode_OPU_VOP3__V_MAD_U32_U24
6636 
6637  GPUStaticInst*
6639  {
6640  return new Inst_VOP3__V_CUBEID_F32(&iFmt->iFmt_VOP3A);
6641  } // decode_OPU_VOP3__V_CUBEID_F32
6642 
6643  GPUStaticInst*
6645  {
6646  return new Inst_VOP3__V_CUBESC_F32(&iFmt->iFmt_VOP3A);
6647  } // decode_OPU_VOP3__V_CUBESC_F32
6648 
6649  GPUStaticInst*
6651  {
6652  return new Inst_VOP3__V_CUBETC_F32(&iFmt->iFmt_VOP3A);
6653  } // decode_OPU_VOP3__V_CUBETC_F32
6654 
6655  GPUStaticInst*
6657  {
6658  return new Inst_VOP3__V_CUBEMA_F32(&iFmt->iFmt_VOP3A);
6659  } // decode_OPU_VOP3__V_CUBEMA_F32
6660 
6661  GPUStaticInst*
6663  {
6664  return new Inst_VOP3__V_BFE_U32(&iFmt->iFmt_VOP3A);
6665  } // decode_OPU_VOP3__V_BFE_U32
6666 
6667  GPUStaticInst*
6669  {
6670  return new Inst_VOP3__V_BFE_I32(&iFmt->iFmt_VOP3A);
6671  } // decode_OPU_VOP3__V_BFE_I32
6672 
6673  GPUStaticInst*
6675  {
6676  return new Inst_VOP3__V_BFI_B32(&iFmt->iFmt_VOP3A);
6677  } // decode_OPU_VOP3__V_BFI_B32
6678 
6679  GPUStaticInst*
6681  {
6682  return new Inst_VOP3__V_FMA_F32(&iFmt->iFmt_VOP3A);
6683  } // decode_OPU_VOP3__V_FMA_F32
6684 
6685  GPUStaticInst*
6687  {
6688  return new Inst_VOP3__V_FMA_F64(&iFmt->iFmt_VOP3A);
6689  } // decode_OPU_VOP3__V_FMA_F64
6690 
6691  GPUStaticInst*
6693  {
6694  return new Inst_VOP3__V_LERP_U8(&iFmt->iFmt_VOP3A);
6695  } // decode_OPU_VOP3__V_LERP_U8
6696 
6697  GPUStaticInst*
6699  {
6700  return new Inst_VOP3__V_ALIGNBIT_B32(&iFmt->iFmt_VOP3A);
6701  } // decode_OPU_VOP3__V_ALIGNBIT_B32
6702 
6703  GPUStaticInst*
6705  {
6706  return new Inst_VOP3__V_ALIGNBYTE_B32(&iFmt->iFmt_VOP3A);
6707  } // decode_OPU_VOP3__V_ALIGNBYTE_B32
6708 
6709  GPUStaticInst*
6711  {
6712  return new Inst_VOP3__V_MIN3_F32(&iFmt->iFmt_VOP3A);
6713  } // decode_OPU_VOP3__V_MIN3_F32
6714 
6715  GPUStaticInst*
6717  {
6718  return new Inst_VOP3__V_MIN3_I32(&iFmt->iFmt_VOP3A);
6719  } // decode_OPU_VOP3__V_MIN3_I32
6720 
6721  GPUStaticInst*
6723  {
6724  return new Inst_VOP3__V_MIN3_U32(&iFmt->iFmt_VOP3A);
6725  } // decode_OPU_VOP3__V_MIN3_U32
6726 
6727  GPUStaticInst*
6729  {
6730  return new Inst_VOP3__V_MAX3_F32(&iFmt->iFmt_VOP3A);
6731  } // decode_OPU_VOP3__V_MAX3_F32
6732 
6733  GPUStaticInst*
6735  {
6736  return new Inst_VOP3__V_MAX3_I32(&iFmt->iFmt_VOP3A);
6737  } // decode_OPU_VOP3__V_MAX3_I32
6738 
6739  GPUStaticInst*
6741  {
6742  return new Inst_VOP3__V_MAX3_U32(&iFmt->iFmt_VOP3A);
6743  } // decode_OPU_VOP3__V_MAX3_U32
6744 
6745  GPUStaticInst*
6747  {
6748  return new Inst_VOP3__V_MED3_F32(&iFmt->iFmt_VOP3A);
6749  } // decode_OPU_VOP3__V_MED3_F32
6750 
6751  GPUStaticInst*
6753  {
6754  return new Inst_VOP3__V_MED3_I32(&iFmt->iFmt_VOP3A);
6755  } // decode_OPU_VOP3__V_MED3_I32
6756 
6757  GPUStaticInst*
6759  {
6760  return new Inst_VOP3__V_MED3_U32(&iFmt->iFmt_VOP3A);
6761  } // decode_OPU_VOP3__V_MED3_U32
6762 
6763  GPUStaticInst*
6765  {
6766  return new Inst_VOP3__V_SAD_U8(&iFmt->iFmt_VOP3A);
6767  } // decode_OPU_VOP3__V_SAD_U8
6768 
6769  GPUStaticInst*
6771  {
6772  return new Inst_VOP3__V_SAD_HI_U8(&iFmt->iFmt_VOP3A);
6773  } // decode_OPU_VOP3__V_SAD_HI_U8
6774 
6775  GPUStaticInst*
6777  {
6778  return new Inst_VOP3__V_SAD_U16(&iFmt->iFmt_VOP3A);
6779  } // decode_OPU_VOP3__V_SAD_U16
6780 
6781  GPUStaticInst*
6783  {
6784  return new Inst_VOP3__V_SAD_U32(&iFmt->iFmt_VOP3A);
6785  } // decode_OPU_VOP3__V_SAD_U32
6786 
6787  GPUStaticInst*
6789  {
6790  return new Inst_VOP3__V_CVT_PK_U8_F32(&iFmt->iFmt_VOP3A);
6791  } // decode_OPU_VOP3__V_CVT_PK_U8_F32
6792 
6793  GPUStaticInst*
6795  {
6796  return new Inst_VOP3__V_DIV_FIXUP_F32(&iFmt->iFmt_VOP3A);
6797  } // decode_OPU_VOP3__V_DIV_FIXUP_F32
6798 
6799  GPUStaticInst*
6801  {
6802  return new Inst_VOP3__V_DIV_FIXUP_F64(&iFmt->iFmt_VOP3A);
6803  } // decode_OPU_VOP3__V_DIV_FIXUP_F64
6804 
6805  GPUStaticInst*
6807  {
6808  return new Inst_VOP3__V_DIV_SCALE_F32(&iFmt->iFmt_VOP3B);
6809  } // decode_OPU_VOP3__V_DIV_SCALE_F32
6810 
6811  GPUStaticInst*
6813  {
6814  return new Inst_VOP3__V_DIV_SCALE_F64(&iFmt->iFmt_VOP3B);
6815  } // decode_OPU_VOP3__V_DIV_SCALE_F64
6816 
6817  GPUStaticInst*
6819  {
6820  return new Inst_VOP3__V_DIV_FMAS_F32(&iFmt->iFmt_VOP3A);
6821  } // decode_OPU_VOP3__V_DIV_FMAS_F32
6822 
6823  GPUStaticInst*
6825  {
6826  return new Inst_VOP3__V_DIV_FMAS_F64(&iFmt->iFmt_VOP3A);
6827  } // decode_OPU_VOP3__V_DIV_FMAS_F64
6828 
6829  GPUStaticInst*
6831  {
6832  return new Inst_VOP3__V_MSAD_U8(&iFmt->iFmt_VOP3A);
6833  } // decode_OPU_VOP3__V_MSAD_U8
6834 
6835  GPUStaticInst*
6837  {
6838  return new Inst_VOP3__V_QSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6839  } // decode_OPU_VOP3__V_QSAD_PK_U16_U8
6840 
6841  GPUStaticInst*
6843  {
6844  return new Inst_VOP3__V_MQSAD_PK_U16_U8(&iFmt->iFmt_VOP3A);
6845  } // decode_OPU_VOP3__V_MQSAD_PK_U16_U8
6846 
6847  GPUStaticInst*
6849  {
6850  return new Inst_VOP3__V_MQSAD_U32_U8(&iFmt->iFmt_VOP3A);
6851  } // decode_OPU_VOP3__V_MQSAD_U32_U8
6852 
6853  GPUStaticInst*
6855  {
6856  return new Inst_VOP3__V_MAD_U64_U32(&iFmt->iFmt_VOP3B);
6857  } // decode_OPU_VOP3__V_MAD_U64_U32
6858 
6859  GPUStaticInst*
6861  {
6862  return new Inst_VOP3__V_MAD_I64_I32(&iFmt->iFmt_VOP3B);
6863  } // decode_OPU_VOP3__V_MAD_I64_I32
6864 
6865  GPUStaticInst*
6867  {
6868  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
6869  } // decode_OPU_VOP3__V_MAD_LEGACY_F16
6870 
6871  GPUStaticInst*
6873  {
6874  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
6875  } // decode_OPU_VOP3__V_MAD_LEGACY_U16
6876 
6877  GPUStaticInst*
6879  {
6880  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
6881  } // decode_OPU_VOP3__V_MAD_LEGACY_I16
6882 
6883  GPUStaticInst*
6885  {
6886  return new Inst_VOP3__V_PERM_B32(&iFmt->iFmt_VOP3A);
6887  } // decode_OPU_VOP3__V_PERM_B32
6888 
6889  GPUStaticInst*
6891  {
6892  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
6893  } // decode_OPU_VOP3__V_FMA_LEGACY_F16
6894 
6895  GPUStaticInst*
6897  {
6898  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
6899  } // decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
6900 
6901  GPUStaticInst*
6903  {
6904  return new Inst_VOP3__V_CVT_PKACCUM_U8_F32(&iFmt->iFmt_VOP3A);
6905  } // decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
6906 
6907  GPUStaticInst*
6909  {
6910  fatal("Trying to decode instruction without a class\n");
6911  return nullptr;
6912  }
6913 
6914  GPUStaticInst*
6916  {
6917  fatal("Trying to decode instruction without a class\n");
6918  return nullptr;
6919  }
6920 
6921  GPUStaticInst*
6923  {
6924  return new Inst_VOP3__V_XAD_U32(&iFmt->iFmt_VOP3A);
6925  }
6926 
6927  GPUStaticInst*
6929  {
6930  fatal("Trying to decode instruction without a class\n");
6931  return nullptr;
6932  }
6933 
6934  GPUStaticInst*
6936  {
6937  fatal("Trying to decode instruction without a class\n");
6938  return nullptr;
6939  }
6940 
6941  GPUStaticInst*
6943  {
6944  fatal("Trying to decode instruction without a class\n");
6945  return nullptr;
6946  }
6947 
6948  GPUStaticInst*
6950  {
6951  fatal("Trying to decode instruction without a class\n");
6952  return nullptr;
6953  }
6954 
6955  GPUStaticInst*
6957  {
6958  fatal("Trying to decode instruction without a class\n");
6959  return nullptr;
6960  }
6961 
6962  GPUStaticInst*
6964  {
6965  fatal("Trying to decode instruction without a class\n");
6966  return nullptr;
6967  }
6968 
6969  GPUStaticInst*
6971  {
6972  fatal("Trying to decode instruction without a class\n");
6973  return nullptr;
6974  }
6975 
6976  GPUStaticInst*
6978  {
6979  fatal("Trying to decode instruction without a class\n");
6980  return nullptr;
6981  }
6982 
6983  GPUStaticInst*
6985  {
6986  fatal("Trying to decode instruction without a class\n");
6987  return nullptr;
6988  }
6989 
6990  GPUStaticInst*
6992  {
6993  return new Inst_VOP3__V_LSHL_ADD_U32(&iFmt->iFmt_VOP3A);
6994  }
6995 
6996  GPUStaticInst*
6998  {
6999  return new Inst_VOP3__V_ADD_LSHL_U32(&iFmt->iFmt_VOP3A);
7000  }
7001 
7002  GPUStaticInst*
7004  {
7005  return new Inst_VOP3__V_ADD3_U32(&iFmt->iFmt_VOP3A);
7006  }
7007 
7008  GPUStaticInst*
7010  {
7011  return new Inst_VOP3__V_LSHL_OR_B32(&iFmt->iFmt_VOP3A);
7012  }
7013 
7014  GPUStaticInst*
7016  {
7017  return new Inst_VOP3__V_AND_OR_B32(&iFmt->iFmt_VOP3A);
7018  }
7019 
7020  GPUStaticInst*
7022  {
7023  return new Inst_VOP3__V_OR_B32(&iFmt->iFmt_VOP3A);
7024  }
7025 
7026  GPUStaticInst*
7028  {
7029  return new Inst_VOP3__V_MAD_F16(&iFmt->iFmt_VOP3A);
7030  }
7031 
7032  GPUStaticInst*
7034  {
7035  return new Inst_VOP3__V_MAD_U16(&iFmt->iFmt_VOP3A);
7036  }
7037 
7038  GPUStaticInst*
7040  {
7041  return new Inst_VOP3__V_MAD_I16(&iFmt->iFmt_VOP3A);
7042  }
7043 
7044  GPUStaticInst*
7046  {
7047  return new Inst_VOP3__V_FMA_F16(&iFmt->iFmt_VOP3A);
7048  }
7049 
7050  GPUStaticInst*
7052  {
7053  return new Inst_VOP3__V_DIV_FIXUP_F16(&iFmt->iFmt_VOP3A);
7054  }
7055 
7056  GPUStaticInst*
7058  {
7059  return new Inst_VOP3__V_INTERP_P1_F32(&iFmt->iFmt_VOP3A);
7060  } // decode_OPU_VOP3__V_INTERP_P1_F32
7061 
7062  GPUStaticInst*
7064  {
7065  return new Inst_VOP3__V_INTERP_P2_F32(&iFmt->iFmt_VOP3A);
7066  } // decode_OPU_VOP3__V_INTERP_P2_F32
7067 
7068  GPUStaticInst*
7070  {
7071  return new Inst_VOP3__V_INTERP_MOV_F32(&iFmt->iFmt_VOP3A);
7072  } // decode_OPU_VOP3__V_INTERP_MOV_F32
7073 
7074  GPUStaticInst*
7076  {
7077  return new Inst_VOP3__V_INTERP_P1LL_F16(&iFmt->iFmt_VOP3A);
7078  } // decode_OPU_VOP3__V_INTERP_P1LL_F16
7079 
7080  GPUStaticInst*
7082  {
7083  return new Inst_VOP3__V_INTERP_P1LV_F16(&iFmt->iFmt_VOP3A);
7084  } // decode_OPU_VOP3__V_INTERP_P1LV_F16
7085 
7086  GPUStaticInst*
7088  {
7089  fatal("Trying to decode instruction without a class\n");
7090  return nullptr;
7091  }
7092 
7093  GPUStaticInst*
7095  {
7096  return new Inst_VOP3__V_INTERP_P2_F16(&iFmt->iFmt_VOP3A);
7097  } // decode_OPU_VOP3__V_INTERP_P2_F16
7098 
7099  GPUStaticInst*
7101  {
7102  return new Inst_VOP3__V_ADD_F64(&iFmt->iFmt_VOP3A);
7103  } // decode_OPU_VOP3__V_ADD_F64
7104 
7105  GPUStaticInst*
7107  {
7108  return new Inst_VOP3__V_MUL_F64(&iFmt->iFmt_VOP3A);
7109  } // decode_OPU_VOP3__V_MUL_F64
7110 
7111  GPUStaticInst*
7113  {
7114  return new Inst_VOP3__V_MIN_F64(&iFmt->iFmt_VOP3A);
7115  } // decode_OPU_VOP3__V_MIN_F64
7116 
7117  GPUStaticInst*
7119  {
7120  return new Inst_VOP3__V_MAX_F64(&iFmt->iFmt_VOP3A);
7121  } // decode_OPU_VOP3__V_MAX_F64
7122 
7123  GPUStaticInst*
7125  {
7126  return new Inst_VOP3__V_LDEXP_F64(&iFmt->iFmt_VOP3A);
7127  } // decode_OPU_VOP3__V_LDEXP_F64
7128 
7129  GPUStaticInst*
7131  {
7132  return new Inst_VOP3__V_MUL_LO_U32(&iFmt->iFmt_VOP3A);
7133  } // decode_OPU_VOP3__V_MUL_LO_U32
7134 
7135  GPUStaticInst*
7137  {
7138  return new Inst_VOP3__V_MUL_HI_U32(&iFmt->iFmt_VOP3A);
7139  } // decode_OPU_VOP3__V_MUL_HI_U32
7140 
7141  GPUStaticInst*
7143  {
7144  return new Inst_VOP3__V_MUL_HI_I32(&iFmt->iFmt_VOP3A);
7145  } // decode_OPU_VOP3__V_MUL_HI_I32
7146 
7147  GPUStaticInst*
7149  {
7150  return new Inst_VOP3__V_LDEXP_F32(&iFmt->iFmt_VOP3A);
7151  } // decode_OPU_VOP3__V_LDEXP_F32
7152 
7153  GPUStaticInst*
7155  {
7156  return new Inst_VOP3__V_READLANE_B32(&iFmt->iFmt_VOP3A);
7157  } // decode_OPU_VOP3__V_READLANE_B32
7158 
7159  GPUStaticInst*
7161  {
7162  return new Inst_VOP3__V_WRITELANE_B32(&iFmt->iFmt_VOP3A);
7163  } // decode_OPU_VOP3__V_WRITELANE_B32
7164 
7165  GPUStaticInst*
7167  {
7168  return new Inst_VOP3__V_BCNT_U32_B32(&iFmt->iFmt_VOP3A);
7169  } // decode_OPU_VOP3__V_BCNT_U32_B32
7170 
7171  GPUStaticInst*
7173  {
7174  return new Inst_VOP3__V_MBCNT_LO_U32_B32(&iFmt->iFmt_VOP3A);
7175  } // decode_OPU_VOP3__V_MBCNT_LO_U32_B32
7176 
7177  GPUStaticInst*
7179  {
7180  return new Inst_VOP3__V_MBCNT_HI_U32_B32(&iFmt->iFmt_VOP3A);
7181  } // decode_OPU_VOP3__V_MBCNT_HI_U32_B32
7182 
7183  GPUStaticInst*
7185  {
7186  return new Inst_VOP3__V_LSHLREV_B64(&iFmt->iFmt_VOP3A);
7187  } // decode_OPU_VOP3__V_LSHLREV_B64
7188 
7189  GPUStaticInst*
7191  {
7192  return new Inst_VOP3__V_LSHRREV_B64(&iFmt->iFmt_VOP3A);
7193  } // decode_OPU_VOP3__V_LSHRREV_B64
7194 
7195  GPUStaticInst*
7197  {
7198  return new Inst_VOP3__V_ASHRREV_I64(&iFmt->iFmt_VOP3A);
7199  } // decode_OPU_VOP3__V_ASHRREV_I64
7200 
7201  GPUStaticInst*
7203  {
7204  return new Inst_VOP3__V_TRIG_PREOP_F64(&iFmt->iFmt_VOP3A);
7205  } // decode_OPU_VOP3__V_TRIG_PREOP_F64
7206 
7207  GPUStaticInst*
7209  {
7210  return new Inst_VOP3__V_BFM_B32(&iFmt->iFmt_VOP3A);
7211  } // decode_OPU_VOP3__V_BFM_B32
7212 
7213  GPUStaticInst*
7215  {
7216  return new Inst_VOP3__V_CVT_PKNORM_I16_F32(&iFmt->iFmt_VOP3A);
7217  } // decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
7218 
7219  GPUStaticInst*
7221  {
7222  return new Inst_VOP3__V_CVT_PKNORM_U16_F32(&iFmt->iFmt_VOP3A);
7223  } // decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
7224 
7225  GPUStaticInst*
7227  {
7228  return new Inst_VOP3__V_CVT_PKRTZ_F16_F32(&iFmt->iFmt_VOP3A);
7229  } // decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
7230 
7231  GPUStaticInst*
7233  {
7234  return new Inst_VOP3__V_CVT_PK_U16_U32(&iFmt->iFmt_VOP3A);
7235  } // decode_OPU_VOP3__V_CVT_PK_U16_U32
7236 
7237  GPUStaticInst*
7239  {
7240  return new Inst_VOP3__V_CVT_PK_I16_I32(&iFmt->iFmt_VOP3A);
7241  } // decode_OPU_VOP3__V_CVT_PK_I16_I32
7242 
7243  GPUStaticInst*
7245  {
7246  fatal("Trying to decode instruction without a class\n");
7247  return nullptr;
7248  }
7249 
7250  GPUStaticInst*
7252  {
7253  fatal("Trying to decode instruction without a class\n");
7254  return nullptr;
7255  }
7256 
7257  GPUStaticInst*
7259  {
7260  fatal("Trying to decode instruction without a class\n");
7261  return nullptr;
7262  }
7263 
7264  GPUStaticInst*
7266  {
7267  fatal("Trying to decode instruction without a class\n");
7268  return nullptr;
7269  }
7270 
7271  GPUStaticInst*
7273  {
7274  fatal("Trying to decode instruction without a class\n");
7275  return nullptr;
7276  }
7277 
7278  GPUStaticInst*
7280  {
7281  fatal("Trying to decode instruction without a class\n");
7282  return nullptr;
7283  }
7284 
7285  GPUStaticInst*
7287  {
7288  fatal("Trying to decode instruction without a class\n");
7289  return nullptr;
7290  }
7291 
7292  GPUStaticInst*
7294  {
7295  return new Inst_DS__DS_ADD_U32(&iFmt->iFmt_DS);
7296  } // decode_OP_DS__DS_ADD_U32
7297 
7298  GPUStaticInst*
7300  {
7301  return new Inst_DS__DS_SUB_U32(&iFmt->iFmt_DS);
7302  } // decode_OP_DS__DS_SUB_U32
7303 
7304  GPUStaticInst*
7306  {
7307  return new Inst_DS__DS_RSUB_U32(&iFmt->iFmt_DS);
7308  } // decode_OP_DS__DS_RSUB_U32
7309 
7310  GPUStaticInst*
7312  {
7313  return new Inst_DS__DS_INC_U32(&iFmt->iFmt_DS);
7314  } // decode_OP_DS__DS_INC_U32
7315 
7316  GPUStaticInst*
7318  {
7319  return new Inst_DS__DS_DEC_U32(&iFmt->iFmt_DS);
7320  } // decode_OP_DS__DS_DEC_U32
7321 
7322  GPUStaticInst*
7324  {
7325  return new Inst_DS__DS_MIN_I32(&iFmt->iFmt_DS);
7326  } // decode_OP_DS__DS_MIN_I32
7327 
7328  GPUStaticInst*
7330  {
7331  return new Inst_DS__DS_MAX_I32(&iFmt->iFmt_DS);
7332  } // decode_OP_DS__DS_MAX_I32
7333 
7334  GPUStaticInst*
7336  {
7337  return new Inst_DS__DS_MIN_U32(&iFmt->iFmt_DS);
7338  } // decode_OP_DS__DS_MIN_U32
7339 
7340  GPUStaticInst*
7342  {
7343  return new Inst_DS__DS_MAX_U32(&iFmt->iFmt_DS);
7344  } // decode_OP_DS__DS_MAX_U32
7345 
7346  GPUStaticInst*
7348  {
7349  return new Inst_DS__DS_AND_B32(&iFmt->iFmt_DS);
7350  } // decode_OP_DS__DS_AND_B32
7351 
7352  GPUStaticInst*
7354  {
7355  return new Inst_DS__DS_OR_B32(&iFmt->iFmt_DS);
7356  } // decode_OP_DS__DS_OR_B32
7357 
7358  GPUStaticInst*
7360  {
7361  return new Inst_DS__DS_XOR_B32(&iFmt->iFmt_DS);
7362  } // decode_OP_DS__DS_XOR_B32
7363 
7364  GPUStaticInst*
7366  {
7367  return new Inst_DS__DS_MSKOR_B32(&iFmt->iFmt_DS);
7368  } // decode_OP_DS__DS_MSKOR_B32
7369 
7370  GPUStaticInst*
7372  {
7373  return new Inst_DS__DS_WRITE_B32(&iFmt->iFmt_DS);
7374  } // decode_OP_DS__DS_WRITE_B32
7375 
7376  GPUStaticInst*
7378  {
7379  return new Inst_DS__DS_WRITE2_B32(&iFmt->iFmt_DS);
7380  } // decode_OP_DS__DS_WRITE2_B32
7381 
7382  GPUStaticInst*
7384  {
7385  return new Inst_DS__DS_WRITE2ST64_B32(&iFmt->iFmt_DS);
7386  } // decode_OP_DS__DS_WRITE2ST64_B32
7387 
7388  GPUStaticInst*
7390  {
7391  return new Inst_DS__DS_CMPST_B32(&iFmt->iFmt_DS);
7392  } // decode_OP_DS__DS_CMPST_B32
7393 
7394  GPUStaticInst*
7396  {
7397  return new Inst_DS__DS_CMPST_F32(&iFmt->iFmt_DS);
7398  } // decode_OP_DS__DS_CMPST_F32
7399 
7400  GPUStaticInst*
7402  {
7403  return new Inst_DS__DS_MIN_F32(&iFmt->iFmt_DS);
7404  } // decode_OP_DS__DS_MIN_F32
7405 
7406  GPUStaticInst*
7408  {
7409  return new Inst_DS__DS_MAX_F32(&iFmt->iFmt_DS);
7410  } // decode_OP_DS__DS_MAX_F32
7411 
7412  GPUStaticInst*
7414  {
7415  return new Inst_DS__DS_NOP(&iFmt->iFmt_DS);
7416  } // decode_OP_DS__DS_NOP
7417 
7418  GPUStaticInst*
7420  {
7421  return new Inst_DS__DS_ADD_F32(&iFmt->iFmt_DS);
7422  } // decode_OP_DS__DS_ADD_F32
7423 
7424  GPUStaticInst*
7426  {
7427  fatal("Trying to decode instruction without a class\n");
7428  return nullptr;
7429  }
7430 
7431  GPUStaticInst*
7433  {
7434  return new Inst_DS__DS_WRITE_B8(&iFmt->iFmt_DS);
7435  } // decode_OP_DS__DS_WRITE_B8
7436 
7437  GPUStaticInst*
7439  {
7440  return new Inst_DS__DS_WRITE_B16(&iFmt->iFmt_DS);
7441  } // decode_OP_DS__DS_WRITE_B16
7442 
7443  GPUStaticInst*
7445  {
7446  return new Inst_DS__DS_ADD_RTN_U32(&iFmt->iFmt_DS);
7447  } // decode_OP_DS__DS_ADD_RTN_U32
7448 
7449  GPUStaticInst*
7451  {
7452  return new Inst_DS__DS_SUB_RTN_U32(&iFmt->iFmt_DS);
7453  } // decode_OP_DS__DS_SUB_RTN_U32
7454 
7455  GPUStaticInst*
7457  {
7458  return new Inst_DS__DS_RSUB_RTN_U32(&iFmt->iFmt_DS);
7459  } // decode_OP_DS__DS_RSUB_RTN_U32
7460 
7461  GPUStaticInst*
7463  {
7464  return new Inst_DS__DS_INC_RTN_U32(&iFmt->iFmt_DS);
7465  } // decode_OP_DS__DS_INC_RTN_U32
7466 
7467  GPUStaticInst*
7469  {
7470  return new Inst_DS__DS_DEC_RTN_U32(&iFmt->iFmt_DS);
7471  } // decode_OP_DS__DS_DEC_RTN_U32
7472 
7473  GPUStaticInst*
7475  {
7476  return new Inst_DS__DS_MIN_RTN_I32(&iFmt->iFmt_DS);
7477  } // decode_OP_DS__DS_MIN_RTN_I32
7478 
7479  GPUStaticInst*
7481  {
7482  return new Inst_DS__DS_MAX_RTN_I32(&iFmt->iFmt_DS);
7483  } // decode_OP_DS__DS_MAX_RTN_I32
7484 
7485  GPUStaticInst*
7487  {
7488  return new Inst_DS__DS_MIN_RTN_U32(&iFmt->iFmt_DS);
7489  } // decode_OP_DS__DS_MIN_RTN_U32
7490 
7491  GPUStaticInst*
7493  {
7494  return new Inst_DS__DS_MAX_RTN_U32(&iFmt->iFmt_DS);
7495  } // decode_OP_DS__DS_MAX_RTN_U32
7496 
7497  GPUStaticInst*
7499  {
7500  return new Inst_DS__DS_AND_RTN_B32(&iFmt->iFmt_DS);
7501  } // decode_OP_DS__DS_AND_RTN_B32
7502 
7503  GPUStaticInst*
7505  {
7506  return new Inst_DS__DS_OR_RTN_B32(&iFmt->iFmt_DS);
7507  } // decode_OP_DS__DS_OR_RTN_B32
7508 
7509  GPUStaticInst*
7511  {
7512  return new Inst_DS__DS_XOR_RTN_B32(&iFmt->iFmt_DS);
7513  } // decode_OP_DS__DS_XOR_RTN_B32
7514 
7515  GPUStaticInst*
7517  {
7518  return new Inst_DS__DS_MSKOR_RTN_B32(&iFmt->iFmt_DS);
7519  } // decode_OP_DS__DS_MSKOR_RTN_B32
7520 
7521  GPUStaticInst*
7523  {
7524  return new Inst_DS__DS_WRXCHG_RTN_B32(&iFmt->iFmt_DS);
7525  } // decode_OP_DS__DS_WRXCHG_RTN_B32
7526 
7527  GPUStaticInst*
7529  {
7530  return new Inst_DS__DS_WRXCHG2_RTN_B32(&iFmt->iFmt_DS);
7531  } // decode_OP_DS__DS_WRXCHG2_RTN_B32
7532 
7533  GPUStaticInst*
7535  {
7536  return new Inst_DS__DS_WRXCHG2ST64_RTN_B32(&iFmt->iFmt_DS);
7537  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
7538 
7539  GPUStaticInst*
7541  {
7542  return new Inst_DS__DS_CMPST_RTN_B32(&iFmt->iFmt_DS);
7543  } // decode_OP_DS__DS_CMPST_RTN_B32
7544 
7545  GPUStaticInst*
7547  {
7548  return new Inst_DS__DS_CMPST_RTN_F32(&iFmt->iFmt_DS);
7549  } // decode_OP_DS__DS_CMPST_RTN_F32
7550 
7551  GPUStaticInst*
7553  {
7554  return new Inst_DS__DS_MIN_RTN_F32(&iFmt->iFmt_DS);
7555  } // decode_OP_DS__DS_MIN_RTN_F32
7556 
7557  GPUStaticInst*
7559  {
7560  return new Inst_DS__DS_MAX_RTN_F32(&iFmt->iFmt_DS);
7561  } // decode_OP_DS__DS_MAX_RTN_F32
7562 
7563  GPUStaticInst*
7565  {
7566  return new Inst_DS__DS_WRAP_RTN_B32(&iFmt->iFmt_DS);
7567  } // decode_OP_DS__DS_WRAP_RTN_B32
7568 
7569  GPUStaticInst*
7571  {
7572  return new Inst_DS__DS_ADD_RTN_F32(&iFmt->iFmt_DS);
7573  } // decode_OP_DS__DS_ADD_RTN_F32
7574 
7575  GPUStaticInst*
7577  {
7578  return new Inst_DS__DS_READ_B32(&iFmt->iFmt_DS);
7579  } // decode_OP_DS__DS_READ_B32
7580 
7581  GPUStaticInst*
7583  {
7584  return new Inst_DS__DS_READ2_B32(&iFmt->iFmt_DS);
7585  } // decode_OP_DS__DS_READ2_B32
7586 
7587  GPUStaticInst*
7589  {
7590  return new Inst_DS__DS_READ2ST64_B32(&iFmt->iFmt_DS);
7591  } // decode_OP_DS__DS_READ2ST64_B32
7592 
7593  GPUStaticInst*
7595  {
7596  return new Inst_DS__DS_READ_I8(&iFmt->iFmt_DS);
7597  } // decode_OP_DS__DS_READ_I8
7598 
7599  GPUStaticInst*
7601  {
7602  return new Inst_DS__DS_READ_U8(&iFmt->iFmt_DS);
7603  } // decode_OP_DS__DS_READ_U8
7604 
7605  GPUStaticInst*
7607  {
7608  return new Inst_DS__DS_READ_I16(&iFmt->iFmt_DS);
7609  } // decode_OP_DS__DS_READ_I16
7610 
7611  GPUStaticInst*
7613  {
7614  return new Inst_DS__DS_READ_U16(&iFmt->iFmt_DS);
7615  } // decode_OP_DS__DS_READ_U16
7616 
7617  GPUStaticInst*
7619  {
7620  return new Inst_DS__DS_SWIZZLE_B32(&iFmt->iFmt_DS);
7621  } // decode_OP_DS__DS_SWIZZLE_B32
7622 
7623  GPUStaticInst*
7625  {
7626  return new Inst_DS__DS_PERMUTE_B32(&iFmt->iFmt_DS);
7627  } // decode_OP_DS__DS_PERMUTE_B32
7628 
7629  GPUStaticInst*
7631  {
7632  return new Inst_DS__DS_BPERMUTE_B32(&iFmt->iFmt_DS);
7633  } // decode_OP_DS__DS_BPERMUTE_B32
7634 
7635  GPUStaticInst*
7637  {
7638  return new Inst_DS__DS_ADD_U64(&iFmt->iFmt_DS);
7639  } // decode_OP_DS__DS_ADD_U64
7640 
7641  GPUStaticInst*
7643  {
7644  return new Inst_DS__DS_SUB_U64(&iFmt->iFmt_DS);
7645  } // decode_OP_DS__DS_SUB_U64
7646 
7647  GPUStaticInst*
7649  {
7650  return new Inst_DS__DS_RSUB_U64(&iFmt->iFmt_DS);
7651  } // decode_OP_DS__DS_RSUB_U64
7652 
7653  GPUStaticInst*
7655  {
7656  return new Inst_DS__DS_INC_U64(&iFmt->iFmt_DS);
7657  } // decode_OP_DS__DS_INC_U64
7658 
7659  GPUStaticInst*
7661  {
7662  return new Inst_DS__DS_DEC_U64(&iFmt->iFmt_DS);
7663  } // decode_OP_DS__DS_DEC_U64
7664 
7665  GPUStaticInst*
7667  {
7668  return new Inst_DS__DS_MIN_I64(&iFmt->iFmt_DS);
7669  } // decode_OP_DS__DS_MIN_I64
7670 
7671  GPUStaticInst*
7673  {
7674  return new Inst_DS__DS_MAX_I64(&iFmt->iFmt_DS);
7675  } // decode_OP_DS__DS_MAX_I64
7676 
7677  GPUStaticInst*
7679  {
7680  return new Inst_DS__DS_MIN_U64(&iFmt->iFmt_DS);
7681  } // decode_OP_DS__DS_MIN_U64
7682 
7683  GPUStaticInst*
7685  {
7686  return new Inst_DS__DS_MAX_U64(&iFmt->iFmt_DS);
7687  } // decode_OP_DS__DS_MAX_U64
7688 
7689  GPUStaticInst*
7691  {
7692  return new Inst_DS__DS_AND_B64(&iFmt->iFmt_DS);
7693  } // decode_OP_DS__DS_AND_B64
7694 
7695  GPUStaticInst*
7697  {
7698  return new Inst_DS__DS_OR_B64(&iFmt->iFmt_DS);
7699  } // decode_OP_DS__DS_OR_B64
7700 
7701  GPUStaticInst*
7703  {
7704  return new Inst_DS__DS_XOR_B64(&iFmt->iFmt_DS);
7705  } // decode_OP_DS__DS_XOR_B64
7706 
7707  GPUStaticInst*
7709  {
7710  return new Inst_DS__DS_MSKOR_B64(&iFmt->iFmt_DS);
7711  } // decode_OP_DS__DS_MSKOR_B64
7712 
7713  GPUStaticInst*
7715  {
7716  return new Inst_DS__DS_WRITE_B64(&iFmt->iFmt_DS);
7717  } // decode_OP_DS__DS_WRITE_B64
7718 
7719  GPUStaticInst*
7721  {
7722  return new Inst_DS__DS_WRITE2_B64(&iFmt->iFmt_DS);
7723  } // decode_OP_DS__DS_WRITE2_B64
7724 
7725  GPUStaticInst*
7727  {
7728  return new Inst_DS__DS_WRITE2ST64_B64(&iFmt->iFmt_DS);
7729  } // decode_OP_DS__DS_WRITE2ST64_B64
7730 
7731  GPUStaticInst*
7733  {
7734  return new Inst_DS__DS_CMPST_B64(&iFmt->iFmt_DS);
7735  } // decode_OP_DS__DS_CMPST_B64
7736 
7737  GPUStaticInst*
7739  {
7740  return new Inst_DS__DS_CMPST_F64(&iFmt->iFmt_DS);
7741  } // decode_OP_DS__DS_CMPST_F64
7742 
7743  GPUStaticInst*
7745  {
7746  return new Inst_DS__DS_MIN_F64(&iFmt->iFmt_DS);
7747  } // decode_OP_DS__DS_MIN_F64
7748 
7749  GPUStaticInst*
7751  {
7752  return new Inst_DS__DS_MAX_F64(&iFmt->iFmt_DS);
7753  } // decode_OP_DS__DS_MAX_F64
7754 
7755  GPUStaticInst*
7757  {
7758  return new Inst_DS__DS_WRITE_B8_D16_HI(&iFmt->iFmt_DS);
7759  }
7760 
7761  GPUStaticInst*
7763  {
7764  fatal("Trying to decode instruction without a class\n");
7765  return nullptr;
7766  }
7767 
7768  GPUStaticInst*
7770  {
7771  fatal("Trying to decode instruction without a class\n");
7772  return nullptr;
7773  }
7774 
7775  GPUStaticInst*
7777  {
7778  fatal("Trying to decode instruction without a class\n");
7779  return nullptr;
7780  }
7781 
7782  GPUStaticInst*
7784  {
7785  fatal("Trying to decode instruction without a class\n");
7786  return nullptr;
7787  }
7788 
7789  GPUStaticInst*
7791  {
7792  fatal("Trying to decode instruction without a class\n");
7793  return nullptr;
7794  }
7795 
7796  GPUStaticInst*
7798  {
7799  fatal("Trying to decode instruction without a class\n");
7800  return nullptr;
7801  }
7802 
7803  GPUStaticInst*
7805  {
7806  fatal("Trying to decode instruction without a class\n");
7807  return nullptr;
7808  }
7809 
7810  GPUStaticInst*
7812  {
7813  return new Inst_DS__DS_ADD_RTN_U64(&iFmt->iFmt_DS);
7814  } // decode_OP_DS__DS_ADD_RTN_U64
7815 
7816  GPUStaticInst*
7818  {
7819  return new Inst_DS__DS_SUB_RTN_U64(&iFmt->iFmt_DS);
7820  } // decode_OP_DS__DS_SUB_RTN_U64
7821 
7822  GPUStaticInst*
7824  {
7825  return new Inst_DS__DS_RSUB_RTN_U64(&iFmt->iFmt_DS);
7826  } // decode_OP_DS__DS_RSUB_RTN_U64
7827 
7828  GPUStaticInst*
7830  {
7831  return new Inst_DS__DS_INC_RTN_U64(&iFmt->iFmt_DS);
7832  } // decode_OP_DS__DS_INC_RTN_U64
7833 
7834  GPUStaticInst*
7836  {
7837  return new Inst_DS__DS_DEC_RTN_U64(&iFmt->iFmt_DS);
7838  } // decode_OP_DS__DS_DEC_RTN_U64
7839 
7840  GPUStaticInst*
7842  {
7843  return new Inst_DS__DS_MIN_RTN_I64(&iFmt->iFmt_DS);
7844  } // decode_OP_DS__DS_MIN_RTN_I64
7845 
7846  GPUStaticInst*
7848  {
7849  return new Inst_DS__DS_MAX_RTN_I64(&iFmt->iFmt_DS);
7850  } // decode_OP_DS__DS_MAX_RTN_I64
7851 
7852  GPUStaticInst*
7854  {
7855  return new Inst_DS__DS_MIN_RTN_U64(&iFmt->iFmt_DS);
7856  } // decode_OP_DS__DS_MIN_RTN_U64
7857 
7858  GPUStaticInst*
7860  {
7861  return new Inst_DS__DS_MAX_RTN_U64(&iFmt->iFmt_DS);
7862  } // decode_OP_DS__DS_MAX_RTN_U64
7863 
7864  GPUStaticInst*
7866  {
7867  return new Inst_DS__DS_AND_RTN_B64(&iFmt->iFmt_DS);
7868  } // decode_OP_DS__DS_AND_RTN_B64
7869 
7870  GPUStaticInst*
7872  {
7873  return new Inst_DS__DS_OR_RTN_B64(&iFmt->iFmt_DS);
7874  } // decode_OP_DS__DS_OR_RTN_B64
7875 
7876  GPUStaticInst*
7878  {
7879  return new Inst_DS__DS_XOR_RTN_B64(&iFmt->iFmt_DS);
7880  } // decode_OP_DS__DS_XOR_RTN_B64
7881 
7882  GPUStaticInst*
7884  {
7885  return new Inst_DS__DS_MSKOR_RTN_B64(&iFmt->iFmt_DS);
7886  } // decode_OP_DS__DS_MSKOR_RTN_B64
7887 
7888  GPUStaticInst*
7890  {
7891  return new Inst_DS__DS_WRXCHG_RTN_B64(&iFmt->iFmt_DS);
7892  } // decode_OP_DS__DS_WRXCHG_RTN_B64
7893 
7894  GPUStaticInst*
7896  {
7897  return new Inst_DS__DS_WRXCHG2_RTN_B64(&iFmt->iFmt_DS);
7898  } // decode_OP_DS__DS_WRXCHG2_RTN_B64
7899 
7900  GPUStaticInst*
7902  {
7903  return new Inst_DS__DS_WRXCHG2ST64_RTN_B64(&iFmt->iFmt_DS);
7904  } // decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
7905 
7906  GPUStaticInst*
7908  {
7909  return new Inst_DS__DS_CMPST_RTN_B64(&iFmt->iFmt_DS);
7910  } // decode_OP_DS__DS_CMPST_RTN_B64
7911 
7912  GPUStaticInst*
7914  {
7915  return new Inst_DS__DS_CMPST_RTN_F64(&iFmt->iFmt_DS);
7916  } // decode_OP_DS__DS_CMPST_RTN_F64
7917 
7918  GPUStaticInst*
7920  {
7921  return new Inst_DS__DS_MIN_RTN_F64(&iFmt->iFmt_DS);
7922  } // decode_OP_DS__DS_MIN_RTN_F64
7923 
7924  GPUStaticInst*
7926  {
7927  return new Inst_DS__DS_MAX_RTN_F64(&iFmt->iFmt_DS);
7928  } // decode_OP_DS__DS_MAX_RTN_F64
7929 
7930  GPUStaticInst*
7932  {
7933  return new Inst_DS__DS_READ_B64(&iFmt->iFmt_DS);
7934  } // decode_OP_DS__DS_READ_B64
7935 
7936  GPUStaticInst*
7938  {
7939  return new Inst_DS__DS_READ2_B64(&iFmt->iFmt_DS);
7940  } // decode_OP_DS__DS_READ2_B64
7941 
7942  GPUStaticInst*
7944  {
7945  return new Inst_DS__DS_READ2ST64_B64(&iFmt->iFmt_DS);
7946  } // decode_OP_DS__DS_READ2ST64_B64
7947 
7948  GPUStaticInst*
7950  {
7951  return new Inst_DS__DS_CONDXCHG32_RTN_B64(&iFmt->iFmt_DS);
7952  } // decode_OP_DS__DS_CONDXCHG32_RTN_B64
7953 
7954  GPUStaticInst*
7956  {
7957  return new Inst_DS__DS_ADD_SRC2_U32(&iFmt->iFmt_DS);
7958  } // decode_OP_DS__DS_ADD_SRC2_U32
7959 
7960  GPUStaticInst*
7962  {
7963  return new Inst_DS__DS_SUB_SRC2_U32(&iFmt->iFmt_DS);
7964  } // decode_OP_DS__DS_SUB_SRC2_U32
7965 
7966  GPUStaticInst*
7968  {
7969  return new Inst_DS__DS_RSUB_SRC2_U32(&iFmt->iFmt_DS);
7970  } // decode_OP_DS__DS_RSUB_SRC2_U32
7971 
7972  GPUStaticInst*
7974  {
7975  return new Inst_DS__DS_INC_SRC2_U32(&iFmt->iFmt_DS);
7976  } // decode_OP_DS__DS_INC_SRC2_U32
7977 
7978  GPUStaticInst*
7980  {
7981  return new Inst_DS__DS_DEC_SRC2_U32(&iFmt->iFmt_DS);
7982  } // decode_OP_DS__DS_DEC_SRC2_U32
7983 
7984  GPUStaticInst*
7986  {
7987  return new Inst_DS__DS_MIN_SRC2_I32(&iFmt->iFmt_DS);
7988  } // decode_OP_DS__DS_MIN_SRC2_I32
7989 
7990  GPUStaticInst*
7992  {
7993  return new Inst_DS__DS_MAX_SRC2_I32(&iFmt->iFmt_DS);
7994  } // decode_OP_DS__DS_MAX_SRC2_I32
7995 
7996  GPUStaticInst*
7998  {
7999  return new Inst_DS__DS_MIN_SRC2_U32(&iFmt->iFmt_DS);
8000  } // decode_OP_DS__DS_MIN_SRC2_U32
8001 
8002  GPUStaticInst*
8004  {
8005  return new Inst_DS__DS_MAX_SRC2_U32(&iFmt->iFmt_DS);
8006  } // decode_OP_DS__DS_MAX_SRC2_U32
8007 
8008  GPUStaticInst*
8010  {
8011  return new Inst_DS__DS_AND_SRC2_B32(&iFmt->iFmt_DS);
8012  } // decode_OP_DS__DS_AND_SRC2_B32
8013 
8014  GPUStaticInst*
8016  {
8017  return new Inst_DS__DS_OR_SRC2_B32(&iFmt->iFmt_DS);
8018  } // decode_OP_DS__DS_OR_SRC2_B32
8019 
8020  GPUStaticInst*
8022  {
8023  return new Inst_DS__DS_XOR_SRC2_B32(&iFmt->iFmt_DS);
8024  } // decode_OP_DS__DS_XOR_SRC2_B32
8025 
8026  GPUStaticInst*
8028  {
8029  return new Inst_DS__DS_WRITE_SRC2_B32(&iFmt->iFmt_DS);
8030  } // decode_OP_DS__DS_WRITE_SRC2_B32
8031 
8032  GPUStaticInst*
8034  {
8035  return new Inst_DS__DS_MIN_SRC2_F32(&iFmt->iFmt_DS);
8036  } // decode_OP_DS__DS_MIN_SRC2_F32
8037 
8038  GPUStaticInst*
8040  {
8041  return new Inst_DS__DS_MAX_SRC2_F32(&iFmt->iFmt_DS);
8042  } // decode_OP_DS__DS_MAX_SRC2_F32
8043 
8044  GPUStaticInst*
8046  {
8047  return new Inst_DS__DS_ADD_SRC2_F32(&iFmt->iFmt_DS);
8048  } // decode_OP_DS__DS_ADD_SRC2_F32
8049 
8050  GPUStaticInst*
8052  {
8053  return new Inst_DS__DS_GWS_SEMA_RELEASE_ALL(&iFmt->iFmt_DS);
8054  } // decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
8055 
8056  GPUStaticInst*
8058  {
8059  return new Inst_DS__DS_GWS_INIT(&iFmt->iFmt_DS);
8060  } // decode_OP_DS__DS_GWS_INIT
8061 
8062  GPUStaticInst*
8064  {
8065  return new Inst_DS__DS_GWS_SEMA_V(&iFmt->iFmt_DS);
8066  } // decode_OP_DS__DS_GWS_SEMA_V
8067 
8068  GPUStaticInst*
8070  {
8071  return new Inst_DS__DS_GWS_SEMA_BR(&iFmt->iFmt_DS);
8072  } // decode_OP_DS__DS_GWS_SEMA_BR
8073 
8074  GPUStaticInst*
8076  {
8077  return new Inst_DS__DS_GWS_SEMA_P(&iFmt->iFmt_DS);
8078  } // decode_OP_DS__DS_GWS_SEMA_P
8079 
8080  GPUStaticInst*
8082  {
8083  return new Inst_DS__DS_GWS_BARRIER(&iFmt->iFmt_DS);
8084  } // decode_OP_DS__DS_GWS_BARRIER
8085 
8086  GPUStaticInst*
8088  {
8089  fatal("Trying to decode instruction without a class\n");
8090  return nullptr;
8091  }
8092 
8093  GPUStaticInst*
8095  {
8096  return new Inst_DS__DS_CONSUME(&iFmt->iFmt_DS);
8097  } // decode_OP_DS__DS_CONSUME
8098 
8099  GPUStaticInst*
8101  {
8102  return new Inst_DS__DS_APPEND(&iFmt->iFmt_DS);
8103  } // decode_OP_DS__DS_APPEND
8104 
8105  GPUStaticInst*
8107  {
8108  return new Inst_DS__DS_ORDERED_COUNT(&iFmt->iFmt_DS);
8109  } // decode_OP_DS__DS_ORDERED_COUNT
8110 
8111  GPUStaticInst*
8113  {
8114  return new Inst_DS__DS_ADD_SRC2_U64(&iFmt->iFmt_DS);
8115  } // decode_OP_DS__DS_ADD_SRC2_U64
8116 
8117  GPUStaticInst*
8119  {
8120  return new Inst_DS__DS_SUB_SRC2_U64(&iFmt->iFmt_DS);
8121  } // decode_OP_DS__DS_SUB_SRC2_U64
8122 
8123  GPUStaticInst*
8125  {
8126  return new Inst_DS__DS_RSUB_SRC2_U64(&iFmt->iFmt_DS);
8127  } // decode_OP_DS__DS_RSUB_SRC2_U64
8128 
8129  GPUStaticInst*
8131  {
8132  return new Inst_DS__DS_INC_SRC2_U64(&iFmt->iFmt_DS);
8133  } // decode_OP_DS__DS_INC_SRC2_U64
8134 
8135  GPUStaticInst*
8137  {
8138  return new Inst_DS__DS_DEC_SRC2_U64(&iFmt->iFmt_DS);
8139  } // decode_OP_DS__DS_DEC_SRC2_U64
8140 
8141  GPUStaticInst*
8143  {
8144  return new Inst_DS__DS_MIN_SRC2_I64(&iFmt->iFmt_DS);
8145  } // decode_OP_DS__DS_MIN_SRC2_I64
8146 
8147  GPUStaticInst*
8149  {
8150  return new Inst_DS__DS_MAX_SRC2_I64(&iFmt->iFmt_DS);
8151  } // decode_OP_DS__DS_MAX_SRC2_I64
8152 
8153  GPUStaticInst*
8155  {
8156  return new Inst_DS__DS_MIN_SRC2_U64(&iFmt->iFmt_DS);
8157  } // decode_OP_DS__DS_MIN_SRC2_U64
8158 
8159  GPUStaticInst*
8161  {
8162  return new Inst_DS__DS_MAX_SRC2_U64(&iFmt->iFmt_DS);
8163  } // decode_OP_DS__DS_MAX_SRC2_U64
8164 
8165  GPUStaticInst*
8167  {
8168  return new Inst_DS__DS_AND_SRC2_B64(&iFmt->iFmt_DS);
8169  } // decode_OP_DS__DS_AND_SRC2_B64
8170 
8171  GPUStaticInst*
8173  {
8174  return new Inst_DS__DS_OR_SRC2_B64(&iFmt->iFmt_DS);
8175  } // decode_OP_DS__DS_OR_SRC2_B64
8176 
8177  GPUStaticInst*
8179  {
8180  return new Inst_DS__DS_XOR_SRC2_B64(&iFmt->iFmt_DS);
8181  } // decode_OP_DS__DS_XOR_SRC2_B64
8182 
8183  GPUStaticInst*
8185  {
8186  return new Inst_DS__DS_WRITE_SRC2_B64(&iFmt->iFmt_DS);
8187  } // decode_OP_DS__DS_WRITE_SRC2_B64
8188 
8189  GPUStaticInst*
8191  {
8192  return new Inst_DS__DS_MIN_SRC2_F64(&iFmt->iFmt_DS);
8193  } // decode_OP_DS__DS_MIN_SRC2_F64
8194 
8195  GPUStaticInst*
8197  {
8198  return new Inst_DS__DS_MAX_SRC2_F64(&iFmt->iFmt_DS);
8199  } // decode_OP_DS__DS_MAX_SRC2_F64
8200 
8201  GPUStaticInst*
8203  {
8204  return new Inst_DS__DS_WRITE_B96(&iFmt->iFmt_DS);
8205  } // decode_OP_DS__DS_WRITE_B96
8206 
8207  GPUStaticInst*
8209  {
8210  return new Inst_DS__DS_WRITE_B128(&iFmt->iFmt_DS);
8211  } // decode_OP_DS__DS_WRITE_B128
8212 
8213  GPUStaticInst*
8215  {
8216  return new Inst_DS__DS_READ_B96(&iFmt->iFmt_DS);
8217  } // decode_OP_DS__DS_READ_B96
8218 
8219  GPUStaticInst*
8221  {
8222  return new Inst_DS__DS_READ_B128(&iFmt->iFmt_DS);
8223  } // decode_OP_DS__DS_READ_B128
8224 
8225  GPUStaticInst*
8227  {
8228  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8229  } // decode_OP_FLAT__FLAT_LOAD_UBYTE
8230 
8231  GPUStaticInst*
8233  {
8234  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8235  } // decode_OP_FLAT__FLAT_LOAD_SBYTE
8236 
8237  GPUStaticInst*
8239  {
8240  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8241  } // decode_OP_FLAT__FLAT_LOAD_USHORT
8242 
8243  GPUStaticInst*
8245  {
8246  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8247  } // decode_OP_FLAT__FLAT_LOAD_SSHORT
8248 
8249  GPUStaticInst*
8251  {
8252  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8253  } // decode_OP_FLAT__FLAT_LOAD_DWORD
8254 
8255  GPUStaticInst*
8257  {
8258  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8259  } // decode_OP_FLAT__FLAT_LOAD_DWORDX2
8260 
8261  GPUStaticInst*
8263  {
8264  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8265  } // decode_OP_FLAT__FLAT_LOAD_DWORDX3
8266 
8267  GPUStaticInst*
8269  {
8270  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8271  } // decode_OP_FLAT__FLAT_LOAD_DWORDX4
8272 
8273  GPUStaticInst*
8275  {
8276  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8277  } // decode_OP_FLAT__FLAT_STORE_BYTE
8278 
8279  GPUStaticInst*
8281  {
8282  fatal("Trying to decode instruction without a class\n");
8283  return nullptr;
8284  }
8285 
8286  GPUStaticInst*
8288  {
8289  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8290  } // decode_OP_FLAT__FLAT_STORE_SHORT
8291 
8292  GPUStaticInst*
8294  {
8295  fatal("Trying to decode instruction without a class\n");
8296  return nullptr;
8297  }
8298 
8299  GPUStaticInst*
8301  {
8302  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8303  } // decode_OP_FLAT__FLAT_STORE_DWORD
8304 
8305  GPUStaticInst*
8307  {
8308  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8309  } // decode_OP_FLAT__FLAT_STORE_DWORDX2
8310 
8311  GPUStaticInst*
8313  {
8314  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8315  } // decode_OP_FLAT__FLAT_STORE_DWORDX3
8316 
8317  GPUStaticInst*
8319  {
8320  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8321  } // decode_OP_FLAT__FLAT_STORE_DWORDX4
8322 
8323  GPUStaticInst*
8325  {
8326  fatal("Trying to decode instruction without a class\n");
8327  return nullptr;
8328  }
8329 
8330  GPUStaticInst*
8332  {
8333  fatal("Trying to decode instruction without a class\n");
8334  return nullptr;
8335  }
8336 
8337  GPUStaticInst*
8339  {
8340  fatal("Trying to decode instruction without a class\n");
8341  return nullptr;
8342  }
8343 
8344  GPUStaticInst*
8346  {
8347  fatal("Trying to decode instruction without a class\n");
8348  return nullptr;
8349  }
8350 
8351  GPUStaticInst*
8353  {
8354  fatal("Trying to decode instruction without a class\n");
8355  return nullptr;
8356  }
8357 
8358  GPUStaticInst*
8360  {
8361  fatal("Trying to decode instruction without a class\n");
8362  return nullptr;
8363  }
8364 
8365  GPUStaticInst*
8367  {
8368  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8369  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP
8370 
8371  GPUStaticInst*
8373  {
8374  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8375  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
8376 
8377  GPUStaticInst*
8379  {
8380  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8381  } // decode_OP_FLAT__FLAT_ATOMIC_ADD
8382 
8383  GPUStaticInst*
8385  {
8386  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8387  } // decode_OP_FLAT__FLAT_ATOMIC_SUB
8388 
8389  GPUStaticInst*
8391  {
8392  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8393  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN
8394 
8395  GPUStaticInst*
8397  {
8398  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8399  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN
8400 
8401  GPUStaticInst*
8403  {
8404  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8405  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX
8406 
8407  GPUStaticInst*
8409  {
8410  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8411  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX
8412 
8413  GPUStaticInst*
8415  {
8416  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8417  } // decode_OP_FLAT__FLAT_ATOMIC_AND
8418 
8419  GPUStaticInst*
8421  {
8422  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8423  } // decode_OP_FLAT__FLAT_ATOMIC_OR
8424 
8425  GPUStaticInst*
8427  {
8428  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8429  } // decode_OP_FLAT__FLAT_ATOMIC_XOR
8430 
8431  GPUStaticInst*
8433  {
8434  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8435  } // decode_OP_FLAT__FLAT_ATOMIC_INC
8436 
8437  GPUStaticInst*
8439  {
8440  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8441  } // decode_OP_FLAT__FLAT_ATOMIC_DEC
8442 
8443  GPUStaticInst*
8445  {
8446  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8447  } // decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
8448 
8449  GPUStaticInst*
8451  {
8452  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8453  } // decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
8454 
8455  GPUStaticInst*
8457  {
8458  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8459  } // decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
8460 
8461  GPUStaticInst*
8463  {
8464  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8465  } // decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
8466 
8467  GPUStaticInst*
8469  {
8470  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8471  } // decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
8472 
8473  GPUStaticInst*
8475  {
8476  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8477  } // decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
8478 
8479  GPUStaticInst*
8481  {
8482  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8483  } // decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
8484 
8485  GPUStaticInst*
8487  {
8488  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8489  } // decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
8490 
8491  GPUStaticInst*
8493  {
8494  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8495  } // decode_OP_FLAT__FLAT_ATOMIC_AND_X2
8496 
8497  GPUStaticInst*
8499  {
8500  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8501  } // decode_OP_FLAT__FLAT_ATOMIC_OR_X2
8502 
8503  GPUStaticInst*
8505  {
8506  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8507  } // decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
8508 
8509  GPUStaticInst*
8511  {
8512  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8513  } // decode_OP_FLAT__FLAT_ATOMIC_INC_X2
8514 
8515  GPUStaticInst*
8517  {
8518  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8519  } // decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
8520 
8521  GPUStaticInst*
8523  {
8524  return new Inst_FLAT__FLAT_LOAD_UBYTE(&iFmt->iFmt_FLAT);
8525  }
8526 
8527  GPUStaticInst*
8529  {
8530  return new Inst_FLAT__FLAT_LOAD_SBYTE(&iFmt->iFmt_FLAT);
8531  }
8532 
8533  GPUStaticInst*
8535  {
8536  return new Inst_FLAT__FLAT_LOAD_USHORT(&iFmt->iFmt_FLAT);
8537  }
8538 
8539  GPUStaticInst*
8541  {
8542  return new Inst_FLAT__FLAT_LOAD_SSHORT(&iFmt->iFmt_FLAT);
8543  }
8544 
8545  GPUStaticInst*
8547  {
8548  return new Inst_FLAT__FLAT_LOAD_DWORD(&iFmt->iFmt_FLAT);
8549  }
8550 
8551  GPUStaticInst*
8553  {
8554  return new Inst_FLAT__FLAT_LOAD_DWORDX2(&iFmt->iFmt_FLAT);
8555  }
8556 
8557  GPUStaticInst*
8559  {
8560  return new Inst_FLAT__FLAT_LOAD_DWORDX3(&iFmt->iFmt_FLAT);
8561  }
8562 
8563  GPUStaticInst*
8565  {
8566  return new Inst_FLAT__FLAT_LOAD_DWORDX4(&iFmt->iFmt_FLAT);
8567  }
8568 
8569  GPUStaticInst*
8571  {
8572  return new Inst_FLAT__FLAT_STORE_BYTE(&iFmt->iFmt_FLAT);
8573  }
8574 
8575  GPUStaticInst*
8577  {
8578  fatal("Trying to decode instruction without a class\n");
8579  return nullptr;
8580  }
8581 
8582  GPUStaticInst*
8584  {
8585  return new Inst_FLAT__FLAT_STORE_SHORT(&iFmt->iFmt_FLAT);
8586  }
8587 
8588  GPUStaticInst*
8590  {
8591  fatal("Trying to decode instruction without a class\n");
8592  return nullptr;
8593  }
8594 
8595  GPUStaticInst*
8597  {
8598  return new Inst_FLAT__FLAT_STORE_DWORD(&iFmt->iFmt_FLAT);
8599  return nullptr;
8600  }
8601 
8602  GPUStaticInst*
8604  {
8605  return new Inst_FLAT__FLAT_STORE_DWORDX2(&iFmt->iFmt_FLAT);
8606  }
8607 
8608  GPUStaticInst*
8610  {
8611  return new Inst_FLAT__FLAT_STORE_DWORDX3(&iFmt->iFmt_FLAT);
8612  }
8613 
8614  GPUStaticInst*
8616  {
8617  return new Inst_FLAT__FLAT_STORE_DWORDX4(&iFmt->iFmt_FLAT);
8618  }
8619 
8620  GPUStaticInst*
8622  {
8623  fatal("Trying to decode instruction without a class\n");
8624  return nullptr;
8625  }
8626 
8627  GPUStaticInst*
8629  {
8630  fatal("Trying to decode instruction without a class\n");
8631  return nullptr;
8632  }
8633 
8634  GPUStaticInst*
8636  {
8637  fatal("Trying to decode instruction without a class\n");
8638  return nullptr;
8639  }
8640 
8641  GPUStaticInst*
8643  {
8644  fatal("Trying to decode instruction without a class\n");
8645  return nullptr;
8646  }
8647 
8648  GPUStaticInst*
8650  {
8651  fatal("Trying to decode instruction without a class\n");
8652  return nullptr;
8653  }
8654 
8655  GPUStaticInst*
8657  {
8658  fatal("Trying to decode instruction without a class\n");
8659  return nullptr;
8660  }
8661 
8662  GPUStaticInst*
8664  {
8665  return new Inst_FLAT__FLAT_ATOMIC_SWAP(&iFmt->iFmt_FLAT);
8666  }
8667 
8668  GPUStaticInst*
8670  {
8671  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP(&iFmt->iFmt_FLAT);
8672  }
8673 
8674  GPUStaticInst*
8676  {
8677  return new Inst_FLAT__FLAT_ATOMIC_ADD(&iFmt->iFmt_FLAT);
8678  }
8679 
8680  GPUStaticInst*
8682  {
8683  return new Inst_FLAT__FLAT_ATOMIC_SUB(&iFmt->iFmt_FLAT);
8684  }
8685 
8686  GPUStaticInst*
8688  {
8689  return new Inst_FLAT__FLAT_ATOMIC_SMIN(&iFmt->iFmt_FLAT);
8690  }
8691 
8692  GPUStaticInst*
8694  {
8695  return new Inst_FLAT__FLAT_ATOMIC_UMIN(&iFmt->iFmt_FLAT);
8696  }
8697 
8698  GPUStaticInst*
8700  {
8701  return new Inst_FLAT__FLAT_ATOMIC_SMAX(&iFmt->iFmt_FLAT);
8702  }
8703 
8704  GPUStaticInst*
8706  {
8707  return new Inst_FLAT__FLAT_ATOMIC_UMAX(&iFmt->iFmt_FLAT);
8708  }
8709 
8710  GPUStaticInst*
8712  {
8713  return new Inst_FLAT__FLAT_ATOMIC_AND(&iFmt->iFmt_FLAT);
8714  }
8715 
8716  GPUStaticInst*
8718  {
8719  return new Inst_FLAT__FLAT_ATOMIC_OR(&iFmt->iFmt_FLAT);
8720  }
8721 
8722  GPUStaticInst*
8724  {
8725  return new Inst_FLAT__FLAT_ATOMIC_XOR(&iFmt->iFmt_FLAT);
8726  }
8727 
8728  GPUStaticInst*
8730  {
8731  return new Inst_FLAT__FLAT_ATOMIC_INC(&iFmt->iFmt_FLAT);
8732  }
8733 
8734  GPUStaticInst*
8736  {
8737  return new Inst_FLAT__FLAT_ATOMIC_DEC(&iFmt->iFmt_FLAT);
8738  }
8739 
8740  GPUStaticInst*
8742  {
8743  return new Inst_FLAT__FLAT_ATOMIC_SWAP_X2(&iFmt->iFmt_FLAT);
8744  }
8745 
8746  GPUStaticInst*
8748  {
8749  return new Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2(&iFmt->iFmt_FLAT);
8750  }
8751 
8752  GPUStaticInst*
8754  {
8755  return new Inst_FLAT__FLAT_ATOMIC_ADD_X2(&iFmt->iFmt_FLAT);
8756  }
8757 
8758  GPUStaticInst*
8760  {
8761  return new Inst_FLAT__FLAT_ATOMIC_SUB_X2(&iFmt->iFmt_FLAT);
8762  }
8763 
8764  GPUStaticInst*
8766  {
8767  return new Inst_FLAT__FLAT_ATOMIC_SMIN_X2(&iFmt->iFmt_FLAT);
8768  }
8769 
8770  GPUStaticInst*
8772  {
8773  return new Inst_FLAT__FLAT_ATOMIC_UMIN_X2(&iFmt->iFmt_FLAT);
8774  }
8775 
8776  GPUStaticInst*
8778  {
8779  return new Inst_FLAT__FLAT_ATOMIC_SMAX_X2(&iFmt->iFmt_FLAT);
8780  }
8781 
8782  GPUStaticInst*
8784  {
8785  return new Inst_FLAT__FLAT_ATOMIC_UMAX_X2(&iFmt->iFmt_FLAT);
8786  }
8787 
8788  GPUStaticInst*
8790  {
8791  return new Inst_FLAT__FLAT_ATOMIC_AND_X2(&iFmt->iFmt_FLAT);
8792  }
8793 
8794  GPUStaticInst*
8796  {
8797  return new Inst_FLAT__FLAT_ATOMIC_OR_X2(&iFmt->iFmt_FLAT);
8798  }
8799 
8800  GPUStaticInst*
8802  {
8803  return new Inst_FLAT__FLAT_ATOMIC_XOR_X2(&iFmt->iFmt_FLAT);
8804  }
8805 
8806  GPUStaticInst*
8808  {
8809  return new Inst_FLAT__FLAT_ATOMIC_INC_X2(&iFmt->iFmt_FLAT);
8810  }
8811 
8812  GPUStaticInst*
8814  {
8815  return new Inst_FLAT__FLAT_ATOMIC_DEC_X2(&iFmt->iFmt_FLAT);
8816  }
8817 
8818  GPUStaticInst*
8820  {
8821  return new Inst_MIMG__IMAGE_LOAD(&iFmt->iFmt_MIMG);
8822  } // decode_OP_MIMG__IMAGE_LOAD
8823 
8824  GPUStaticInst*
8826  {
8827  return new Inst_MIMG__IMAGE_LOAD_MIP(&iFmt->iFmt_MIMG);
8828  } // decode_OP_MIMG__IMAGE_LOAD_MIP
8829 
8830  GPUStaticInst*
8832  {
8833  return new Inst_MIMG__IMAGE_LOAD_PCK(&iFmt->iFmt_MIMG);
8834  } // decode_OP_MIMG__IMAGE_LOAD_PCK
8835 
8836  GPUStaticInst*
8838  {
8839  return new Inst_MIMG__IMAGE_LOAD_PCK_SGN(&iFmt->iFmt_MIMG);
8840  } // decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
8841 
8842  GPUStaticInst*
8844  {
8845  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK(&iFmt->iFmt_MIMG);
8846  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
8847 
8848  GPUStaticInst*
8850  {
8851  return new Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN(&iFmt->iFmt_MIMG);
8852  } // decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
8853 
8854  GPUStaticInst*
8856  {
8857  return new Inst_MIMG__IMAGE_STORE(&iFmt->iFmt_MIMG);
8858  } // decode_OP_MIMG__IMAGE_STORE
8859 
8860  GPUStaticInst*
8862  {
8863  return new Inst_MIMG__IMAGE_STORE_MIP(&iFmt->iFmt_MIMG);
8864  } // decode_OP_MIMG__IMAGE_STORE_MIP
8865 
8866  GPUStaticInst*
8868  {
8869  return new Inst_MIMG__IMAGE_STORE_PCK(&iFmt->iFmt_MIMG);
8870  } // decode_OP_MIMG__IMAGE_STORE_PCK
8871 
8872  GPUStaticInst*
8874  {
8875  return new Inst_MIMG__IMAGE_STORE_MIP_PCK(&iFmt->iFmt_MIMG);
8876  } // decode_OP_MIMG__IMAGE_STORE_MIP_PCK
8877 
8878  GPUStaticInst*
8880  {
8881  return new Inst_MIMG__IMAGE_GET_RESINFO(&iFmt->iFmt_MIMG);
8882  } // decode_OP_MIMG__IMAGE_GET_RESINFO
8883 
8884  GPUStaticInst*
8886  {
8887  return new Inst_MIMG__IMAGE_ATOMIC_SWAP(&iFmt->iFmt_MIMG);
8888  } // decode_OP_MIMG__IMAGE_ATOMIC_SWAP
8889 
8890  GPUStaticInst*
8892  {
8893  return new Inst_MIMG__IMAGE_ATOMIC_CMPSWAP(&iFmt->iFmt_MIMG);
8894  } // decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
8895 
8896  GPUStaticInst*
8898  {
8899  return new Inst_MIMG__IMAGE_ATOMIC_ADD(&iFmt->iFmt_MIMG);
8900  } // decode_OP_MIMG__IMAGE_ATOMIC_ADD
8901 
8902  GPUStaticInst*
8904  {
8905  return new Inst_MIMG__IMAGE_ATOMIC_SUB(&iFmt->iFmt_MIMG);
8906  } // decode_OP_MIMG__IMAGE_ATOMIC_SUB
8907 
8908  GPUStaticInst*
8910  {
8911  return new Inst_MIMG__IMAGE_ATOMIC_SMIN(&iFmt->iFmt_MIMG);
8912  } // decode_OP_MIMG__IMAGE_ATOMIC_SMIN
8913 
8914  GPUStaticInst*
8916  {
8917  return new Inst_MIMG__IMAGE_ATOMIC_UMIN(&iFmt->iFmt_MIMG);
8918  } // decode_OP_MIMG__IMAGE_ATOMIC_UMIN
8919 
8920  GPUStaticInst*
8922  {
8923  return new Inst_MIMG__IMAGE_ATOMIC_SMAX(&iFmt->iFmt_MIMG);
8924  } // decode_OP_MIMG__IMAGE_ATOMIC_SMAX
8925 
8926  GPUStaticInst*
8928  {
8929  return new Inst_MIMG__IMAGE_ATOMIC_UMAX(&iFmt->iFmt_MIMG);
8930  } // decode_OP_MIMG__IMAGE_ATOMIC_UMAX
8931 
8932  GPUStaticInst*
8934  {
8935  return new Inst_MIMG__IMAGE_ATOMIC_AND(&iFmt->iFmt_MIMG);
8936  } // decode_OP_MIMG__IMAGE_ATOMIC_AND
8937 
8938  GPUStaticInst*
8940  {
8941  return new Inst_MIMG__IMAGE_ATOMIC_OR(&iFmt->iFmt_MIMG);
8942  } // decode_OP_MIMG__IMAGE_ATOMIC_OR
8943 
8944  GPUStaticInst*
8946  {
8947  return new Inst_MIMG__IMAGE_ATOMIC_XOR(&iFmt->iFmt_MIMG);
8948  } // decode_OP_MIMG__IMAGE_ATOMIC_XOR
8949 
8950  GPUStaticInst*
8952  {
8953  return new Inst_MIMG__IMAGE_ATOMIC_INC(&iFmt->iFmt_MIMG);
8954  } // decode_OP_MIMG__IMAGE_ATOMIC_INC
8955 
8956  GPUStaticInst*
8958  {
8959  return new Inst_MIMG__IMAGE_ATOMIC_DEC(&iFmt->iFmt_MIMG);
8960  } // decode_OP_MIMG__IMAGE_ATOMIC_DEC
8961 
8962  GPUStaticInst*
8964  {
8965  return new Inst_MIMG__IMAGE_SAMPLE(&iFmt->iFmt_MIMG);
8966  } // decode_OP_MIMG__IMAGE_SAMPLE
8967 
8968  GPUStaticInst*
8970  {
8971  return new Inst_MIMG__IMAGE_SAMPLE_CL(&iFmt->iFmt_MIMG);
8972  } // decode_OP_MIMG__IMAGE_SAMPLE_CL
8973 
8974  GPUStaticInst*
8976  {
8977  return new Inst_MIMG__IMAGE_SAMPLE_D(&iFmt->iFmt_MIMG);
8978  } // decode_OP_MIMG__IMAGE_SAMPLE_D
8979 
8980  GPUStaticInst*
8982  {
8983  return new Inst_MIMG__IMAGE_SAMPLE_D_CL(&iFmt->iFmt_MIMG);
8984  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL
8985 
8986  GPUStaticInst*
8988  {
8989  return new Inst_MIMG__IMAGE_SAMPLE_L(&iFmt->iFmt_MIMG);
8990  } // decode_OP_MIMG__IMAGE_SAMPLE_L
8991 
8992  GPUStaticInst*
8994  {
8995  return new Inst_MIMG__IMAGE_SAMPLE_B(&iFmt->iFmt_MIMG);
8996  } // decode_OP_MIMG__IMAGE_SAMPLE_B
8997 
8998  GPUStaticInst*
9000  {
9001  return new Inst_MIMG__IMAGE_SAMPLE_B_CL(&iFmt->iFmt_MIMG);
9002  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL
9003 
9004  GPUStaticInst*
9006  {
9007  return new Inst_MIMG__IMAGE_SAMPLE_LZ(&iFmt->iFmt_MIMG);
9008  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ
9009 
9010  GPUStaticInst*
9012  {
9013  return new Inst_MIMG__IMAGE_SAMPLE_C(&iFmt->iFmt_MIMG);
9014  } // decode_OP_MIMG__IMAGE_SAMPLE_C
9015 
9016  GPUStaticInst*
9018  {
9019  return new Inst_MIMG__IMAGE_SAMPLE_C_CL(&iFmt->iFmt_MIMG);
9020  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL
9021 
9022  GPUStaticInst*
9024  {
9025  return new Inst_MIMG__IMAGE_SAMPLE_C_D(&iFmt->iFmt_MIMG);
9026  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D
9027 
9028  GPUStaticInst*
9030  {
9031  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL(&iFmt->iFmt_MIMG);
9032  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
9033 
9034  GPUStaticInst*
9036  {
9037  return new Inst_MIMG__IMAGE_SAMPLE_C_L(&iFmt->iFmt_MIMG);
9038  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L
9039 
9040  GPUStaticInst*
9042  {
9043  return new Inst_MIMG__IMAGE_SAMPLE_C_B(&iFmt->iFmt_MIMG);
9044  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B
9045 
9046  GPUStaticInst*
9048  {
9049  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL(&iFmt->iFmt_MIMG);
9050  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
9051 
9052  GPUStaticInst*
9054  {
9055  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ(&iFmt->iFmt_MIMG);
9056  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
9057 
9058  GPUStaticInst*
9060  {
9061  return new Inst_MIMG__IMAGE_SAMPLE_O(&iFmt->iFmt_MIMG);
9062  } // decode_OP_MIMG__IMAGE_SAMPLE_O
9063 
9064  GPUStaticInst*
9066  {
9067  return new Inst_MIMG__IMAGE_SAMPLE_CL_O(&iFmt->iFmt_MIMG);
9068  } // decode_OP_MIMG__IMAGE_SAMPLE_CL_O
9069 
9070  GPUStaticInst*
9072  {
9073  return new Inst_MIMG__IMAGE_SAMPLE_D_O(&iFmt->iFmt_MIMG);
9074  } // decode_OP_MIMG__IMAGE_SAMPLE_D_O
9075 
9076  GPUStaticInst*
9078  {
9079  return new Inst_MIMG__IMAGE_SAMPLE_D_CL_O(&iFmt->iFmt_MIMG);
9080  } // decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
9081 
9082  GPUStaticInst*
9084  {
9085  return new Inst_MIMG__IMAGE_SAMPLE_L_O(&iFmt->iFmt_MIMG);
9086  } // decode_OP_MIMG__IMAGE_SAMPLE_L_O
9087 
9088  GPUStaticInst*
9090  {
9091  return new Inst_MIMG__IMAGE_SAMPLE_B_O(&iFmt->iFmt_MIMG);
9092  } // decode_OP_MIMG__IMAGE_SAMPLE_B_O
9093 
9094  GPUStaticInst*
9096  {
9097  return new Inst_MIMG__IMAGE_SAMPLE_B_CL_O(&iFmt->iFmt_MIMG);
9098  } // decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
9099 
9100  GPUStaticInst*
9102  {
9103  return new Inst_MIMG__IMAGE_SAMPLE_LZ_O(&iFmt->iFmt_MIMG);
9104  } // decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
9105 
9106  GPUStaticInst*
9108  {
9109  return new Inst_MIMG__IMAGE_SAMPLE_C_O(&iFmt->iFmt_MIMG);
9110  } // decode_OP_MIMG__IMAGE_SAMPLE_C_O
9111 
9112  GPUStaticInst*
9114  {
9115  return new Inst_MIMG__IMAGE_SAMPLE_C_CL_O(&iFmt->iFmt_MIMG);
9116  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
9117 
9118  GPUStaticInst*
9120  {
9121  return new Inst_MIMG__IMAGE_SAMPLE_C_D_O(&iFmt->iFmt_MIMG);
9122  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
9123 
9124  GPUStaticInst*
9126  {
9127  return new Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O(&iFmt->iFmt_MIMG);
9128  } // decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
9129 
9130  GPUStaticInst*
9132  {
9133  return new Inst_MIMG__IMAGE_SAMPLE_C_L_O(&iFmt->iFmt_MIMG);
9134  } // decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
9135 
9136  GPUStaticInst*
9138  {
9139  return new Inst_MIMG__IMAGE_SAMPLE_C_B_O(&iFmt->iFmt_MIMG);
9140  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
9141 
9142  GPUStaticInst*
9144  {
9145  return new Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O(&iFmt->iFmt_MIMG);
9146  } // decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
9147 
9148  GPUStaticInst*
9150  {
9151  return new Inst_MIMG__IMAGE_SAMPLE_C_LZ_O(&iFmt->iFmt_MIMG);
9152  } // decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
9153 
9154  GPUStaticInst*
9156  {
9157  return new Inst_MIMG__IMAGE_GATHER4(&iFmt->iFmt_MIMG);
9158  } // decode_OP_MIMG__IMAGE_GATHER4
9159 
9160  GPUStaticInst*
9162  {
9163  return new Inst_MIMG__IMAGE_GATHER4_CL(&iFmt->iFmt_MIMG);
9164  } // decode_OP_MIMG__IMAGE_GATHER4_CL
9165 
9166  GPUStaticInst*
9168  {
9169  fatal("Trying to decode instruction without a class\n");
9170  return nullptr;
9171  }
9172 
9173  GPUStaticInst*
9175  {
9176  return new Inst_MIMG__IMAGE_GATHER4_L(&iFmt->iFmt_MIMG);
9177  } // decode_OP_MIMG__IMAGE_GATHER4_L
9178 
9179  GPUStaticInst*
9181  {
9182  return new Inst_MIMG__IMAGE_GATHER4_B(&iFmt->iFmt_MIMG);
9183  } // decode_OP_MIMG__IMAGE_GATHER4_B
9184 
9185  GPUStaticInst*
9187  {
9188  return new Inst_MIMG__IMAGE_GATHER4_B_CL(&iFmt->iFmt_MIMG);
9189  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL
9190 
9191  GPUStaticInst*
9193  {
9194  return new Inst_MIMG__IMAGE_GATHER4_LZ(&iFmt->iFmt_MIMG);
9195  } // decode_OP_MIMG__IMAGE_GATHER4_LZ
9196 
9197  GPUStaticInst*
9199  {
9200  return new Inst_MIMG__IMAGE_GATHER4_C(&iFmt->iFmt_MIMG);
9201  } // decode_OP_MIMG__IMAGE_GATHER4_C
9202 
9203  GPUStaticInst*
9205  {
9206  return new Inst_MIMG__IMAGE_GATHER4_C_CL(&iFmt->iFmt_MIMG);
9207  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL
9208 
9209  GPUStaticInst*
9211  {
9212  fatal("Trying to decode instruction without a class\n");
9213  return nullptr;
9214  }
9215 
9216  GPUStaticInst*
9218  {
9219  fatal("Trying to decode instruction without a class\n");
9220  return nullptr;
9221  }
9222 
9223  GPUStaticInst*
9225  {
9226  return new Inst_MIMG__IMAGE_GATHER4_C_L(&iFmt->iFmt_MIMG);
9227  } // decode_OP_MIMG__IMAGE_GATHER4_C_L
9228 
9229  GPUStaticInst*
9231  {
9232  return new Inst_MIMG__IMAGE_GATHER4_C_B(&iFmt->iFmt_MIMG);
9233  } // decode_OP_MIMG__IMAGE_GATHER4_C_B
9234 
9235  GPUStaticInst*
9237  {
9238  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL(&iFmt->iFmt_MIMG);
9239  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
9240 
9241  GPUStaticInst*
9243  {
9244  return new Inst_MIMG__IMAGE_GATHER4_C_LZ(&iFmt->iFmt_MIMG);
9245  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ
9246 
9247  GPUStaticInst*
9249  {
9250  return new Inst_MIMG__IMAGE_GATHER4_O(&iFmt->iFmt_MIMG);
9251  } // decode_OP_MIMG__IMAGE_GATHER4_O
9252 
9253  GPUStaticInst*
9255  {
9256  return new Inst_MIMG__IMAGE_GATHER4_CL_O(&iFmt->iFmt_MIMG);
9257  } // decode_OP_MIMG__IMAGE_GATHER4_CL_O
9258 
9259  GPUStaticInst*
9261  {
9262  return new Inst_MIMG__IMAGE_GATHER4_L_O(&iFmt->iFmt_MIMG);
9263  } // decode_OP_MIMG__IMAGE_GATHER4_L_O
9264 
9265  GPUStaticInst*
9267  {
9268  return new Inst_MIMG__IMAGE_GATHER4_B_O(&iFmt->iFmt_MIMG);
9269  } // decode_OP_MIMG__IMAGE_GATHER4_B_O
9270 
9271  GPUStaticInst*
9273  {
9274  return new Inst_MIMG__IMAGE_GATHER4_B_CL_O(&iFmt->iFmt_MIMG);
9275  } // decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
9276 
9277  GPUStaticInst*
9279  {
9280  return new Inst_MIMG__IMAGE_GATHER4_LZ_O(&iFmt->iFmt_MIMG);
9281  } // decode_OP_MIMG__IMAGE_GATHER4_LZ_O
9282 
9283  GPUStaticInst*
9285  {
9286  return new Inst_MIMG__IMAGE_GATHER4_C_O(&iFmt->iFmt_MIMG);
9287  } // decode_OP_MIMG__IMAGE_GATHER4_C_O
9288 
9289  GPUStaticInst*
9291  {
9292  return new Inst_MIMG__IMAGE_GATHER4_C_CL_O(&iFmt->iFmt_MIMG);
9293  } // decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
9294 
9295  GPUStaticInst*
9297  {
9298  return new Inst_MIMG__IMAGE_GATHER4_C_L_O(&iFmt->iFmt_MIMG);
9299  } // decode_OP_MIMG__IMAGE_GATHER4_C_L_O
9300 
9301  GPUStaticInst*
9303  {
9304  return new Inst_MIMG__IMAGE_GATHER4_C_B_O(&iFmt->iFmt_MIMG);
9305  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_O
9306 
9307  GPUStaticInst*
9309  {
9310  return new Inst_MIMG__IMAGE_GATHER4_C_B_CL_O(&iFmt->iFmt_MIMG);
9311  } // decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
9312 
9313  GPUStaticInst*
9315  {
9316  return new Inst_MIMG__IMAGE_GATHER4_C_LZ_O(&iFmt->iFmt_MIMG);
9317  } // decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
9318 
9319  GPUStaticInst*
9321  {
9322  return new Inst_MIMG__IMAGE_GET_LOD(&iFmt->iFmt_MIMG);
9323  } // decode_OP_MIMG__IMAGE_GET_LOD
9324 
9325  GPUStaticInst*
9327  {
9328  return new Inst_MIMG__IMAGE_SAMPLE_CD(&iFmt->iFmt_MIMG);
9329  } // decode_OP_MIMG__IMAGE_SAMPLE_CD
9330 
9331  GPUStaticInst*
9333  {
9334  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL(&iFmt->iFmt_MIMG);
9335  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
9336 
9337  GPUStaticInst*
9339  {
9340  return new Inst_MIMG__IMAGE_SAMPLE_C_CD(&iFmt->iFmt_MIMG);
9341  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD
9342 
9343  GPUStaticInst*
9345  {
9346  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL(&iFmt->iFmt_MIMG);
9347  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
9348 
9349  GPUStaticInst*
9351  {
9352  return new Inst_MIMG__IMAGE_SAMPLE_CD_O(&iFmt->iFmt_MIMG);
9353  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_O
9354 
9355  GPUStaticInst*
9357  {
9358  return new Inst_MIMG__IMAGE_SAMPLE_CD_CL_O(&iFmt->iFmt_MIMG);
9359  } // decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
9360 
9361  GPUStaticInst*
9363  {
9364  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_O(&iFmt->iFmt_MIMG);
9365  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
9366 
9367  GPUStaticInst*
9369  {
9370  return new Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O(&iFmt->iFmt_MIMG);
9371  } // decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
9372 
9373  GPUStaticInst*
9375  {
9376  return new Inst_MTBUF__TBUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MTBUF);
9377  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
9378 
9379  GPUStaticInst*
9381  {
9383  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
9384 
9385  GPUStaticInst*
9387  {
9389  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
9390 
9391  GPUStaticInst*
9393  {
9395  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
9396 
9397  GPUStaticInst*
9399  {
9401  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
9402 
9403  GPUStaticInst*
9405  {
9407  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
9408 
9409  GPUStaticInst*
9411  {
9413  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
9414 
9415  GPUStaticInst*
9417  {
9419  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
9420 
9421  GPUStaticInst*
9423  {
9425  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
9426 
9427  GPUStaticInst*
9429  {
9431  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
9432 
9433  GPUStaticInst*
9435  {
9437  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
9438 
9439  GPUStaticInst*
9441  {
9443  } // decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
9444 
9445  GPUStaticInst*
9447  {
9449  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
9450 
9451  GPUStaticInst*
9453  {
9455  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
9456 
9457  GPUStaticInst*
9459  {
9461  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
9462 
9463  GPUStaticInst*
9465  {
9466  return new
9468  } // decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
9469 
9470  GPUStaticInst*
9472  {
9473  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_X(&iFmt->iFmt_MUBUF);
9474  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
9475 
9476  GPUStaticInst*
9478  {
9479  return new Inst_MUBUF__BUFFER_LOAD_FORMAT_XY(&iFmt->iFmt_MUBUF);
9480  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
9481 
9482  GPUStaticInst*
9484  {
9486  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
9487 
9488  GPUStaticInst*
9490  {
9492  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
9493 
9494  GPUStaticInst*
9496  {
9497  return new Inst_MUBUF__BUFFER_STORE_FORMAT_X(&iFmt->iFmt_MUBUF);
9498  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
9499 
9500  GPUStaticInst*
9502  {
9504  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
9505 
9506  GPUStaticInst*
9508  {
9510  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
9511 
9512  GPUStaticInst*
9514  {
9516  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
9517 
9518  GPUStaticInst*
9520  {
9522  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
9523 
9524  GPUStaticInst*
9526  {
9528  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
9529 
9530  GPUStaticInst*
9532  {
9534  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
9535 
9536  GPUStaticInst*
9538  {
9540  } // decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
9541 
9542  GPUStaticInst*
9544  {
9546  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
9547 
9548  GPUStaticInst*
9550  {
9552  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
9553 
9554  GPUStaticInst*
9556  {
9558  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
9559 
9560  GPUStaticInst*
9562  {
9564  } // decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
9565 
9566  GPUStaticInst*
9568  {
9569  return new Inst_MUBUF__BUFFER_LOAD_UBYTE(&iFmt->iFmt_MUBUF);
9570  } // decode_OP_MUBUF__BUFFER_LOAD_UBYTE
9571 
9572  GPUStaticInst*
9574  {
9575  return new Inst_MUBUF__BUFFER_LOAD_SBYTE(&iFmt->iFmt_MUBUF);
9576  } // decode_OP_MUBUF__BUFFER_LOAD_SBYTE
9577 
9578  GPUStaticInst*
9580  {
9581  return new Inst_MUBUF__BUFFER_LOAD_USHORT(&iFmt->iFmt_MUBUF);
9582  } // decode_OP_MUBUF__BUFFER_LOAD_USHORT
9583 
9584  GPUStaticInst*
9586  {
9587  return new Inst_MUBUF__BUFFER_LOAD_SSHORT(&iFmt->iFmt_MUBUF);
9588  } // decode_OP_MUBUF__BUFFER_LOAD_SSHORT
9589 
9590  GPUStaticInst*
9592  {
9593  return new Inst_MUBUF__BUFFER_LOAD_DWORD(&iFmt->iFmt_MUBUF);
9594  } // decode_OP_MUBUF__BUFFER_LOAD_DWORD
9595 
9596  GPUStaticInst*
9598  {
9599  return new Inst_MUBUF__BUFFER_LOAD_DWORDX2(&iFmt->iFmt_MUBUF);
9600  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
9601 
9602  GPUStaticInst*
9604  {
9605  return new Inst_MUBUF__BUFFER_LOAD_DWORDX3(&iFmt->iFmt_MUBUF);
9606  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
9607 
9608  GPUStaticInst*
9610  {
9611  return new Inst_MUBUF__BUFFER_LOAD_DWORDX4(&iFmt->iFmt_MUBUF);
9612  } // decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
9613 
9614  GPUStaticInst*
9616  {
9617  return new Inst_MUBUF__BUFFER_STORE_BYTE(&iFmt->iFmt_MUBUF);
9618  } // decode_OP_MUBUF__BUFFER_STORE_BYTE
9619 
9620  GPUStaticInst*
9622  {
9623  fatal("Trying to decode instruction without a class\n");
9624  return nullptr;
9625  }
9626 
9627  GPUStaticInst*
9629  {
9630  return new Inst_MUBUF__BUFFER_STORE_SHORT(&iFmt->iFmt_MUBUF);
9631  } // decode_OP_MUBUF__BUFFER_STORE_SHORT
9632 
9633  GPUStaticInst*
9635  {
9636  fatal("Trying to decode instruction without a class\n");
9637  return nullptr;
9638  }
9639 
9640  GPUStaticInst*
9642  {
9643  return new Inst_MUBUF__BUFFER_STORE_DWORD(&iFmt->iFmt_MUBUF);
9644  } // decode_OP_MUBUF__BUFFER_STORE_DWORD
9645 
9646  GPUStaticInst*
9648  {
9649  return new Inst_MUBUF__BUFFER_STORE_DWORDX2(&iFmt->iFmt_MUBUF);
9650  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX2
9651 
9652  GPUStaticInst*
9654  {
9655  return new Inst_MUBUF__BUFFER_STORE_DWORDX3(&iFmt->iFmt_MUBUF);
9656  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX3
9657 
9658  GPUStaticInst*
9660  {
9661  return new Inst_MUBUF__BUFFER_STORE_DWORDX4(&iFmt->iFmt_MUBUF);
9662  } // decode_OP_MUBUF__BUFFER_STORE_DWORDX4
9663 
9664  GPUStaticInst*
9666  {
9668  } // decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
9669 
9670  GPUStaticInst*
9672  {
9673  return new Inst_MUBUF__BUFFER_WBINVL1(&iFmt->iFmt_MUBUF);
9674  } // decode_OP_MUBUF__BUFFER_WBINVL1
9675 
9676  GPUStaticInst*
9678  {
9679  return new Inst_MUBUF__BUFFER_WBINVL1_VOL(&iFmt->iFmt_MUBUF);
9680  } // decode_OP_MUBUF__BUFFER_WBINVL1_VOL
9681 
9682  GPUStaticInst*
9684  {
9685  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP(&iFmt->iFmt_MUBUF);
9686  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
9687 
9688  GPUStaticInst*
9690  {
9691  return new Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP(&iFmt->iFmt_MUBUF);
9692  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
9693 
9694  GPUStaticInst*
9696  {
9697  return new Inst_MUBUF__BUFFER_ATOMIC_ADD(&iFmt->iFmt_MUBUF);
9698  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD
9699 
9700  GPUStaticInst*
9702  {
9703  return new Inst_MUBUF__BUFFER_ATOMIC_SUB(&iFmt->iFmt_MUBUF);
9704  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB
9705 
9706  GPUStaticInst*
9708  {
9709  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN(&iFmt->iFmt_MUBUF);
9710  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
9711 
9712  GPUStaticInst*
9714  {
9715  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN(&iFmt->iFmt_MUBUF);
9716  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
9717 
9718  GPUStaticInst*
9720  {
9721  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX(&iFmt->iFmt_MUBUF);
9722  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
9723 
9724  GPUStaticInst*
9726  {
9727  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX(&iFmt->iFmt_MUBUF);
9728  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
9729 
9730  GPUStaticInst*
9732  {
9733  return new Inst_MUBUF__BUFFER_ATOMIC_AND(&iFmt->iFmt_MUBUF);
9734  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND
9735 
9736  GPUStaticInst*
9738  {
9739  return new Inst_MUBUF__BUFFER_ATOMIC_OR(&iFmt->iFmt_MUBUF);
9740  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR
9741 
9742  GPUStaticInst*
9744  {
9745  return new Inst_MUBUF__BUFFER_ATOMIC_XOR(&iFmt->iFmt_MUBUF);
9746  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR
9747 
9748  GPUStaticInst*
9750  {
9751  return new Inst_MUBUF__BUFFER_ATOMIC_INC(&iFmt->iFmt_MUBUF);
9752  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC
9753 
9754  GPUStaticInst*
9756  {
9757  return new Inst_MUBUF__BUFFER_ATOMIC_DEC(&iFmt->iFmt_MUBUF);
9758  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC
9759 
9760  GPUStaticInst*
9762  {
9763  return new Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2(&iFmt->iFmt_MUBUF);
9764  } // decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
9765 
9766  GPUStaticInst*
9768  {
9770  } // decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
9771 
9772  GPUStaticInst*
9774  {
9775  return new Inst_MUBUF__BUFFER_ATOMIC_ADD_X2(&iFmt->iFmt_MUBUF);
9776  } // decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
9777 
9778  GPUStaticInst*
9780  {
9781  return new Inst_MUBUF__BUFFER_ATOMIC_SUB_X2(&iFmt->iFmt_MUBUF);
9782  } // decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
9783 
9784  GPUStaticInst*
9786  {
9787  return new Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2(&iFmt->iFmt_MUBUF);
9788  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
9789 
9790  GPUStaticInst*
9792  {
9793  return new Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2(&iFmt->iFmt_MUBUF);
9794  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
9795 
9796  GPUStaticInst*
9798  {
9799  return new Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2(&iFmt->iFmt_MUBUF);
9800  } // decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
9801 
9802  GPUStaticInst*
9804  {
9805  return new Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2(&iFmt->iFmt_MUBUF);
9806  } // decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
9807 
9808  GPUStaticInst*
9810  {
9811  return new Inst_MUBUF__BUFFER_ATOMIC_AND_X2(&iFmt->iFmt_MUBUF);
9812  } // decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
9813 
9814  GPUStaticInst*
9816  {
9817  return new Inst_MUBUF__BUFFER_ATOMIC_OR_X2(&iFmt->iFmt_MUBUF);
9818  } // decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
9819 
9820  GPUStaticInst*
9822  {
9823  return new Inst_MUBUF__BUFFER_ATOMIC_XOR_X2(&iFmt->iFmt_MUBUF);
9824  } // decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
9825 
9826  GPUStaticInst*
9828  {
9829  return new Inst_MUBUF__BUFFER_ATOMIC_INC_X2(&iFmt->iFmt_MUBUF);
9830  } // decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
9831 
9832  GPUStaticInst*
9834  {
9835  return new Inst_MUBUF__BUFFER_ATOMIC_DEC_X2(&iFmt->iFmt_MUBUF);
9836  } // decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
9837 
9838  GPUStaticInst*
9840  {
9841  fatal("Trying to decode instruction without a class\n");
9842  return nullptr;
9843  }
9844 
9845  GPUStaticInst*
9847  {
9848  fatal("Trying to decode instruction without a class\n");
9849  return nullptr;
9850  }
9851 
9852  GPUStaticInst*
9854  {
9855  fatal("Trying to decode instruction without a class\n");
9856  return nullptr;
9857  }
9858 
9859  GPUStaticInst*
9861  {
9862  fatal("Trying to decode instruction without a class\n");
9863  return nullptr;
9864  }
9865 
9866  GPUStaticInst*
9868  {
9869  fatal("Trying to decode instruction without a class\n");
9870  return nullptr;
9871  }
9872 
9873  GPUStaticInst*
9875  {
9876  fatal("Trying to decode instruction without a class\n");
9877  return nullptr;
9878  }
9879 
9880  GPUStaticInst*
9882  {
9883  fatal("Trying to decode instruction without a class\n");
9884  return nullptr;
9885  }
9886 
9887  GPUStaticInst*
9889  {
9890  fatal("Trying to decode instruction without a class\n");
9891  return nullptr;
9892  }
9893 
9894  GPUStaticInst*
9896  {
9897  fatal("Trying to decode instruction without a class\n");
9898  return nullptr;
9899  }
9900 
9901  GPUStaticInst*
9903  {
9904  fatal("Trying to decode instruction without a class\n");
9905  return nullptr;
9906  }
9907 
9908  GPUStaticInst*
9910  {
9911  fatal("Trying to decode instruction without a class\n");
9912  return nullptr;
9913  }
9914 
9915  GPUStaticInst*
9917  {
9918  fatal("Trying to decode instruction without a class\n");
9919  return nullptr;
9920  }
9921 
9922  GPUStaticInst*
9924  {
9925  fatal("Trying to decode instruction without a class\n");
9926  return nullptr;
9927  }
9928 
9929  GPUStaticInst*
9931  {
9932  fatal("Trying to decode instruction without a class\n");
9933  return nullptr;
9934  }
9935 
9936  GPUStaticInst*
9938  {
9939  fatal("Trying to decode instruction without a class\n");
9940  return nullptr;
9941  }
9942 
9943  GPUStaticInst*
9945  {
9946  fatal("Trying to decode instruction without a class\n");
9947  return nullptr;
9948  }
9949 
9950  GPUStaticInst*
9952  {
9953  fatal("Trying to decode instruction without a class\n");
9954  return nullptr;
9955  }
9956 
9957  GPUStaticInst*
9959  {
9960  fatal("Trying to decode instruction without a class\n");
9961  return nullptr;
9962  }
9963 
9964  GPUStaticInst*
9966  {
9967  fatal("Trying to decode instruction without a class\n");
9968  return nullptr;
9969  }
9970 
9971  GPUStaticInst*
9973  {
9974  fatal("Trying to decode instruction without a class\n");
9975  return nullptr;
9976  }
9977 
9978  GPUStaticInst*
9980  {
9981  fatal("Trying to decode instruction without a class\n");
9982  return nullptr;
9983  }
9984 
9985  GPUStaticInst*
9987  {
9988  fatal("Trying to decode instruction without a class\n");
9989  return nullptr;
9990  }
9991 
9992  GPUStaticInst*
9994  {
9995  return new Inst_SMEM__S_LOAD_DWORD(&iFmt->iFmt_SMEM);
9996  } // decode_OP_SMEM__S_LOAD_DWORD
9997 
9998  GPUStaticInst*
10000  {
10001  return new Inst_SMEM__S_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
10002  } // decode_OP_SMEM__S_LOAD_DWORDX2
10003 
10004  GPUStaticInst*
10006  {
10007  return new Inst_SMEM__S_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
10008  } // decode_OP_SMEM__S_LOAD_DWORDX4
10009 
10010  GPUStaticInst*
10012  {
10013  return new Inst_SMEM__S_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
10014  } // decode_OP_SMEM__S_LOAD_DWORDX8
10015 
10016  GPUStaticInst*
10018  {
10019  return new Inst_SMEM__S_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
10020  } // decode_OP_SMEM__S_LOAD_DWORDX16
10021 
10022  GPUStaticInst*
10024  {
10025  fatal("Trying to decode instruction without a class\n");
10026  return nullptr;
10027  }
10028 
10029  GPUStaticInst*
10031  {
10032  fatal("Trying to decode instruction without a class\n");
10033  return nullptr;
10034  }
10035 
10036  GPUStaticInst*
10038  {
10039  fatal("Trying to decode instruction without a class\n");
10040  return nullptr;
10041  }
10042 
10043  GPUStaticInst*
10045  {
10046  return new Inst_SMEM__S_BUFFER_LOAD_DWORD(&iFmt->iFmt_SMEM);
10047  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORD
10048 
10049  GPUStaticInst*
10051  {
10052  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX2(&iFmt->iFmt_SMEM);
10053  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
10054 
10055  GPUStaticInst*
10057  {
10058  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX4(&iFmt->iFmt_SMEM);
10059  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
10060 
10061  GPUStaticInst*
10063  {
10064  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX8(&iFmt->iFmt_SMEM);
10065  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
10066 
10067  GPUStaticInst*
10069  {
10070  return new Inst_SMEM__S_BUFFER_LOAD_DWORDX16(&iFmt->iFmt_SMEM);
10071  } // decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
10072 
10073  GPUStaticInst*
10075  {
10076  return new Inst_SMEM__S_STORE_DWORD(&iFmt->iFmt_SMEM);
10077  } // decode_OP_SMEM__S_STORE_DWORD
10078 
10079  GPUStaticInst*
10081  {
10082  return new Inst_SMEM__S_STORE_DWORDX2(&iFmt->iFmt_SMEM);
10083  } // decode_OP_SMEM__S_STORE_DWORDX2
10084 
10085  GPUStaticInst*
10087  {
10088  return new Inst_SMEM__S_STORE_DWORDX4(&iFmt->iFmt_SMEM);
10089  } // decode_OP_SMEM__S_STORE_DWORDX4
10090 
10091  GPUStaticInst*
10093  {
10094  fatal("Trying to decode instruction without a class\n");
10095  return nullptr;
10096  }
10097 
10098  GPUStaticInst*
10100  {
10101  fatal("Trying to decode instruction without a class\n");
10102  return nullptr;
10103  }
10104 
10105  GPUStaticInst*
10107  {
10108  fatal("Trying to decode instruction without a class\n");
10109  return nullptr;
10110  }
10111 
10112  GPUStaticInst*
10114  {
10115  return new Inst_SMEM__S_BUFFER_STORE_DWORD(&iFmt->iFmt_SMEM);
10116  } // decode_OP_SMEM__S_BUFFER_STORE_DWORD
10117 
10118  GPUStaticInst*
10120  {
10121  return new Inst_SMEM__S_BUFFER_STORE_DWORDX2(&iFmt->iFmt_SMEM);
10122  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
10123 
10124  GPUStaticInst*
10126  {
10127  return new Inst_SMEM__S_BUFFER_STORE_DWORDX4(&iFmt->iFmt_SMEM);
10128  } // decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
10129 
10130  GPUStaticInst*
10132  {
10133  fatal("Trying to decode instruction without a class\n");
10134  return nullptr;
10135  }
10136  GPUStaticInst*
10138  {
10139  fatal("Trying to decode instruction without a class\n");
10140  return nullptr;
10141  }
10142  GPUStaticInst*
10144  {
10145  fatal("Trying to decode instruction without a class\n");
10146  return nullptr;
10147  }
10148  GPUStaticInst*
10150  {
10151  fatal("Trying to decode instruction without a class\n");
10152  return nullptr;
10153  }
10154  GPUStaticInst*
10156  {
10157  fatal("Trying to decode instruction without a class\n");
10158  return nullptr;
10159  }
10160  GPUStaticInst*
10162  {
10163  fatal("Trying to decode instruction without a class\n");
10164  return nullptr;
10165  }
10166  GPUStaticInst*
10168  {
10169  fatal("Trying to decode instruction without a class\n");
10170  return nullptr;
10171  }
10172  GPUStaticInst*
10174  {
10175  fatal("Trying to decode instruction without a class\n");
10176  return nullptr;
10177  }
10178 
10179  GPUStaticInst*
10181  {
10182  return new Inst_SMEM__S_DCACHE_INV(&iFmt->iFmt_SMEM);
10183  } // decode_OP_SMEM__S_DCACHE_INV
10184 
10185  GPUStaticInst*
10187  {
10188  return new Inst_SMEM__S_DCACHE_WB(&iFmt->iFmt_SMEM);
10189  } // decode_OP_SMEM__S_DCACHE_WB
10190 
10191  GPUStaticInst*
10193  {
10194  return new Inst_SMEM__S_DCACHE_INV_VOL(&iFmt->iFmt_SMEM);
10195  } // decode_OP_SMEM__S_DCACHE_INV_VOL
10196 
10197  GPUStaticInst*
10199  {
10200  return new Inst_SMEM__S_DCACHE_WB_VOL(&iFmt->iFmt_SMEM);
10201  } // decode_OP_SMEM__S_DCACHE_WB_VOL
10202 
10203  GPUStaticInst*
10205  {
10206  return new Inst_SMEM__S_MEMTIME(&iFmt->iFmt_SMEM);
10207  } // decode_OP_SMEM__S_MEMTIME
10208 
10209  GPUStaticInst*
10211  {
10212  return new Inst_SMEM__S_MEMREALTIME(&iFmt->iFmt_SMEM);
10213  } // decode_OP_SMEM__S_MEMREALTIME
10214 
10215  GPUStaticInst*
10217  {
10218  return new Inst_SMEM__S_ATC_PROBE(&iFmt->iFmt_SMEM);
10219  } // decode_OP_SMEM__S_ATC_PROBE
10220 
10221  GPUStaticInst*
10223  {
10224  return new Inst_SMEM__S_ATC_PROBE_BUFFER(&iFmt->iFmt_SMEM);
10225  } // decode_OP_SMEM__S_ATC_PROBE_BUFFER
10226 
10227  GPUStaticInst*
10229  {
10230  fatal("Trying to decode instruction without a class\n");
10231  return nullptr;
10232  }
10233 
10234  GPUStaticInst*
10236  {
10237  fatal("Trying to decode instruction without a class\n");
10238  return nullptr;
10239  }
10240 
10241  GPUStaticInst*
10243  {
10244  fatal("Trying to decode instruction without a class\n");
10245  return nullptr;
10246  }
10247 
10248  GPUStaticInst*
10250  {
10251  fatal("Trying to decode instruction without a class\n");
10252  return nullptr;
10253  }
10254 
10255  GPUStaticInst*
10257  {
10258  fatal("Trying to decode instruction without a class\n");
10259  return nullptr;
10260  }
10261 
10262  GPUStaticInst*
10264  {
10265  fatal("Trying to decode instruction without a class\n");
10266  return nullptr;
10267  }
10268 
10269  GPUStaticInst*
10271  {
10272  fatal("Trying to decode instruction without a class\n");
10273  return nullptr;
10274  }
10275 
10276  GPUStaticInst*
10278  {
10279  fatal("Trying to decode instruction without a class\n");
10280  return nullptr;
10281  }
10282 
10283  GPUStaticInst*
10285  {
10286  fatal("Trying to decode instruction without a class\n");
10287  return nullptr;
10288  }
10289 
10290  GPUStaticInst*
10292  {
10293  fatal("Trying to decode instruction without a class\n");
10294  return nullptr;
10295  }
10296 
10297  GPUStaticInst*
10299  {
10300  fatal("Trying to decode instruction without a class\n");
10301  return nullptr;
10302  }
10303 
10304  GPUStaticInst*
10306  {
10307  fatal("Trying to decode instruction without a class\n");
10308  return nullptr;
10309  }
10310 
10311  GPUStaticInst*
10313  {
10314  fatal("Trying to decode instruction without a class\n");
10315  return nullptr;
10316  }
10317 
10318  GPUStaticInst*
10320  {
10321  fatal("Trying to decode instruction without a class\n");
10322  return nullptr;
10323  }
10324 
10325  GPUStaticInst*
10327  {
10328  fatal("Trying to decode instruction without a class\n");
10329  return nullptr;
10330  }
10331 
10332  GPUStaticInst*
10334  {
10335  fatal("Trying to decode instruction without a class\n");
10336  return nullptr;
10337  }
10338 
10339  GPUStaticInst*
10341  {
10342  fatal("Trying to decode instruction without a class\n");
10343  return nullptr;
10344  }
10345 
10346  GPUStaticInst*
10348  {
10349  fatal("Trying to decode instruction without a class\n");
10350  return nullptr;
10351  }
10352 
10353  GPUStaticInst*
10355  {
10356  fatal("Trying to decode instruction without a class\n");
10357  return nullptr;
10358  }
10359 
10360  GPUStaticInst*
10362  {
10363  fatal("Trying to decode instruction without a class\n");
10364  return nullptr;
10365  }
10366 
10367  GPUStaticInst*
10369  {
10370  fatal("Trying to decode instruction without a class\n");
10371  return nullptr;
10372  }
10373 
10374  GPUStaticInst*
10376  {
10377  fatal("Trying to decode instruction without a class\n");
10378  return nullptr;
10379  }
10380 
10381  GPUStaticInst*
10383  {
10384  fatal("Trying to decode instruction without a class\n");
10385  return nullptr;
10386  }
10387 
10388  GPUStaticInst*
10390  {
10391  fatal("Trying to decode instruction without a class\n");
10392  return nullptr;
10393  }
10394 
10395  GPUStaticInst*
10397  {
10398  fatal("Trying to decode instruction without a class\n");
10399  return nullptr;
10400  }
10401 
10402  GPUStaticInst*
10404  {
10405  fatal("Trying to decode instruction without a class\n");
10406  return nullptr;
10407  }
10408 
10409  GPUStaticInst*
10411  {
10412  fatal("Trying to decode instruction without a class\n");
10413  return nullptr;
10414  }
10415 
10416  GPUStaticInst*
10418  {
10419  fatal("Trying to decode instruction without a class\n");
10420  return nullptr;
10421  }
10422 
10423  GPUStaticInst*
10425  {
10426  fatal("Trying to decode instruction without a class\n");
10427  return nullptr;
10428  }
10429 
10430  GPUStaticInst*
10432  {
10433  fatal("Trying to decode instruction without a class\n");
10434  return nullptr;
10435  }
10436 
10437  GPUStaticInst*
10439  {
10440  fatal("Trying to decode instruction without a class\n");
10441  return nullptr;
10442  }
10443 
10444  GPUStaticInst*
10446  {
10447  fatal("Trying to decode instruction without a class\n");
10448  return nullptr;
10449  }
10450 
10451  GPUStaticInst*
10453  {
10454  fatal("Trying to decode instruction without a class\n");
10455  return nullptr;
10456  }
10457 
10458  GPUStaticInst*
10460  {
10461  fatal("Trying to decode instruction without a class\n");
10462  return nullptr;
10463  }
10464 
10465  GPUStaticInst*
10467  {
10468  fatal("Trying to decode instruction without a class\n");
10469  return nullptr;
10470  }
10471 
10472  GPUStaticInst*
10474  {
10475  fatal("Trying to decode instruction without a class\n");
10476  return nullptr;
10477  }
10478 
10479  GPUStaticInst*
10481  {
10482  fatal("Trying to decode instruction without a class\n");
10483  return nullptr;
10484  }
10485 
10486  GPUStaticInst*
10488  {
10489  fatal("Trying to decode instruction without a class\n");
10490  return nullptr;
10491  }
10492 
10493  GPUStaticInst*
10495  {
10496  fatal("Trying to decode instruction without a class\n");
10497  return nullptr;
10498  }
10499 
10500  GPUStaticInst*
10502  {
10503  fatal("Trying to decode instruction without a class\n");
10504  return nullptr;
10505  }
10506 
10507  GPUStaticInst*
10509  {
10510  fatal("Trying to decode instruction without a class\n");
10511  return nullptr;
10512  }
10513 
10514  GPUStaticInst*
10516  {
10517  fatal("Trying to decode instruction without a class\n");
10518  return nullptr;
10519  }
10520 
10521  GPUStaticInst*
10523  {
10524  fatal("Trying to decode instruction without a class\n");
10525  return nullptr;
10526  }
10527 
10528  GPUStaticInst*
10530  {
10531  fatal("Trying to decode instruction without a class\n");
10532  return nullptr;
10533  }
10534 
10535  GPUStaticInst*
10537  {
10538  fatal("Trying to decode instruction without a class\n");
10539  return nullptr;
10540  }
10541 
10542  GPUStaticInst*
10544  {
10545  fatal("Trying to decode instruction without a class\n");
10546  return nullptr;
10547  }
10548 
10549  GPUStaticInst*
10551  {
10552  fatal("Trying to decode instruction without a class\n");
10553  return nullptr;
10554  }
10555 
10556  GPUStaticInst*
10558  {
10559  fatal("Trying to decode instruction without a class\n");
10560  return nullptr;
10561  }
10562 
10563  GPUStaticInst*
10565  {
10566  fatal("Trying to decode instruction without a class\n");
10567  return nullptr;
10568  }
10569 
10570  GPUStaticInst*
10572  {
10573  fatal("Trying to decode instruction without a class\n");
10574  return nullptr;
10575  }
10576 
10577  GPUStaticInst*
10579  {
10580  fatal("Trying to decode instruction without a class\n");
10581  return nullptr;
10582  }
10583 
10584  GPUStaticInst*
10586  {
10587  fatal("Trying to decode instruction without a class\n");
10588  return nullptr;
10589  }
10590 
10591  GPUStaticInst*
10593  {
10594  fatal("Trying to decode instruction without a class\n");
10595  return nullptr;
10596  }
10597 
10598  GPUStaticInst*
10600  {
10601  fatal("Trying to decode instruction without a class\n");
10602  return nullptr;
10603  }
10604 
10605  GPUStaticInst*
10607  {
10608  return new Inst_SOP1__S_MOV_B32(&iFmt->iFmt_SOP1);
10609  } // decode_OP_SOP1__S_MOV_B32
10610 
10611  GPUStaticInst*
10613  {
10614  return new Inst_SOP1__S_MOV_B64(&iFmt->iFmt_SOP1);
10615  } // decode_OP_SOP1__S_MOV_B64
10616 
10617  GPUStaticInst*
10619  {
10620  return new Inst_SOP1__S_CMOV_B32(&iFmt->iFmt_SOP1);
10621  } // decode_OP_SOP1__S_CMOV_B32
10622 
10623  GPUStaticInst*
10625  {
10626  return new Inst_SOP1__S_CMOV_B64(&iFmt->iFmt_SOP1);
10627  } // decode_OP_SOP1__S_CMOV_B64
10628 
10629  GPUStaticInst*
10631  {
10632  return new Inst_SOP1__S_NOT_B32(&iFmt->iFmt_SOP1);
10633  } // decode_OP_SOP1__S_NOT_B32
10634 
10635  GPUStaticInst*
10637  {
10638  return new Inst_SOP1__S_NOT_B64(&iFmt->iFmt_SOP1);
10639  } // decode_OP_SOP1__S_NOT_B64
10640 
10641  GPUStaticInst*
10643  {
10644  return new Inst_SOP1__S_WQM_B32(&iFmt->iFmt_SOP1);
10645  } // decode_OP_SOP1__S_WQM_B32
10646 
10647  GPUStaticInst*
10649  {
10650  return new Inst_SOP1__S_WQM_B64(&iFmt->iFmt_SOP1);
10651  } // decode_OP_SOP1__S_WQM_B64
10652 
10653  GPUStaticInst*
10655  {
10656  return new Inst_SOP1__S_BREV_B32(&iFmt->iFmt_SOP1);
10657  } // decode_OP_SOP1__S_BREV_B32
10658 
10659  GPUStaticInst*
10661  {
10662  return new Inst_SOP1__S_BREV_B64(&iFmt->iFmt_SOP1);
10663  } // decode_OP_SOP1__S_BREV_B64
10664 
10665  GPUStaticInst*
10667  {
10668  return new Inst_SOP1__S_BCNT0_I32_B32(&iFmt->iFmt_SOP1);
10669  } // decode_OP_SOP1__S_BCNT0_I32_B32
10670 
10671  GPUStaticInst*
10673  {
10674  return new Inst_SOP1__S_BCNT0_I32_B64(&iFmt->iFmt_SOP1);
10675  } // decode_OP_SOP1__S_BCNT0_I32_B64
10676 
10677  GPUStaticInst*
10679  {
10680  return new Inst_SOP1__S_BCNT1_I32_B32(&iFmt->iFmt_SOP1);
10681  } // decode_OP_SOP1__S_BCNT1_I32_B32
10682 
10683  GPUStaticInst*
10685  {
10686  return new Inst_SOP1__S_BCNT1_I32_B64(&iFmt->iFmt_SOP1);
10687  } // decode_OP_SOP1__S_BCNT1_I32_B64
10688 
10689  GPUStaticInst*
10691  {
10692  return new Inst_SOP1__S_FF0_I32_B32(&iFmt->iFmt_SOP1);
10693  } // decode_OP_SOP1__S_FF0_I32_B32
10694 
10695  GPUStaticInst*
10697  {
10698  return new Inst_SOP1__S_FF0_I32_B64(&iFmt->iFmt_SOP1);
10699  } // decode_OP_SOP1__S_FF0_I32_B64
10700 
10701  GPUStaticInst*
10703  {
10704  return new Inst_SOP1__S_FF1_I32_B32(&iFmt->iFmt_SOP1);
10705  } // decode_OP_SOP1__S_FF1_I32_B32
10706 
10707  GPUStaticInst*
10709  {
10710  return new Inst_SOP1__S_FF1_I32_B64(&iFmt->iFmt_SOP1);
10711  } // decode_OP_SOP1__S_FF1_I32_B64
10712 
10713  GPUStaticInst*
10715  {
10716  return new Inst_SOP1__S_FLBIT_I32_B32(&iFmt->iFmt_SOP1);
10717  } // decode_OP_SOP1__S_FLBIT_I32_B32
10718 
10719  GPUStaticInst*
10721  {
10722  return new Inst_SOP1__S_FLBIT_I32_B64(&iFmt->iFmt_SOP1);
10723  } // decode_OP_SOP1__S_FLBIT_I32_B64
10724 
10725  GPUStaticInst*
10727  {
10728  return new Inst_SOP1__S_FLBIT_I32(&iFmt->iFmt_SOP1);
10729  } // decode_OP_SOP1__S_FLBIT_I32
10730 
10731  GPUStaticInst*
10733  {
10734  return new Inst_SOP1__S_FLBIT_I32_I64(&iFmt->iFmt_SOP1);
10735  } // decode_OP_SOP1__S_FLBIT_I32_I64
10736 
10737  GPUStaticInst*
10739  {
10740  return new Inst_SOP1__S_SEXT_I32_I8(&iFmt->iFmt_SOP1);
10741  } // decode_OP_SOP1__S_SEXT_I32_I8
10742 
10743  GPUStaticInst*
10745  {
10746  return new Inst_SOP1__S_SEXT_I32_I16(&iFmt->iFmt_SOP1);
10747  } // decode_OP_SOP1__S_SEXT_I32_I16
10748 
10749  GPUStaticInst*
10751  {
10752  return new Inst_SOP1__S_BITSET0_B32(&iFmt->iFmt_SOP1);
10753  } // decode_OP_SOP1__S_BITSET0_B32
10754 
10755  GPUStaticInst*
10757  {
10758  return new Inst_SOP1__S_BITSET0_B64(&iFmt->iFmt_SOP1);
10759  } // decode_OP_SOP1__S_BITSET0_B64
10760 
10761  GPUStaticInst*
10763  {
10764  return new Inst_SOP1__S_BITSET1_B32(&iFmt->iFmt_SOP1);
10765  } // decode_OP_SOP1__S_BITSET1_B32
10766 
10767  GPUStaticInst*
10769  {
10770  return new Inst_SOP1__S_BITSET1_B64(&iFmt->iFmt_SOP1);
10771  } // decode_OP_SOP1__S_BITSET1_B64
10772 
10773  GPUStaticInst*
10775  {
10776  return new Inst_SOP1__S_GETPC_B64(&iFmt->iFmt_SOP1);
10777  } // decode_OP_SOP1__S_GETPC_B64
10778 
10779  GPUStaticInst*
10781  {
10782  return new Inst_SOP1__S_SETPC_B64(&iFmt->iFmt_SOP1);
10783  } // decode_OP_SOP1__S_SETPC_B64
10784 
10785  GPUStaticInst*
10787  {
10788  return new Inst_SOP1__S_SWAPPC_B64(&iFmt->iFmt_SOP1);
10789  } // decode_OP_SOP1__S_SWAPPC_B64
10790 
10791  GPUStaticInst*
10793  {
10794  return new Inst_SOP1__S_RFE_B64(&iFmt->iFmt_SOP1);
10795  } // decode_OP_SOP1__S_RFE_B64
10796 
10797  GPUStaticInst*
10799  {
10800  return new Inst_SOP1__S_AND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10801  } // decode_OP_SOP1__S_AND_SAVEEXEC_B64
10802 
10803  GPUStaticInst*
10805  {
10806  return new Inst_SOP1__S_OR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10807  } // decode_OP_SOP1__S_OR_SAVEEXEC_B64
10808 
10809  GPUStaticInst*
10811  {
10812  return new Inst_SOP1__S_XOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10813  } // decode_OP_SOP1__S_XOR_SAVEEXEC_B64
10814 
10815  GPUStaticInst*
10817  {
10818  return new Inst_SOP1__S_ANDN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10819  } // decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
10820 
10821  GPUStaticInst*
10823  {
10824  return new Inst_SOP1__S_ORN2_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10825  } // decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
10826 
10827  GPUStaticInst*
10829  {
10830  return new Inst_SOP1__S_NAND_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10831  } // decode_OP_SOP1__S_NAND_SAVEEXEC_B64
10832 
10833  GPUStaticInst*
10835  {
10836  return new Inst_SOP1__S_NOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10837  } // decode_OP_SOP1__S_NOR_SAVEEXEC_B64
10838 
10839  GPUStaticInst*
10841  {
10842  return new Inst_SOP1__S_XNOR_SAVEEXEC_B64(&iFmt->iFmt_SOP1);
10843  } // decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
10844 
10845  GPUStaticInst*
10847  {
10848  return new Inst_SOP1__S_QUADMASK_B32(&iFmt->iFmt_SOP1);
10849  } // decode_OP_SOP1__S_QUADMASK_B32
10850 
10851  GPUStaticInst*
10853  {
10854  return new Inst_SOP1__S_QUADMASK_B64(&iFmt->iFmt_SOP1);
10855  } // decode_OP_SOP1__S_QUADMASK_B64
10856 
10857  GPUStaticInst*
10859  {
10860  return new Inst_SOP1__S_MOVRELS_B32(&iFmt->iFmt_SOP1);
10861  } // decode_OP_SOP1__S_MOVRELS_B32
10862 
10863  GPUStaticInst*
10865  {
10866  return new Inst_SOP1__S_MOVRELS_B64(&iFmt->iFmt_SOP1);
10867  } // decode_OP_SOP1__S_MOVRELS_B64
10868 
10869  GPUStaticInst*
10871  {
10872  return new Inst_SOP1__S_MOVRELD_B32(&iFmt->iFmt_SOP1);
10873  } // decode_OP_SOP1__S_MOVRELD_B32
10874 
10875  GPUStaticInst*
10877  {
10878  return new Inst_SOP1__S_MOVRELD_B64(&iFmt->iFmt_SOP1);
10879  } // decode_OP_SOP1__S_MOVRELD_B64
10880 
10881  GPUStaticInst*
10883  {
10884  return new Inst_SOP1__S_CBRANCH_JOIN(&iFmt->iFmt_SOP1);
10885  } // decode_OP_SOP1__S_CBRANCH_JOIN
10886 
10887  GPUStaticInst*
10889  {
10890  return new Inst_SOP1__S_ABS_I32(&iFmt->iFmt_SOP1);
10891  } // decode_OP_SOP1__S_ABS_I32
10892 
10893  GPUStaticInst*
10895  {
10896  return new Inst_SOP1__S_SET_GPR_IDX_IDX(&iFmt->iFmt_SOP1);
10897  } // decode_OP_SOP1__S_SET_GPR_IDX_IDX
10898 
10899  GPUStaticInst*
10901  {
10902  fatal("Trying to decode instruction without a class\n");
10903  return nullptr;
10904  }
10905 
10906  GPUStaticInst*
10908  {
10909  fatal("Trying to decode instruction without a class\n");
10910  return nullptr;
10911  }
10912 
10913  GPUStaticInst*
10915  {
10916  fatal("Trying to decode instruction without a class\n");
10917  return nullptr;
10918  }
10919 
10920  GPUStaticInst*
10922  {
10923  fatal("Trying to decode instruction without a class\n");
10924  return nullptr;
10925  }
10926 
10927  GPUStaticInst*
10929  {
10930  fatal("Trying to decode instruction without a class\n");
10931  return nullptr;
10932  }
10933 
10934  GPUStaticInst*
10936  {
10937  return new Inst_SOPC__S_CMP_EQ_I32(&iFmt->iFmt_SOPC);
10938  } // decode_OP_SOPC__S_CMP_EQ_I32
10939 
10940  GPUStaticInst*
10942  {
10943  return new Inst_SOPC__S_CMP_LG_I32(&iFmt->iFmt_SOPC);
10944  } // decode_OP_SOPC__S_CMP_LG_I32
10945 
10946  GPUStaticInst*
10948  {
10949  return new Inst_SOPC__S_CMP_GT_I32(&iFmt->iFmt_SOPC);
10950  } // decode_OP_SOPC__S_CMP_GT_I32
10951 
10952  GPUStaticInst*
10954  {
10955  return new Inst_SOPC__S_CMP_GE_I32(&iFmt->iFmt_SOPC);
10956  } // decode_OP_SOPC__S_CMP_GE_I32
10957 
10958  GPUStaticInst*
10960  {
10961  return new Inst_SOPC__S_CMP_LT_I32(&iFmt->iFmt_SOPC);
10962  } // decode_OP_SOPC__S_CMP_LT_I32
10963 
10964  GPUStaticInst*
10966  {
10967  return new Inst_SOPC__S_CMP_LE_I32(&iFmt->iFmt_SOPC);
10968  } // decode_OP_SOPC__S_CMP_LE_I32
10969 
10970  GPUStaticInst*
10972  {
10973  return new Inst_SOPC__S_CMP_EQ_U32(&iFmt->iFmt_SOPC);
10974  } // decode_OP_SOPC__S_CMP_EQ_U32
10975 
10976  GPUStaticInst*
10978  {
10979  return new Inst_SOPC__S_CMP_LG_U32(&iFmt->iFmt_SOPC);
10980  } // decode_OP_SOPC__S_CMP_LG_U32
10981 
10982  GPUStaticInst*
10984  {
10985  return new Inst_SOPC__S_CMP_GT_U32(&iFmt->iFmt_SOPC);
10986  } // decode_OP_SOPC__S_CMP_GT_U32
10987 
10988  GPUStaticInst*
10990  {
10991  return new Inst_SOPC__S_CMP_GE_U32(&iFmt->iFmt_SOPC);
10992  } // decode_OP_SOPC__S_CMP_GE_U32
10993 
10994  GPUStaticInst*
10996  {
10997  return new Inst_SOPC__S_CMP_LT_U32(&iFmt->iFmt_SOPC);
10998  } // decode_OP_SOPC__S_CMP_LT_U32
10999 
11000  GPUStaticInst*
11002  {
11003  return new Inst_SOPC__S_CMP_LE_U32(&iFmt->iFmt_SOPC);
11004  } // decode_OP_SOPC__S_CMP_LE_U32
11005 
11006  GPUStaticInst*
11008  {
11009  return new Inst_SOPC__S_BITCMP0_B32(&iFmt->iFmt_SOPC);
11010  } // decode_OP_SOPC__S_BITCMP0_B32
11011 
11012  GPUStaticInst*
11014  {
11015  return new Inst_SOPC__S_BITCMP1_B32(&iFmt->iFmt_SOPC);
11016  } // decode_OP_SOPC__S_BITCMP1_B32
11017 
11018  GPUStaticInst*
11020  {
11021  return new Inst_SOPC__S_BITCMP0_B64(&iFmt->iFmt_SOPC);
11022  } // decode_OP_SOPC__S_BITCMP0_B64
11023 
11024  GPUStaticInst*
11026  {
11027  return new Inst_SOPC__S_BITCMP1_B64(&iFmt->iFmt_SOPC);
11028  } // decode_OP_SOPC__S_BITCMP1_B64
11029 
11030  GPUStaticInst*
11032  {
11033  return new Inst_SOPC__S_SETVSKIP(&iFmt->iFmt_SOPC);
11034  } // decode_OP_SOPC__S_SETVSKIP
11035 
11036  GPUStaticInst*
11038  {
11039  return new Inst_SOPC__S_SET_GPR_IDX_ON(&iFmt->iFmt_SOPC);
11040  } // decode_OP_SOPC__S_SET_GPR_IDX_ON
11041 
11042  GPUStaticInst*
11044  {
11045  return new Inst_SOPC__S_CMP_EQ_U64(&iFmt->iFmt_SOPC);
11046  } // decode_OP_SOPC__S_CMP_EQ_U64
11047 
11048  GPUStaticInst*
11050  {
11051  return new Inst_SOPC__S_CMP_LG_U64(&iFmt->iFmt_SOPC);
11052  } // decode_OP_SOPC__S_CMP_LG_U64
11053 
11054  GPUStaticInst*
11056  {
11057  return new Inst_SOPP__S_NOP(&iFmt->iFmt_SOPP);
11058  } // decode_OP_SOPP__S_NOP
11059 
11060  GPUStaticInst*
11062  {
11063  return new Inst_SOPP__S_ENDPGM(&iFmt->iFmt_SOPP);
11064  } // decode_OP_SOPP__S_ENDPGM
11065 
11066  GPUStaticInst*
11068  {
11069  return new Inst_SOPP__S_BRANCH(&iFmt->iFmt_SOPP);
11070  } // decode_OP_SOPP__S_BRANCH
11071 
11072  GPUStaticInst*
11074  {
11075  return new Inst_SOPP__S_WAKEUP(&iFmt->iFmt_SOPP);
11076  } // decode_OP_SOPP__S_WAKEUP
11077 
11078  GPUStaticInst*
11080  {
11081  return new Inst_SOPP__S_CBRANCH_SCC0(&iFmt->iFmt_SOPP);
11082  } // decode_OP_SOPP__S_CBRANCH_SCC0
11083 
11084  GPUStaticInst*
11086  {
11087  return new Inst_SOPP__S_CBRANCH_SCC1(&iFmt->iFmt_SOPP);
11088  } // decode_OP_SOPP__S_CBRANCH_SCC1
11089 
11090  GPUStaticInst*
11092  {
11093  return new Inst_SOPP__S_CBRANCH_VCCZ(&iFmt->iFmt_SOPP);
11094  } // decode_OP_SOPP__S_CBRANCH_VCCZ
11095 
11096  GPUStaticInst*
11098  {
11099  return new Inst_SOPP__S_CBRANCH_VCCNZ(&iFmt->iFmt_SOPP);
11100  } // decode_OP_SOPP__S_CBRANCH_VCCNZ
11101 
11102  GPUStaticInst*
11104  {
11105  return new Inst_SOPP__S_CBRANCH_EXECZ(&iFmt->iFmt_SOPP);
11106  } // decode_OP_SOPP__S_CBRANCH_EXECZ
11107 
11108  GPUStaticInst*
11110  {
11111  return new Inst_SOPP__S_CBRANCH_EXECNZ(&iFmt->iFmt_SOPP);
11112  } // decode_OP_SOPP__S_CBRANCH_EXECNZ
11113 
11114  GPUStaticInst*
11116  {
11117  return new Inst_SOPP__S_BARRIER(&iFmt->iFmt_SOPP);
11118  } // decode_OP_SOPP__S_BARRIER
11119 
11120  GPUStaticInst*
11122  {
11123  return new Inst_SOPP__S_SETKILL(&iFmt->iFmt_SOPP);
11124  } // decode_OP_SOPP__S_SETKILL
11125 
11126  GPUStaticInst*
11128  {
11129  return new Inst_SOPP__S_WAITCNT(&iFmt->iFmt_SOPP);
11130  } // decode_OP_SOPP__S_WAITCNT
11131 
11132  GPUStaticInst*
11134  {
11135  return new Inst_SOPP__S_SETHALT(&iFmt->iFmt_SOPP);
11136  } // decode_OP_SOPP__S_SETHALT
11137 
11138  GPUStaticInst*
11140  {
11141  return new Inst_SOPP__S_SLEEP(&iFmt->iFmt_SOPP);
11142  } // decode_OP_SOPP__S_SLEEP
11143 
11144  GPUStaticInst*
11146  {
11147  return new Inst_SOPP__S_SETPRIO(&iFmt->iFmt_SOPP);
11148  } // decode_OP_SOPP__S_SETPRIO
11149 
11150  GPUStaticInst*
11152  {
11153  return new Inst_SOPP__S_SENDMSG(&iFmt->iFmt_SOPP);
11154  } // decode_OP_SOPP__S_SENDMSG
11155 
11156  GPUStaticInst*
11158  {
11159  return new Inst_SOPP__S_SENDMSGHALT(&iFmt->iFmt_SOPP);
11160  } // decode_OP_SOPP__S_SENDMSGHALT
11161 
11162  GPUStaticInst*
11164  {
11165  return new Inst_SOPP__S_TRAP(&iFmt->iFmt_SOPP);
11166  } // decode_OP_SOPP__S_TRAP
11167 
11168  GPUStaticInst*
11170  {
11171  return new Inst_SOPP__S_ICACHE_INV(&iFmt->iFmt_SOPP);
11172  } // decode_OP_SOPP__S_ICACHE_INV
11173 
11174  GPUStaticInst*
11176  {
11177  return new Inst_SOPP__S_INCPERFLEVEL(&iFmt->iFmt_SOPP);
11178  } // decode_OP_SOPP__S_INCPERFLEVEL
11179 
11180  GPUStaticInst*
11182  {
11183  return new Inst_SOPP__S_DECPERFLEVEL(&iFmt->iFmt_SOPP);
11184  } // decode_OP_SOPP__S_DECPERFLEVEL
11185 
11186  GPUStaticInst*
11188  {
11189  return new Inst_SOPP__S_TTRACEDATA(&iFmt->iFmt_SOPP);
11190  } // decode_OP_SOPP__S_TTRACEDATA
11191 
11192  GPUStaticInst*
11194  {
11195  return new Inst_SOPP__S_CBRANCH_CDBGSYS(&iFmt->iFmt_SOPP);
11196  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS
11197 
11198  GPUStaticInst*
11200  {
11201  return new Inst_SOPP__S_CBRANCH_CDBGUSER(&iFmt->iFmt_SOPP);
11202  } // decode_OP_SOPP__S_CBRANCH_CDBGUSER
11203 
11204  GPUStaticInst*
11206  {
11208  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
11209 
11210  GPUStaticInst*
11212  {
11214  } // decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
11215 
11216  GPUStaticInst*
11218  {
11219  return new Inst_SOPP__S_ENDPGM_SAVED(&iFmt->iFmt_SOPP);
11220  } // decode_OP_SOPP__S_ENDPGM_SAVED
11221 
11222  GPUStaticInst*
11224  {
11225  return new Inst_SOPP__S_SET_GPR_IDX_OFF(&iFmt->iFmt_SOPP);
11226  } // decode_OP_SOPP__S_SET_GPR_IDX_OFF
11227 
11228  GPUStaticInst*
11230  {
11231  return new Inst_SOPP__S_SET_GPR_IDX_MODE(&iFmt->iFmt_SOPP);
11232  } // decode_OP_SOPP__S_SET_GPR_IDX_MODE
11233 
11234  GPUStaticInst*
11236  {
11237  fatal("Trying to decode instruction without a class\n");
11238  return nullptr;
11239  }
11240 
11241  GPUStaticInst*
11243  {
11244  return new Inst_VINTRP__V_INTERP_P1_F32(&iFmt->iFmt_VINTRP);
11245  } // decode_OP_VINTRP__V_INTERP_P1_F32
11246 
11247  GPUStaticInst*
11249  {
11250  return new Inst_VINTRP__V_INTERP_P2_F32(&iFmt->iFmt_VINTRP);
11251  } // decode_OP_VINTRP__V_INTERP_P2_F32
11252 
11253  GPUStaticInst*
11255  {
11256  return new Inst_VINTRP__V_INTERP_MOV_F32(&iFmt->iFmt_VINTRP);
11257  } // decode_OP_VINTRP__V_INTERP_MOV_F32
11258 
11259  GPUStaticInst*
11261  {
11262  return new Inst_VOP1__V_NOP(&iFmt->iFmt_VOP1);
11263  } // decode_OP_VOP1__V_NOP
11264 
11265  GPUStaticInst*
11267  {
11268  return new Inst_VOP1__V_MOV_B32(&iFmt->iFmt_VOP1);
11269  } // decode_OP_VOP1__V_MOV_B32
11270 
11271  GPUStaticInst*
11273  {
11274  return new Inst_VOP1__V_READFIRSTLANE_B32(&iFmt->iFmt_VOP1);
11275  } // decode_OP_VOP1__V_READFIRSTLANE_B32
11276 
11277  GPUStaticInst*
11279  {
11280  return new Inst_VOP1__V_CVT_I32_F64(&iFmt->iFmt_VOP1);
11281  } // decode_OP_VOP1__V_CVT_I32_F64
11282 
11283  GPUStaticInst*
11285  {
11286  return new Inst_VOP1__V_CVT_F64_I32(&iFmt->iFmt_VOP1);
11287  } // decode_OP_VOP1__V_CVT_F64_I32
11288 
11289  GPUStaticInst*
11291  {
11292  return new Inst_VOP1__V_CVT_F32_I32(&iFmt->iFmt_VOP1);
11293  } // decode_OP_VOP1__V_CVT_F32_I32
11294 
11295  GPUStaticInst*
11297  {
11298  return new Inst_VOP1__V_CVT_F32_U32(&iFmt->iFmt_VOP1);
11299  } // decode_OP_VOP1__V_CVT_F32_U32
11300 
11301  GPUStaticInst*
11303  {
11304  return new Inst_VOP1__V_CVT_U32_F32(&iFmt->iFmt_VOP1);
11305  } // decode_OP_VOP1__V_CVT_U32_F32
11306 
11307  GPUStaticInst*
11309  {
11310  return new Inst_VOP1__V_CVT_I32_F32(&iFmt->iFmt_VOP1);
11311  } // decode_OP_VOP1__V_CVT_I32_F32
11312 
11313  GPUStaticInst*
11315  {
11316  return new Inst_VOP1__V_CVT_F16_F32(&iFmt->iFmt_VOP1);
11317  } // decode_OP_VOP1__V_CVT_F16_F32
11318 
11319  GPUStaticInst*
11321  {
11322  return new Inst_VOP1__V_CVT_F32_F16(&iFmt->iFmt_VOP1);
11323  } // decode_OP_VOP1__V_CVT_F32_F16
11324 
11325  GPUStaticInst*
11327  {
11328  return new Inst_VOP1__V_CVT_RPI_I32_F32(&iFmt->iFmt_VOP1);
11329  } // decode_OP_VOP1__V_CVT_RPI_I32_F32
11330 
11331  GPUStaticInst*
11333  {
11334  return new Inst_VOP1__V_CVT_FLR_I32_F32(&iFmt->iFmt_VOP1);
11335  } // decode_OP_VOP1__V_CVT_FLR_I32_F32
11336 
11337  GPUStaticInst*
11339  {
11340  return new Inst_VOP1__V_CVT_OFF_F32_I4(&iFmt->iFmt_VOP1);
11341  } // decode_OP_VOP1__V_CVT_OFF_F32_I4
11342 
11343  GPUStaticInst*
11345  {
11346  return new Inst_VOP1__V_CVT_F32_F64(&iFmt->iFmt_VOP1);
11347  } // decode_OP_VOP1__V_CVT_F32_F64
11348 
11349  GPUStaticInst*
11351  {
11352  return new Inst_VOP1__V_CVT_F64_F32(&iFmt->iFmt_VOP1);
11353  } // decode_OP_VOP1__V_CVT_F64_F32
11354 
11355  GPUStaticInst*
11357  {
11358  return new Inst_VOP1__V_CVT_F32_UBYTE0(&iFmt->iFmt_VOP1);
11359  } // decode_OP_VOP1__V_CVT_F32_UBYTE0
11360 
11361  GPUStaticInst*
11363  {
11364  return new Inst_VOP1__V_CVT_F32_UBYTE1(&iFmt->iFmt_VOP1);
11365  } // decode_OP_VOP1__V_CVT_F32_UBYTE1
11366 
11367  GPUStaticInst*
11369  {
11370  return new Inst_VOP1__V_CVT_F32_UBYTE2(&iFmt->iFmt_VOP1);
11371  } // decode_OP_VOP1__V_CVT_F32_UBYTE2
11372 
11373  GPUStaticInst*
11375  {
11376  return new Inst_VOP1__V_CVT_F32_UBYTE3(&iFmt->iFmt_VOP1);
11377  } // decode_OP_VOP1__V_CVT_F32_UBYTE3
11378 
11379  GPUStaticInst*
11381  {
11382  return new Inst_VOP1__V_CVT_U32_F64(&iFmt->iFmt_VOP1);
11383  } // decode_OP_VOP1__V_CVT_U32_F64
11384 
11385  GPUStaticInst*
11387  {
11388  return new Inst_VOP1__V_CVT_F64_U32(&iFmt->iFmt_VOP1);
11389  } // decode_OP_VOP1__V_CVT_F64_U32
11390 
11391  GPUStaticInst*
11393  {
11394  return new Inst_VOP1__V_TRUNC_F64(&iFmt->iFmt_VOP1);
11395  } // decode_OP_VOP1__V_TRUNC_F64
11396 
11397  GPUStaticInst*
11399  {
11400  return new Inst_VOP1__V_CEIL_F64(&iFmt->iFmt_VOP1);
11401  } // decode_OP_VOP1__V_CEIL_F64
11402 
11403  GPUStaticInst*
11405  {
11406  return new Inst_VOP1__V_RNDNE_F64(&iFmt->iFmt_VOP1);
11407  } // decode_OP_VOP1__V_RNDNE_F64
11408 
11409  GPUStaticInst*
11411  {
11412  return new Inst_VOP1__V_FLOOR_F64(&iFmt->iFmt_VOP1);
11413  } // decode_OP_VOP1__V_FLOOR_F64
11414 
11415  GPUStaticInst*
11417  {
11418  return new Inst_VOP1__V_FRACT_F32(&iFmt->iFmt_VOP1);
11419  } // decode_OP_VOP1__V_FRACT_F32
11420 
11421  GPUStaticInst*
11423  {
11424  return new Inst_VOP1__V_TRUNC_F32(&iFmt->iFmt_VOP1);
11425  } // decode_OP_VOP1__V_TRUNC_F32
11426 
11427  GPUStaticInst*
11429  {
11430  return new Inst_VOP1__V_CEIL_F32(&iFmt->iFmt_VOP1);
11431  } // decode_OP_VOP1__V_CEIL_F32
11432 
11433  GPUStaticInst*
11435  {
11436  return new Inst_VOP1__V_RNDNE_F32(&iFmt->iFmt_VOP1);
11437  } // decode_OP_VOP1__V_RNDNE_F32
11438 
11439  GPUStaticInst*
11441  {
11442  return new Inst_VOP1__V_FLOOR_F32(&iFmt->iFmt_VOP1);
11443  } // decode_OP_VOP1__V_FLOOR_F32
11444 
11445  GPUStaticInst*
11447  {
11448  return new Inst_VOP1__V_EXP_F32(&iFmt->iFmt_VOP1);
11449  } // decode_OP_VOP1__V_EXP_F32
11450 
11451  GPUStaticInst*
11453  {
11454  return new Inst_VOP1__V_LOG_F32(&iFmt->iFmt_VOP1);
11455  } // decode_OP_VOP1__V_LOG_F32
11456 
11457  GPUStaticInst*
11459  {
11460  return new Inst_VOP1__V_RCP_F32(&iFmt->iFmt_VOP1);
11461  } // decode_OP_VOP1__V_RCP_F32
11462 
11463  GPUStaticInst*
11465  {
11466  return new Inst_VOP1__V_RCP_IFLAG_F32(&iFmt->iFmt_VOP1);
11467  } // decode_OP_VOP1__V_RCP_IFLAG_F32
11468 
11469  GPUStaticInst*
11471  {
11472  return new Inst_VOP1__V_RSQ_F32(&iFmt->iFmt_VOP1);
11473  } // decode_OP_VOP1__V_RSQ_F32
11474 
11475  GPUStaticInst*
11477  {
11478  return new Inst_VOP1__V_RCP_F64(&iFmt->iFmt_VOP1);
11479  } // decode_OP_VOP1__V_RCP_F64
11480 
11481  GPUStaticInst*
11483  {
11484  return new Inst_VOP1__V_RSQ_F64(&iFmt->iFmt_VOP1);
11485  } // decode_OP_VOP1__V_RSQ_F64
11486 
11487  GPUStaticInst*
11489  {
11490  return new Inst_VOP1__V_SQRT_F32(&iFmt->iFmt_VOP1);
11491  } // decode_OP_VOP1__V_SQRT_F32
11492 
11493  GPUStaticInst*
11495  {
11496  return new Inst_VOP1__V_SQRT_F64(&iFmt->iFmt_VOP1);
11497  } // decode_OP_VOP1__V_SQRT_F64
11498 
11499  GPUStaticInst*
11501  {
11502  return new Inst_VOP1__V_SIN_F32(&iFmt->iFmt_VOP1);
11503  } // decode_OP_VOP1__V_SIN_F32
11504 
11505  GPUStaticInst*
11507  {
11508  return new Inst_VOP1__V_COS_F32(&iFmt->iFmt_VOP1);
11509  } // decode_OP_VOP1__V_COS_F32
11510 
11511  GPUStaticInst*
11513  {
11514  return new Inst_VOP1__V_NOT_B32(&iFmt->iFmt_VOP1);
11515  } // decode_OP_VOP1__V_NOT_B32
11516 
11517  GPUStaticInst*
11519  {
11520  return new Inst_VOP1__V_BFREV_B32(&iFmt->iFmt_VOP1);
11521  } // decode_OP_VOP1__V_BFREV_B32
11522 
11523  GPUStaticInst*
11525  {
11526  return new Inst_VOP1__V_FFBH_U32(&iFmt->iFmt_VOP1);
11527  } // decode_OP_VOP1__V_FFBH_U32
11528 
11529  GPUStaticInst*
11531  {
11532  return new Inst_VOP1__V_FFBL_B32(&iFmt->iFmt_VOP1);
11533  } // decode_OP_VOP1__V_FFBL_B32
11534 
11535  GPUStaticInst*
11537  {
11538  return new Inst_VOP1__V_FFBH_I32(&iFmt->iFmt_VOP1);
11539  } // decode_OP_VOP1__V_FFBH_I32
11540 
11541  GPUStaticInst*
11543  {
11544  return new Inst_VOP1__V_FREXP_EXP_I32_F64(&iFmt->iFmt_VOP1);
11545  } // decode_OP_VOP1__V_FREXP_EXP_I32_F64
11546 
11547  GPUStaticInst*
11549  {
11550  return new Inst_VOP1__V_FREXP_MANT_F64(&iFmt->iFmt_VOP1);
11551  } // decode_OP_VOP1__V_FREXP_MANT_F64
11552 
11553  GPUStaticInst*
11555  {
11556  return new Inst_VOP1__V_FRACT_F64(&iFmt->iFmt_VOP1);
11557  } // decode_OP_VOP1__V_FRACT_F64
11558 
11559  GPUStaticInst*
11561  {
11562  return new Inst_VOP1__V_FREXP_EXP_I32_F32(&iFmt->iFmt_VOP1);
11563  } // decode_OP_VOP1__V_FREXP_EXP_I32_F32
11564 
11565  GPUStaticInst*
11567  {
11568  return new Inst_VOP1__V_FREXP_MANT_F32(&iFmt->iFmt_VOP1);
11569  } // decode_OP_VOP1__V_FREXP_MANT_F32
11570 
11571  GPUStaticInst*
11573  {
11574  return new Inst_VOP1__V_CLREXCP(&iFmt->iFmt_VOP1);
11575  } // decode_OP_VOP1__V_CLREXCP
11576 
11577  GPUStaticInst*
11579  {
11580  fatal("Trying to decode instruction without a class\n");
11581  return nullptr;
11582  }
11583 
11584  GPUStaticInst*
11586  {
11587  return new Inst_VOP1__V_CVT_F16_U16(&iFmt->iFmt_VOP1);
11588  } // decode_OP_VOP1__V_CVT_F16_U16
11589 
11590  GPUStaticInst*
11592  {
11593  return new Inst_VOP1__V_CVT_F16_I16(&iFmt->iFmt_VOP1);
11594  } // decode_OP_VOP1__V_CVT_F16_I16
11595 
11596  GPUStaticInst*
11598  {
11599  return new Inst_VOP1__V_CVT_U16_F16(&iFmt->iFmt_VOP1);
11600  } // decode_OP_VOP1__V_CVT_U16_F16
11601 
11602  GPUStaticInst*
11604  {
11605  return new Inst_VOP1__V_CVT_I16_F16(&iFmt->iFmt_VOP1);
11606  } // decode_OP_VOP1__V_CVT_I16_F16
11607 
11608  GPUStaticInst*
11610  {
11611  return new Inst_VOP1__V_RCP_F16(&iFmt->iFmt_VOP1);
11612  } // decode_OP_VOP1__V_RCP_F16
11613 
11614  GPUStaticInst*
11616  {
11617  return new Inst_VOP1__V_SQRT_F16(&iFmt->iFmt_VOP1);
11618  } // decode_OP_VOP1__V_SQRT_F16
11619 
11620  GPUStaticInst*
11622  {
11623  return new Inst_VOP1__V_RSQ_F16(&iFmt->iFmt_VOP1);
11624  } // decode_OP_VOP1__V_RSQ_F16
11625 
11626  GPUStaticInst*
11628  {
11629  return new Inst_VOP1__V_LOG_F16(&iFmt->iFmt_VOP1);
11630  } // decode_OP_VOP1__V_LOG_F16
11631 
11632  GPUStaticInst*
11634  {
11635  return new Inst_VOP1__V_EXP_F16(&iFmt->iFmt_VOP1);
11636  } // decode_OP_VOP1__V_EXP_F16
11637 
11638  GPUStaticInst*
11640  {
11641  return new Inst_VOP1__V_FREXP_MANT_F16(&iFmt->iFmt_VOP1);
11642  } // decode_OP_VOP1__V_FREXP_MANT_F16
11643 
11644  GPUStaticInst*
11646  {
11647  return new Inst_VOP1__V_FREXP_EXP_I16_F16(&iFmt->iFmt_VOP1);
11648  } // decode_OP_VOP1__V_FREXP_EXP_I16_F16
11649 
11650  GPUStaticInst*
11652  {
11653  return new Inst_VOP1__V_FLOOR_F16(&iFmt->iFmt_VOP1);
11654  } // decode_OP_VOP1__V_FLOOR_F16
11655 
11656  GPUStaticInst*
11658  {
11659  return new Inst_VOP1__V_CEIL_F16(&iFmt->iFmt_VOP1);
11660  } // decode_OP_VOP1__V_CEIL_F16
11661 
11662  GPUStaticInst*
11664  {
11665  return new Inst_VOP1__V_TRUNC_F16(&iFmt->iFmt_VOP1);
11666  } // decode_OP_VOP1__V_TRUNC_F16
11667 
11668  GPUStaticInst*
11670  {
11671  return new Inst_VOP1__V_RNDNE_F16(&iFmt->iFmt_VOP1);
11672  } // decode_OP_VOP1__V_RNDNE_F16
11673 
11674  GPUStaticInst*
11676  {
11677  return new Inst_VOP1__V_FRACT_F16(&iFmt->iFmt_VOP1);
11678  } // decode_OP_VOP1__V_FRACT_F16
11679 
11680  GPUStaticInst*
11682  {
11683  return new Inst_VOP1__V_SIN_F16(&iFmt->iFmt_VOP1);
11684  } // decode_OP_VOP1__V_SIN_F16
11685 
11686  GPUStaticInst*
11688  {
11689  return new Inst_VOP1__V_COS_F16(&iFmt->iFmt_VOP1);
11690  } // decode_OP_VOP1__V_COS_F16
11691 
11692  GPUStaticInst*
11694  {
11695  return new Inst_VOP1__V_EXP_LEGACY_F32(&iFmt->iFmt_VOP1);
11696  } // decode_OP_VOP1__V_EXP_LEGACY_F32
11697 
11698  GPUStaticInst*
11700  {
11701  return new Inst_VOP1__V_LOG_LEGACY_F32(&iFmt->iFmt_VOP1);
11702  } // decode_OP_VOP1__V_LOG_LEGACY_F32
11703 
11704  GPUStaticInst*
11706  {
11707  fatal("Trying to decode instruction without a class\n");
11708  return nullptr;
11709  }
11710 
11711  GPUStaticInst*
11713  {
11714  fatal("Trying to decode instruction without a class\n");
11715  return nullptr;
11716  }
11717 
11718  GPUStaticInst*
11720  {
11721  fatal("Trying to decode instruction without a class\n");
11722  return nullptr;
11723  }
11724 
11725  GPUStaticInst*
11727  {
11728  fatal("Trying to decode instruction without a class\n");
11729  return nullptr;
11730  }
11731 
11732  GPUStaticInst*
11734  {
11735  return new Inst_VOPC__V_CMP_CLASS_F32(&iFmt->iFmt_VOPC);
11736  } // decode_OP_VOPC__V_CMP_CLASS_F32
11737 
11738  GPUStaticInst*
11740  {
11741  return new Inst_VOPC__V_CMPX_CLASS_F32(&iFmt->iFmt_VOPC);
11742  } // decode_OP_VOPC__V_CMPX_CLASS_F32
11743 
11744  GPUStaticInst*
11746  {
11747  return new Inst_VOPC__V_CMP_CLASS_F64(&iFmt->iFmt_VOPC);
11748  } // decode_OP_VOPC__V_CMP_CLASS_F64
11749 
11750  GPUStaticInst*
11752  {
11753  return new Inst_VOPC__V_CMPX_CLASS_F64(&iFmt->iFmt_VOPC);
11754  } // decode_OP_VOPC__V_CMPX_CLASS_F64
11755 
11756  GPUStaticInst*
11758  {
11759  return new Inst_VOPC__V_CMP_CLASS_F16(&iFmt->iFmt_VOPC);
11760  } // decode_OP_VOPC__V_CMP_CLASS_F16
11761 
11762  GPUStaticInst*
11764  {
11765  return new Inst_VOPC__V_CMPX_CLASS_F16(&iFmt->iFmt_VOPC);
11766  } // decode_OP_VOPC__V_CMPX_CLASS_F16
11767 
11768  GPUStaticInst*
11770  {
11771  return new Inst_VOPC__V_CMP_F_F16(&iFmt->iFmt_VOPC);
11772  } // decode_OP_VOPC__V_CMP_F_F16
11773 
11774  GPUStaticInst*
11776  {
11777  return new Inst_VOPC__V_CMP_LT_F16(&iFmt->iFmt_VOPC);
11778  } // decode_OP_VOPC__V_CMP_LT_F16
11779 
11780  GPUStaticInst*
11782  {
11783  return new Inst_VOPC__V_CMP_EQ_F16(&iFmt->iFmt_VOPC);
11784  } // decode_OP_VOPC__V_CMP_EQ_F16
11785 
11786  GPUStaticInst*
11788  {
11789  return new Inst_VOPC__V_CMP_LE_F16(&iFmt->iFmt_VOPC);
11790  } // decode_OP_VOPC__V_CMP_LE_F16
11791 
11792  GPUStaticInst*
11794  {
11795  return new Inst_VOPC__V_CMP_GT_F16(&iFmt->iFmt_VOPC);
11796  } // decode_OP_VOPC__V_CMP_GT_F16
11797 
11798  GPUStaticInst*
11800  {
11801  return new Inst_VOPC__V_CMP_LG_F16(&iFmt->iFmt_VOPC);
11802  } // decode_OP_VOPC__V_CMP_LG_F16
11803 
11804  GPUStaticInst*
11806  {
11807  return new Inst_VOPC__V_CMP_GE_F16(&iFmt->iFmt_VOPC);
11808  } // decode_OP_VOPC__V_CMP_GE_F16
11809 
11810  GPUStaticInst*
11812  {
11813  return new Inst_VOPC__V_CMP_O_F16(&iFmt->iFmt_VOPC);
11814  } // decode_OP_VOPC__V_CMP_O_F16
11815 
11816  GPUStaticInst*
11818  {
11819  return new Inst_VOPC__V_CMP_U_F16(&iFmt->iFmt_VOPC);
11820  } // decode_OP_VOPC__V_CMP_U_F16
11821 
11822  GPUStaticInst*
11824  {
11825  return new Inst_VOPC__V_CMP_NGE_F16(&iFmt->iFmt_VOPC);
11826  } // decode_OP_VOPC__V_CMP_NGE_F16
11827 
11828  GPUStaticInst*
11830  {
11831  return new Inst_VOPC__V_CMP_NLG_F16(&iFmt->iFmt_VOPC);
11832  } // decode_OP_VOPC__V_CMP_NLG_F16
11833 
11834  GPUStaticInst*
11836  {
11837  return new Inst_VOPC__V_CMP_NGT_F16(&iFmt->iFmt_VOPC);
11838  } // decode_OP_VOPC__V_CMP_NGT_F16
11839 
11840  GPUStaticInst*
11842  {
11843  return new Inst_VOPC__V_CMP_NLE_F16(&iFmt->iFmt_VOPC);
11844  } // decode_OP_VOPC__V_CMP_NLE_F16
11845 
11846  GPUStaticInst*
11848  {
11849  return new Inst_VOPC__V_CMP_NEQ_F16(&iFmt->iFmt_VOPC);
11850  } // decode_OP_VOPC__V_CMP_NEQ_F16
11851 
11852  GPUStaticInst*
11854  {
11855  return new Inst_VOPC__V_CMP_NLT_F16(&iFmt->iFmt_VOPC);
11856  } // decode_OP_VOPC__V_CMP_NLT_F16
11857 
11858  GPUStaticInst*
11860  {
11861  return new Inst_VOPC__V_CMP_TRU_F16(&iFmt->iFmt_VOPC);
11862  } // decode_OP_VOPC__V_CMP_TRU_F16
11863 
11864  GPUStaticInst*
11866  {
11867  return new Inst_VOPC__V_CMPX_F_F16(&iFmt->iFmt_VOPC);
11868  } // decode_OP_VOPC__V_CMPX_F_F16
11869 
11870  GPUStaticInst*
11872  {
11873  return new Inst_VOPC__V_CMPX_LT_F16(&iFmt->iFmt_VOPC);
11874  } // decode_OP_VOPC__V_CMPX_LT_F16
11875 
11876  GPUStaticInst*
11878  {
11879  return new Inst_VOPC__V_CMPX_EQ_F16(&iFmt->iFmt_VOPC);
11880  } // decode_OP_VOPC__V_CMPX_EQ_F16
11881 
11882  GPUStaticInst*
11884  {
11885  return new Inst_VOPC__V_CMPX_LE_F16(&iFmt->iFmt_VOPC);
11886  } // decode_OP_VOPC__V_CMPX_LE_F16
11887 
11888  GPUStaticInst*
11890  {
11891  return new Inst_VOPC__V_CMPX_GT_F16(&iFmt->iFmt_VOPC);
11892  } // decode_OP_VOPC__V_CMPX_GT_F16
11893 
11894  GPUStaticInst*
11896  {
11897  return new Inst_VOPC__V_CMPX_LG_F16(&iFmt->iFmt_VOPC);
11898  } // decode_OP_VOPC__V_CMPX_LG_F16
11899 
11900  GPUStaticInst*
11902  {
11903  return new Inst_VOPC__V_CMPX_GE_F16(&iFmt->iFmt_VOPC);
11904  } // decode_OP_VOPC__V_CMPX_GE_F16
11905 
11906  GPUStaticInst*
11908  {
11909  return new Inst_VOPC__V_CMPX_O_F16(&iFmt->iFmt_VOPC);
11910  } // decode_OP_VOPC__V_CMPX_O_F16
11911 
11912  GPUStaticInst*
11914  {
11915  return new Inst_VOPC__V_CMPX_U_F16(&iFmt->iFmt_VOPC);
11916  } // decode_OP_VOPC__V_CMPX_U_F16
11917 
11918  GPUStaticInst*
11920  {
11921  return new Inst_VOPC__V_CMPX_NGE_F16(&iFmt->iFmt_VOPC);
11922  } // decode_OP_VOPC__V_CMPX_NGE_F16
11923 
11924  GPUStaticInst*
11926  {
11927  return new Inst_VOPC__V_CMPX_NLG_F16(&iFmt->iFmt_VOPC);
11928  } // decode_OP_VOPC__V_CMPX_NLG_F16
11929 
11930  GPUStaticInst*
11932  {
11933  return new Inst_VOPC__V_CMPX_NGT_F16(&iFmt->iFmt_VOPC);
11934  } // decode_OP_VOPC__V_CMPX_NGT_F16
11935 
11936  GPUStaticInst*
11938  {
11939  return new Inst_VOPC__V_CMPX_NLE_F16(&iFmt->iFmt_VOPC);
11940  } // decode_OP_VOPC__V_CMPX_NLE_F16
11941 
11942  GPUStaticInst*
11944  {
11945  return new Inst_VOPC__V_CMPX_NEQ_F16(&iFmt->iFmt_VOPC);
11946  } // decode_OP_VOPC__V_CMPX_NEQ_F16
11947 
11948  GPUStaticInst*
11950  {
11951  return new Inst_VOPC__V_CMPX_NLT_F16(&iFmt->iFmt_VOPC);
11952  } // decode_OP_VOPC__V_CMPX_NLT_F16
11953 
11954  GPUStaticInst*
11956  {
11957  return new Inst_VOPC__V_CMPX_TRU_F16(&iFmt->iFmt_VOPC);
11958  } // decode_OP_VOPC__V_CMPX_TRU_F16
11959 
11960  GPUStaticInst*
11962  {
11963  return new Inst_VOPC__V_CMP_F_F32(&iFmt->iFmt_VOPC);
11964  } // decode_OP_VOPC__V_CMP_F_F32
11965 
11966  GPUStaticInst*
11968  {
11969  return new Inst_VOPC__V_CMP_LT_F32(&iFmt->iFmt_VOPC);
11970  } // decode_OP_VOPC__V_CMP_LT_F32
11971 
11972  GPUStaticInst*
11974  {
11975  return new Inst_VOPC__V_CMP_EQ_F32(&iFmt->iFmt_VOPC);
11976  } // decode_OP_VOPC__V_CMP_EQ_F32
11977 
11978  GPUStaticInst*
11980  {
11981  return new Inst_VOPC__V_CMP_LE_F32(&iFmt->iFmt_VOPC);
11982  } // decode_OP_VOPC__V_CMP_LE_F32
11983 
11984  GPUStaticInst*
11986  {
11987  return new Inst_VOPC__V_CMP_GT_F32(&iFmt->iFmt_VOPC);
11988  } // decode_OP_VOPC__V_CMP_GT_F32
11989 
11990  GPUStaticInst*
11992  {
11993  return new Inst_VOPC__V_CMP_LG_F32(&iFmt->iFmt_VOPC);
11994  } // decode_OP_VOPC__V_CMP_LG_F32
11995 
11996  GPUStaticInst*
11998  {
11999  return new Inst_VOPC__V_CMP_GE_F32(&iFmt->iFmt_VOPC);
12000  } // decode_OP_VOPC__V_CMP_GE_F32
12001 
12002  GPUStaticInst*
12004  {
12005  return new Inst_VOPC__V_CMP_O_F32(&iFmt->iFmt_VOPC);
12006  } // decode_OP_VOPC__V_CMP_O_F32
12007 
12008  GPUStaticInst*
12010  {
12011  return new Inst_VOPC__V_CMP_U_F32(&iFmt->iFmt_VOPC);
12012  } // decode_OP_VOPC__V_CMP_U_F32
12013 
12014  GPUStaticInst*
12016  {
12017  return new Inst_VOPC__V_CMP_NGE_F32(&iFmt->iFmt_VOPC);
12018  } // decode_OP_VOPC__V_CMP_NGE_F32
12019 
12020  GPUStaticInst*
12022  {
12023  return new Inst_VOPC__V_CMP_NLG_F32(&iFmt->iFmt_VOPC);
12024  } // decode_OP_VOPC__V_CMP_NLG_F32
12025 
12026  GPUStaticInst*
12028  {
12029  return new Inst_VOPC__V_CMP_NGT_F32(&iFmt->iFmt_VOPC);
12030  } // decode_OP_VOPC__V_CMP_NGT_F32
12031 
12032  GPUStaticInst*
12034  {
12035  return new Inst_VOPC__V_CMP_NLE_F32(&iFmt->iFmt_VOPC);
12036  } // decode_OP_VOPC__V_CMP_NLE_F32
12037 
12038  GPUStaticInst*
12040  {
12041  return new Inst_VOPC__V_CMP_NEQ_F32(&iFmt->iFmt_VOPC);
12042  } // decode_OP_VOPC__V_CMP_NEQ_F32
12043 
12044  GPUStaticInst*
12046  {
12047  return new Inst_VOPC__V_CMP_NLT_F32(&iFmt->iFmt_VOPC);
12048  } // decode_OP_VOPC__V_CMP_NLT_F32
12049 
12050  GPUStaticInst*
12052  {
12053  return new Inst_VOPC__V_CMP_TRU_F32(&iFmt->iFmt_VOPC);
12054  } // decode_OP_VOPC__V_CMP_TRU_F32
12055 
12056  GPUStaticInst*
12058  {
12059  return new Inst_VOPC__V_CMPX_F_F32(&iFmt->iFmt_VOPC);
12060  } // decode_OP_VOPC__V_CMPX_F_F32
12061 
12062  GPUStaticInst*
12064  {
12065  return new Inst_VOPC__V_CMPX_LT_F32(&iFmt->iFmt_VOPC);
12066  } // decode_OP_VOPC__V_CMPX_LT_F32
12067 
12068  GPUStaticInst*
12070  {
12071  return new Inst_VOPC__V_CMPX_EQ_F32(&iFmt->iFmt_VOPC);
12072  } // decode_OP_VOPC__V_CMPX_EQ_F32
12073 
12074  GPUStaticInst*
12076  {
12077  return new Inst_VOPC__V_CMPX_LE_F32(&iFmt->iFmt_VOPC);
12078  } // decode_OP_VOPC__V_CMPX_LE_F32
12079 
12080  GPUStaticInst*
12082  {
12083  return new Inst_VOPC__V_CMPX_GT_F32(&iFmt->iFmt_VOPC);
12084  } // decode_OP_VOPC__V_CMPX_GT_F32
12085 
12086  GPUStaticInst*
12088  {
12089  return new Inst_VOPC__V_CMPX_LG_F32(&iFmt->iFmt_VOPC);
12090  } // decode_OP_VOPC__V_CMPX_LG_F32
12091 
12092  GPUStaticInst*
12094  {
12095  return new Inst_VOPC__V_CMPX_GE_F32(&iFmt->iFmt_VOPC);
12096  } // decode_OP_VOPC__V_CMPX_GE_F32
12097 
12098  GPUStaticInst*
12100  {
12101  return new Inst_VOPC__V_CMPX_O_F32(&iFmt->iFmt_VOPC);
12102  } // decode_OP_VOPC__V_CMPX_O_F32
12103 
12104  GPUStaticInst*
12106  {
12107  return new Inst_VOPC__V_CMPX_U_F32(&iFmt->iFmt_VOPC);
12108  } // decode_OP_VOPC__V_CMPX_U_F32
12109 
12110  GPUStaticInst*
12112  {
12113  return new Inst_VOPC__V_CMPX_NGE_F32(&iFmt->iFmt_VOPC);
12114  } // decode_OP_VOPC__V_CMPX_NGE_F32
12115 
12116  GPUStaticInst*
12118  {
12119  return new Inst_VOPC__V_CMPX_NLG_F32(&iFmt->iFmt_VOPC);
12120  } // decode_OP_VOPC__V_CMPX_NLG_F32
12121 
12122  GPUStaticInst*
12124  {
12125  return new Inst_VOPC__V_CMPX_NGT_F32(&iFmt->iFmt_VOPC);
12126  } // decode_OP_VOPC__V_CMPX_NGT_F32
12127 
12128  GPUStaticInst*
12130  {
12131  return new Inst_VOPC__V_CMPX_NLE_F32(&iFmt->iFmt_VOPC);
12132  } // decode_OP_VOPC__V_CMPX_NLE_F32
12133 
12134  GPUStaticInst*
12136  {
12137  return new Inst_VOPC__V_CMPX_NEQ_F32(&iFmt->iFmt_VOPC);
12138  } // decode_OP_VOPC__V_CMPX_NEQ_F32
12139 
12140  GPUStaticInst*
12142  {
12143  return new Inst_VOPC__V_CMPX_NLT_F32(&iFmt->iFmt_VOPC);
12144  } // decode_OP_VOPC__V_CMPX_NLT_F32
12145 
12146  GPUStaticInst*
12148  {
12149  return new Inst_VOPC__V_CMPX_TRU_F32(&iFmt->iFmt_VOPC);
12150  } // decode_OP_VOPC__V_CMPX_TRU_F32
12151 
12152  GPUStaticInst*
12154  {
12155  return new Inst_VOPC__V_CMP_F_F64(&iFmt->iFmt_VOPC);
12156  } // decode_OP_VOPC__V_CMP_F_F64
12157 
12158  GPUStaticInst*
12160  {
12161  return new Inst_VOPC__V_CMP_LT_F64(&iFmt->iFmt_VOPC);
12162  } // decode_OP_VOPC__V_CMP_LT_F64
12163 
12164  GPUStaticInst*
12166  {
12167  return new Inst_VOPC__V_CMP_EQ_F64(&iFmt->iFmt_VOPC);
12168  } // decode_OP_VOPC__V_CMP_EQ_F64
12169 
12170  GPUStaticInst*
12172  {
12173  return new Inst_VOPC__V_CMP_LE_F64(&iFmt->iFmt_VOPC);
12174  } // decode_OP_VOPC__V_CMP_LE_F64
12175 
12176  GPUStaticInst*
12178  {
12179  return new Inst_VOPC__V_CMP_GT_F64(&iFmt->iFmt_VOPC);
12180  } // decode_OP_VOPC__V_CMP_GT_F64
12181 
12182  GPUStaticInst*
12184  {
12185  return new Inst_VOPC__V_CMP_LG_F64(&iFmt->iFmt_VOPC);
12186  } // decode_OP_VOPC__V_CMP_LG_F64
12187 
12188  GPUStaticInst*
12190  {
12191  return new Inst_VOPC__V_CMP_GE_F64(&iFmt->iFmt_VOPC);
12192  } // decode_OP_VOPC__V_CMP_GE_F64
12193 
12194  GPUStaticInst*
12196  {
12197  return new Inst_VOPC__V_CMP_O_F64(&iFmt->iFmt_VOPC);
12198  } // decode_OP_VOPC__V_CMP_O_F64
12199 
12200  GPUStaticInst*
12202  {
12203  return new Inst_VOPC__V_CMP_U_F64(&iFmt->iFmt_VOPC);
12204  } // decode_OP_VOPC__V_CMP_U_F64
12205 
12206  GPUStaticInst*
12208  {
12209  return new Inst_VOPC__V_CMP_NGE_F64(&iFmt->iFmt_VOPC);
12210  } // decode_OP_VOPC__V_CMP_NGE_F64
12211 
12212  GPUStaticInst*
12214  {
12215  return new Inst_VOPC__V_CMP_NLG_F64(&iFmt->iFmt_VOPC);
12216  } // decode_OP_VOPC__V_CMP_NLG_F64
12217 
12218  GPUStaticInst*
12220  {
12221  return new Inst_VOPC__V_CMP_NGT_F64(&iFmt->iFmt_VOPC);
12222  } // decode_OP_VOPC__V_CMP_NGT_F64
12223 
12224  GPUStaticInst*
12226  {
12227  return new Inst_VOPC__V_CMP_NLE_F64(&iFmt->iFmt_VOPC);
12228  } // decode_OP_VOPC__V_CMP_NLE_F64
12229 
12230  GPUStaticInst*
12232  {
12233  return new Inst_VOPC__V_CMP_NEQ_F64(&iFmt->iFmt_VOPC);
12234  } // decode_OP_VOPC__V_CMP_NEQ_F64
12235 
12236  GPUStaticInst*
12238  {
12239  return new Inst_VOPC__V_CMP_NLT_F64(&iFmt->iFmt_VOPC);
12240  } // decode_OP_VOPC__V_CMP_NLT_F64
12241 
12242  GPUStaticInst*
12244  {
12245  return new Inst_VOPC__V_CMP_TRU_F64(&iFmt->iFmt_VOPC);
12246  } // decode_OP_VOPC__V_CMP_TRU_F64
12247 
12248  GPUStaticInst*
12250  {
12251  return new Inst_VOPC__V_CMPX_F_F64(&iFmt->iFmt_VOPC);
12252  } // decode_OP_VOPC__V_CMPX_F_F64
12253 
12254  GPUStaticInst*
12256  {
12257  return new Inst_VOPC__V_CMPX_LT_F64(&iFmt->iFmt_VOPC);
12258  } // decode_OP_VOPC__V_CMPX_LT_F64
12259 
12260  GPUStaticInst*
12262  {
12263  return new Inst_VOPC__V_CMPX_EQ_F64(&iFmt->iFmt_VOPC);
12264  } // decode_OP_VOPC__V_CMPX_EQ_F64
12265 
12266  GPUStaticInst*
12268  {
12269  return new Inst_VOPC__V_CMPX_LE_F64(&iFmt->iFmt_VOPC);
12270  } // decode_OP_VOPC__V_CMPX_LE_F64
12271 
12272  GPUStaticInst*
12274  {
12275  return new Inst_VOPC__V_CMPX_GT_F64(&iFmt->iFmt_VOPC);
12276  } // decode_OP_VOPC__V_CMPX_GT_F64
12277 
12278  GPUStaticInst*
12280  {
12281  return new Inst_VOPC__V_CMPX_LG_F64(&iFmt->iFmt_VOPC);
12282  } // decode_OP_VOPC__V_CMPX_LG_F64
12283 
12284  GPUStaticInst*
12286  {
12287  return new Inst_VOPC__V_CMPX_GE_F64(&iFmt->iFmt_VOPC);
12288  } // decode_OP_VOPC__V_CMPX_GE_F64
12289 
12290  GPUStaticInst*
12292  {
12293  return new Inst_VOPC__V_CMPX_O_F64(&iFmt->iFmt_VOPC);
12294  } // decode_OP_VOPC__V_CMPX_O_F64
12295 
12296  GPUStaticInst*
12298  {
12299  return new Inst_VOPC__V_CMPX_U_F64(&iFmt->iFmt_VOPC);
12300  } // decode_OP_VOPC__V_CMPX_U_F64
12301 
12302  GPUStaticInst*
12304  {
12305  return new Inst_VOPC__V_CMPX_NGE_F64(&iFmt->iFmt_VOPC);
12306  } // decode_OP_VOPC__V_CMPX_NGE_F64
12307 
12308  GPUStaticInst*
12310  {
12311  return new Inst_VOPC__V_CMPX_NLG_F64(&iFmt->iFmt_VOPC);
12312  } // decode_OP_VOPC__V_CMPX_NLG_F64
12313 
12314  GPUStaticInst*
12316  {
12317  return new Inst_VOPC__V_CMPX_NGT_F64(&iFmt->iFmt_VOPC);
12318  } // decode_OP_VOPC__V_CMPX_NGT_F64
12319 
12320  GPUStaticInst*
12322  {
12323  return new Inst_VOPC__V_CMPX_NLE_F64(&iFmt->iFmt_VOPC);
12324  } // decode_OP_VOPC__V_CMPX_NLE_F64
12325 
12326  GPUStaticInst*
12328  {
12329  return new Inst_VOPC__V_CMPX_NEQ_F64(&iFmt->iFmt_VOPC);
12330  } // decode_OP_VOPC__V_CMPX_NEQ_F64
12331 
12332  GPUStaticInst*
12334  {
12335  return new Inst_VOPC__V_CMPX_NLT_F64(&iFmt->iFmt_VOPC);
12336  } // decode_OP_VOPC__V_CMPX_NLT_F64
12337 
12338  GPUStaticInst*
12340  {
12341  return new Inst_VOPC__V_CMPX_TRU_F64(&iFmt->iFmt_VOPC);
12342  } // decode_OP_VOPC__V_CMPX_TRU_F64
12343 
12344  GPUStaticInst*
12346  {
12347  return new Inst_VOPC__V_CMP_F_I16(&iFmt->iFmt_VOPC);
12348  } // decode_OP_VOPC__V_CMP_F_I16
12349 
12350  GPUStaticInst*
12352  {
12353  return new Inst_VOPC__V_CMP_LT_I16(&iFmt->iFmt_VOPC);
12354  } // decode_OP_VOPC__V_CMP_LT_I16
12355 
12356  GPUStaticInst*
12358  {
12359  return new Inst_VOPC__V_CMP_EQ_I16(&iFmt->iFmt_VOPC);
12360  } // decode_OP_VOPC__V_CMP_EQ_I16
12361 
12362  GPUStaticInst*
12364  {
12365  return new Inst_VOPC__V_CMP_LE_I16(&iFmt->iFmt_VOPC);
12366  } // decode_OP_VOPC__V_CMP_LE_I16
12367 
12368  GPUStaticInst*
12370  {
12371  return new Inst_VOPC__V_CMP_GT_I16(&iFmt->iFmt_VOPC);
12372  } // decode_OP_VOPC__V_CMP_GT_I16
12373 
12374  GPUStaticInst*
12376  {
12377  return new Inst_VOPC__V_CMP_NE_I16(&iFmt->iFmt_VOPC);
12378  } // decode_OP_VOPC__V_CMP_NE_I16
12379 
12380  GPUStaticInst*
12382  {
12383  return new Inst_VOPC__V_CMP_GE_I16(&iFmt->iFmt_VOPC);
12384  } // decode_OP_VOPC__V_CMP_GE_I16
12385 
12386  GPUStaticInst*
12388  {
12389  return new Inst_VOPC__V_CMP_T_I16(&iFmt->iFmt_VOPC);
12390  } // decode_OP_VOPC__V_CMP_T_I16
12391 
12392  GPUStaticInst*
12394  {
12395  return new Inst_VOPC__V_CMP_F_U16(&iFmt->iFmt_VOPC);
12396  } // decode_OP_VOPC__V_CMP_F_U16
12397 
12398  GPUStaticInst*
12400  {
12401  return new Inst_VOPC__V_CMP_LT_U16(&iFmt->iFmt_VOPC);
12402  } // decode_OP_VOPC__V_CMP_LT_U16
12403 
12404  GPUStaticInst*
12406  {
12407  return new Inst_VOPC__V_CMP_EQ_U16(&iFmt->iFmt_VOPC);
12408  } // decode_OP_VOPC__V_CMP_EQ_U16
12409 
12410  GPUStaticInst*
12412  {
12413  return new Inst_VOPC__V_CMP_LE_U16(&iFmt->iFmt_VOPC);
12414  } // decode_OP_VOPC__V_CMP_LE_U16
12415 
12416  GPUStaticInst*
12418  {
12419  return new Inst_VOPC__V_CMP_GT_U16(&iFmt->iFmt_VOPC);
12420  } // decode_OP_VOPC__V_CMP_GT_U16
12421 
12422  GPUStaticInst*
12424  {
12425  return new Inst_VOPC__V_CMP_NE_U16(&iFmt->iFmt_VOPC);
12426  } // decode_OP_VOPC__V_CMP_NE_U16
12427 
12428  GPUStaticInst*
12430  {
12431  return new Inst_VOPC__V_CMP_GE_U16(&iFmt->iFmt_VOPC);
12432  } // decode_OP_VOPC__V_CMP_GE_U16
12433 
12434  GPUStaticInst*
12436  {
12437  return new Inst_VOPC__V_CMP_T_U16(&iFmt->iFmt_VOPC);
12438  } // decode_OP_VOPC__V_CMP_T_U16
12439 
12440  GPUStaticInst*
12442  {
12443  return new Inst_VOPC__V_CMPX_F_I16(&iFmt->iFmt_VOPC);
12444  } // decode_OP_VOPC__V_CMPX_F_I16
12445 
12446  GPUStaticInst*
12448  {
12449  return new Inst_VOPC__V_CMPX_LT_I16(&iFmt->iFmt_VOPC);
12450  } // decode_OP_VOPC__V_CMPX_LT_I16
12451 
12452  GPUStaticInst*
12454  {
12455  return new Inst_VOPC__V_CMPX_EQ_I16(&iFmt->iFmt_VOPC);
12456  } // decode_OP_VOPC__V_CMPX_EQ_I16
12457 
12458  GPUStaticInst*
12460  {
12461  return new Inst_VOPC__V_CMPX_LE_I16(&iFmt->iFmt_VOPC);
12462  } // decode_OP_VOPC__V_CMPX_LE_I16
12463 
12464  GPUStaticInst*
12466  {
12467  return new Inst_VOPC__V_CMPX_GT_I16(&iFmt->iFmt_VOPC);
12468  } // decode_OP_VOPC__V_CMPX_GT_I16
12469 
12470  GPUStaticInst*
12472  {
12473  return new Inst_VOPC__V_CMPX_NE_I16(&iFmt->iFmt_VOPC);
12474  } // decode_OP_VOPC__V_CMPX_NE_I16
12475 
12476  GPUStaticInst*
12478  {
12479  return new Inst_VOPC__V_CMPX_GE_I16(&iFmt->iFmt_VOPC);
12480  } // decode_OP_VOPC__V_CMPX_GE_I16
12481 
12482  GPUStaticInst*
12484  {
12485  return new Inst_VOPC__V_CMPX_T_I16(&iFmt->iFmt_VOPC);
12486  } // decode_OP_VOPC__V_CMPX_T_I16
12487 
12488  GPUStaticInst*
12490  {
12491  return new Inst_VOPC__V_CMPX_F_U16(&iFmt->iFmt_VOPC);
12492  } // decode_OP_VOPC__V_CMPX_F_U16
12493 
12494  GPUStaticInst*
12496  {
12497  return new Inst_VOPC__V_CMPX_LT_U16(&iFmt->iFmt_VOPC);
12498  } // decode_OP_VOPC__V_CMPX_LT_U16
12499 
12500  GPUStaticInst*
12502  {
12503  return new Inst_VOPC__V_CMPX_EQ_U16(&iFmt->iFmt_VOPC);
12504  } // decode_OP_VOPC__V_CMPX_EQ_U16
12505 
12506  GPUStaticInst*
12508  {
12509  return new Inst_VOPC__V_CMPX_LE_U16(&iFmt->iFmt_VOPC);
12510  } // decode_OP_VOPC__V_CMPX_LE_U16
12511 
12512  GPUStaticInst*
12514  {
12515  return new Inst_VOPC__V_CMPX_GT_U16(&iFmt->iFmt_VOPC);
12516  } // decode_OP_VOPC__V_CMPX_GT_U16
12517 
12518  GPUStaticInst*
12520  {
12521  return new Inst_VOPC__V_CMPX_NE_U16(&iFmt->iFmt_VOPC);
12522  } // decode_OP_VOPC__V_CMPX_NE_U16
12523 
12524  GPUStaticInst*
12526  {
12527  return new Inst_VOPC__V_CMPX_GE_U16(&iFmt->iFmt_VOPC);
12528  } // decode_OP_VOPC__V_CMPX_GE_U16
12529 
12530  GPUStaticInst*
12532  {
12533  return new Inst_VOPC__V_CMPX_T_U16(&iFmt->iFmt_VOPC);
12534  } // decode_OP_VOPC__V_CMPX_T_U16
12535 
12536  GPUStaticInst*
12538  {
12539  return new Inst_VOPC__V_CMP_F_I32(&iFmt->iFmt_VOPC);
12540  } // decode_OP_VOPC__V_CMP_F_I32
12541 
12542  GPUStaticInst*
12544  {
12545  return new Inst_VOPC__V_CMP_LT_I32(&iFmt->iFmt_VOPC);
12546  } // decode_OP_VOPC__V_CMP_LT_I32
12547 
12548  GPUStaticInst*
12550  {
12551  return new Inst_VOPC__V_CMP_EQ_I32(&iFmt->iFmt_VOPC);
12552  } // decode_OP_VOPC__V_CMP_EQ_I32
12553 
12554  GPUStaticInst*
12556  {
12557  return new Inst_VOPC__V_CMP_LE_I32(&iFmt->iFmt_VOPC);
12558  } // decode_OP_VOPC__V_CMP_LE_I32
12559 
12560  GPUStaticInst*
12562  {
12563  return new Inst_VOPC__V_CMP_GT_I32(&iFmt->iFmt_VOPC);
12564  } // decode_OP_VOPC__V_CMP_GT_I32
12565 
12566  GPUStaticInst*
12568  {
12569  return new Inst_VOPC__V_CMP_NE_I32(&iFmt->iFmt_VOPC);
12570  } // decode_OP_VOPC__V_CMP_NE_I32
12571 
12572  GPUStaticInst*
12574  {
12575  return new Inst_VOPC__V_CMP_GE_I32(&iFmt->iFmt_VOPC);
12576  } // decode_OP_VOPC__V_CMP_GE_I32
12577 
12578  GPUStaticInst*
12580  {
12581  return new Inst_VOPC__V_CMP_T_I32(&iFmt->iFmt_VOPC);
12582  } // decode_OP_VOPC__V_CMP_T_I32
12583 
12584  GPUStaticInst*
12586  {
12587  return new Inst_VOPC__V_CMP_F_U32(&iFmt->iFmt_VOPC);
12588  } // decode_OP_VOPC__V_CMP_F_U32
12589 
12590  GPUStaticInst*
12592  {
12593  return new Inst_VOPC__V_CMP_LT_U32(&iFmt->iFmt_VOPC);
12594  } // decode_OP_VOPC__V_CMP_LT_U32
12595 
12596  GPUStaticInst*
12598  {
12599  return new Inst_VOPC__V_CMP_EQ_U32(&iFmt->iFmt_VOPC);
12600  } // decode_OP_VOPC__V_CMP_EQ_U32
12601 
12602  GPUStaticInst*
12604  {
12605  return new Inst_VOPC__V_CMP_LE_U32(&iFmt->iFmt_VOPC);
12606  } // decode_OP_VOPC__V_CMP_LE_U32
12607 
12608  GPUStaticInst*
12610  {
12611  return new Inst_VOPC__V_CMP_GT_U32(&iFmt->iFmt_VOPC);
12612  } // decode_OP_VOPC__V_CMP_GT_U32
12613 
12614  GPUStaticInst*
12616  {
12617  return new Inst_VOPC__V_CMP_NE_U32(&iFmt->iFmt_VOPC);
12618  } // decode_OP_VOPC__V_CMP_NE_U32
12619 
12620  GPUStaticInst*
12622  {
12623  return new Inst_VOPC__V_CMP_GE_U32(&iFmt->iFmt_VOPC);
12624  } // decode_OP_VOPC__V_CMP_GE_U32
12625 
12626  GPUStaticInst*
12628  {
12629  return new Inst_VOPC__V_CMP_T_U32(&iFmt->iFmt_VOPC);
12630  } // decode_OP_VOPC__V_CMP_T_U32
12631 
12632  GPUStaticInst*
12634  {
12635  return new Inst_VOPC__V_CMPX_F_I32(&iFmt->iFmt_VOPC);
12636  } // decode_OP_VOPC__V_CMPX_F_I32
12637 
12638  GPUStaticInst*
12640  {
12641  return new Inst_VOPC__V_CMPX_LT_I32(&iFmt->iFmt_VOPC);
12642  } // decode_OP_VOPC__V_CMPX_LT_I32
12643 
12644  GPUStaticInst*
12646  {
12647  return new Inst_VOPC__V_CMPX_EQ_I32(&iFmt->iFmt_VOPC);
12648  } // decode_OP_VOPC__V_CMPX_EQ_I32
12649 
12650  GPUStaticInst*
12652  {
12653  return new Inst_VOPC__V_CMPX_LE_I32(&iFmt->iFmt_VOPC);
12654  } // decode_OP_VOPC__V_CMPX_LE_I32
12655 
12656  GPUStaticInst*
12658  {
12659  return new Inst_VOPC__V_CMPX_GT_I32(&iFmt->iFmt_VOPC);
12660  } // decode_OP_VOPC__V_CMPX_GT_I32
12661 
12662  GPUStaticInst*
12664  {
12665  return new Inst_VOPC__V_CMPX_NE_I32(&iFmt->iFmt_VOPC);
12666  } // decode_OP_VOPC__V_CMPX_NE_I32
12667 
12668  GPUStaticInst*
12670  {
12671  return new Inst_VOPC__V_CMPX_GE_I32(&iFmt->iFmt_VOPC);
12672  } // decode_OP_VOPC__V_CMPX_GE_I32
12673 
12674  GPUStaticInst*
12676  {
12677  return new Inst_VOPC__V_CMPX_T_I32(&iFmt->iFmt_VOPC);
12678  } // decode_OP_VOPC__V_CMPX_T_I32
12679 
12680  GPUStaticInst*
12682  {
12683  return new Inst_VOPC__V_CMPX_F_U32(&iFmt->iFmt_VOPC);
12684  } // decode_OP_VOPC__V_CMPX_F_U32
12685 
12686  GPUStaticInst*
12688  {
12689  return new Inst_VOPC__V_CMPX_LT_U32(&iFmt->iFmt_VOPC);
12690  } // decode_OP_VOPC__V_CMPX_LT_U32
12691 
12692  GPUStaticInst*
12694  {
12695  return new Inst_VOPC__V_CMPX_EQ_U32(&iFmt->iFmt_VOPC);
12696  } // decode_OP_VOPC__V_CMPX_EQ_U32
12697 
12698  GPUStaticInst*
12700  {
12701  return new Inst_VOPC__V_CMPX_LE_U32(&iFmt->iFmt_VOPC);
12702  } // decode_OP_VOPC__V_CMPX_LE_U32
12703 
12704  GPUStaticInst*
12706  {
12707  return new Inst_VOPC__V_CMPX_GT_U32(&iFmt->iFmt_VOPC);
12708  } // decode_OP_VOPC__V_CMPX_GT_U32
12709 
12710  GPUStaticInst*
12712  {
12713  return new Inst_VOPC__V_CMPX_NE_U32(&iFmt->iFmt_VOPC);
12714  } // decode_OP_VOPC__V_CMPX_NE_U32
12715 
12716  GPUStaticInst*
12718  {
12719  return new Inst_VOPC__V_CMPX_GE_U32(&iFmt->iFmt_VOPC);
12720  } // decode_OP_VOPC__V_CMPX_GE_U32
12721 
12722  GPUStaticInst*
12724  {
12725  return new Inst_VOPC__V_CMPX_T_U32(&iFmt->iFmt_VOPC);
12726  } // decode_OP_VOPC__V_CMPX_T_U32
12727 
12728  GPUStaticInst*
12730  {
12731  return new Inst_VOPC__V_CMP_F_I64(&iFmt->iFmt_VOPC);
12732  } // decode_OP_VOPC__V_CMP_F_I64
12733 
12734  GPUStaticInst*
12736  {
12737  return new Inst_VOPC__V_CMP_LT_I64(&iFmt->iFmt_VOPC);
12738  } // decode_OP_VOPC__V_CMP_LT_I64
12739 
12740  GPUStaticInst*
12742  {
12743  return new Inst_VOPC__V_CMP_EQ_I64(&iFmt->iFmt_VOPC);
12744  } // decode_OP_VOPC__V_CMP_EQ_I64
12745 
12746  GPUStaticInst*
12748  {
12749  return new Inst_VOPC__V_CMP_LE_I64(&iFmt->iFmt_VOPC);
12750  } // decode_OP_VOPC__V_CMP_LE_I64
12751 
12752  GPUStaticInst*
12754  {
12755  return new Inst_VOPC__V_CMP_GT_I64(&iFmt->iFmt_VOPC);
12756  } // decode_OP_VOPC__V_CMP_GT_I64
12757 
12758  GPUStaticInst*
12760  {
12761  return new Inst_VOPC__V_CMP_NE_I64(&iFmt->iFmt_VOPC);
12762  } // decode_OP_VOPC__V_CMP_NE_I64
12763 
12764  GPUStaticInst*
12766  {
12767  return new Inst_VOPC__V_CMP_GE_I64(&iFmt->iFmt_VOPC);
12768  } // decode_OP_VOPC__V_CMP_GE_I64
12769 
12770  GPUStaticInst*
12772  {
12773  return new Inst_VOPC__V_CMP_T_I64(&iFmt->iFmt_VOPC);
12774  } // decode_OP_VOPC__V_CMP_T_I64
12775 
12776  GPUStaticInst*
12778  {
12779  return new Inst_VOPC__V_CMP_F_U64(&iFmt->iFmt_VOPC);
12780  } // decode_OP_VOPC__V_CMP_F_U64
12781 
12782  GPUStaticInst*
12784  {
12785  return new Inst_VOPC__V_CMP_LT_U64(&iFmt->iFmt_VOPC);
12786  } // decode_OP_VOPC__V_CMP_LT_U64
12787 
12788  GPUStaticInst*
12790  {
12791  return new Inst_VOPC__V_CMP_EQ_U64(&iFmt->iFmt_VOPC);
12792  } // decode_OP_VOPC__V_CMP_EQ_U64
12793 
12794  GPUStaticInst*
12796  {
12797  return new Inst_VOPC__V_CMP_LE_U64(&iFmt->iFmt_VOPC);
12798  } // decode_OP_VOPC__V_CMP_LE_U64
12799 
12800  GPUStaticInst*
12802  {
12803  return new Inst_VOPC__V_CMP_GT_U64(&iFmt->iFmt_VOPC);
12804  } // decode_OP_VOPC__V_CMP_GT_U64
12805 
12806  GPUStaticInst*
12808  {
12809  return new Inst_VOPC__V_CMP_NE_U64(&iFmt->iFmt_VOPC);
12810  } // decode_OP_VOPC__V_CMP_NE_U64
12811 
12812  GPUStaticInst*
12814  {
12815  return new Inst_VOPC__V_CMP_GE_U64(&iFmt->iFmt_VOPC);
12816  } // decode_OP_VOPC__V_CMP_GE_U64
12817 
12818  GPUStaticInst*
12820  {
12821  return new Inst_VOPC__V_CMP_T_U64(&iFmt->iFmt_VOPC);
12822  } // decode_OP_VOPC__V_CMP_T_U64
12823 
12824  GPUStaticInst*
12826  {
12827  return new Inst_VOPC__V_CMPX_F_I64(&iFmt->iFmt_VOPC);
12828  } // decode_OP_VOPC__V_CMPX_F_I64
12829 
12830  GPUStaticInst*
12832  {
12833  return new Inst_VOPC__V_CMPX_LT_I64(&iFmt->iFmt_VOPC);
12834  } // decode_OP_VOPC__V_CMPX_LT_I64
12835 
12836  GPUStaticInst*
12838  {
12839  return new Inst_VOPC__V_CMPX_EQ_I64(&iFmt->iFmt_VOPC);
12840  } // decode_OP_VOPC__V_CMPX_EQ_I64
12841 
12842  GPUStaticInst*
12844  {
12845  return new Inst_VOPC__V_CMPX_LE_I64(&iFmt->iFmt_VOPC);
12846  } // decode_OP_VOPC__V_CMPX_LE_I64
12847 
12848  GPUStaticInst*
12850  {
12851  return new Inst_VOPC__V_CMPX_GT_I64(&iFmt->iFmt_VOPC);
12852  } // decode_OP_VOPC__V_CMPX_GT_I64
12853 
12854  GPUStaticInst*
12856  {
12857  return new Inst_VOPC__V_CMPX_NE_I64(&iFmt->iFmt_VOPC);
12858  } // decode_OP_VOPC__V_CMPX_NE_I64
12859 
12860  GPUStaticInst*
12862  {
12863  return new Inst_VOPC__V_CMPX_GE_I64(&iFmt->iFmt_VOPC);
12864  } // decode_OP_VOPC__V_CMPX_GE_I64
12865 
12866  GPUStaticInst*
12868  {
12869  return new Inst_VOPC__V_CMPX_T_I64(&iFmt->iFmt_VOPC);
12870  } // decode_OP_VOPC__V_CMPX_T_I64
12871 
12872  GPUStaticInst*
12874  {
12875  return new Inst_VOPC__V_CMPX_F_U64(&iFmt->iFmt_VOPC);
12876  } // decode_OP_VOPC__V_CMPX_F_U64
12877 
12878  GPUStaticInst*
12880  {
12881  return new Inst_VOPC__V_CMPX_LT_U64(&iFmt->iFmt_VOPC);
12882  } // decode_OP_VOPC__V_CMPX_LT_U64
12883 
12884  GPUStaticInst*
12886  {
12887  return new Inst_VOPC__V_CMPX_EQ_U64(&iFmt->iFmt_VOPC);
12888  } // decode_OP_VOPC__V_CMPX_EQ_U64
12889 
12890  GPUStaticInst*
12892  {
12893  return new Inst_VOPC__V_CMPX_LE_U64(&iFmt->iFmt_VOPC);
12894  } // decode_OP_VOPC__V_CMPX_LE_U64
12895 
12896  GPUStaticInst*
12898  {
12899  return new Inst_VOPC__V_CMPX_GT_U64(&iFmt->iFmt_VOPC);
12900  } // decode_OP_VOPC__V_CMPX_GT_U64
12901 
12902  GPUStaticInst*
12904  {
12905  return new Inst_VOPC__V_CMPX_NE_U64(&iFmt->iFmt_VOPC);
12906  } // decode_OP_VOPC__V_CMPX_NE_U64
12907 
12908  GPUStaticInst*
12910  {
12911  return new Inst_VOPC__V_CMPX_GE_U64(&iFmt->iFmt_VOPC);
12912  } // decode_OP_VOPC__V_CMPX_GE_U64
12913 
12914  GPUStaticInst*
12916  {
12917  return new Inst_VOPC__V_CMPX_T_U64(&iFmt->iFmt_VOPC);
12918  } // decode_OP_VOPC__V_CMPX_T_U64
12919 
12920  GPUStaticInst*
12922  {
12923  fatal("Trying to decode instruction without a class\n");
12924  return nullptr;
12925  }
12926 
12927  GPUStaticInst*
12929  {
12930  fatal("Trying to decode instruction without a class\n");
12931  return nullptr;
12932  }
12933 
12934  GPUStaticInst*
12936  {
12937  fatal("Trying to decode instruction without a class\n");
12938  return nullptr;
12939  }
12940 
12941  GPUStaticInst*
12943  {
12944  fatal("Trying to decode instruction without a class\n");
12945  return nullptr;
12946  }
12947 
12948  GPUStaticInst*
12950  {
12951  fatal("Trying to decode instruction without a class\n");
12952  return nullptr;
12953  }
12954 
12955  GPUStaticInst*
12957  {
12958  fatal("Trying to decode instruction without a class\n");
12959  return nullptr;
12960  }
12961 
12962  GPUStaticInst*
12964  {
12965  fatal("Trying to decode instruction without a class\n");
12966  return nullptr;
12967  }
12968 
12969  GPUStaticInst*
12971  {
12972  fatal("Trying to decode instruction without a class\n");
12973  return nullptr;
12974  }
12975 
12976  GPUStaticInst*
12978  {
12979  fatal("Trying to decode instruction without a class\n");
12980  return nullptr;
12981  }
12982 
12983  GPUStaticInst*
12985  {
12986  fatal("Trying to decode instruction without a class\n");
12987  return nullptr;
12988  }
12989 
12990  GPUStaticInst*
12992  {
12993  fatal("Trying to decode instruction without a class\n");
12994  return nullptr;
12995  }
12996 
12997  GPUStaticInst*
12999  {
13000  fatal("Trying to decode instruction without a class\n");
13001  return nullptr;
13002  }
13003 
13004  GPUStaticInst*
13006  {
13007  fatal("Trying to decode instruction without a class\n");
13008  return nullptr;
13009  }
13010 
13011  GPUStaticInst*
13013  {
13014  fatal("Trying to decode instruction without a class\n");
13015  return nullptr;
13016  }
13017 
13018  GPUStaticInst*
13020  {
13021  fatal("Trying to decode instruction without a class\n");
13022  return nullptr;
13023  }
13024 
13025  GPUStaticInst*
13027  {
13028  fatal("Trying to decode instruction without a class\n");
13029  return nullptr;
13030  }
13031 
13032  GPUStaticInst*
13034  {
13035  fatal("Trying to decode instruction without a class\n");
13036  return nullptr;
13037  }
13038 
13039  GPUStaticInst*
13041  {
13042  fatal("Trying to decode instruction without a class\n");
13043  return nullptr;
13044  }
13045 
13046  GPUStaticInst*
13048  {
13049  fatal("Trying to decode instruction without a class\n");
13050  return nullptr;
13051  }
13052 
13053  GPUStaticInst*
13055  {
13056  fatal("Trying to decode instruction without a class\n");
13057  return nullptr;
13058  }
13059 
13060  GPUStaticInst*
13062  {
13063  fatal("Trying to decode instruction without a class\n");
13064  return nullptr;
13065  }
13066 
13067  GPUStaticInst*
13069  {
13070  fatal("Trying to decode instruction without a class\n");
13071  return nullptr;
13072  }
13073 
13074  GPUStaticInst*
13076  {
13077  fatal("Invalid opcode encountered: %#x\n", iFmt->imm_u32);
13078 
13079  return nullptr;
13080  }
13081 } // namespace VegaISA
13082 } // namespace gem5
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8312
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:11823
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F16
GPUStaticInst * decode_OPU_VOP3__V_MUL_F16(MachInst)
Definition: decoder.cc:6062
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:42959
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16(MachInst)
Definition: decoder.cc:7769
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B64(MachInst)
Definition: decoder.cc:7895
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64
Definition: instructions.hh:16785
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8456
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8444
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSGHALT
GPUStaticInst * decode_OP_SOPP__S_SENDMSGHALT(MachInst)
Definition: decoder.cc:11157
gem5::VegaISA::Inst_SOP2__S_ADD_U32
Definition: instructions.hh:45
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_I32(MachInst)
Definition: decoder.cc:10965
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:5234
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F16
GPUStaticInst * decode_OPU_VOP3__V_LOG_F16(MachInst)
Definition: decoder.cc:6536
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC1
Definition: instructions.hh:4637
gem5::VegaISA::Inst_VOP3__V_ADD_F64
Definition: instructions.hh:30369
gem5::VegaISA::Decoder::tableSubDecode_OP_MIMG
static IsaDecodeMethod tableSubDecode_OP_MIMG[128]
Definition: gpu_decoder.hh:66
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_LOD
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_LOD(MachInst)
Definition: decoder.cc:9320
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:5420
gem5::VegaISA::Inst_VOP1__V_RNDNE_F64
Definition: instructions.hh:8897
gem5::VegaISA::Inst_VOP1__V_CLREXCP
Definition: instructions.hh:9793
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:5516
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B64
GPUStaticInst * decode_OP_SOP2__S_BFM_B64(MachInst)
Definition: decoder.cc:4434
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:12261
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_B32(MachInst)
Definition: decoder.cc:4657
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32
Definition: instructions.hh:18757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:5780
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:12573
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:12099
gem5::VegaISA::Inst_VOP3__V_MED3_I32
Definition: instructions.hh:28973
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64
Definition: instructions.hh:16513
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_P
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_P(MachInst)
Definition: decoder.cc:8075
fatal
#define fatal(...)
This implements a cprintf based fatal() function.
Definition: logging.hh:200
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F16
Definition: instructions.hh:11277
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32
Definition: instructions.hh:12467
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D
Definition: instructions.hh:39893
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B32
GPUStaticInst * decode_OP_SOP1__S_WQM_B32(MachInst)
Definition: decoder.cc:10642
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F16
Definition: instructions.hh:11175
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:12759
gem5::VegaISA::Inst_SOP2__S_OR_B64
Definition: instructions.hh:555
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U32(MachInst)
Definition: decoder.cc:10977
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U64(MachInst)
Definition: decoder.cc:8124
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:5006
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64
Definition: instructions.hh:16207
gem5::VegaISA::InFmt_VINTRP::OP
unsigned int OP
Definition: gpu_decoder.hh:1790
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_O(MachInst)
Definition: decoder.cc:9089
gem5::VegaISA::Inst_VOP3__V_BFM_B32
Definition: instructions.hh:30981
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_U16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:6494
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB_X2
Definition: instructions.hh:37729
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16
Definition: instructions.hh:14541
gem5::VegaISA::Decoder::decode_OP_SOP1__S_WQM_B64
GPUStaticInst * decode_OP_SOP1__S_WQM_B64(MachInst)
Definition: decoder.cc:10648
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SBYTE
Definition: instructions.hh:36559
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_B64(MachInst)
Definition: decoder.cc:7708
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:12231
gem5::VegaISA::Inst_VOP3__V_MED3_F32
Definition: instructions.hh:28937
gem5::VegaISA::Decoder::decode_OP_SOP1__S_OR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_OR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10804
gem5::VegaISA::Inst_VOP3__V_SQRT_F16
Definition: instructions.hh:27665
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:6548
gem5::VegaISA::Inst_DS__DS_OR_RTN_B64
Definition: instructions.hh:34081
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8492
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN_X2
Definition: instructions.hh:37801
gem5::VegaISA::Inst_VOP2__V_SUB_U32
Definition: instructions.hh:8033
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:10037
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL_O
Definition: instructions.hh:41153
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10810
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F32
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F32(MachInst)
Definition: decoder.cc:6404
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:4688
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8885
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64
Definition: instructions.hh:12943
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:12063
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B64
Definition: instructions.hh:2857
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:38317
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U64
Definition: instructions.hh:35409
gem5::VegaISA::Inst_VOP3__V_CLREXCP
Definition: instructions.hh:27477
gem5::VegaISA::Inst_VOP3__V_CEIL_F64
Definition: instructions.hh:26549
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F16
Definition: instructions.hh:18179
gem5::VegaISA::Inst_VOP3__V_MUL_LEGACY_F32
Definition: instructions.hh:24165
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_U32(MachInst)
Definition: decoder.cc:7305
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F64
GPUStaticInst * decode_OP_VOP1__V_CEIL_F64(MachInst)
Definition: decoder.cc:11398
gem5::VegaISA::Inst_VINTRP__V_INTERP_P1_F32
Definition: instructions.hh:17193
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U64
GPUStaticInst * decode_OP_SOP2__S_BFE_U64(MachInst)
Definition: decoder.cc:4458
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:5756
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8552
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX
Definition: instructions.hh:42659
gem5::VegaISA::Inst_SOP2__S_MAX_U32
Definition: instructions.hh:351
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64
Definition: instructions.hh:20015
gem5::VegaISA::Inst_DS__DS_GWS_BARRIER
Definition: instructions.hh:35191
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:12465
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:11949
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16
Definition: instructions.hh:21443
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:5618
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B64(MachInst)
Definition: decoder.cc:7190
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32
Definition: instructions.hh:15391
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX_X2
Definition: instructions.hh:37837
gem5::VegaISA::InFmt_SMEM
Definition: gpu_decoder.hh:1733
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L_O
Definition: instructions.hh:40253
gem5::VegaISA::Inst_SOP2__S_LSHR_B64
Definition: instructions.hh:1099
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64
Definition: instructions.hh:16921
gem5::VegaISA::Inst_VOP3__V_LERP_U8
Definition: instructions.hh:28613
gem5::VegaISA::Inst_DS__DS_CONSUME
Definition: instructions.hh:35223
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:9701
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_HI_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_HI_U32_B32(MachInst)
Definition: decoder.cc:7178
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9597
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B32(MachInst)
Definition: decoder.cc:10690
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9603
gem5::VegaISA::Inst_VOP3__V_MAD_U16
Definition: instructions.hh:29919
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_I64
Definition: instructions.hh:2921
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F32
Definition: instructions.hh:8321
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B32(MachInst)
Definition: decoder.cc:10678
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CBRANCH_G_FORK
GPUStaticInst * decode_OP_SOP2__S_CBRANCH_G_FORK(MachInst)
Definition: decoder.cc:4470
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SETPC_B64
GPUStaticInst * decode_OP_SOP1__S_SETPC_B64(MachInst)
Definition: decoder.cc:10780
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT(MachInst)
Definition: decoder.cc:8583
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9555
gem5::VegaISA::Inst_DS__DS_CMPST_B32
Definition: instructions.hh:31711
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_MOV_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:11254
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL
Definition: instructions.hh:41693
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:9803
gem5::VegaISA::Decoder::tableSubDecode_OP_SOP1
static IsaDecodeMethod tableSubDecode_OP_SOP1[256]
Definition: gpu_decoder.hh:71
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64
Definition: instructions.hh:17397
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORD(MachInst)
Definition: decoder.cc:8300
gem5::VegaISA::Inst_VOP1__V_SIN_F16
Definition: instructions.hh:10333
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F64
Definition: instructions.hh:8193
gem5::VegaISA::Inst_DS__DS_READ_B96
Definition: instructions.hh:35837
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16
Definition: instructions.hh:14099
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I32
Definition: instructions.hh:32209
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F32(MachInst)
Definition: decoder.cc:4958
gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32
Definition: instructions.hh:33055
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I64
Definition: instructions.hh:30913
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U32
Definition: instructions.hh:34557
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:4874
gem5::VegaISA::Inst_DS__DS_CMPST_F32
Definition: instructions.hh:31743
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F16
Definition: instructions.hh:18213
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:9773
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:11344
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I32(MachInst)
Definition: decoder.cc:12567
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F64
GPUStaticInst * decode_OPU_VOP3__V_RCP_F64(MachInst)
Definition: decoder.cc:6392
gem5::VegaISA::Inst_VOP3__V_FLOOR_F64
Definition: instructions.hh:26613
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:9951
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B32(MachInst)
Definition: decoder.cc:10870
gem5::VegaISA::Inst_VOP3__V_MAD_I32_I24
Definition: instructions.hh:28217
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F32
Definition: instructions.hh:32651
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL
Definition: instructions.hh:39857
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B64
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B64(MachInst)
Definition: decoder.cc:7943
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B32
GPUStaticInst * decode_OP_DS__DS_AND_B32(MachInst)
Definition: decoder.cc:7347
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:5204
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8615
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MOVK_I32
GPUStaticInst * decode_OP_SOPK__S_MOVK_I32(MachInst)
Definition: decoder.cc:4549
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F32
GPUStaticInst * decode_OPU_VOP3__V_SUB_F32(MachInst)
Definition: decoder.cc:5882
gem5::VegaISA::Inst_DS__DS_READ2ST64_B64
Definition: instructions.hh:34489
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F64
Definition: instructions.hh:25877
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:10319
gem5::VegaISA::Inst_DS__DS_WRITE_B8
Definition: instructions.hh:31903
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32
Definition: instructions.hh:12365
gem5::VegaISA::Decoder::subDecode_OP_SOP1
GPUStaticInst * subDecode_OP_SOP1(MachInst)
Definition: decoder.cc:3744
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F32
Definition: instructions.hh:26005
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_I16_F16(MachInst)
Definition: decoder.cc:7244
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:3893
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9471
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:12015
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B16
Definition: instructions.hh:7693
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR_X2
Definition: instructions.hh:43259
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_P
Definition: instructions.hh:35161
gem5::VegaISA::Inst_VOP3__V_BFI_B32
Definition: instructions.hh:28505
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8331
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:6236
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE
Definition: instructions.hh:41948
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_MODE
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_MODE(MachInst)
Definition: decoder.cc:11229
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F64
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F64(MachInst)
Definition: decoder.cc:11410
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCZ
Definition: instructions.hh:4667
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F64
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F64(MachInst)
Definition: decoder.cc:11392
gem5::VegaISA::Inst_VOP3__V_RSQ_F16
Definition: instructions.hh:27697
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8462
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:5270
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32
Definition: instructions.hh:15629
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F16
GPUStaticInst * decode_OP_VOP1__V_CEIL_F16(MachInst)
Definition: decoder.cc:11657
gem5::VegaISA::Inst_VOP3__V_RCP_F16
Definition: instructions.hh:27633
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10361
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U32
Definition: instructions.hh:34767
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BARRIER
GPUStaticInst * decode_OP_SOPP__S_BARRIER(MachInst)
Definition: decoder.cc:11115
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I32
GPUStaticInst * decode_OP_VOP2__V_MAX_I32(MachInst)
Definition: decoder.cc:3923
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F32
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F32(MachInst)
Definition: decoder.cc:6338
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_F16(MachInst)
Definition: decoder.cc:13033
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B64(MachInst)
Definition: decoder.cc:10864
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8366
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F64(MachInst)
Definition: decoder.cc:5102
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B8_D16_HI(MachInst)
Definition: decoder.cc:7756
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:12429
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U16(MachInst)
Definition: decoder.cc:7033
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U32(MachInst)
Definition: decoder.cc:8003
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_FED_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_FED_B32(MachInst)
Definition: decoder.cc:6224
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I64(MachInst)
Definition: decoder.cc:12729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_ADD_U32(MachInst)
Definition: decoder.cc:6991
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:12105
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9398
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10473
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B16
Definition: instructions.hh:7659
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B32
GPUStaticInst * decode_OP_DS__DS_READ2_B32(MachInst)
Definition: decoder.cc:7582
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B64
Definition: instructions.hh:35589
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:11955
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F32
Definition: instructions.hh:9761
gem5::VegaISA::Inst_SOP2__S_CSELECT_B32
Definition: instructions.hh:385
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:11380
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:12615
gem5::VegaISA::Inst_VOP2__V_MADAK_F32
Definition: instructions.hh:7025
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:11907
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10099
gem5::VegaISA::Inst_VOP3__V_ALIGNBYTE_B32
Definition: instructions.hh:28685
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64
Definition: instructions.hh:20185
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64
Definition: instructions.hh:23755
gem5::VegaISA::InstFormat::iFmt_VOP3P
InFmt_VOP3P iFmt_VOP3P
Definition: gpu_decoder.hh:1942
gem5::VegaISA::InFmt_SOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1753
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F64
Definition: instructions.hh:9665
gem5::VegaISA::Inst_SOP2__S_ASHR_I64
Definition: instructions.hh:1167
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR(MachInst)
Definition: decoder.cc:10487
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_F32(MachInst)
Definition: decoder.cc:7401
gem5::VegaISA::Decoder::decode_OP_DS__DS_PERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_PERMUTE_B32(MachInst)
Definition: decoder.cc:7624
gem5::VegaISA::Inst_VOP1__V_RCP_F64
Definition: instructions.hh:9281
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10417
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_INC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_INC(MachInst)
Definition: decoder.cc:8951
gem5::VegaISA::Inst_VOP1__V_LOG_F16
Definition: instructions.hh:10045
gem5::VegaISA::Inst_SOPC__S_SETVSKIP
Definition: instructions.hh:4359
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX
Definition: instructions.hh:42698
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64
Definition: instructions.hh:23041
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F64
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F64(MachInst)
Definition: decoder.cc:6398
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F64
GPUStaticInst * decode_OP_DS__DS_MAX_F64(MachInst)
Definition: decoder.cc:7750
gem5::VegaISA::Inst_VOP3__V_NOP
Definition: instructions.hh:25817
gem5::VegaISA::Inst_SOP2__S_BFM_B32
Definition: instructions.hh:1201
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I16
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I16(MachInst)
Definition: decoder.cc:10744
gem5::VegaISA::Inst_VOP1__V_CVT_F64_I32
Definition: instructions.hh:8225
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I64
GPUStaticInst * decode_OP_SOP2__S_BFE_I64(MachInst)
Definition: decoder.cc:4464
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8352
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:12339
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I32(MachInst)
Definition: decoder.cc:7480
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_U16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_U16_F32(MachInst)
Definition: decoder.cc:7220
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8268
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_F16(MachInst)
Definition: decoder.cc:11320
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:11973
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64
Definition: instructions.hh:19777
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:5246
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_F32(MachInst)
Definition: decoder.cc:6620
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGUSER
Definition: instructions.hh:5211
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F32
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F32(MachInst)
Definition: decoder.cc:6332
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR_X2
Definition: instructions.hh:37945
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR(MachInst)
Definition: decoder.cc:8420
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:4970
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:6476
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_INC
Definition: instructions.hh:39465
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD
Definition: instructions.hh:37225
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64
Definition: instructions.hh:16955
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:6032
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F64(MachInst)
Definition: decoder.cc:8196
gem5::VegaISA::Inst_VOP1__V_LOG_LEGACY_F32
Definition: instructions.hh:10429
gem5::VegaISA::InFmt_SOPP::OP
unsigned int OP
Definition: gpu_decoder.hh:1782
gem5::VegaISA::Inst_VOP1__V_CVT_F64_F32
Definition: instructions.hh:8609
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORD(MachInst)
Definition: decoder.cc:9993
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL(MachInst)
Definition: decoder.cc:8969
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFM_B32
GPUStaticInst * decode_OP_SOP2__S_BFM_B32(MachInst)
Definition: decoder.cc:4428
gem5::VegaISA::Decoder::decode_OP_VOP2__V_DOT2C_I32_I16
GPUStaticInst * decode_OP_VOP2__V_DOT2C_I32_I16(MachInst)
Definition: decoder.cc:4182
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8540
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHL_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHL_OR_B32(MachInst)
Definition: decoder.cc:7009
gem5::VegaISA::Inst_VOP3__V_CVT_F64_I32
Definition: instructions.hh:25909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U16(MachInst)
Definition: decoder.cc:5342
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F16
Definition: instructions.hh:8449
gem5::VegaISA::Inst_VOP3__V_CMP_T_U32
Definition: instructions.hh:22361
gem5::VegaISA::Inst_VOP3__V_CMP_F_U32
Definition: instructions.hh:22123
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F16
Definition: instructions.hh:11243
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:38393
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64
Definition: instructions.hh:13283
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:12867
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XY
Definition: instructions.hh:36095
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:12291
gem5::VegaISA::Decoder::tableSubDecode_OPU_VOP3
static IsaDecodeMethod tableSubDecode_OPU_VOP3[768]
Definition: gpu_decoder.hh:62
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10571
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32
Definition: instructions.hh:15221
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMREALTIME
GPUStaticInst * decode_OP_SMEM__S_MEMREALTIME(MachInst)
Definition: decoder.cc:10210
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:10030
gem5::VegaISA::Inst_SOP2__S_AND_B64
Definition: instructions.hh:487
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_U16(MachInst)
Definition: decoder.cc:13005
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3
Definition: instructions.hh:36985
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:12309
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9410
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U64
Definition: instructions.hh:33877
gem5::VegaISA::Inst_VOP3__V_MQSAD_PK_U16_U8
Definition: instructions.hh:29519
gem5::VegaISA::Inst_VOP3__V_CVT_F64_F32
Definition: instructions.hh:26293
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F64(MachInst)
Definition: decoder.cc:5150
gpu_static_inst.hh
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_I16_F32
Definition: instructions.hh:31015
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F16
Definition: instructions.hh:26133
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:9761
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOP
GPUStaticInst * decode_OP_VOP1__V_NOP(MachInst)
Definition: decoder.cc:11260
gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32
Definition: instructions.hh:7059
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHRREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHRREV_B16(MachInst)
Definition: decoder.cc:12956
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F16
Definition: instructions.hh:17975
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16
Definition: instructions.hh:14507
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F64(MachInst)
Definition: decoder.cc:7925
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U64(MachInst)
Definition: decoder.cc:11043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I32(MachInst)
Definition: decoder.cc:12537
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:5588
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETHALT
GPUStaticInst * decode_OP_SOPP__S_SETHALT(MachInst)
Definition: decoder.cc:11133
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:12327
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:6242
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32
Definition: instructions.hh:11957
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:6554
gem5::VegaISA::Decoder::decode_OP_DS__DS_ORDERED_COUNT
GPUStaticInst * decode_OP_DS__DS_ORDERED_COUNT(MachInst)
Definition: decoder.cc:8106
gem5::VegaISA::Inst_VOP3__V_MAD_I16
Definition: instructions.hh:29955
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8226
gem5::VegaISA::InstFormat::iFmt_VINTRP
InFmt_VINTRP iFmt_VINTRP
Definition: gpu_decoder.hh:1932
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16
Definition: instructions.hh:20933
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B64
GPUStaticInst * decode_OP_SOP2__S_LSHL_B64(MachInst)
Definition: decoder.cc:4398
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SSHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9585
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_O(MachInst)
Definition: decoder.cc:9071
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F32
GPUStaticInst * decode_OP_VOP1__V_RSQ_F32(MachInst)
Definition: decoder.cc:11470
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:11350
gem5::VegaISA::Inst_VOP3__V_FLOOR_F32
Definition: instructions.hh:26773
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:12135
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:10143
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64
Definition: instructions.hh:23313
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8359
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10106
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32
Definition: instructions.hh:12399
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:6458
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_OR_USER(MachInst)
Definition: decoder.cc:11205
gem5::VegaISA::Inst_VOP3__V_CMP_T_U64
Definition: instructions.hh:23449
gem5::VegaISA::Inst_DS__DS_INC_SRC2_U32
Definition: instructions.hh:34647
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BCNT_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_BCNT_U32_B32(MachInst)
Definition: decoder.cc:7166
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:11883
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TRAP
GPUStaticInst * decode_OP_SOPP__S_TRAP(MachInst)
Definition: decoder.cc:11163
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:9972
gem5::VegaISA::Inst_VOP3__V_MAD_F16
Definition: instructions.hh:29883
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I32(MachInst)
Definition: decoder.cc:7985
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMIN
Definition: instructions.hh:37333
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F64
Definition: instructions.hh:29261
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U16(MachInst)
Definition: decoder.cc:5378
gem5::VegaISA::Inst_SOP1__S_BITSET1_B64
Definition: instructions.hh:3113
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:12225
gem5::VegaISA::Inst_VOP3__V_CMP_O_F16
Definition: instructions.hh:17737
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32
Definition: instructions.hh:15663
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U32
Definition: instructions.hh:34797
gem5::VegaISA::Inst_SOP1__S_XNOR_SAVEEXEC_B64
Definition: instructions.hh:3495
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16
Definition: instructions.hh:21681
gem5::VegaISA::Inst_VOP2__V_SUBBREV_CO_U32
Definition: instructions.hh:7243
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:12843
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U64(MachInst)
Definition: decoder.cc:5768
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64
Definition: instructions.hh:13011
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U32(MachInst)
Definition: decoder.cc:6740
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:4748
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B64
GPUStaticInst * decode_OP_SOP2__S_XOR_B64(MachInst)
Definition: decoder.cc:4326
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:5042
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XOR_B32
GPUStaticInst * decode_OP_SOP2__S_XOR_B32(MachInst)
Definition: decoder.cc:4320
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:38583
gem5::VegaISA::Inst_DS__DS_AND_B64
Definition: instructions.hh:33379
gem5::VegaISA::Decoder::decode_OP_SOPP__S_DECPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_DECPERFLEVEL(MachInst)
Definition: decoder.cc:11181
gem5::VegaISA::Inst_SOP2__S_NOR_B64
Definition: instructions.hh:895
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL
Definition: instructions.hh:39569
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64
Definition: instructions.hh:13725
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2_B32(MachInst)
Definition: decoder.cc:7377
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:6098
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64
Definition: instructions.hh:20083
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I16(MachInst)
Definition: decoder.cc:6935
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F32
Definition: instructions.hh:27413
gem5::VegaISA::Inst_SOP2__S_ADD_I32
Definition: instructions.hh:113
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16
Definition: instructions.hh:14881
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:10543
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U32
Definition: instructions.hh:32277
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:9689
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEMA_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEMA_F32(MachInst)
Definition: decoder.cc:6656
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9930
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP
Definition: instructions.hh:37153
gem5::VegaISA::Inst_SOP2__S_CSELECT_B64
Definition: instructions.hh:419
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:5546
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32
Definition: instructions.hh:12229
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8324
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:12561
gem5::VegaISA::Inst_SOP2__S_LSHL_B64
Definition: instructions.hh:1031
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP_PCK(MachInst)
Definition: decoder.cc:8873
gem5::VegaISA::Inst_VOP3__V_COS_F16
Definition: instructions.hh:28049
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:5762
gem5::VegaISA::Inst_DS__DS_WRITE_B64
Definition: instructions.hh:33507
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32
Definition: instructions.hh:15153
gem5::VegaISA::Inst_VOP3__V_RSQ_F64
Definition: instructions.hh:26997
gem5::VegaISA::InstFormat::imm_u32
uint32_t imm_u32
Definition: gpu_decoder.hh:1944
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CNDMASK_B32
GPUStaticInst * decode_OPU_VOP3__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:5870
gem5::VegaISA::Inst_SOP2__S_ADDC_U32
Definition: instructions.hh:181
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_U32(MachInst)
Definition: decoder.cc:6164
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:10155
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_F32(MachInst)
Definition: decoder.cc:7558
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL3_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL3_ADD_U32(MachInst)
Definition: decoder.cc:4514
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F64
Definition: instructions.hh:35709
gem5::VegaISA::Inst_SOP1__S_NOT_B32
Definition: instructions.hh:2377
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:12825
gem5::VegaISA::Inst_VOP1__V_FFBL_B32
Definition: instructions.hh:9569
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16
Definition: instructions.hh:21205
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:5462
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P1_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:11242
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAITCNT
GPUStaticInst * decode_OP_SOPP__S_WAITCNT(MachInst)
Definition: decoder.cc:11127
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F64
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F64(MachInst)
Definition: decoder.cc:6470
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:5558
gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32
Definition: instructions.hh:2217
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_U32(MachInst)
Definition: decoder.cc:6158
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN_U16(MachInst)
Definition: decoder.cc:6140
gem5::VegaISA::InstFormat::iFmt_SOPP
InFmt_SOPP iFmt_SOPP
Definition: gpu_decoder.hh:1931
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL_O
Definition: instructions.hh:41369
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX3
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9653
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F16(MachInst)
Definition: decoder.cc:7094
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32
Definition: instructions.hh:11889
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SUB
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8384
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I64
Definition: instructions.hh:35469
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE3
Definition: instructions.hh:26421
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_U16(MachInst)
Definition: decoder.cc:12991
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_F32
GPUStaticInst * decode_OP_DS__DS_ADD_F32(MachInst)
Definition: decoder.cc:7419
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:11895
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:11302
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F16
GPUStaticInst * decode_OPU_VOP3__V_COS_F16(MachInst)
Definition: decoder.cc:6596
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10522
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F16
Definition: instructions.hh:18145
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9609
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD(MachInst)
Definition: decoder.cc:10228
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8372
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBEID_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBEID_F32(MachInst)
Definition: decoder.cc:6638
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I64(MachInst)
Definition: decoder.cc:5774
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:5498
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U64
GPUStaticInst * decode_OP_DS__DS_DEC_U64(MachInst)
Definition: decoder.cc:7660
gem5::VegaISA::Inst_SOP2__S_MAX_I32
Definition: instructions.hh:317
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:12375
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I32(MachInst)
Definition: decoder.cc:5486
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F16
GPUStaticInst * decode_OP_VOP1__V_SIN_F16(MachInst)
Definition: decoder.cc:11681
gem5::VegaISA::Decoder::decode_OP_SOPK__S_SETREG_IMM32_B32
GPUStaticInst * decode_OP_SOPK__S_SETREG_IMM32_B32(MachInst)
Definition: decoder.cc:4663
gem5::VegaISA::Inst_SOP1__S_ORN2_SAVEEXEC_B64
Definition: instructions.hh:3399
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2
Definition: instructions.hh:5607
gem5::VegaISA::Inst_VOP2__V_SUB_F32
Definition: instructions.hh:6277
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_I32
Definition: instructions.hh:3847
gem5::VegaISA::Inst_SOPK__S_ADDK_I32
Definition: instructions.hh:2057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:5024
gem5::VegaISA::Inst_DS__DS_DEC_U32
Definition: instructions.hh:31315
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16
Definition: instructions.hh:21409
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:11931
gem5::VegaISA::Inst_DS__DS_WRITE2_B64
Definition: instructions.hh:33541
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32
Definition: instructions.hh:19403
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1_VOL
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1_VOL(MachInst)
Definition: decoder.cc:9677
gem5::VegaISA::Inst_VOP2__V_MAX_U32
Definition: instructions.hh:6719
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F16
Definition: instructions.hh:11685
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32
Definition: instructions.hh:30607
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F16(MachInst)
Definition: decoder.cc:11817
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F16
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F16(MachInst)
Definition: decoder.cc:6530
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32
Definition: instructions.hh:22055
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:10291
gem5::VegaISA::InFmt_SMEM::OP
unsigned int OP
Definition: gpu_decoder.hh:1741
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9525
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL_O
Definition: instructions.hh:40325
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F16
GPUStaticInst * decode_OPU_VOP3__V_MED3_F16(MachInst)
Definition: decoder.cc:6970
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64
Definition: instructions.hh:23959
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9531
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B32
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B32(MachInst)
Definition: decoder.cc:10666
gem5::VegaISA::Decoder::subDecode_OP_SMEM
GPUStaticInst * subDecode_OP_SMEM(MachInst)
Definition: decoder.cc:3768
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B64
GPUStaticInst * decode_OP_SOP2__S_LSHR_B64(MachInst)
Definition: decoder.cc:4410
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:11979
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_CMPSWAP
Definition: instructions.hh:39125
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32
Definition: instructions.hh:18791
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:8621
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPC
static IsaDecodeMethod tableSubDecode_OP_SOPC[128]
Definition: gpu_decoder.hh:72
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8801
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_U32
Definition: instructions.hh:1865
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32
Definition: instructions.hh:12569
gem5::VegaISA::Inst_DS__DS_INC_U64
Definition: instructions.hh:33187
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9464
gem5::VegaISA::Inst_VOP3__V_MIN3_U32
Definition: instructions.hh:28793
gem5::VegaISA::InFmt_VOP1::OP
unsigned int OP
Definition: gpu_decoder.hh:1797
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_U32
Definition: instructions.hh:1897
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XAD_U32
GPUStaticInst * decode_OPU_VOP3__V_XAD_U32(MachInst)
Definition: decoder.cc:6922
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B32
Definition: instructions.hh:32379
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U32(MachInst)
Definition: decoder.cc:7961
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CLREXCP
GPUStaticInst * decode_OPU_VOP3__V_CLREXCP(MachInst)
Definition: decoder.cc:6488
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:12747
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U32
Definition: instructions.hh:30539
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORD(MachInst)
Definition: decoder.cc:10074
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_U64(MachInst)
Definition: decoder.cc:7678
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRIG_PREOP_F64
GPUStaticInst * decode_OPU_VOP3__V_TRIG_PREOP_F64(MachInst)
Definition: decoder.cc:7202
gem5::VegaISA::Inst_SOPP__S_DECPERFLEVEL
Definition: instructions.hh:5121
gem5::VegaISA::Inst_VOP3__V_ADD_CO_U32
Definition: instructions.hh:24847
gem5::VegaISA::Inst_VOP3__V_SUBREV_CO_U32
Definition: instructions.hh:24919
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:5624
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F16
Definition: instructions.hh:11107
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:38469
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U32
Definition: instructions.hh:4039
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B
Definition: instructions.hh:40001
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:5504
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORD
Definition: instructions.hh:5571
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL(MachInst)
Definition: decoder.cc:9236
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2
Definition: instructions.hh:42318
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:12657
gem5::VegaISA::Inst_VOP3__V_MUL_F32
Definition: instructions.hh:24199
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8783
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_F32
GPUStaticInst * decode_OP_DS__DS_MAX_F32(MachInst)
Definition: decoder.cc:7407
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F16(MachInst)
Definition: decoder.cc:4880
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64
Definition: instructions.hh:16819
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9999
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B32
Definition: instructions.hh:4231
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_F32(MachInst)
Definition: decoder.cc:11446
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK(MachInst)
Definition: decoder.cc:8843
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16
Definition: instructions.hh:18553
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F16
Definition: instructions.hh:18281
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:5348
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10396
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32(MachInst)
Definition: decoder.cc:7136
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10410
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16_D16_HI
GPUStaticInst * decode_OP_DS__DS_WRITE_B16_D16_HI(MachInst)
Definition: decoder.cc:7762
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL_O(MachInst)
Definition: decoder.cc:9125
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:10340
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U64(MachInst)
Definition: decoder.cc:7829
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U64
GPUStaticInst * decode_OP_DS__DS_MAX_U64(MachInst)
Definition: decoder.cc:7684
gem5::VegaISA::Inst_SOPK__S_CMOVK_I32
Definition: instructions.hh:1641
gem5::VegaISA::Inst_VOP2__V_MUL_I32_I24
Definition: instructions.hh:6413
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_U32_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_U32_U8(MachInst)
Definition: decoder.cc:6848
gem5::VegaISA::Inst_DS__DS_MAX_F64
Definition: instructions.hh:33709
gem5::VegaISA::Inst_VOP3__V_SUBBREV_CO_U32
Definition: instructions.hh:25031
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_F32(MachInst)
Definition: decoder.cc:6368
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:6230
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONDXCHG32_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CONDXCHG32_RTN_B64(MachInst)
Definition: decoder.cc:7949
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64
Definition: instructions.hh:19845
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:38545
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9458
gem5::VegaISA::Inst_VOP3__V_MIN3_I32
Definition: instructions.hh:28757
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F16(MachInst)
Definition: decoder.cc:4898
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F16
Definition: instructions.hh:11447
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64
Definition: instructions.hh:19981
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL(MachInst)
Definition: decoder.cc:9047
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U32(MachInst)
Definition: decoder.cc:12597
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:12357
gem5::VegaISA::Inst_DS__DS_MAX_I64
Definition: instructions.hh:33283
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C
Definition: instructions.hh:39821
gem5::VegaISA::Inst_VOP3__V_LSHL_OR_B32
Definition: instructions.hh:29811
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:10599
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:38127
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SWAP_B32
GPUStaticInst * decode_OP_VOP1__V_SWAP_B32(MachInst)
Definition: decoder.cc:11726
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B(MachInst)
Definition: decoder.cc:9180
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9567
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_O(MachInst)
Definition: decoder.cc:9119
gem5::VegaISA::Inst_VOP3__V_MUL_I32_I24
Definition: instructions.hh:24233
gem5::VegaISA::InstFormat::iFmt_MIMG
InFmt_MIMG iFmt_MIMG
Definition: gpu_decoder.hh:1919
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64
Definition: instructions.hh:20423
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMAX
Definition: instructions.hh:37369
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L(MachInst)
Definition: decoder.cc:9224
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16
Definition: instructions.hh:21545
gem5::VegaISA::Inst_VOP3__V_CNDMASK_B32
Definition: instructions.hh:24027
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_XOR_B32
GPUStaticInst * decode_OPU_VOP3__V_XOR_B32(MachInst)
Definition: decoder.cc:5996
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32
Definition: instructions.hh:22327
gem5::VegaISA::Inst_VOP3__V_TRUNC_F16
Definition: instructions.hh:27921
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16
Definition: instructions.hh:13997
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64
Definition: instructions.hh:17363
gem5::VegaISA::Inst_VOPC__V_CMP_O_F16
Definition: instructions.hh:10903
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F16(MachInst)
Definition: decoder.cc:4718
gem5::VegaISA::Inst_VOP3__V_MIN3_F32
Definition: instructions.hh:28721
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F16
Definition: instructions.hh:30091
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORD
Definition: instructions.hh:5859
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE_BUFFER
Definition: instructions.hh:6173
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64
Definition: instructions.hh:23687
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9846
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:3953
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F16
Definition: instructions.hh:18519
gem5::VegaISA::Inst_DS__DS_SUB_U32
Definition: instructions.hh:31219
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F64
GPUStaticInst * decode_OP_VOP1__V_FRACT_F64(MachInst)
Definition: decoder.cc:11554
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:5834
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4
Definition: instructions.hh:42392
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I32(MachInst)
Definition: decoder.cc:6734
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B64
GPUStaticInst * decode_OP_DS__DS_XOR_B64(MachInst)
Definition: decoder.cc:7702
gem5::VegaISA::Inst_VOP3__V_SIN_F16
Definition: instructions.hh:28017
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:5162
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32
Definition: instructions.hh:21987
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F16(MachInst)
Definition: decoder.cc:11769
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:9707
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32
Definition: instructions.hh:12773
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ABSDIFF_I32
GPUStaticInst * decode_OP_SOP2__S_ABSDIFF_I32(MachInst)
Definition: decoder.cc:4476
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_I32
GPUStaticInst * decode_OPU_VOP3__V_BFE_I32(MachInst)
Definition: decoder.cc:6668
gem5::VegaISA::Inst_VOP1__V_CEIL_F32
Definition: instructions.hh:9025
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F16
Definition: instructions.hh:10733
gem5::VegaISA::Inst_DS__DS_READ_U8
Definition: instructions.hh:32889
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B32
Definition: instructions.hh:2761
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64
Definition: instructions.hh:16309
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:5636
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:12207
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16
Definition: instructions.hh:14711
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE(MachInst)
Definition: decoder.cc:8855
gem5::VegaISA::Inst_MIMG__IMAGE_STORE
Definition: instructions.hh:38913
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32
Definition: instructions.hh:18723
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I32(MachInst)
Definition: decoder.cc:7474
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B64
Definition: instructions.hh:33577
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64
Definition: instructions.hh:16479
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:12501
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:11733
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBYTE_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBYTE_B32(MachInst)
Definition: decoder.cc:6704
gem5::VegaISA::Inst_DS__DS_MAX_U64
Definition: instructions.hh:33347
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_X
Definition: instructions.hh:38241
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10312
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:10592
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64
Definition: instructions.hh:13045
gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32
Definition: instructions.hh:31675
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:12171
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9621
gem5::VegaISA::Inst_SOP2__S_MUL_I32
Definition: instructions.hh:1269
gem5::VegaISA::InFmt_VOP3A
Definition: gpu_decoder.hh:1810
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE(MachInst)
Definition: decoder.cc:8274
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F16
GPUStaticInst * decode_OP_VOP2__V_MUL_F16(MachInst)
Definition: decoder.cc:4049
gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32
Definition: instructions.hh:12195
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F32
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F32(MachInst)
Definition: decoder.cc:6356
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:5396
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:9737
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCNZ(MachInst)
Definition: decoder.cc:11097
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B64
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B64(MachInst)
Definition: decoder.cc:4338
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10459
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT(MachInst)
Definition: decoder.cc:9909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_I32(MachInst)
Definition: decoder.cc:6716
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:12753
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B32
GPUStaticInst * decode_OP_SOP1__S_NOT_B32(MachInst)
Definition: decoder.cc:10630
gem5::VegaISA::Decoder::decode_OP_VOP2__V_PK_FMAC_F16
GPUStaticInst * decode_OP_VOP2__V_PK_FMAC_F16(MachInst)
Definition: decoder.cc:4210
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64
Definition: instructions.hh:10563
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:8256
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:5858
gem5::VegaISA::Inst_VOP2__V_CNDMASK_B32
Definition: instructions.hh:6207
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I64
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I64(MachInst)
Definition: decoder.cc:7196
gem5::VegaISA::Inst_VOP3__V_CMP_F_F32
Definition: instructions.hh:18587
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I32(MachInst)
Definition: decoder.cc:5522
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F16
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F16(MachInst)
Definition: decoder.cc:11651
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64
Definition: instructions.hh:20389
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:4778
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I32(MachInst)
Definition: decoder.cc:5510
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:4754
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B16
Definition: instructions.hh:25409
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10515
gem5::VegaISA::Inst_VOP2__V_SUBREV_U32
Definition: instructions.hh:8067
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B64(MachInst)
Definition: decoder.cc:8178
gem5::VegaISA::Inst_SOPP__S_CBRANCH_SCC0
Definition: instructions.hh:4607
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_L
Definition: instructions.hh:39677
gem5::VegaISA::Inst_VOP3__V_MAD_I64_I32
Definition: instructions.hh:29629
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B64(MachInst)
Definition: decoder.cc:8166
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:6602
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM
GPUStaticInst * decode_OP_SOPP__S_ENDPGM(MachInst)
Definition: decoder.cc:11061
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC(MachInst)
Definition: decoder.cc:8729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F32(MachInst)
Definition: decoder.cc:5054
gem5::VegaISA::Inst_SOP2__S_XOR_B64
Definition: instructions.hh:623
gem5::VegaISA::Inst_VOP1__V_CVT_U32_F64
Definition: instructions.hh:8769
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_F32
Definition: instructions.hh:35007
gem5::VegaISA::Inst_VOP3__V_BFREV_B32
Definition: instructions.hh:27189
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_U8(MachInst)
Definition: decoder.cc:6764
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ANDN2_B32
GPUStaticInst * decode_OP_SOP2__S_ANDN2_B32(MachInst)
Definition: decoder.cc:4332
gem5::VegaISA::Inst_VOP3__V_CMP_T_I32
Definition: instructions.hh:22089
gem5::VegaISA::Inst_VOP3__V_CMP_F_I32
Definition: instructions.hh:21851
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9519
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U32(MachInst)
Definition: decoder.cc:12585
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_O(MachInst)
Definition: decoder.cc:9362
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS_AND_USER(MachInst)
Definition: decoder.cc:11211
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_AND_SRC2_B32(MachInst)
Definition: decoder.cc:8009
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PKNORM_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_PKNORM_U16_F16(MachInst)
Definition: decoder.cc:7251
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32
Definition: instructions.hh:22259
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F32
GPUStaticInst * decode_OP_VOP2__V_MAC_F32(MachInst)
Definition: decoder.cc:3977
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:12117
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B16
Definition: instructions.hh:25375
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F32(MachInst)
Definition: decoder.cc:4922
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16
Definition: instructions.hh:14371
gem5::VegaISA::Decoder::decode_OP_DS__DS_CONSUME
GPUStaticInst * decode_OP_DS__DS_CONSUME(MachInst)
Definition: decoder.cc:8094
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SSHORT
Definition: instructions.hh:36635
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I32(MachInst)
Definition: decoder.cc:5528
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I32
Definition: instructions.hh:24607
gem5::VegaISA::Inst_VOP3__V_RCP_F64
Definition: instructions.hh:26965
gem5::VegaISA::Inst_VOP3__V_FFBL_B32
Definition: instructions.hh:27253
gem5::VegaISA::Inst_VOP3__V_LOG_F16
Definition: instructions.hh:27729
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U32(MachInst)
Definition: decoder.cc:7997
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:5924
gem5::VegaISA::Inst_VOP3__V_RNDNE_F32
Definition: instructions.hh:26741
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U32
GPUStaticInst * decode_OP_DS__DS_INC_U32(MachInst)
Definition: decoder.cc:7311
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:12183
gem5::VegaISA::Inst_VOP3__V_MBCNT_LO_U32_B32
Definition: instructions.hh:30777
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_BR
Definition: instructions.hh:35129
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32
Definition: instructions.hh:19607
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:12705
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U16(MachInst)
Definition: decoder.cc:12435
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_U32(MachInst)
Definition: decoder.cc:4615
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F32(MachInst)
Definition: decoder.cc:12057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I32
GPUStaticInst * decode_OPU_VOP3__V_MIN_I32(MachInst)
Definition: decoder.cc:5942
gem5::VegaISA::InFmt_DS::OP
unsigned int OP
Definition: gpu_decoder.hh:1614
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:12651
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_O
Definition: instructions.hh:41333
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SET_GPR_IDX_IDX
GPUStaticInst * decode_OP_SOP1__S_SET_GPR_IDX_IDX(MachInst)
Definition: decoder.cc:10894
gem5::VegaISA::Inst_VOP3__V_MUL_F64
Definition: instructions.hh:30403
gem5::VegaISA::Inst_SOP2__S_BFE_U64
Definition: instructions.hh:1371
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F16
Definition: instructions.hh:11719
gem5::VegaISA::Inst_SOP2__S_MUL_HI_U32
Definition: instructions.hh:1541
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32
Definition: instructions.hh:22837
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10452
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_SUB_SRC2_U64(MachInst)
Definition: decoder.cc:8118
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_U16(MachInst)
Definition: decoder.cc:6872
gem5::VegaISA::Inst_VOP1__V_CEIL_F16
Definition: instructions.hh:10205
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B64
GPUStaticInst * decode_OP_DS__DS_READ_B64(MachInst)
Definition: decoder.cc:7931
gem5::VegaISA::Inst_VOP3__V_CVT_U32_F64
Definition: instructions.hh:26453
gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32
Definition: instructions.hh:32989
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:5372
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_U16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U16(MachInst)
Definition: decoder.cc:6086
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_F32
Definition: instructions.hh:34947
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32
Definition: instructions.hh:18961
gem5::VegaISA::InFmt_MIMG
Definition: gpu_decoder.hh:1666
gem5::VegaISA::Inst_VOP1__V_CVT_I32_F32
Definition: instructions.hh:8353
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8635
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:5552
gem5::VegaISA::Decoder::tableSubDecode_OP_SMEM
static IsaDecodeMethod tableSubDecode_OP_SMEM[256]
Definition: gpu_decoder.hh:70
gem5::VegaISA::Inst_VOP1__V_SQRT_F32
Definition: instructions.hh:9345
gem5::VegaISA::Inst_SOP2__S_SUB_U32
Definition: instructions.hh:79
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_U32(MachInst)
Definition: decoder.cc:4597
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B64(MachInst)
Definition: decoder.cc:7901
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2
Definition: instructions.hh:5787
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_I32
Definition: instructions.hh:34707
gem5::VegaISA::Inst_VOP3__V_CMP_T_I64
Definition: instructions.hh:23177
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC
Definition: instructions.hh:42848
gem5::VegaISA::Inst_VOP2__V_MADMK_F16
Definition: instructions.hh:7451
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U8_D16_HI(MachInst)
Definition: decoder.cc:7776
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F32
GPUStaticInst * decode_OPU_VOP3__V_ADD_F32(MachInst)
Definition: decoder.cc:5876
gem5::VegaISA::Decoder::decode_OP_SOP2__S_RFE_RESTORE_B64
GPUStaticInst * decode_OP_SOP2__S_RFE_RESTORE_B64(MachInst)
Definition: decoder.cc:4482
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:12045
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B64(MachInst)
Definition: decoder.cc:8184
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B32
GPUStaticInst * decode_OP_SOP2__S_XNOR_B32(MachInst)
Definition: decoder.cc:4380
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHLREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHLREV_B16(MachInst)
Definition: decoder.cc:4097
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16
Definition: instructions.hh:14847
gem5::VegaISA::InFmt_SOP1::ENCODING
unsigned int ENCODING
Definition: gpu_decoder.hh:1755
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10529
gem5::VegaISA::Decoder::decode_OP_SMEM__S_MEMTIME
GPUStaticInst * decode_OP_SMEM__S_MEMTIME(MachInst)
Definition: decoder.cc:10204
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64
Definition: instructions.hh:13215
gem5::VegaISA::Inst_VOP3__V_CVT_I32_F32
Definition: instructions.hh:26037
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:12111
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC0
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC0(MachInst)
Definition: decoder.cc:11079
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U32(MachInst)
Definition: decoder.cc:7450
gem5::VegaISA::Inst_VOP3__V_SUB_U32
Definition: instructions.hh:25749
gem5::VegaISA::Inst_VOP1__V_FFBH_U32
Definition: instructions.hh:9537
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16
Definition: instructions.hh:20831
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B64
Definition: instructions.hh:2729
gem5::VegaISA::InstFormat::iFmt_MTBUF
InFmt_MTBUF iFmt_MTBUF
Definition: gpu_decoder.hh:1921
gem5::VegaISA::InFmt_FLAT::OP
unsigned int OP
Definition: gpu_decoder.hh:1649
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8735
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL
Definition: instructions.hh:40829
gem5::VegaISA::Inst_DS__DS_READ2_B64
Definition: instructions.hh:34455
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:9809
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_F32(MachInst)
Definition: decoder.cc:5900
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F64(MachInst)
Definition: decoder.cc:12201
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F16
GPUStaticInst * decode_OP_VOP2__V_MAX_F16(MachInst)
Definition: decoder.cc:4115
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B64
Definition: instructions.hh:34217
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F16
Definition: instructions.hh:17567
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8280
gem5::VegaISA::InFmt_DS
Definition: gpu_decoder.hh:1610
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECZ(MachInst)
Definition: decoder.cc:11103
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT
Definition: instructions.hh:41985
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U16(MachInst)
Definition: decoder.cc:12393
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I64(MachInst)
Definition: decoder.cc:5702
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B32
Definition: instructions.hh:3591
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I32
Definition: instructions.hh:6787
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F16
Definition: instructions.hh:17805
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U32
GPUStaticInst * decode_OPU_VOP3__V_SAD_U32(MachInst)
Definition: decoder.cc:6782
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL(MachInst)
Definition: decoder.cc:9017
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B64
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B64(MachInst)
Definition: decoder.cc:7865
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ(MachInst)
Definition: decoder.cc:9005
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64
Definition: instructions.hh:23143
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CBRANCH_I_FORK
GPUStaticInst * decode_OP_SOPK__S_CBRANCH_I_FORK(MachInst)
Definition: decoder.cc:4645
gem5::VegaISA::Inst_VOP1__V_READFIRSTLANE_B32
Definition: instructions.hh:8161
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_F32
GPUStaticInst * decode_OP_VOP2__V_MAX_F32(MachInst)
Definition: decoder.cc:3911
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_U32
Definition: instructions.hh:2025
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_RTN_B32
GPUStaticInst * decode_OP_DS__DS_AND_RTN_B32(MachInst)
Definition: decoder.cc:7498
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:5036
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_U16(MachInst)
Definition: decoder.cc:12984
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64
Definition: instructions.hh:23721
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64
Definition: instructions.hh:13419
gem5::VegaISA::Inst_VOPC__V_CMP_F_U64
Definition: instructions.hh:16377
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:12543
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F16
GPUStaticInst * decode_OP_VOP1__V_RCP_F16(MachInst)
Definition: decoder.cc:11609
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:11757
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64
Definition: instructions.hh:19879
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_ADDTID_B32(MachInst)
Definition: decoder.cc:7425
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B32
Definition: instructions.hh:34917
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:12897
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32
Definition: instructions.hh:22565
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B32(MachInst)
Definition: decoder.cc:10762
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F32
Definition: instructions.hh:29297
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:5360
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64
Definition: instructions.hh:16683
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B64
Definition: instructions.hh:34251
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F64(MachInst)
Definition: decoder.cc:5120
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_USHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_USHORT(MachInst)
Definition: decoder.cc:8238
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETPRIO
GPUStaticInst * decode_OP_SOPP__S_SETPRIO(MachInst)
Definition: decoder.cc:11145
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D(MachInst)
Definition: decoder.cc:8975
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U16
GPUStaticInst * decode_OP_VOP2__V_SUB_U16(MachInst)
Definition: decoder.cc:4079
gem5::VegaISA::Inst_SOPC__S_CMP_EQ_U64
Definition: instructions.hh:4423
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B32
Definition: instructions.hh:34887
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64
Definition: instructions.hh:16887
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL2_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL2_ADD_U32(MachInst)
Definition: decoder.cc:4507
gem5::VegaISA::Inst_VOP2__V_MAX_I32
Definition: instructions.hh:6651
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10242
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32
Definition: instructions.hh:15187
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV_VOL
Definition: instructions.hh:6023
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F16
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F16(MachInst)
Definition: decoder.cc:6524
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F16
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F16(MachInst)
Definition: decoder.cc:11663
gem5::VegaISA::Inst_DS__DS_READ_U16
Definition: instructions.hh:32955
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F32(MachInst)
Definition: decoder.cc:6818
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE2
Definition: instructions.hh:8705
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:11597
gem5::VegaISA::Inst_SOPP__S_SLEEP
Definition: instructions.hh:4911
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F16
GPUStaticInst * decode_OP_VOP1__V_FRACT_F16(MachInst)
Definition: decoder.cc:11675
gem5::VegaISA::Inst_VOP1__V_CVT_OFF_F32_I4
Definition: instructions.hh:8545
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32
Definition: instructions.hh:15493
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:9647
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:5642
gem5::VegaISA::Inst_SOP2__S_OR_B32
Definition: instructions.hh:521
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP_X2
Definition: instructions.hh:42922
gem5::GPUStaticInst
Definition: gpu_static_inst.hh:61
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:9767
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10256
gem5::VegaISA::Inst_SMEM__S_MEMTIME
Definition: instructions.hh:6079
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16
Definition: instructions.hh:21103
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL_O
Definition: instructions.hh:40505
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9537
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B64
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B64(MachInst)
Definition: decoder.cc:4290
gem5::VegaISA::Inst_VOP2__V_MAX_F32
Definition: instructions.hh:6583
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10834
gem5::VegaISA::InstFormat::iFmt_VOP1
InFmt_VOP1 iFmt_VOP1
Definition: gpu_decoder.hh:1933
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CBRANCH_JOIN
GPUStaticInst * decode_OP_SOP1__S_CBRANCH_JOIN(MachInst)
Definition: decoder.cc:10882
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:5216
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK_SGN
Definition: instructions.hh:38877
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_I32(MachInst)
Definition: decoder.cc:4591
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD
Definition: instructions.hh:38697
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F64
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F64(MachInst)
Definition: decoder.cc:6314
gem5::VegaISA::Decoder::decode_OP_EXP
GPUStaticInst * decode_OP_EXP(MachInst)
Definition: decoder.cc:4676
gem5::VegaISA::Decoder::decode_OP_SOPP__S_WAKEUP
GPUStaticInst * decode_OP_SOPP__S_WAKEUP(MachInst)
Definition: decoder.cc:11073
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKNORM_I16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKNORM_I16_F32(MachInst)
Definition: decoder.cc:7214
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FLOOR_F32
GPUStaticInst * decode_OP_VOP1__V_FLOOR_F32(MachInst)
Definition: decoder.cc:11440
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:36437
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L
Definition: instructions.hh:39965
gem5::VegaISA::Inst_VOP2__V_MAC_F16
Definition: instructions.hh:7417
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64
Definition: instructions.hh:17125
gem5::VegaISA::Inst_VOP1__V_TRUNC_F16
Definition: instructions.hh:10237
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR(MachInst)
Definition: decoder.cc:8717
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10431
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX2
Definition: instructions.hh:5895
gem5::VegaISA::Inst_VOP2__V_MUL_LO_U16
Definition: instructions.hh:7625
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:5672
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK
Definition: instructions.hh:38769
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:12735
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:11985
gem5::VegaISA::Inst_VOP3__V_CEIL_F32
Definition: instructions.hh:26709
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F16
Definition: instructions.hh:10631
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_WRITELANE_B32
GPUStaticInst * decode_OPU_VOP3__V_WRITELANE_B32(MachInst)
Definition: decoder.cc:7160
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64
Definition: instructions.hh:23857
gem5::VegaISA::Inst_VOP1__V_CVT_RPI_I32_F32
Definition: instructions.hh:8481
gem5::VegaISA::Inst_SOPK__S_MULK_I32
Definition: instructions.hh:2089
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64
Definition: instructions.hh:23415
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SSHORT(MachInst)
Definition: decoder.cc:9860
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B64
GPUStaticInst * decode_OP_SOP2__S_NOR_B64(MachInst)
Definition: decoder.cc:4374
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:5444
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:5432
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_I16_F16(MachInst)
Definition: decoder.cc:11705
gem5::VegaISA::InstFormat::iFmt_VOPC
InFmt_VOPC iFmt_VOPC
Definition: gpu_decoder.hh:1938
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_F32(MachInst)
Definition: decoder.cc:7395
gem5::VegaISA::Inst_VOP1__V_CVT_U16_F16
Definition: instructions.hh:9885
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B32
GPUStaticInst * decode_OP_SOP2__S_OR_B32(MachInst)
Definition: decoder.cc:4308
gem5::VegaISA::Inst_SOPK__S_CMPK_EQ_I32
Definition: instructions.hh:1673
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:38165
gem5::VegaISA::Inst_SOPK__S_CMPK_LG_I32
Definition: instructions.hh:1705
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U16(MachInst)
Definition: decoder.cc:5384
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORD(MachInst)
Definition: decoder.cc:8596
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND_X2
Definition: instructions.hh:43222
gem5::VegaISA::Inst_VOP2__V_SUBREV_F32
Definition: instructions.hh:6311
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B32
GPUStaticInst * decode_OP_DS__DS_OR_B32(MachInst)
Definition: decoder.cc:7353
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F32
Definition: instructions.hh:34977
gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32
Definition: instructions.hh:18893
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8438
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8426
gem5::VegaISA::Inst_SOP2__S_ABSDIFF_I32
Definition: instructions.hh:1473
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9501
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_U32(MachInst)
Definition: decoder.cc:10983
gem5::VegaISA::Decoder::decode_OP_VOP1__V_TRUNC_F32
GPUStaticInst * decode_OP_VOP1__V_TRUNC_F32(MachInst)
Definition: decoder.cc:11422
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_LSHL_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_LSHL_U32(MachInst)
Definition: decoder.cc:6997
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8705
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F64(MachInst)
Definition: decoder.cc:7913
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I16(MachInst)
Definition: decoder.cc:12471
gem5::VegaISA::Decoder::subDecode_OP_VOP3P
GPUStaticInst * subDecode_OP_VOP3P(MachInst)
Definition: decoder.cc:3728
gem5::VegaISA::Inst_DS__DS_WRITE_B96
Definition: instructions.hh:35769
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I32
Definition: instructions.hh:34737
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_U16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_U16(MachInst)
Definition: decoder.cc:11585
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16_HI(MachInst)
Definition: decoder.cc:7790
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8510
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F64(MachInst)
Definition: decoder.cc:5180
gem5::VegaISA::Inst_SOPP__S_TRAP
Definition: instructions.hh:5031
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F16
Definition: instructions.hh:11345
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC
Definition: instructions.hh:42885
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8
Definition: instructions.hh:5679
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:5072
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B64(MachInst)
Definition: decoder.cc:10708
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F64
GPUStaticInst * decode_OPU_VOP3__V_MAX_F64(MachInst)
Definition: decoder.cc:7118
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHR_B32
GPUStaticInst * decode_OP_SOP2__S_LSHR_B32(MachInst)
Definition: decoder.cc:4404
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:9874
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10263
gem5::VegaISA::Inst_VOP2__V_ADD_U32
Definition: instructions.hh:7999
gem5::VegaISA::Inst_VOP1__V_LOG_F32
Definition: instructions.hh:9153
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:4838
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_LDS_DWORD
Definition: instructions.hh:37061
gem5::VegaISA::Inst_VOP3__V_CVT_U16_F16
Definition: instructions.hh:27569
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16
Definition: instructions.hh:14609
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F32(MachInst)
Definition: decoder.cc:6212
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_MODE
Definition: instructions.hh:5361
gem5::VegaISA::Inst_SOP2__S_XOR_B32
Definition: instructions.hh:589
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F16
Definition: instructions.hh:11651
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F32
GPUStaticInst * decode_OPU_VOP3__V_SIN_F32(MachInst)
Definition: decoder.cc:6416
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32
Definition: instructions.hh:22803
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FRACT_F32
GPUStaticInst * decode_OP_VOP1__V_FRACT_F32(MachInst)
Definition: decoder.cc:11416
gem5::VegaISA::Inst_VOP3__V_SAD_U16
Definition: instructions.hh:29117
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I64
Definition: instructions.hh:33911
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I32
GPUStaticInst * decode_OPU_VOP3__V_SUB_I32(MachInst)
Definition: decoder.cc:7265
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8915
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L
Definition: instructions.hh:40973
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_AND
Definition: instructions.hh:39363
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64
Definition: instructions.hh:20321
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ_O(MachInst)
Definition: decoder.cc:9278
gem5::VegaISA::Inst_SOP2__S_XNOR_B64
Definition: instructions.hh:963
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:5612
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U32(MachInst)
Definition: decoder.cc:12687
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SEXT_I32_I8
GPUStaticInst * decode_OP_SOP1__S_SEXT_I32_I8(MachInst)
Definition: decoder.cc:10738
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10550
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B32
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B32(MachInst)
Definition: decoder.cc:7383
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16
Definition: instructions.hh:5715
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U64
GPUStaticInst * decode_OP_DS__DS_ADD_U64(MachInst)
Definition: decoder.cc:7636
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U64
Definition: instructions.hh:35379
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F64
Definition: instructions.hh:34353
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32
Definition: instructions.hh:15425
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U32(MachInst)
Definition: decoder.cc:7468
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX_X2
Definition: instructions.hh:37873
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F32
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F32(MachInst)
Definition: decoder.cc:7148
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F64
GPUStaticInst * decode_OPU_VOP3__V_MIN_F64(MachInst)
Definition: decoder.cc:7112
gem5::VegaISA::Inst_VOP1__V_FFBH_I32
Definition: instructions.hh:9601
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUBB_U32
GPUStaticInst * decode_OP_SOP2__S_SUBB_U32(MachInst)
Definition: decoder.cc:4254
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:4850
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:11745
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64
Definition: instructions.hh:23585
gem5::VegaISA::Inst_VOP3__V_CMP_T_U16
Definition: instructions.hh:21273
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:5312
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:8486
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_LZ(MachInst)
Definition: decoder.cc:9192
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_U32(MachInst)
Definition: decoder.cc:4603
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10564
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:11699
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4(MachInst)
Definition: decoder.cc:9155
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT
Definition: instructions.hh:36597
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F16
Definition: instructions.hh:11379
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_NORM_U16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_NORM_U16_F16(MachInst)
Definition: decoder.cc:11712
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT(MachInst)
Definition: decoder.cc:8287
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64
Definition: instructions.hh:13317
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SWAP
Definition: instructions.hh:39091
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_ADD_U32(MachInst)
Definition: decoder.cc:4224
gem5::VegaISA::Inst_VOP3__V_SUB_F32
Definition: instructions.hh:24097
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:12417
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U32(MachInst)
Definition: decoder.cc:5654
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16
Definition: instructions.hh:21783
gem5::VegaISA::Inst_VOP3__V_CEIL_F16
Definition: instructions.hh:27889
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:10011
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:36247
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F64(MachInst)
Definition: decoder.cc:5288
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_F32(MachInst)
Definition: decoder.cc:4910
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL(MachInst)
Definition: decoder.cc:9344
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32
Definition: instructions.hh:19437
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKRTZ_F16_F32(MachInst)
Definition: decoder.cc:7226
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_B32(MachInst)
Definition: decoder.cc:7365
gem5::VegaISA::Inst_SOPP__S_WAITCNT
Definition: instructions.hh:4851
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16
Definition: instructions.hh:14983
gem5::VegaISA::Inst_VOP3__V_SQRT_F32
Definition: instructions.hh:27029
gem5::VegaISA::Inst_DS__DS_XOR_RTN_B64
Definition: instructions.hh:34115
gem5::VegaISA::Inst_VOP3__V_CVT_PKACCUM_U8_F32
Definition: instructions.hh:30127
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F16
Definition: instructions.hh:17839
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I32(MachInst)
Definition: decoder.cc:7991
gem5::VegaISA::Decoder::decode_OP_DS__DS_NOP
GPUStaticInst * decode_OP_DS__DS_NOP(MachInst)
Definition: decoder.cc:7413
gem5::VegaISA::Inst_VOP2__V_SUB_U16
Definition: instructions.hh:7557
gem5::VegaISA::Decoder::subDecode_OP_VOP1
GPUStaticInst * subDecode_OP_VOP1(MachInst)
Definition: decoder.cc:3736
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE0
Definition: instructions.hh:26325
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMAX
Definition: instructions.hh:39295
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F16
GPUStaticInst * decode_OPU_VOP3__V_ADD_F16(MachInst)
Definition: decoder.cc:6044
gem5::VegaISA::Inst_SOP2__S_BFE_U32
Definition: instructions.hh:1303
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F32
Definition: instructions.hh:30195
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F16
GPUStaticInst * decode_OPU_VOP3__V_RCP_F16(MachInst)
Definition: decoder.cc:6518
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32
Definition: instructions.hh:22021
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:10389
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F32
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F32(MachInst)
Definition: decoder.cc:6350
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32
Definition: instructions.hh:19267
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U16(MachInst)
Definition: decoder.cc:5366
gem5::VegaISA::Inst_SOP2__S_LSHR_B32
Definition: instructions.hh:1065
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8474
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_UMAX
Definition: instructions.hh:37405
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:4886
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:11386
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE(MachInst)
Definition: decoder.cc:8522
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:10092
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I32
GPUStaticInst * decode_OP_DS__DS_MIN_I32(MachInst)
Definition: decoder.cc:7323
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_F16(MachInst)
Definition: decoder.cc:13026
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I32
GPUStaticInst * decode_OPU_VOP3__V_ADD_I32(MachInst)
Definition: decoder.cc:7258
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16(MachInst)
Definition: decoder.cc:7797
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SMIN
Definition: instructions.hh:39227
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:3995
gem5::VegaISA::Decoder::subDecode_OP_SOPP
GPUStaticInst * subDecode_OP_SOPP(MachInst)
Definition: decoder.cc:3760
gem5::VegaISA::Inst_VOP2__V_SUBB_CO_U32
Definition: instructions.hh:7205
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9507
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32
Definition: instructions.hh:22531
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XY
Definition: instructions.hh:36399
gem5::VegaISA::Inst_VOP3__V_FFBH_U32
Definition: instructions.hh:27221
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_ORDERED_PS_DONE(MachInst)
Definition: decoder.cc:11235
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_O(MachInst)
Definition: decoder.cc:9059
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I64(MachInst)
Definition: decoder.cc:5708
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_U64(MachInst)
Definition: decoder.cc:8154
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64
Definition: instructions.hh:20457
gem5::VegaISA::Inst_SOP1__S_OR_SAVEEXEC_B64
Definition: instructions.hh:3303
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:5090
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FMAS_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FMAS_F64(MachInst)
Definition: decoder.cc:6824
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_SRC2_U32(MachInst)
Definition: decoder.cc:7967
gem5::VegaISA::Inst_SMEM__S_DCACHE_INV
Definition: instructions.hh:5967
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:9713
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F64(MachInst)
Definition: decoder.cc:12267
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_U32(MachInst)
Definition: decoder.cc:4609
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR
Definition: instructions.hh:37513
gem5::VegaISA::Inst_VOP3__V_SUBB_CO_U32
Definition: instructions.hh:24993
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F16
Definition: instructions.hh:17465
gem5::VegaISA::Decoder::~Decoder
~Decoder()
Definition: decoder.cc:47
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_V
Definition: instructions.hh:35099
gem5::VegaISA::Decoder::tableSubDecode_OP_VINTRP
static IsaDecodeMethod tableSubDecode_OP_VINTRP[4]
Definition: gpu_decoder.hh:74
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10900
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8921
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B32(MachInst)
Definition: decoder.cc:7540
gem5::VegaISA::Inst_VOPC__V_CMP_T_U32
Definition: instructions.hh:15527
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FF0_I32_B64(MachInst)
Definition: decoder.cc:10696
gem5::VegaISA::Inst_VOPC__V_CMP_F_U32
Definition: instructions.hh:15289
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8687
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:12633
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_IFLAG_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:11464
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:7063
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B64(MachInst)
Definition: decoder.cc:10720
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U8_F32
Definition: instructions.hh:29189
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64
Definition: instructions.hh:13623
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F64(MachInst)
Definition: decoder.cc:8190
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP
Definition: instructions.hh:37189
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:10249
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SSHORT
Definition: instructions.hh:42022
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B64(MachInst)
Definition: decoder.cc:11019
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_U32
GPUStaticInst * decode_OP_SOP2__S_SUB_U32(MachInst)
Definition: decoder.cc:4230
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR_X2
Definition: instructions.hh:43296
gem5::VegaISA::Inst_SOP2__S_BFE_I64
Definition: instructions.hh:1405
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64
Definition: instructions.hh:20627
gem5::VegaISA::Inst_SOPP__S_SENDMSG
Definition: instructions.hh:4971
gem5::VegaISA::Inst_DS__DS_READ_B128
Definition: instructions.hh:35871
gem5::VegaISA::Inst_DS__DS_READ2_B32
Definition: instructions.hh:32787
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F16
Definition: instructions.hh:18247
gem5::VegaISA::InFmt_MTBUF
Definition: gpu_decoder.hh:1690
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP0_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP0_B32(MachInst)
Definition: decoder.cc:11007
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F16
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F16(MachInst)
Definition: decoder.cc:6056
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F32
Definition: instructions.hh:27445
gem5::VegaISA::Inst_VOP1__V_CVT_F16_F32
Definition: instructions.hh:8417
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_B32(MachInst)
Definition: decoder.cc:10714
gem5::VegaISA::Decoder::decode_OP_SOP1__S_GETPC_B64
GPUStaticInst * decode_OP_SOP1__S_GETPC_B64(MachInst)
Definition: decoder.cc:10774
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLG_F16(MachInst)
Definition: decoder.cc:11925
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_ADD
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_ADD(MachInst)
Definition: decoder.cc:9695
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I32(MachInst)
Definition: decoder.cc:12663
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16
Definition: instructions.hh:21511
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMAX_X2(MachInst)
Definition: decoder.cc:10382
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I16(MachInst)
Definition: decoder.cc:5306
gem5::VegaISA::Inst_VOP3__V_SAD_U8
Definition: instructions.hh:29045
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_ADDTID_B32
GPUStaticInst * decode_OP_DS__DS_READ_ADDTID_B32(MachInst)
Definition: decoder.cc:8087
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32
Definition: instructions.hh:16003
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_O
Definition: instructions.hh:40397
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F32(MachInst)
Definition: decoder.cc:11560
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32
Definition: instructions.hh:12093
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:12219
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16
Definition: instructions.hh:14065
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:5810
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U32
GPUStaticInst * decode_OP_DS__DS_SUB_U32(MachInst)
Definition: decoder.cc:7299
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U16
GPUStaticInst * decode_OP_VOP2__V_MAX_U16(MachInst)
Definition: decoder.cc:4127
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_L_O
Definition: instructions.hh:41405
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F64
Definition: instructions.hh:27349
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D(MachInst)
Definition: decoder.cc:9023
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:9958
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:5912
gem5::VegaISA::Inst_VOP1__V_SQRT_F64
Definition: instructions.hh:9377
gem5::VegaISA::Inst_VOP3__V_CVT_F16_F32
Definition: instructions.hh:26101
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE
Definition: instructions.hh:39533
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F32(MachInst)
Definition: decoder.cc:6710
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32
Definition: instructions.hh:22293
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_OR_B32(MachInst)
Definition: decoder.cc:7015
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK(MachInst)
Definition: decoder.cc:8831
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB(MachInst)
Definition: decoder.cc:10186
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_I32
GPUStaticInst * decode_OP_SOP2__S_BFE_I32(MachInst)
Definition: decoder.cc:4452
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32
Definition: instructions.hh:22871
gem5::VegaISA::Inst_SOPC__S_CMP_LT_I32
Definition: instructions.hh:3975
gem5::VegaISA::Inst_SOP1__S_MOV_B64
Definition: instructions.hh:2281
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16
Definition: instructions.hh:21817
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL(MachInst)
Definition: decoder.cc:9332
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F16
Definition: instructions.hh:10801
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U64(MachInst)
Definition: decoder.cc:7859
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B32
Definition: instructions.hh:3527
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16
Definition: instructions.hh:14269
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ(MachInst)
Definition: decoder.cc:9242
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8765
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B64
Definition: instructions.hh:4327
gem5::VegaISA::Inst_DS__DS_INC_RTN_U64
Definition: instructions.hh:33843
gem5::VegaISA::Inst_SOP2__S_SUB_I32
Definition: instructions.hh:147
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I32
GPUStaticInst * decode_OP_SOP2__S_ASHR_I32(MachInst)
Definition: decoder.cc:4416
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_U32
GPUStaticInst * decode_OP_SOP2__S_MIN_U32(MachInst)
Definition: decoder.cc:4266
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16
Definition: instructions.hh:13963
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1
Definition: instructions.hh:37093
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:5318
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F32(MachInst)
Definition: decoder.cc:12093
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:11793
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LEGACY_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:3869
gem5::VegaISA::InFmt_SOPP
Definition: gpu_decoder.hh:1780
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U24(MachInst)
Definition: decoder.cc:6632
gem5::VegaISA::Inst_DS__DS_NOP
Definition: instructions.hh:31839
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_U32(MachInst)
Definition: decoder.cc:7335
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_I16(MachInst)
Definition: decoder.cc:12970
gem5::VegaISA::Inst_SOP1__S_QUADMASK_B64
Definition: instructions.hh:3559
gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F16
Definition: instructions.hh:10109
gem5::VegaISA::Inst_SOP2__S_ASHR_I32
Definition: instructions.hh:1133
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_WB_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_WB_VOL(MachInst)
Definition: decoder.cc:10198
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE(MachInst)
Definition: decoder.cc:9895
gem5::VegaISA::Inst_SOP1__S_BITSET0_B32
Definition: instructions.hh:3017
gem5::VegaISA::Inst_DS__DS_OR_RTN_B32
Definition: instructions.hh:32345
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F64(MachInst)
Definition: decoder.cc:5174
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64
Definition: instructions.hh:16581
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:11967
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:12849
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_XOR
Definition: instructions.hh:42811
gem5::VegaISA::InFmt_MUBUF
Definition: gpu_decoder.hh:1711
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XY
Definition: instructions.hh:35943
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F16
Definition: instructions.hh:10699
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SUB
Definition: instructions.hh:37261
gem5::VegaISA::Inst_VOP3__V_MAX_U32
Definition: instructions.hh:24539
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_O(MachInst)
Definition: decoder.cc:9137
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_X
Definition: instructions.hh:36057
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B32
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B32(MachInst)
Definition: decoder.cc:10846
gem5::VegaISA::InstFormat::iFmt_SOP1
InFmt_SOP1 iFmt_SOP1
Definition: gpu_decoder.hh:1927
gem5::VegaISA::Inst_SMEM__S_ATC_PROBE
Definition: instructions.hh:6139
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:10068
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F32(MachInst)
Definition: decoder.cc:6806
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10125
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B32
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:3941
gem5::VegaISA::Inst_VOP3__V_FRACT_F32
Definition: instructions.hh:26645
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:12039
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9634
gem5::VegaISA::Inst_DS__DS_WRAP_RTN_B32
Definition: instructions.hh:32685
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64
Definition: instructions.hh:20661
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_I32(MachInst)
Definition: decoder.cc:4585
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F32(MachInst)
Definition: decoder.cc:4952
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F64
Definition: instructions.hh:9633
gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32
Definition: instructions.hh:17329
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F16
GPUStaticInst * decode_OP_VOP2__V_SUB_F16(MachInst)
Definition: decoder.cc:4037
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_U64(MachInst)
Definition: decoder.cc:8160
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_O
Definition: instructions.hh:40289
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_F16(MachInst)
Definition: decoder.cc:6928
gem5::VegaISA::Inst_SOPC__S_CMP_LT_U32
Definition: instructions.hh:4167
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2_RTN_B32(MachInst)
Definition: decoder.cc:7528
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B32
GPUStaticInst * decode_OP_SOP1__S_CMOV_B32(MachInst)
Definition: decoder.cc:10618
gem5::VegaISA::Inst_VOPC__V_CMP_T_U16
Definition: instructions.hh:14439
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32
Definition: instructions.hh:12603
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_F64
GPUStaticInst * decode_OP_DS__DS_CMPST_F64(MachInst)
Definition: decoder.cc:7738
gem5::VegaISA::Inst_VOPC__V_CMP_F_F64
Definition: instructions.hh:12841
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELD_B64
GPUStaticInst * decode_OP_SOP1__S_MOVRELD_B64(MachInst)
Definition: decoder.cc:10876
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_CL
Definition: instructions.hh:40937
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64
Definition: instructions.hh:20525
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SLEEP
GPUStaticInst * decode_OP_SOPP__S_SLEEP(MachInst)
Definition: decoder.cc:11139
gem5::VegaISA::Inst_SOP1__S_XOR_SAVEEXEC_B64
Definition: instructions.hh:3335
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SWAP_X2
Definition: instructions.hh:37621
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:12591
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_B64(MachInst)
Definition: decoder.cc:7907
gem5::VegaISA::Inst_SOPK__S_CMPK_LE_I32
Definition: instructions.hh:1833
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F64(MachInst)
Definition: decoder.cc:12195
gem5::VegaISA::Decoder::decode_OP_SOP2__S_OR_B64
GPUStaticInst * decode_OP_SOP2__S_OR_B64(MachInst)
Definition: decoder.cc:4314
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U64
Definition: instructions.hh:33979
gem5::VegaISA::Inst_SOPP__S_SENDMSGHALT
Definition: instructions.hh:5001
gem5::VegaISA::Inst_VOP1__V_RSQ_F32
Definition: instructions.hh:9249
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_U32
Definition: instructions.hh:1929
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LT_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LT_U32(MachInst)
Definition: decoder.cc:4621
gem5::VegaISA::Inst_DS__DS_GWS_SEMA_RELEASE_ALL
Definition: instructions.hh:35037
gem5::VegaISA::Inst_VOP1__V_RCP_F32
Definition: instructions.hh:9185
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_F32(MachInst)
Definition: decoder.cc:12075
gem5::VegaISA::Inst_VOPC__V_CMP_F_I64
Definition: instructions.hh:16105
gem5::VegaISA::Inst_SOP1__S_RFE_B64
Definition: instructions.hh:3239
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8693
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_U32
Definition: instructions.hh:1993
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32
Definition: instructions.hh:19335
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D
Definition: instructions.hh:39605
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADDC_CO_U32
GPUStaticInst * decode_OP_VOP2__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:4013
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LE_U32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LE_U32(MachInst)
Definition: decoder.cc:4627
gem5::VegaISA::Inst_DS__DS_READ_I8
Definition: instructions.hh:32855
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NOT_B64
GPUStaticInst * decode_OP_SOP1__S_NOT_B64(MachInst)
Definition: decoder.cc:10636
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ENDPGM_SAVED
GPUStaticInst * decode_OP_SOPP__S_ENDPGM_SAVED(MachInst)
Definition: decoder.cc:11217
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_U64(MachInst)
Definition: decoder.cc:12777
gem5::VegaISA::InFmt_MIMG::OP
unsigned int OP
Definition: gpu_decoder.hh:1676
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PKACCUM_U8_F32(MachInst)
Definition: decoder.cc:6902
gem5::VegaISA::Decoder::decode_OP_SOP1__S_CMOV_B64
GPUStaticInst * decode_OP_SOP1__S_CMOV_B64(MachInst)
Definition: decoder.cc:10624
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B64
GPUStaticInst * decode_OP_DS__DS_CMPST_B64(MachInst)
Definition: decoder.cc:7732
gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32
Definition: instructions.hh:22599
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F64(MachInst)
Definition: decoder.cc:5240
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:5456
gem5::VegaISA::Inst_SOP2__S_NOR_B32
Definition: instructions.hh:861
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F16_I16
GPUStaticInst * decode_OPU_VOP3__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:6500
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:12717
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:3881
gem5::VegaISA::Inst_MIMG__IMAGE_GET_LOD
Definition: instructions.hh:41549
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:6194
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F64(MachInst)
Definition: decoder.cc:5132
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:4814
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3
Definition: instructions.hh:42355
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OPU_VOP3__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:6254
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64
Definition: instructions.hh:17159
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:9815
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX_F32(MachInst)
Definition: decoder.cc:5936
gem5::VegaISA::Inst_VOP1__V_RNDNE_F16
Definition: instructions.hh:10269
gem5::VegaISA::Inst_VOP3__V_LSHL_ADD_U32
Definition: instructions.hh:29703
gem5::VegaISA::Inst_VOP3__V_LDEXP_F32
Definition: instructions.hh:30641
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U64(MachInst)
Definition: decoder.cc:12909
gem5::VegaISA::Inst_DS__DS_READ_I16
Definition: instructions.hh:32923
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:12351
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_U32(MachInst)
Definition: decoder.cc:10989
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:12873
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE(MachInst)
Definition: decoder.cc:9573
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8
GPUStaticInst * decode_OP_DS__DS_READ_I8(MachInst)
Definition: decoder.cc:7594
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_U32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_U32(MachInst)
Definition: decoder.cc:6440
gem5::VegaISA::Inst_DS__DS_WRITE_B32
Definition: instructions.hh:31605
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F32(MachInst)
Definition: decoder.cc:11961
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_U32
GPUStaticInst * decode_OP_DS__DS_ADD_U32(MachInst)
Definition: decoder.cc:7293
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL_O(MachInst)
Definition: decoder.cc:9290
gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F64
Definition: instructions.hh:29335
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B32
GPUStaticInst * decode_OP_SOP1__S_BREV_B32(MachInst)
Definition: decoder.cc:10654
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:9965
gem5::VegaISA::Inst_VOP3__V_FFBH_I32
Definition: instructions.hh:27285
gem5::VegaISA::Inst_VOP1__V_CVT_F32_U32
Definition: instructions.hh:8289
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:11290
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:5690
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FF1_I32_B32
GPUStaticInst * decode_OP_SOP1__S_FF1_I32_B32(MachInst)
Definition: decoder.cc:10702
gem5::VegaISA::Inst_VOP3__V_READLANE_B32
Definition: instructions.hh:30675
gem5::VegaISA::Inst_SOP2__S_MIN_U32
Definition: instructions.hh:283
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN_U32(MachInst)
Definition: decoder.cc:5954
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64
Definition: instructions.hh:13793
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64
Definition: instructions.hh:17023
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9386
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:12621
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:5126
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:11841
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:38659
gem5::VegaISA::Inst_SOP2__S_MUL_HI_I32
Definition: instructions.hh:1575
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_U32(MachInst)
Definition: decoder.cc:10971
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:10347
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_O(MachInst)
Definition: decoder.cc:9284
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F16
Definition: instructions.hh:11311
gem5::VegaISA::Inst_VOP3__V_CVT_F32_U32
Definition: instructions.hh:25973
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_L_O
Definition: instructions.hh:40541
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F32(MachInst)
Definition: decoder.cc:12123
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_U32
GPUStaticInst * decode_OP_SOP2__S_MAX_U32(MachInst)
Definition: decoder.cc:4278
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F64
GPUStaticInst * decode_OP_VOP1__V_RCP_F64(MachInst)
Definition: decoder.cc:11476
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8681
gem5::VegaISA::Inst_SOP1__S_MOVRELS_B64
Definition: instructions.hh:3623
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16
Definition: instructions.hh:20899
gem5::VegaISA::Inst_VOP3__V_FRACT_F16
Definition: instructions.hh:27985
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32
Definition: instructions.hh:10461
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10326
gem5::VegaISA::Inst_SOPC__S_CMP_LG_I32
Definition: instructions.hh:3879
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10403
gem5::VegaISA::Inst_VOP3__V_CMP_O_F32
Definition: instructions.hh:18825
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:5438
gem5::VegaISA::Inst_DS__DS_DEC_U64
Definition: instructions.hh:33219
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F16
Definition: instructions.hh:17635
gem5::VegaISA::Inst_VOPC__V_CMP_U_F64
Definition: instructions.hh:13113
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F16
Definition: instructions.hh:17907
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16
Definition: instructions.hh:14575
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR3_B32
GPUStaticInst * decode_OPU_VOP3__V_OR3_B32(MachInst)
Definition: decoder.cc:7021
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SMIN
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8909
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8589
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:12699
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U8_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U8_F32(MachInst)
Definition: decoder.cc:6788
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32
Definition: instructions.hh:19097
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:5096
gem5::VegaISA::Inst_VOP2__V_ADD_F32
Definition: instructions.hh:6243
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:11913
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SETVSKIP
GPUStaticInst * decode_OP_SOPC__S_SETVSKIP(MachInst)
Definition: decoder.cc:11031
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECZ
Definition: instructions.hh:4731
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ
Definition: instructions.hh:40073
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_B64
GPUStaticInst * decode_OP_DS__DS_OR_B64(MachInst)
Definition: decoder.cc:7696
gem5::VegaISA::Inst_SOP2__S_LSHL_B32
Definition: instructions.hh:997
gem5::VegaISA::Inst_VOP3__V_QSAD_PK_U16_U8
Definition: instructions.hh:29483
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16
Definition: instructions.hh:20797
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B64
GPUStaticInst * decode_OP_DS__DS_WRITE_B64(MachInst)
Definition: decoder.cc:7714
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32
Definition: instructions.hh:15969
gem5::VegaISA::Inst_SOP1__S_ANDN2_SAVEEXEC_B64
Definition: instructions.hh:3367
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U16
GPUStaticInst * decode_OP_VOP2__V_MIN_U16(MachInst)
Definition: decoder.cc:4139
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_X
Definition: instructions.hh:38089
gem5::VegaISA::Inst_VOP3__V_EXP_LEGACY_F32
Definition: instructions.hh:28081
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV(MachInst)
Definition: decoder.cc:10180
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F16
Definition: instructions.hh:17533
gem5::VegaISA::Inst_SOPP__S_INCPERFLEVEL
Definition: instructions.hh:5091
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_U32
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:11296
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:12159
gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4
Definition: instructions.hh:5643
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFI_B32
GPUStaticInst * decode_OPU_VOP3__V_BFI_B32(MachInst)
Definition: decoder.cc:6674
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F16
GPUStaticInst * decode_OPU_VOP3__V_MIN_F16(MachInst)
Definition: decoder.cc:6122
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:9797
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_SCALE_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_SCALE_F64(MachInst)
Definition: decoder.cc:6812
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL
Definition: instructions.hh:41045
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U32(MachInst)
Definition: decoder.cc:7444
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:11997
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32_I64
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32_I64(MachInst)
Definition: decoder.cc:10732
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_I16(MachInst)
Definition: decoder.cc:12369
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9477
gem5::VegaISA::Inst_DS__DS_RSUB_SRC2_U32
Definition: instructions.hh:34617
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:11787
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LERP_U8
GPUStaticInst * decode_OPU_VOP3__V_LERP_U8(MachInst)
Definition: decoder.cc:6692
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64
Definition: instructions.hh:23993
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_B32
GPUStaticInst * decode_OP_DS__DS_XOR_B32(MachInst)
Definition: decoder.cc:7359
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN1_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN1_WREXEC_B64(MachInst)
Definition: decoder.cc:10914
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I32
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:5972
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U32
Definition: instructions.hh:4071
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_OR_USER
Definition: instructions.hh:5241
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_AND(MachInst)
Definition: decoder.cc:10480
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_BYTE
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_BYTE(MachInst)
Definition: decoder.cc:9615
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F32
GPUStaticInst * decode_OP_VOP1__V_SQRT_F32(MachInst)
Definition: decoder.cc:11488
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_B32
GPUStaticInst * decode_OP_DS__DS_CMPST_B32(MachInst)
Definition: decoder.cc:7389
gem5::VegaISA::Decoder::subDecode_OPU_VOP3
GPUStaticInst * subDecode_OPU_VOP3(MachInst)
Definition: decoder.cc:3776
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I16_F16
Definition: instructions.hh:10141
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAD_I16(MachInst)
Definition: decoder.cc:12921
gem5::VegaISA::Inst_VOP3__V_MAX_I32
Definition: instructions.hh:24471
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64
Definition: instructions.hh:20559
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:5804
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64
Definition: instructions.hh:13691
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_U64
GPUStaticInst * decode_OP_DS__DS_SUB_U64(MachInst)
Definition: decoder.cc:7642
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:9591
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:12033
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MAX_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MAX_F16(MachInst)
Definition: decoder.cc:13047
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL
Definition: instructions.hh:39641
gem5::VegaISA::Inst_VOP3__V_CMP_T_I16
Definition: instructions.hh:21001
gem5::VegaISA::Inst_VOP3__V_RNDNE_F64
Definition: instructions.hh:26581
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16
Definition: instructions.hh:14949
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX4(MachInst)
Definition: decoder.cc:10086
gem5::VegaISA::Inst_VOP3__V_FMA_F64
Definition: instructions.hh:28577
gem5::VegaISA::Inst_VOP1__V_RCP_IFLAG_F32
Definition: instructions.hh:9217
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:8771
gem5::VegaISA::Inst_SOP2__S_BFE_I32
Definition: instructions.hh:1337
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16
Definition: instructions.hh:21171
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP_PCK_SGN(MachInst)
Definition: decoder.cc:8849
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_DEC
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_DEC(MachInst)
Definition: decoder.cc:8957
gem5::VegaISA::Decoder::decode_OP_DS__DS_SUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_SUB_RTN_U64(MachInst)
Definition: decoder.cc:7817
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16_D16_HI
GPUStaticInst * decode_OP_DS__DS_READ_U16_D16_HI(MachInst)
Definition: decoder.cc:7804
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32
Definition: instructions.hh:15459
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F16
Definition: instructions.hh:11039
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:11853
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F16
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F16(MachInst)
Definition: decoder.cc:6572
gem5::VegaISA::Inst_VOP3__V_MAX_F32
Definition: instructions.hh:24403
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:9791
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32
Definition: instructions.hh:12161
gem5::VegaISA::Inst_VOP3__V_LOG_F32
Definition: instructions.hh:26837
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B64
Definition: instructions.hh:34183
gem5::VegaISA::Inst_VOP3__V_SQRT_F64
Definition: instructions.hh:27061
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:10149
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8813
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U32
Definition: instructions.hh:32073
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_U64
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_U64(MachInst)
Definition: decoder.cc:11049
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F16
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F16(MachInst)
Definition: decoder.cc:6566
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_I16_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_I16_I32(MachInst)
Definition: decoder.cc:7238
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_READLANE_B32
GPUStaticInst * decode_OPU_VOP3__V_READLANE_B32(MachInst)
Definition: decoder.cc:7154
gem5::VegaISA::Inst_VOP2__V_SUB_F16
Definition: instructions.hh:7315
gem5::VegaISA::Inst_VOP3__V_MAC_F16
Definition: instructions.hh:25205
gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE
Definition: instructions.hh:42207
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:8516
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2
Definition: instructions.hh:5427
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F16
Definition: instructions.hh:18485
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZ(MachInst)
Definition: decoder.cc:9483
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT
Definition: instructions.hh:36871
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10466
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64
Definition: instructions.hh:13589
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_U64
GPUStaticInst * decode_OP_DS__DS_INC_U64(MachInst)
Definition: decoder.cc:7654
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:4700
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9916
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32_B32
Definition: instructions.hh:2825
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:5630
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I64(MachInst)
Definition: decoder.cc:12771
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F16
Definition: instructions.hh:10597
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I16(MachInst)
Definition: decoder.cc:7039
gem5::VegaISA::Decoder::decode_OP_VINTRP__V_INTERP_P2_F32
GPUStaticInst * decode_OP_VINTRP__V_INTERP_P2_F32(MachInst)
Definition: decoder.cc:11248
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B
Definition: instructions.hh:41009
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_U64(MachInst)
Definition: decoder.cc:7648
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16
Definition: instructions.hh:21069
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B32(MachInst)
Definition: decoder.cc:7516
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:36171
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F16
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F16(MachInst)
Definition: decoder.cc:6578
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32
Definition: instructions.hh:22701
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_U16(MachInst)
Definition: decoder.cc:6963
gem5::VegaISA::Decoder::decode_OP_SOPP__S_ICACHE_INV
GPUStaticInst * decode_OP_SOPP__S_ICACHE_INV(MachInst)
Definition: decoder.cc:11169
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16(MachInst)
Definition: decoder.cc:10131
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64
Definition: instructions.hh:16853
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:12915
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE
Definition: instructions.hh:36513
gem5::VegaISA::Inst_VOP3__V_LDEXP_F64
Definition: instructions.hh:30505
gem5::VegaISA::Inst_DS__DS_SUB_U64
Definition: instructions.hh:33123
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_AND
Definition: instructions.hh:42735
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:9888
gem5::VegaISA::Inst_DS__DS_MAX_RTN_I64
Definition: instructions.hh:33945
gem5::VegaISA::Inst_SOPP__S_SET_GPR_IDX_OFF
Definition: instructions.hh:5331
gem5::VegaISA::Inst_VOP3__V_OR_B32
Definition: instructions.hh:24709
gem5::VegaISA::Inst_VOP2__V_MUL_LEGACY_F32
Definition: instructions.hh:6345
gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16
Definition: instructions.hh:18009
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZ
Definition: instructions.hh:36285
gem5::VegaISA::Decoder::tableSubDecode_OP_SCRATCH
static IsaDecodeMethod tableSubDecode_OP_SCRATCH[128]
Definition: gpu_decoder.hh:69
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_F64(MachInst)
Definition: decoder.cc:6260
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_F32
GPUStaticInst * decode_OP_VOP2__V_MUL_F32(MachInst)
Definition: decoder.cc:3875
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_F32
GPUStaticInst * decode_OP_VOP2__V_SUB_F32(MachInst)
Definition: decoder.cc:3857
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_MIP(MachInst)
Definition: decoder.cc:8861
gem5::VegaISA::Inst_DS__DS_CONDXCHG32_RTN_B64
Definition: instructions.hh:34523
gem5::VegaISA::Inst_VOP3__V_CUBESC_F32
Definition: instructions.hh:28325
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F64(MachInst)
Definition: decoder.cc:5276
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FRACT_F16
GPUStaticInst * decode_OPU_VOP3__V_FRACT_F16(MachInst)
Definition: decoder.cc:6584
gem5::VegaISA::Inst_DS__DS_MAX_RTN_F64
Definition: instructions.hh:34387
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F16(MachInst)
Definition: decoder.cc:4706
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I32(MachInst)
Definition: decoder.cc:12675
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F16(MachInst)
Definition: decoder.cc:11799
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10816
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F32(MachInst)
Definition: decoder.cc:3863
gem5::VegaISA::Inst_VOPC__V_CMP_F_F32
Definition: instructions.hh:11753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBETC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBETC_F32(MachInst)
Definition: decoder.cc:6650
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_U16(MachInst)
Definition: decoder.cc:12998
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F16(MachInst)
Definition: decoder.cc:11889
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:11919
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32
Definition: instructions.hh:22395
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_HI_U8
GPUStaticInst * decode_OPU_VOP3__V_SAD_HI_U8(MachInst)
Definition: decoder.cc:6770
gem5::VegaISA::Inst_SOP2__S_ORN2_B32
Definition: instructions.hh:725
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F32(MachInst)
Definition: decoder.cc:4916
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XY
Definition: instructions.hh:38279
gem5::VegaISA::Inst_VOP1__V_COS_F32
Definition: instructions.hh:9441
gem5::VegaISA::Inst_VOP1__V_FRACT_F32
Definition: instructions.hh:8961
gem5::VegaISA::Inst_VOPC__V_CMP_T_I32
Definition: instructions.hh:15255
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LL_F16
Definition: instructions.hh:30263
gem5::VegaISA::Inst_VOP2__V_OR_B32
Definition: instructions.hh:6889
gem5::VegaISA::Inst_VOPC__V_CMP_F_I32
Definition: instructions.hh:15017
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:8759
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8480
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B(MachInst)
Definition: decoder.cc:9041
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I16_F16
GPUStaticInst * decode_OP_VOP1__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:11603
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10557
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F64
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:6464
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:5840
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32
Definition: instructions.hh:19131
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F16(MachInst)
Definition: decoder.cc:4772
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SQRT_F64
GPUStaticInst * decode_OPU_VOP3__V_SQRT_F64(MachInst)
Definition: decoder.cc:6410
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I16(MachInst)
Definition: decoder.cc:5300
gem5::VegaISA::Decoder::decode_OP_DS__DS_MSKOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_MSKOR_RTN_B64(MachInst)
Definition: decoder.cc:7883
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F32(MachInst)
Definition: decoder.cc:4934
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_U32(MachInst)
Definition: decoder.cc:5570
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE1
Definition: instructions.hh:8673
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32
Definition: instructions.hh:15561
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GET_RESINFO
GPUStaticInst * decode_OP_MIMG__IMAGE_GET_RESINFO(MachInst)
Definition: decoder.cc:8879
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32
Definition: instructions.hh:19165
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U32
Definition: instructions.hh:32039
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U32
GPUStaticInst * decode_OP_VOP2__V_ADD_U32(MachInst)
Definition: decoder.cc:4157
gem5::VegaISA::Inst_VOP1__V_CVT_I16_F16
Definition: instructions.hh:9917
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_O(MachInst)
Definition: decoder.cc:9350
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U64(MachInst)
Definition: decoder.cc:8130
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32
Definition: instructions.hh:12297
gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64
Definition: instructions.hh:13555
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32
Definition: instructions.hh:16037
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:38203
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U64(MachInst)
Definition: decoder.cc:12819
gem5::VegaISA::Inst_VOP2__V_MUL_F16
Definition: instructions.hh:7383
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE(MachInst)
Definition: decoder.cc:8570
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:10298
gem5::VegaISA::Inst_SOP2__S_NAND_B64
Definition: instructions.hh:827
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:5828
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2ST64_B32
GPUStaticInst * decode_OP_DS__DS_READ2ST64_B32(MachInst)
Definition: decoder.cc:7588
gem5::VegaISA::IsaDecodeMethod
GPUStaticInst *(Decoder::*)(MachInst) IsaDecodeMethod
Definition: gpu_decoder.hh:50
gem5::VegaISA::Inst_VOP3__V_PERM_B32
Definition: instructions.hh:29991
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F64
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F64(MachInst)
Definition: decoder.cc:6800
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32
Definition: instructions.hh:22429
gem5::VegaISA::Inst_VOP2__V_AND_B32
Definition: instructions.hh:6855
gem5::VegaISA::Inst_VOP3__V_TRUNC_F32
Definition: instructions.hh:26677
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B128
GPUStaticInst * decode_OP_DS__DS_WRITE_B128(MachInst)
Definition: decoder.cc:8208
gem5::VegaISA::Inst_SOP1__S_BREV_B32
Definition: instructions.hh:2505
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:12525
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F16
GPUStaticInst * decode_OP_VOP1__V_LOG_F16(MachInst)
Definition: decoder.cc:11627
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT0_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT0_I32_B64(MachInst)
Definition: decoder.cc:10672
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_CL
Definition: instructions.hh:40721
gem5::VegaISA::Inst_VOP3__V_CVT_I16_F16
Definition: instructions.hh:27601
gem5::VegaISA::Inst_VOP3__V_ADD3_U32
Definition: instructions.hh:29775
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:8628
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_U32(MachInst)
Definition: decoder.cc:6206
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORDX4
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9659
gem5::VegaISA::Decoder::decode_OP_DS__DS_AND_B64
GPUStaticInst * decode_OP_DS__DS_AND_B64(MachInst)
Definition: decoder.cc:7690
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F32
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F32(MachInst)
Definition: decoder.cc:6794
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I16
GPUStaticInst * decode_OPU_VOP3__V_MED3_I16(MachInst)
Definition: decoder.cc:6977
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U32_U16
GPUStaticInst * decode_OPU_VOP3__V_MAD_U32_U16(MachInst)
Definition: decoder.cc:6908
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_I16(MachInst)
Definition: decoder.cc:12977
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_PCK
Definition: instructions.hh:38985
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F64(MachInst)
Definition: decoder.cc:12255
gem5::VegaISA::Inst_VOP2__V_SUB_CO_U32
Definition: instructions.hh:7095
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I32(MachInst)
Definition: decoder.cc:5582
gem5::VegaISA::Inst_VOP3__V_MIN_F64
Definition: instructions.hh:30437
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ASHRREV_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ASHRREV_I16(MachInst)
Definition: decoder.cc:12963
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_U32(MachInst)
Definition: decoder.cc:5564
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U16(MachInst)
Definition: decoder.cc:12399
gem5::VegaISA::Inst_VOP3__V_CUBEID_F32
Definition: instructions.hh:28289
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LL_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LL_F16(MachInst)
Definition: decoder.cc:7075
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10536
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U8
GPUStaticInst * decode_OP_DS__DS_READ_U8(MachInst)
Definition: decoder.cc:7600
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_U32(MachInst)
Definition: decoder.cc:7492
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U16
GPUStaticInst * decode_OPU_VOP3__V_MED3_U16(MachInst)
Definition: decoder.cc:6984
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:10270
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U16(MachInst)
Definition: decoder.cc:5474
gem5::VegaISA::InstFormat::iFmt_FLAT
InFmt_FLAT iFmt_FLAT
Definition: gpu_decoder.hh:1916
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2_B64(MachInst)
Definition: decoder.cc:7720
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS
Definition: instructions.hh:5181
gem5::VegaISA::Inst_VOP1__V_EXP_F32
Definition: instructions.hh:9121
gem5::VegaISA::InFmt_VOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1838
gem5::VegaISA::Inst_VOP3__V_AND_OR_B32
Definition: instructions.hh:29847
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL_B32
GPUStaticInst * decode_OP_SOP2__S_LSHL_B32(MachInst)
Definition: decoder.cc:4392
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_F64
GPUStaticInst * decode_OPU_VOP3__V_ADD_F64(MachInst)
Definition: decoder.cc:7100
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RNDNE_F64
GPUStaticInst * decode_OPU_VOP3__V_RNDNE_F64(MachInst)
Definition: decoder.cc:6320
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:10375
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_I16
GPUStaticInst * decode_OP_VOP2__V_MAX_I16(MachInst)
Definition: decoder.cc:4133
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U64
Definition: instructions.hh:35349
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:5594
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:10284
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:5786
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_XYZ
Definition: instructions.hh:36133
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_U16
GPUStaticInst * decode_OPU_VOP3__V_SUB_U16(MachInst)
Definition: decoder.cc:6080
gem5::VegaISA::Inst_VOP3__V_CMP_F_U64
Definition: instructions.hh:23211
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F64
Definition: instructions.hh:34319
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8603
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MSAD_U8
GPUStaticInst * decode_OPU_VOP3__V_MSAD_U8(MachInst)
Definition: decoder.cc:6830
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_U32(MachInst)
Definition: decoder.cc:5648
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_MOV_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_MOV_F32(MachInst)
Definition: decoder.cc:7069
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I32
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I32(MachInst)
Definition: decoder.cc:3947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_CLASS_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:4712
gem5::VegaISA::InstFormat::iFmt_VOP3B
InFmt_VOP3B iFmt_VOP3B
Definition: gpu_decoder.hh:1937
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_DISCARD_X2
GPUStaticInst * decode_OP_SMEM__S_DCACHE_DISCARD_X2(MachInst)
Definition: decoder.cc:10235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I64(MachInst)
Definition: decoder.cc:5792
gem5::VegaISA::Inst_VOP1__V_FRACT_F16
Definition: instructions.hh:10301
gem5::VegaISA::Decoder::decode_OP_SOP1__S_RFE_B64
GPUStaticInst * decode_OP_SOP1__S_RFE_B64(MachInst)
Definition: decoder.cc:10792
gem5::VegaISA::Inst_VOPC__V_CMP_T_I16
Definition: instructions.hh:14167
gem5::VegaISA::Inst_DS__DS_XOR_B32
Definition: instructions.hh:31541
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B64
Definition: instructions.hh:30879
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:8807
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F16
Definition: instructions.hh:11549
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F64
GPUStaticInst * decode_OPU_VOP3__V_FMA_F64(MachInst)
Definition: decoder.cc:6686
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER8H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER8H_PCK(MachInst)
Definition: decoder.cc:9217
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B32
Definition: instructions.hh:32413
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B64
Definition: instructions.hh:34285
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I64(MachInst)
Definition: decoder.cc:5798
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B96
GPUStaticInst * decode_OP_DS__DS_READ_B96(MachInst)
Definition: decoder.cc:8214
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:11368
gem5::VegaISA::Inst_SOPK__S_CMPK_GT_I32
Definition: instructions.hh:1737
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64
Definition: instructions.hh:23823
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B64
GPUStaticInst * decode_OP_SOP1__S_MOV_B64(MachInst)
Definition: decoder.cc:10612
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:6020
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:12801
gem5::VegaISA::Inst_SOPK__S_CMPK_LT_I32
Definition: instructions.hh:1801
gem5::VegaISA::Inst_SOP2__S_SUBB_U32
Definition: instructions.hh:215
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_U32
Definition: instructions.hh:1961
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MAX_RTN_I64(MachInst)
Definition: decoder.cc:7847
gem5::VegaISA::Inst_VOP1__V_MOV_B32
Definition: instructions.hh:8129
gem5::VegaISA::Inst_SOP1__S_CMOV_B64
Definition: instructions.hh:2345
gem5::VegaISA::Inst_DS__DS_XOR_B64
Definition: instructions.hh:33443
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_LO_U16
GPUStaticInst * decode_OP_VOP2__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:4091
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:11835
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1_F32
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1_F32(MachInst)
Definition: decoder.cc:7057
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XY(MachInst)
Definition: decoder.cc:9404
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:12081
gem5::VegaISA::Inst_VOP2__V_XOR_B32
Definition: instructions.hh:6923
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B64
Definition: instructions.hh:30845
gem5::VegaISA::Decoder::decode_OP_VOP2__V_CNDMASK_B32
GPUStaticInst * decode_OP_VOP2__V_CNDMASK_B32(MachInst)
Definition: decoder.cc:3845
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_IFLAG_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_IFLAG_F32(MachInst)
Definition: decoder.cc:6380
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX_F16(MachInst)
Definition: decoder.cc:6116
gem5::VegaISA::Inst_DS__DS_WRXCHG_RTN_B32
Definition: instructions.hh:32447
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U32
GPUStaticInst * decode_OPU_VOP3__V_MAX_U32(MachInst)
Definition: decoder.cc:5960
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_U32
GPUStaticInst * decode_OP_VOP1__V_FFBH_U32(MachInst)
Definition: decoder.cc:11524
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:6218
gem5::VegaISA::Inst_SOP2__S_MIN_I32
Definition: instructions.hh:249
gem5::VegaISA::Inst_VOP3__V_ADD_U32
Definition: instructions.hh:25715
gem5::VegaISA::Decoder::decode_OP_SOP2__S_XNOR_B64
GPUStaticInst * decode_OP_SOP2__S_XNOR_B64(MachInst)
Definition: decoder.cc:4386
gem5::VegaISA::Inst_VOP1__V_EXP_LEGACY_F32
Definition: instructions.hh:10397
gem5::VegaISA::InFmt_VINTRP
Definition: gpu_decoder.hh:1786
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_F32(MachInst)
Definition: decoder.cc:8039
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_O(MachInst)
Definition: decoder.cc:9107
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I16(MachInst)
Definition: decoder.cc:12447
gem5::VegaISA::Decoder::decode_OP_SMEM__S_SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:10023
gem5::VegaISA::Decoder::decode_OP_SOP1__S_AND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_AND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10798
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I16_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I16_F16(MachInst)
Definition: decoder.cc:11645
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_LDS_DWORD(MachInst)
Definition: decoder.cc:9665
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F64(MachInst)
Definition: decoder.cc:11548
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L_O
Definition: instructions.hh:41189
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_F16(MachInst)
Definition: decoder.cc:4742
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CLREXCP
GPUStaticInst * decode_OP_VOP1__V_CLREXCP(MachInst)
Definition: decoder.cc:11572
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F32(MachInst)
Definition: decoder.cc:5012
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32_U24
Definition: instructions.hh:24335
gem5::VegaISA::Inst_SOPK__S_SETREG_B32
Definition: instructions.hh:2185
gem5::VegaISA::Inst_SOPP__S_ENDPGM
Definition: instructions.hh:4517
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MAX_I32
GPUStaticInst * decode_OP_SOP2__S_MAX_I32(MachInst)
Definition: decoder.cc:4272
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_I32
GPUStaticInst * decode_OPU_VOP3__V_MED3_I32(MachInst)
Definition: decoder.cc:6752
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32
Definition: instructions.hh:15731
gem5::VegaISA::Inst_VOP3__V_RSQ_F32
Definition: instructions.hh:26933
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:5192
gem5::VegaISA::InFmt_FLAT::SEG
unsigned int SEG
Definition: gpu_decoder.hh:1646
gem5::VegaISA::Inst_VOP3__V_RCP_F32
Definition: instructions.hh:26869
gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16
Definition: instructions.hh:14337
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F32(MachInst)
Definition: decoder.cc:12021
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16
Definition: instructions.hh:21749
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:12903
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD(MachInst)
Definition: decoder.cc:8819
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I64(MachInst)
Definition: decoder.cc:12837
gem5::VegaISA::Inst_VOP3__V_MAX_F64
Definition: instructions.hh:30471
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_MIP
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_MIP(MachInst)
Definition: decoder.cc:8825
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN1_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN1_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10907
gem5::VegaISA::Inst_SOP2__S_ANDN2_B32
Definition: instructions.hh:657
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_HI_I32
GPUStaticInst * decode_OPU_VOP3__V_MUL_HI_I32(MachInst)
Definition: decoder.cc:7142
gem5::VegaISA::Inst_SOP2__S_XNOR_B32
Definition: instructions.hh:929
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64
Definition: instructions.hh:20117
gem5::VegaISA::Inst_SOPP__S_ICACHE_INV
Definition: instructions.hh:5061
gem5::VegaISA::InstFormat::iFmt_VOP2
InFmt_VOP2 iFmt_VOP2
Definition: gpu_decoder.hh:1934
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_USHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_USHORT(MachInst)
Definition: decoder.cc:9579
gem5::VegaISA::Decoder::decode_OP_DS__DS_APPEND
GPUStaticInst * decode_OP_DS__DS_APPEND(MachInst)
Definition: decoder.cc:8100
gem5::VegaISA::Inst_DS__DS_MAX_RTN_U64
Definition: instructions.hh:34013
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F32
GPUStaticInst * decode_OP_VOP1__V_COS_F32(MachInst)
Definition: decoder.cc:11506
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64
Definition: instructions.hh:20287
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L(MachInst)
Definition: decoder.cc:8987
gem5::VegaISA::Inst_VOP3__V_INTERP_MOV_F32
Definition: instructions.hh:30229
gem5::VegaISA::Inst_VOP3__V_XAD_U32
Definition: instructions.hh:29667
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:10585
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:12315
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F32
GPUStaticInst * decode_OPU_VOP3__V_FMA_F32(MachInst)
Definition: decoder.cc:6680
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F32
GPUStaticInst * decode_OP_VOP2__V_MADAK_F32(MachInst)
Definition: decoder.cc:3989
gem5::VegaISA::Inst_VOP1__V_FLOOR_F16
Definition: instructions.hh:10173
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16
Definition: instructions.hh:14235
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_PK_U16_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_PK_U16_U32(MachInst)
Definition: decoder.cc:7232
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL_O(MachInst)
Definition: decoder.cc:9077
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ASHRREV_I16
GPUStaticInst * decode_OPU_VOP3__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:6110
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADDC_U32
GPUStaticInst * decode_OP_SOP2__S_ADDC_U32(MachInst)
Definition: decoder.cc:4248
gem5::VegaISA::Inst_DS__DS_MSKOR_RTN_B64
Definition: instructions.hh:34149
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_CL_O
Definition: instructions.hh:41837
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64
Definition: instructions.hh:23551
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64
Definition: instructions.hh:13181
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PACK_B32_F16
GPUStaticInst * decode_OPU_VOP3__V_PACK_B32_F16(MachInst)
Definition: decoder.cc:7286
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I64(MachInst)
Definition: decoder.cc:5684
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4
Definition: instructions.hh:36787
gem5::VegaISA::Inst_SOP2__S_CBRANCH_G_FORK
Definition: instructions.hh:1439
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_U16
GPUStaticInst * decode_OPU_VOP3__V_MAX_U16(MachInst)
Definition: decoder.cc:6128
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B32(MachInst)
Definition: decoder.cc:7504
gem5::VegaISA::Inst_VOP3__V_SUB_U16
Definition: instructions.hh:25273
gem5::VegaISA::Inst_VOP2__V_MIN_U32
Definition: instructions.hh:6685
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I64(MachInst)
Definition: decoder.cc:12861
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16(MachInst)
Definition: decoder.cc:8338
gem5::VegaISA::Inst_SOP1__S_BITSET0_B64
Definition: instructions.hh:3049
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:12237
gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32
Definition: instructions.hh:12637
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:5138
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_QSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_QSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6836
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8891
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_LEGACY_F16(MachInst)
Definition: decoder.cc:6890
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:9779
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F64_I32
GPUStaticInst * decode_OP_VOP1__V_CVT_F64_I32(MachInst)
Definition: decoder.cc:11284
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:10056
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U16(MachInst)
Definition: decoder.cc:4085
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SWAP
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:10424
gem5::VegaISA::Inst_VOP2__V_ASHRREV_I16
Definition: instructions.hh:7727
gem5::VegaISA::Inst_VOP3__V_CVT_OFF_F32_I4
Definition: instructions.hh:26229
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_WBINVL1
GPUStaticInst * decode_OP_MUBUF__BUFFER_WBINVL1(MachInst)
Definition: decoder.cc:9671
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_SUB
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_SUB(MachInst)
Definition: decoder.cc:8903
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX4
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX4(MachInst)
Definition: decoder.cc:8318
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_OR_B32
GPUStaticInst * decode_OPU_VOP3__V_OR_B32(MachInst)
Definition: decoder.cc:5990
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_U16(MachInst)
Definition: decoder.cc:5450
gem5::VegaISA::Inst_SMEM__S_STORE_DWORD
Definition: instructions.hh:5751
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBL_B32
GPUStaticInst * decode_OPU_VOP3__V_FFBL_B32(MachInst)
Definition: decoder.cc:6446
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NE_I16(MachInst)
Definition: decoder.cc:5324
gem5::VegaISA::Inst_VOP3__V_SUB_CO_U32
Definition: instructions.hh:24883
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_AND_B32
GPUStaticInst * decode_OPU_VOP3__V_AND_B32(MachInst)
Definition: decoder.cc:5984
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_I64(MachInst)
Definition: decoder.cc:5816
gem5::VegaISA::Inst_VOP1__V_CVT_FLR_I32_F32
Definition: instructions.hh:8513
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_L
Definition: instructions.hh:40757
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND_X2
Definition: instructions.hh:37909
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:5744
gem5::VegaISA::Inst_DS__DS_AND_B32
Definition: instructions.hh:31475
gem5::VegaISA::Inst_SMEM__S_BUFFER_STORE_DWORDX4
Definition: instructions.hh:5931
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_I16
GPUStaticInst * decode_OPU_VOP3__V_ADD_I16(MachInst)
Definition: decoder.cc:7272
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_XOR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8945
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16
Definition: instructions.hh:21477
gem5::VegaISA::Inst_SOPP__S_BARRIER
Definition: instructions.hh:4791
gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64
Definition: instructions.hh:16275
gem5::VegaISA::Decoder::decode_OP_SOP2__S_BFE_U32
GPUStaticInst * decode_OP_SOP2__S_BFE_U32(MachInst)
Definition: decoder.cc:4446
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B64
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B64(MachInst)
Definition: decoder.cc:8172
gem5::VegaISA::Decoder::decode_invalid
GPUStaticInst * decode_invalid(MachInst)
Definition: decoder.cc:13075
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_EQ_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_EQ_I32(MachInst)
Definition: decoder.cc:4561
gem5::VegaISA::InFmt_VOP3P
Definition: gpu_decoder.hh:1893
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BREV_B64
GPUStaticInst * decode_OP_SOP1__S_BREV_B64(MachInst)
Definition: decoder.cc:10660
gem5::VegaISA::Inst_SOP1__S_FF0_I32_B32
Definition: instructions.hh:2697
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C(MachInst)
Definition: decoder.cc:9198
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U32(MachInst)
Definition: decoder.cc:12681
gem5::VegaISA::Inst_VOP1__V_CVT_F32_I32
Definition: instructions.hh:8257
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SAD_U16
GPUStaticInst * decode_OPU_VOP3__V_SAD_U16(MachInst)
Definition: decoder.cc:6776
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:11781
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_I32(MachInst)
Definition: decoder.cc:10959
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:12069
gem5::VegaISA::Inst_VOP3__V_MSAD_U8
Definition: instructions.hh:29447
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:12405
gem5::VegaISA::Inst_SOPP__S_ENDPGM_SAVED
Definition: instructions.hh:5301
gem5::VegaISA::Decoder::subDecode_OP_MTBUF
GPUStaticInst * subDecode_OP_MTBUF(MachInst)
Definition: decoder.cc:3829
gem5::VegaISA::Inst_VOP1__V_NOT_B32
Definition: instructions.hh:9473
gem5::VegaISA::Decoder::decode_OP_DS__DS_SWIZZLE_B32
GPUStaticInst * decode_OP_DS__DS_SWIZZLE_B32(MachInst)
Definition: decoder.cc:7618
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_B32(MachInst)
Definition: decoder.cc:7371
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2
Definition: instructions.hh:42998
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32
Definition: instructions.hh:19063
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMAX
Definition: instructions.hh:39329
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2
Definition: instructions.hh:43037
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F16(MachInst)
Definition: decoder.cc:11763
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ_O
Definition: instructions.hh:41297
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RCP_F32
GPUStaticInst * decode_OP_VOP1__V_RCP_F32(MachInst)
Definition: decoder.cc:11458
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U32(MachInst)
Definition: decoder.cc:7130
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:12453
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SIN_F16
GPUStaticInst * decode_OPU_VOP3__V_SIN_F16(MachInst)
Definition: decoder.cc:6590
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXLO_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXLO_F16(MachInst)
Definition: decoder.cc:13061
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I16(MachInst)
Definition: decoder.cc:12363
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_LZ
Definition: instructions.hh:40865
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64
Definition: instructions.hh:13487
gem5::VegaISA::Inst_VOP3__V_CMP_F_U16
Definition: instructions.hh:21035
gem5::VegaISA::Inst_VOP3__V_CVT_F32_I32
Definition: instructions.hh:25941
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC_X2(MachInst)
Definition: decoder.cc:9827
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_F32(MachInst)
Definition: decoder.cc:8033
gem5::VegaISA::Inst_SOP1__S_MOV_B32
Definition: instructions.hh:2249
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_UMIN
Definition: instructions.hh:39261
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:10113
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32
Definition: instructions.hh:15867
gem5::VegaISA::Inst_SOP1__S_AND_SAVEEXEC_B64
Definition: instructions.hh:3271
gem5::VegaISA::Inst_DS__DS_ADD_SRC2_U64
Definition: instructions.hh:35319
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAC_F16
GPUStaticInst * decode_OP_VOP2__V_MAC_F16(MachInst)
Definition: decoder.cc:4055
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_I32(MachInst)
Definition: decoder.cc:4494
gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16
Definition: instructions.hh:14133
gem5::VegaISA::Inst_VOP1__V_TRUNC_F32
Definition: instructions.hh:8993
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F32(MachInst)
Definition: decoder.cc:5084
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ_O(MachInst)
Definition: decoder.cc:9149
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SENDMSG
GPUStaticInst * decode_OP_SOPP__S_SENDMSG(MachInst)
Definition: decoder.cc:11151
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORD
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORD(MachInst)
Definition: decoder.cc:10044
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL_O(MachInst)
Definition: decoder.cc:9095
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_ADD
Definition: instructions.hh:39159
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRAP_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRAP_RTN_B32(MachInst)
Definition: decoder.cc:7564
gem5::VegaISA::Inst_SOPC__S_SET_GPR_IDX_ON
Definition: instructions.hh:4391
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZ(MachInst)
Definition: decoder.cc:9434
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_U64_U32
GPUStaticInst * decode_OPU_VOP3__V_MAD_U64_U32(MachInst)
Definition: decoder.cc:6854
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX4
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:10005
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64
Definition: instructions.hh:16751
gem5::VegaISA::Decoder::tableSubDecode_OP_MUBUF
static IsaDecodeMethod tableSubDecode_OP_MUBUF[128]
Definition: gpu_decoder.hh:68
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_LZ_O(MachInst)
Definition: decoder.cc:9101
gem5::VegaISA::Inst_VOP3__V_CVT_PKRTZ_F16_F32
Definition: instructions.hh:31083
gem5::VegaISA::Inst_VOP2__V_MIN_U16
Definition: instructions.hh:7897
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:5480
gem5::VegaISA::Decoder::decode_OP_VOP1__V_BFREV_B32
GPUStaticInst * decode_OP_VOP1__V_BFREV_B32(MachInst)
Definition: decoder.cc:11518
gem5::VegaISA::Inst_VOP3__V_MAX3_U32
Definition: instructions.hh:28901
gem5::VegaISA::Inst_VOPC__V_CMP_GE_F16
Definition: instructions.hh:10869
gem5::VegaISA::Decoder::decode_OP_SOP2__S_CSELECT_B32
GPUStaticInst * decode_OP_SOP2__S_CSELECT_B32(MachInst)
Definition: decoder.cc:4284
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:6278
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32
Definition: instructions.hh:15051
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_F32
GPUStaticInst * decode_OPU_VOP3__V_MIN_F32(MachInst)
Definition: decoder.cc:5930
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64
Definition: instructions.hh:13351
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8528
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_ADD
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8378
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16
Definition: instructions.hh:14031
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L_O(MachInst)
Definition: decoder.cc:9131
gem5::VegaISA::Inst_DS__DS_OR_B64
Definition: instructions.hh:33411
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F64
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:11278
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_OR
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_OR(MachInst)
Definition: decoder.cc:8939
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_WRITE_SRC2_B32(MachInst)
Definition: decoder.cc:8027
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:11871
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP_PCK
Definition: instructions.hh:38841
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX8(MachInst)
Definition: decoder.cc:10062
gem5::VegaISA::Inst_VOP3__V_ADD_F32
Definition: instructions.hh:24063
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3
Definition: instructions.hh:42133
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_INC_X2
Definition: instructions.hh:43333
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U32(MachInst)
Definition: decoder.cc:7955
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:11847
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_F16
GPUStaticInst * decode_OP_VOP1__V_EXP_F16(MachInst)
Definition: decoder.cc:11633
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_F64(MachInst)
Definition: decoder.cc:12177
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:5114
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ASHR_I64
GPUStaticInst * decode_OP_SOP2__S_ASHR_I64(MachInst)
Definition: decoder.cc:4422
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SWAP
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:9683
gem5::VegaISA::Decoder::subDecode_OP_FLAT
GPUStaticInst * subDecode_OP_FLAT(MachInst)
Definition: decoder.cc:3800
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_I32_F32(MachInst)
Definition: decoder.cc:11308
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32
Definition: instructions.hh:11787
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CEIL_F32
GPUStaticInst * decode_OP_VOP1__V_CEIL_F32(MachInst)
Definition: decoder.cc:11428
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC_X2(MachInst)
Definition: decoder.cc:9833
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_DWORDX3(MachInst)
Definition: decoder.cc:8609
gem5::VegaISA::Inst_VOP3__V_MAD_F32
Definition: instructions.hh:28181
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F16
Definition: instructions.hh:10767
gem5::VegaISA::Decoder::decode_OP_VOP1__V_NOT_B32
GPUStaticInst * decode_OP_VOP1__V_NOT_B32(MachInst)
Definition: decoder.cc:11512
gem5::VegaISA::Inst_SOPC__S_CMP_LG_U64
Definition: instructions.hh:4455
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B64
GPUStaticInst * decode_OP_SOP2__S_ORN2_B64(MachInst)
Definition: decoder.cc:4350
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F32
Definition: instructions.hh:29373
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32
Definition: instructions.hh:12433
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B32(MachInst)
Definition: decoder.cc:5978
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H(MachInst)
Definition: decoder.cc:9167
gem5::VegaISA::Inst_VOP3__V_MAD_LEGACY_F32
Definition: instructions.hh:28145
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_CL(MachInst)
Definition: decoder.cc:9204
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL1_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL1_ADD_U32(MachInst)
Definition: decoder.cc:4500
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F32(MachInst)
Definition: decoder.cc:5048
gem5::VegaISA::InstFormat::iFmt_DS
InFmt_DS iFmt_DS
Definition: gpu_decoder.hh:1912
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U32
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U32(MachInst)
Definition: decoder.cc:7456
gem5::VegaISA::Inst_VOP2__V_ADD_U16
Definition: instructions.hh:7523
gem5::VegaISA::Inst_VOP2__V_MUL_HI_U32_U24
Definition: instructions.hh:6515
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B16
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:6104
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B64
GPUStaticInst * decode_OP_SOP2__S_NAND_B64(MachInst)
Definition: decoder.cc:4362
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I32(MachInst)
Definition: decoder.cc:12549
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32
Definition: instructions.hh:15697
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_U32(MachInst)
Definition: decoder.cc:4163
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B64
Definition: instructions.hh:35619
gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F64
Definition: instructions.hh:29411
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9452
gem5::VegaISA::Inst_VOP3__V_SAD_U32
Definition: instructions.hh:29153
gem5::VegaISA::Inst_VOP3__V_MAX3_I32
Definition: instructions.hh:28865
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32
Definition: instructions.hh:15833
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10167
gem5::VegaISA::Decoder::subDecode_OP_MUBUF
GPUStaticInst * subDecode_OP_MUBUF(MachInst)
Definition: decoder.cc:3821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F32(MachInst)
Definition: decoder.cc:5066
gem5::VegaISA::Inst_VOP3__V_SAD_HI_U8
Definition: instructions.hh:29081
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F16
Definition: instructions.hh:17941
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_O
Definition: instructions.hh:40469
gem5::VegaISA::Decoder::decode_OP_VOP2__V_FMAC_F32
GPUStaticInst * decode_OP_VOP2__V_FMAC_F32(MachInst)
Definition: decoder.cc:4203
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_U16
GPUStaticInst * decode_OPU_VOP3__V_ADD_U16(MachInst)
Definition: decoder.cc:6074
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LO_U16
GPUStaticInst * decode_OPU_VOP3__V_MUL_LO_U16(MachInst)
Definition: decoder.cc:6092
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I32(MachInst)
Definition: decoder.cc:12669
gem5::VegaISA::Inst_VOP2__V_ADDC_CO_U32
Definition: instructions.hh:7167
gem5::VegaISA::Inst_VOP3__V_MAX3_F32
Definition: instructions.hh:28829
gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F16
Definition: instructions.hh:11141
gem5::VegaISA::Decoder::decode_OP_SOP1__S_FLBIT_I32
GPUStaticInst * decode_OP_SOP1__S_FLBIT_I32(MachInst)
Definition: decoder.cc:10726
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_XOR_SRC2_B32(MachInst)
Definition: decoder.cc:8021
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_U16
GPUStaticInst * decode_OP_DS__DS_READ_U16(MachInst)
Definition: decoder.cc:7612
gem5::VegaISA::Inst_VOP3__V_COS_F32
Definition: instructions.hh:27125
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B_CL
Definition: instructions.hh:39749
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:5282
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F16
Definition: instructions.hh:11413
gem5::VegaISA::Inst_VOP3__V_ADDC_CO_U32
Definition: instructions.hh:24955
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F16(MachInst)
Definition: decoder.cc:11829
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_USHORT
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_USHORT(MachInst)
Definition: decoder.cc:9853
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32
GPUStaticInst * decode_OP_VOP1__V_SCREEN_PARTITION_4SE_B32(MachInst)
Definition: decoder.cc:11578
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_X(MachInst)
Definition: decoder.cc:9374
gem5::VegaISA::Decoder::decode_OP_SOPP__S_TTRACEDATA
GPUStaticInst * decode_OP_SOPP__S_TTRACEDATA(MachInst)
Definition: decoder.cc:11187
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_INC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_INC(MachInst)
Definition: decoder.cc:9749
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LOG_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_LOG_LEGACY_F32(MachInst)
Definition: decoder.cc:6608
gem5::VegaISA::Inst_DS__DS_RSUB_U64
Definition: instructions.hh:33155
gem5::VegaISA::InFmt_VOP3A::OP
unsigned int OP
Definition: gpu_decoder.hh:1815
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_RPI_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_RPI_I32_F32(MachInst)
Definition: decoder.cc:11326
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:12129
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16
Definition: instructions.hh:14677
gem5::VegaISA::Inst_VOP3__V_SUB_F16
Definition: instructions.hh:25103
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP(MachInst)
Definition: decoder.cc:8669
gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64
Definition: instructions.hh:23109
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_O
Definition: instructions.hh:40181
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B32
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B32(MachInst)
Definition: decoder.cc:11013
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F16
Definition: instructions.hh:18315
gem5::VegaISA::Inst_VOP3__V_WRITELANE_B32
Definition: instructions.hh:30709
gem5::VegaISA::Inst_VOP2__V_MAX_U16
Definition: instructions.hh:7829
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F64(MachInst)
Definition: decoder.cc:5186
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLG_F64(MachInst)
Definition: decoder.cc:5258
gem5::VegaISA::Inst_VOP3__V_CMP_F_F64
Definition: instructions.hh:19675
gem5::VegaISA::Decoder::decode_OP_SOP2__S_LSHL4_ADD_U32
GPUStaticInst * decode_OP_SOP2__S_LSHL4_ADD_U32(MachInst)
Definition: decoder.cc:4521
gem5::VegaISA::Inst_VOPC__V_CMP_O_F64
Definition: instructions.hh:13079
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_AND
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_AND(MachInst)
Definition: decoder.cc:8414
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE3
Definition: instructions.hh:8737
gem5::VegaISA::Decoder::decode_OP_VOP1__V_READFIRSTLANE_B32
GPUStaticInst * decode_OP_VOP1__V_READFIRSTLANE_B32(MachInst)
Definition: decoder.cc:11272
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_TRUNC_F64
GPUStaticInst * decode_OPU_VOP3__V_TRUNC_F64(MachInst)
Definition: decoder.cc:6308
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64
Definition: instructions.hh:13759
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL_O(MachInst)
Definition: decoder.cc:9254
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:5426
gem5::VegaISA::InFmt_MTBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1695
gpu_decoder.hh
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_OR
Definition: instructions.hh:39397
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_EXP_I32_F64
GPUStaticInst * decode_OP_VOP1__V_FREXP_EXP_I32_F64(MachInst)
Definition: decoder.cc:11542
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F16
Definition: instructions.hh:11481
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:36323
gem5::VegaISA::Inst_VOP3__V_CMP_F_I64
Definition: instructions.hh:22939
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F16
GPUStaticInst * decode_OP_VOP2__V_MIN_F16(MachInst)
Definition: decoder.cc:4121
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8642
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:12051
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_I16_F16(MachInst)
Definition: decoder.cc:6512
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F16(MachInst)
Definition: decoder.cc:4868
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_DEC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_DEC(MachInst)
Definition: decoder.cc:10508
gem5::VegaISA::Decoder::decode_OP_SOP1__S_QUADMASK_B64
GPUStaticInst * decode_OP_SOP1__S_QUADMASK_B64(MachInst)
Definition: decoder.cc:10852
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64
Definition: instructions.hh:16989
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_ADD_X2
Definition: instructions.hh:37693
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U64(MachInst)
Definition: decoder.cc:5852
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_OR
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_OR(MachInst)
Definition: decoder.cc:10305
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F64
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F64(MachInst)
Definition: decoder.cc:11404
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64
Definition: instructions.hh:13249
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:11374
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBL_B32
GPUStaticInst * decode_OP_VOP1__V_FFBL_B32(MachInst)
Definition: decoder.cc:11530
gem5::VegaISA::Inst_DS__DS_RSUB_RTN_U64
Definition: instructions.hh:33809
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F32(MachInst)
Definition: decoder.cc:4982
gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16
Definition: instructions.hh:20967
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:4826
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:8741
gem5::VegaISA::Decoder::tableSubDecode_OP_MTBUF
static IsaDecodeMethod tableSubDecode_OP_MTBUF[16]
Definition: gpu_decoder.hh:67
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I32
GPUStaticInst * decode_OP_VOP2__V_MIN_I32(MachInst)
Definition: decoder.cc:3917
gem5::VegaISA::Inst_VOPC__V_CMP_F_U16
Definition: instructions.hh:14201
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GE_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GE_I32(MachInst)
Definition: decoder.cc:10953
gem5::VegaISA::Inst_VOP3__V_CMP_U_F32
Definition: instructions.hh:18859
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32
Definition: instructions.hh:22667
gem5::VegaISA::Inst_VOP3__V_CMP_GE_F16
Definition: instructions.hh:17703
gem5::VegaISA::Inst_SOPK__S_CMPK_GE_I32
Definition: instructions.hh:1769
gem5::VegaISA::Inst_SOP1__S_CBRANCH_JOIN
Definition: instructions.hh:3719
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SET_GPR_IDX_OFF
GPUStaticInst * decode_OP_SOPP__S_SET_GPR_IDX_OFF(MachInst)
Definition: decoder.cc:11223
gem5::VegaISA::Inst_VOP3__V_SUBREV_U16
Definition: instructions.hh:25307
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_F16(MachInst)
Definition: decoder.cc:11877
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_INC_SRC2_U32(MachInst)
Definition: decoder.cc:7973
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F64(MachInst)
Definition: decoder.cc:5210
gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32
Definition: instructions.hh:19029
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32
Definition: instructions.hh:21885
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_AND
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_AND(MachInst)
Definition: decoder.cc:9731
gem5::VegaISA::Inst_VOP3__V_EXP_F32
Definition: instructions.hh:26805
gem5::VegaISA::Inst_VOP1__V_CVT_F16_U16
Definition: instructions.hh:9821
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORD
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORD(MachInst)
Definition: decoder.cc:8250
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16
Definition: instructions.hh:20865
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F32
GPUStaticInst * decode_OPU_VOP3__V_MAC_F32(MachInst)
Definition: decoder.cc:6002
gem5::VegaISA::Inst_DS__DS_OR_B32
Definition: instructions.hh:31507
gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F16
Definition: instructions.hh:27793
gem5::VegaISA::Inst_SOPP__S_CBRANCH_EXECNZ
Definition: instructions.hh:4761
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32
Definition: instructions.hh:18621
gem5::VegaISA::Decoder::decode_OP_VOP1__V_COS_F16
GPUStaticInst * decode_OP_VOP1__V_COS_F16(MachInst)
Definition: decoder.cc:11687
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I16(MachInst)
Definition: decoder.cc:5414
gem5::VegaISA::Inst_DS__DS_SUB_SRC2_U32
Definition: instructions.hh:34587
gem5::VegaISA::Inst_SOP1__S_CMOV_B32
Definition: instructions.hh:2313
gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64
Definition: instructions.hh:23381
gem5::VegaISA::Inst_DS__DS_XOR_SRC2_B64
Definition: instructions.hh:35649
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F16
Definition: instructions.hh:17601
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16
Definition: instructions.hh:14915
gem5::VegaISA::Inst_VOP3__V_MUL_F16
Definition: instructions.hh:25171
gem5::VegaISA::Decoder::decode_OP_SOPK__S_ADDK_I32
GPUStaticInst * decode_OP_SOPK__S_ADDK_I32(MachInst)
Definition: decoder.cc:4633
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_ADD
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8897
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32
Definition: instructions.hh:12501
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_X(MachInst)
Definition: decoder.cc:9495
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_B_CL_O(MachInst)
Definition: decoder.cc:9143
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16
Definition: instructions.hh:5535
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_D16_X
Definition: instructions.hh:36209
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F64(MachInst)
Definition: decoder.cc:12321
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BCNT1_I32_B64
GPUStaticInst * decode_OP_SOP1__S_BCNT1_I32_B64(MachInst)
Definition: decoder.cc:10684
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:8576
gem5::VegaISA::Inst_VOP3__V_MAD_U32_U24
Definition: instructions.hh:28253
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_BR
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_BR(MachInst)
Definition: decoder.cc:8069
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32
Definition: instructions.hh:19641
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_L_O(MachInst)
Definition: decoder.cc:9296
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32
Definition: instructions.hh:15085
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MUL_I32_I24(MachInst)
Definition: decoder.cc:5906
gem5::VegaISA::Inst_SOP1__S_SET_GPR_IDX_IDX
Definition: instructions.hh:3815
gem5::VegaISA::Inst_VOP3__V_INTERP_P1LV_F16
Definition: instructions.hh:30297
gem5::VegaISA::Inst_VOP3__V_CVT_F16_U16
Definition: instructions.hh:27505
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX4(MachInst)
Definition: decoder.cc:9944
gem5::VegaISA::Inst_VOP3__V_AND_B32
Definition: instructions.hh:24675
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_HI_X(MachInst)
Definition: decoder.cc:10173
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_U32(MachInst)
Definition: decoder.cc:4169
gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32
Definition: instructions.hh:15765
gem5::VegaISA::Inst_VOP1__V_CVT_F32_F64
Definition: instructions.hh:8577
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:4976
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F64(MachInst)
Definition: decoder.cc:7919
gem5::VegaISA::Inst_VOP3__V_MOV_B32
Definition: instructions.hh:25845
gem5::VegaISA::Inst_VOP3__V_CMP_U_F64
Definition: instructions.hh:19947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:5330
gem5::VegaISA::Inst_VOP2__V_MIN_I32
Definition: instructions.hh:6617
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64
Definition: instructions.hh:23891
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64
Definition: instructions.hh:20593
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_U_F16(MachInst)
Definition: decoder.cc:4862
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F32(MachInst)
Definition: decoder.cc:12141
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32
Definition: instructions.hh:11821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I32(MachInst)
Definition: decoder.cc:5600
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F16(MachInst)
Definition: decoder.cc:11865
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LG_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_LG_I32(MachInst)
Definition: decoder.cc:10941
gem5::VegaISA::Inst_VOP3__V_CUBEMA_F32
Definition: instructions.hh:28397
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_LEGACY_F16(MachInst)
Definition: decoder.cc:6896
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_LZ
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_LZ(MachInst)
Definition: decoder.cc:9053
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_U16(MachInst)
Definition: decoder.cc:13012
gem5::VegaISA::Decoder::subDecode_OP_VINTRP
GPUStaticInst * subDecode_OP_VINTRP(MachInst)
Definition: decoder.cc:3784
gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32
Definition: instructions.hh:22633
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLE_F16(MachInst)
Definition: decoder.cc:11937
gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16
Definition: instructions.hh:21239
gem5::VegaISA::Inst_VOP3__V_CVT_F32_F64
Definition: instructions.hh:26261
gem5::VegaISA::Inst_VOP2__V_MIN_F32
Definition: instructions.hh:6549
gem5::VegaISA::Inst_VOPC__V_CMP_O_F32
Definition: instructions.hh:11991
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_OR
Definition: instructions.hh:42772
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBBREV_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:6038
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F16(MachInst)
Definition: decoder.cc:6949
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F16(MachInst)
Definition: decoder.cc:4802
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B32
Definition: instructions.hh:2633
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_F16(MachInst)
Definition: decoder.cc:7027
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NGT_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_NGT_F32(MachInst)
Definition: decoder.cc:12027
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_CL_O
Definition: instructions.hh:41261
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN_X2
Definition: instructions.hh:43074
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ2_B64
GPUStaticInst * decode_OP_DS__DS_READ2_B64(MachInst)
Definition: decoder.cc:7937
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD_CL_O(MachInst)
Definition: decoder.cc:9368
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_U64
Definition: instructions.hh:35559
instructions.hh
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBB_CO_U32(MachInst)
Definition: decoder.cc:4019
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8408
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16
Definition: instructions.hh:21647
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLT_F32(MachInst)
Definition: decoder.cc:4994
gem5::VegaISA::Inst_VOP3__V_TRIG_PREOP_F64
Definition: instructions.hh:30947
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32
Definition: instructions.hh:22157
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32
Definition: instructions.hh:17295
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F64(MachInst)
Definition: decoder.cc:11751
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD
Definition: instructions.hh:36673
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:11859
gem5::VegaISA::Decoder::decode_OP_SOPC__S_SET_GPR_IDX_ON
GPUStaticInst * decode_OP_SOPC__S_SET_GPR_IDX_ON(MachInst)
Definition: decoder.cc:11037
gem5::VegaISA::Inst_SOPC__S_CMP_LE_I32
Definition: instructions.hh:4007
gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32
Definition: instructions.hh:15799
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_U_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_U_F32(MachInst)
Definition: decoder.cc:12009
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16
Definition: instructions.hh:21137
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CL_O
Definition: instructions.hh:40433
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_ADD
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_ADD(MachInst)
Definition: decoder.cc:10438
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITREPLICATE_B64_B32
GPUStaticInst * decode_OP_SOP1__S_BITREPLICATE_B64_B32(MachInst)
Definition: decoder.cc:10928
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_U64(MachInst)
Definition: decoder.cc:12813
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_U64
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_U64(MachInst)
Definition: decoder.cc:7811
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_X
Definition: instructions.hh:35905
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F16
GPUStaticInst * decode_OP_VOP1__V_RSQ_F16(MachInst)
Definition: decoder.cc:11621
gem5::VegaISA::Inst_VOP3__V_SUBREV_U32
Definition: instructions.hh:25783
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_GT_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_GT_I32(MachInst)
Definition: decoder.cc:10947
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F64(MachInst)
Definition: decoder.cc:5144
gem5::VegaISA::Inst_VOP3__V_LSHRREV_B32
Definition: instructions.hh:24573
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ_O
Definition: instructions.hh:41513
gem5::VegaISA::Decoder::decode_OP_SOP2__S_HH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_HH_B32_B16(MachInst)
Definition: decoder.cc:4542
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MBCNT_LO_U32_B32
GPUStaticInst * decode_OPU_VOP3__V_MBCNT_LO_U32_B32(MachInst)
Definition: decoder.cc:7172
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F16
GPUStaticInst * decode_OP_VOP2__V_ADD_F16(MachInst)
Definition: decoder.cc:4031
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_LG_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_LG_I32(MachInst)
Definition: decoder.cc:4567
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64
Definition: instructions.hh:20049
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U32
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U32(MachInst)
Definition: decoder.cc:7979
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_U_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_U_F16(MachInst)
Definition: decoder.cc:4766
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_F_F64(MachInst)
Definition: decoder.cc:12153
gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT
Definition: instructions.hh:42244
gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32_I24
Definition: instructions.hh:24267
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:11356
gem5::VegaISA::Inst_VOP3__V_XOR_B32
Definition: instructions.hh:24779
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_LOAD_PCK_SGN
GPUStaticInst * decode_OP_MIMG__IMAGE_LOAD_PCK_SGN(MachInst)
Definition: decoder.cc:8837
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16
Definition: instructions.hh:21307
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64
Definition: instructions.hh:20355
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_RTN_U64
GPUStaticInst * decode_OP_DS__DS_DEC_RTN_U64(MachInst)
Definition: decoder.cc:7835
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CL_O
Definition: instructions.hh:40145
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC_X2
Definition: instructions.hh:38017
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NLG_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_NLG_F64(MachInst)
Definition: decoder.cc:12213
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F16
Definition: instructions.hh:10835
gem5::VegaISA::Decoder::decode_OP_SOPP__S_SETKILL
GPUStaticInst * decode_OP_SOPP__S_SETKILL(MachInst)
Definition: decoder.cc:11121
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOT_B32
GPUStaticInst * decode_OPU_VOP3__V_NOT_B32(MachInst)
Definition: decoder.cc:6428
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F16(MachInst)
Definition: decoder.cc:4844
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64
Definition: instructions.hh:13147
gem5::VegaISA::Inst_DS__DS_ADD_F32
Definition: instructions.hh:31869
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64
Definition: instructions.hh:23619
gem5::VegaISA::Inst_VOP3__V_LSHLREV_B32
Definition: instructions.hh:24641
gem5::VegaISA::Inst_SOP1__S_WQM_B64
Definition: instructions.hh:2473
gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64
Definition: instructions.hh:20491
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:12789
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SUB
Definition: instructions.hh:42546
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2
Definition: instructions.hh:36711
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_U32
GPUStaticInst * decode_OPU_VOP3__V_MED3_U32(MachInst)
Definition: decoder.cc:6758
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_OR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8498
gem5::VegaISA::Inst_SOPC__S_BITCMP1_B32
Definition: instructions.hh:4263
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16
Definition: instructions.hh:18043
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE_D16_HI(MachInst)
Definition: decoder.cc:8345
gem5::VegaISA::Inst_VOP3__V_CMP_F_F16
Definition: instructions.hh:17499
gem5::VegaISA::InstFormat::iFmt_SOPC
InFmt_SOPC iFmt_SOPC
Definition: gpu_decoder.hh:1929
gem5::VegaISA::Inst_SOPC__S_CMP_LE_U32
Definition: instructions.hh:4199
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFM_B32
GPUStaticInst * decode_OPU_VOP3__V_BFM_B32(MachInst)
Definition: decoder.cc:7208
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NLE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NLE_F32(MachInst)
Definition: decoder.cc:5078
gem5::VegaISA::Inst_DS__DS_INC_RTN_U32
Definition: instructions.hh:32107
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32
Definition: instructions.hh:12671
gem5::VegaISA::Inst_SOPP__S_SETPRIO
Definition: instructions.hh:4941
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ADD_I32
GPUStaticInst * decode_OP_SOP2__S_ADD_I32(MachInst)
Definition: decoder.cc:4236
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16
Definition: instructions.hh:14473
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GE_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GE_I32(MachInst)
Definition: decoder.cc:4579
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CUBESC_F32
GPUStaticInst * decode_OPU_VOP3__V_CUBESC_F32(MachInst)
Definition: decoder.cc:6644
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U16_F16
GPUStaticInst * decode_OPU_VOP3__V_CVT_U16_F16(MachInst)
Definition: decoder.cc:6506
gem5::VegaISA::Inst_VOP2__V_SUBREV_U16
Definition: instructions.hh:7591
gem5::VegaISA::Inst_VOP3__V_MBCNT_HI_U32_B32
Definition: instructions.hh:30811
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U16(MachInst)
Definition: decoder.cc:5354
gem5::VegaISA::Inst_VOP2__V_MIN_I16
Definition: instructions.hh:7931
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND_X2(MachInst)
Definition: decoder.cc:8789
gem5::VegaISA::Inst_VOP3__V_BCNT_U32_B32
Definition: instructions.hh:30743
gem5::VegaISA::Decoder::decode_OP_SOPP__S_NOP
GPUStaticInst * decode_OP_SOPP__S_NOP(MachInst)
Definition: decoder.cc:11055
gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64
Definition: instructions.hh:13657
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F16
Definition: instructions.hh:18111
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_I64(MachInst)
Definition: decoder.cc:12741
gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32
Definition: instructions.hh:19301
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_I16
GPUStaticInst * decode_OPU_VOP3__V_SUB_I16(MachInst)
Definition: decoder.cc:7279
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F64(MachInst)
Definition: decoder.cc:5168
gem5::VegaISA::Decoder::tableSubDecode_OP_VOPC
static IsaDecodeMethod tableSubDecode_OP_VOPC[256]
Definition: gpu_decoder.hh:76
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F16
Definition: instructions.hh:11209
gem5::VegaISA::Inst_VOP3__V_CMP_F_I16
Definition: instructions.hh:20763
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN_X2
Definition: instructions.hh:37765
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE3
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE3(MachInst)
Definition: decoder.cc:6290
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:12459
gem5::VegaISA::Decoder::decode_OP_SOP2__S_SUB_I32
GPUStaticInst * decode_OP_SOP2__S_SUB_I32(MachInst)
Definition: decoder.cc:4242
gem5::VegaISA::Inst_VOP1__V_FLOOR_F64
Definition: instructions.hh:8929
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORD(MachInst)
Definition: decoder.cc:9923
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_F32
Definition: instructions.hh:32583
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9513
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_U32_U24
GPUStaticInst * decode_OPU_VOP3__V_MUL_U32_U24(MachInst)
Definition: decoder.cc:5918
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9489
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16
Definition: instructions.hh:21375
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_F_I16(MachInst)
Definition: decoder.cc:12345
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U16
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U16(MachInst)
Definition: decoder.cc:6942
gem5::VegaISA::Inst_VOP3__V_FRACT_F64
Definition: instructions.hh:27381
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:5390
gem5::VegaISA::Inst_VOP3__V_ASHRREV_I16
Definition: instructions.hh:25443
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U16(MachInst)
Definition: decoder.cc:12531
gem5::VegaISA::Inst_VOP2__V_MIN_F16
Definition: instructions.hh:7795
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD_CL_O(MachInst)
Definition: decoder.cc:9356
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B
Definition: instructions.hh:40793
gem5::VegaISA::Inst_SOP1__S_ABS_I32
Definition: instructions.hh:3751
gem5::VegaISA::Inst_VOP2__V_LSHRREV_B32
Definition: instructions.hh:6753
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGT_F16(MachInst)
Definition: decoder.cc:4784
gem5::VegaISA::Inst_DS__DS_CMPST_RTN_B32
Definition: instructions.hh:32549
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NLT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NLT_F64(MachInst)
Definition: decoder.cc:12333
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:12519
gem5::VegaISA::Inst_DS__DS_READ_B32
Definition: instructions.hh:32753
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZ
Definition: instructions.hh:35981
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B64
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B64(MachInst)
Definition: decoder.cc:7889
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:11991
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:8795
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32
Definition: instructions.hh:12807
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_U32_U24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_U32_U24(MachInst)
Definition: decoder.cc:3899
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_U64(MachInst)
Definition: decoder.cc:5846
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32
Definition: instructions.hh:22735
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32
Definition: instructions.hh:21919
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_I16
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_I16(MachInst)
Definition: decoder.cc:11591
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B32
Definition: instructions.hh:2569
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_F32
GPUStaticInst * decode_OP_VOP2__V_MIN_F32(MachInst)
Definition: decoder.cc:3905
gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F16
Definition: instructions.hh:17431
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_EQ_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_EQ_F64(MachInst)
Definition: decoder.cc:12165
gem5::VegaISA::Inst_VOP3__V_NOT_B32
Definition: instructions.hh:27157
gem5::VegaISA::Decoder::decode_OP_VOP2__V_XNOR_B32
GPUStaticInst * decode_OP_VOP2__V_XNOR_B32(MachInst)
Definition: decoder.cc:4217
gem5::VegaISA::Inst_SOP1__S_BCNT1_I32_B64
Definition: instructions.hh:2665
gem5::VegaISA::Inst_SOP1__S_FLBIT_I32
Definition: instructions.hh:2889
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_I64(MachInst)
Definition: decoder.cc:5696
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B64
GPUStaticInst * decode_OP_SOP2__S_AND_B64(MachInst)
Definition: decoder.cc:4302
gem5::VegaISA::Inst_VOP3__V_SUBREV_F16
Definition: instructions.hh:25137
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SBYTE
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SBYTE(MachInst)
Definition: decoder.cc:8232
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CD(MachInst)
Definition: decoder.cc:9326
gem5::VegaISA::Inst_DS__DS_ADD_U32
Definition: instructions.hh:31185
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MQSAD_PK_U16_U8
GPUStaticInst * decode_OPU_VOP3__V_MQSAD_PK_U16_U8(MachInst)
Definition: decoder.cc:6842
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F64
Definition: instructions.hh:27317
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC
Definition: instructions.hh:37585
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_AND
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_AND(MachInst)
Definition: decoder.cc:8711
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32
Definition: instructions.hh:18655
gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32
Definition: instructions.hh:6821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I24
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I24(MachInst)
Definition: decoder.cc:6626
gem5::VegaISA::Inst_SOP1__S_SETPC_B64
Definition: instructions.hh:3175
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMOVK_I32
GPUStaticInst * decode_OP_SOPK__S_CMOVK_I32(MachInst)
Definition: decoder.cc:4555
gem5::VegaISA::Decoder::decode_OP_VOP1__V_LOG_F32
GPUStaticInst * decode_OP_VOP1__V_LOG_F32(MachInst)
Definition: decoder.cc:11452
gem5::VegaISA::Inst_VOP2__V_ADD_F16
Definition: instructions.hh:7281
gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64
Definition: instructions.hh:13861
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8450
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F32
GPUStaticInst * decode_OPU_VOP3__V_EXP_F32(MachInst)
Definition: decoder.cc:6362
gem5::VegaISA::Inst_VOP1__V_EXP_F16
Definition: instructions.hh:10077
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_SRC2_B32
GPUStaticInst * decode_OP_DS__DS_OR_SRC2_B32(MachInst)
Definition: decoder.cc:8015
gem5::VegaISA::Inst_VOP2__V_MADMK_F32
Definition: instructions.hh:6991
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP
Definition: instructions.hh:42468
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMAX_X2
Definition: instructions.hh:43148
gem5::VegaISA::Inst_SOPP__S_NOP
Definition: instructions.hh:4487
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:6248
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U32(MachInst)
Definition: decoder.cc:12693
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_UBYTE(MachInst)
Definition: decoder.cc:9839
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C(MachInst)
Definition: decoder.cc:9011
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_U64(MachInst)
Definition: decoder.cc:8112
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_O_F16(MachInst)
Definition: decoder.cc:4760
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B32
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B32(MachInst)
Definition: decoder.cc:10750
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9561
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_STORE_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_STORE_PCK(MachInst)
Definition: decoder.cc:8867
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_RTN_F32
GPUStaticInst * decode_OP_DS__DS_ADD_RTN_F32(MachInst)
Definition: decoder.cc:7570
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB_VOL
Definition: instructions.hh:6051
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADDC_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADDC_CO_U32(MachInst)
Definition: decoder.cc:6026
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F16
Definition: instructions.hh:18451
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_I32(MachInst)
Definition: decoder.cc:12645
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8
Definition: instructions.hh:5499
gem5::VegaISA::Inst_VOP2__V_LDEXP_F16
Definition: instructions.hh:7965
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I32(MachInst)
Definition: decoder.cc:12639
gem5::VegaISA::InstFormat::iFmt_SOP2
InFmt_SOP2 iFmt_SOP2
Definition: gpu_decoder.hh:1928
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U16(MachInst)
Definition: decoder.cc:12507
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I64(MachInst)
Definition: decoder.cc:5678
gem5::VegaISA::Inst_DS__DS_AND_RTN_B32
Definition: instructions.hh:32311
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32
Definition: instructions.hh:19505
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_OR_X2
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_OR_X2(MachInst)
Definition: decoder.cc:10578
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NOR_B32
GPUStaticInst * decode_OP_SOP2__S_NOR_B32(MachInst)
Definition: decoder.cc:4368
gem5::VegaISA::Decoder::tableSubDecode_OP_FLAT
static IsaDecodeMethod tableSubDecode_OP_FLAT[128]
Definition: gpu_decoder.hh:64
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_EQ_I32
GPUStaticInst * decode_OP_SOPC__S_CMP_EQ_I32(MachInst)
Definition: decoder.cc:10935
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_TRU_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_TRU_F64(MachInst)
Definition: decoder.cc:12243
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_D_CL
Definition: instructions.hh:39929
gem5::VegaISA::Decoder::Decoder
Decoder()
Definition: decoder.cc:43
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CEIL_F32
GPUStaticInst * decode_OPU_VOP3__V_CEIL_F32(MachInst)
Definition: decoder.cc:6344
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_I32(MachInst)
Definition: decoder.cc:5606
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_U32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_U32(MachInst)
Definition: decoder.cc:6170
gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F32
Definition: instructions.hh:9729
gem5::VegaISA::Inst_DS__DS_MIN_F64
Definition: instructions.hh:33677
gem5::VegaISA::Inst_VOP3__V_FMA_F16
Definition: instructions.hh:30055
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_CL_O
Definition: instructions.hh:41477
gem5::VegaISA::Inst_DS__DS_WRITE_SRC2_B64
Definition: instructions.hh:35679
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE2
Definition: instructions.hh:26389
gem5::VegaISA::Decoder::tableSubDecode_OP_SOPP
static IsaDecodeMethod tableSubDecode_OP_SOPP[128]
Definition: gpu_decoder.hh:73
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_PERM_B32
GPUStaticInst * decode_OPU_VOP3__V_PERM_B32(MachInst)
Definition: decoder.cc:6884
gem5::VegaISA::Inst_VOP2__V_MAX_I16
Definition: instructions.hh:7863
gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64
Definition: instructions.hh:16547
gem5::VegaISA::Decoder::subDecode_OP_VOPC
GPUStaticInst * subDecode_OP_VOPC(MachInst)
Definition: decoder.cc:3720
gem5::VegaISA::Inst_SOPP__S_SETKILL
Definition: instructions.hh:4821
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD_CO_U32(MachInst)
Definition: decoder.cc:6008
gem5::VegaISA::Inst_VINTRP__V_INTERP_P2_F32
Definition: instructions.hh:17227
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32
Definition: instructions.hh:19199
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LDEXP_F16
GPUStaticInst * decode_OP_VOP2__V_LDEXP_F16(MachInst)
Definition: decoder.cc:4151
gem5::VegaISA::Inst_VOP3__V_CVT_RPI_I32_F32
Definition: instructions.hh:26165
gem5::VegaISA::Inst_DS__DS_MIN_I64
Definition: instructions.hh:33251
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ_O
Definition: instructions.hh:40361
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U64(MachInst)
Definition: decoder.cc:12807
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_BYTE_D16_HI(MachInst)
Definition: decoder.cc:9902
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U64
Definition: instructions.hh:35439
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL_O
Definition: instructions.hh:41765
gem5::VegaISA::Inst_EXP__EXP
Definition: instructions.hh:41873
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD
Definition: instructions.hh:42059
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD
Definition: instructions.hh:41657
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE(MachInst)
Definition: decoder.cc:8963
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD
Definition: instructions.hh:5391
gem5::VegaISA::Inst_DS__DS_WRITE2_B32
Definition: instructions.hh:31639
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_EXP_F16
GPUStaticInst * decode_OPU_VOP3__V_EXP_F16(MachInst)
Definition: decoder.cc:6542
gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32
Definition: instructions.hh:22463
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADAK_F16
GPUStaticInst * decode_OP_VOP2__V_MADAK_F16(MachInst)
Definition: decoder.cc:4067
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32
Definition: instructions.hh:22191
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32
Definition: instructions.hh:12331
gem5::VegaISA::Inst_VOP2__V_MAX_F16
Definition: instructions.hh:7761
gem5::VegaISA::Inst_VOP3__V_CMP_LG_F16
Definition: instructions.hh:17669
gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32
Definition: instructions.hh:12127
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FMA_F16
GPUStaticInst * decode_OPU_VOP3__V_FMA_F16(MachInst)
Definition: decoder.cc:7045
gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64
Definition: instructions.hh:10529
gem5::VegaISA::Inst_VOP3__V_BFE_U32
Definition: instructions.hh:28433
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U16(MachInst)
Definition: decoder.cc:12411
gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64
Definition: instructions.hh:16139
gem5::VegaISA::Inst_SOP2__S_ANDN2_B64
Definition: instructions.hh:691
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10119
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_U32(MachInst)
Definition: decoder.cc:5576
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3
Definition: instructions.hh:36749
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F64(MachInst)
Definition: decoder.cc:5156
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:12783
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_OR
Definition: instructions.hh:37477
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_I16(MachInst)
Definition: decoder.cc:5402
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_L
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_L(MachInst)
Definition: decoder.cc:9035
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL_O(MachInst)
Definition: decoder.cc:9272
gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32
Definition: instructions.hh:10495
gem5::VegaISA::Decoder::decode_OP_VOP2__V_DOT4C_I32_I8
GPUStaticInst * decode_OP_VOP2__V_DOT4C_I32_I8(MachInst)
Definition: decoder.cc:4189
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP1
static IsaDecodeMethod tableSubDecode_OP_VOP1[256]
Definition: gpu_decoder.hh:75
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW(MachInst)
Definition: decoder.cc:9440
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32
Definition: instructions.hh:15595
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64
Definition: instructions.hh:16173
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE2
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE2(MachInst)
Definition: decoder.cc:6284
gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16
Definition: instructions.hh:14405
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16
Definition: instructions.hh:21613
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GT_U64(MachInst)
Definition: decoder.cc:5750
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP
Definition: instructions.hh:42429
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOVRELS_B32
GPUStaticInst * decode_OP_SOP1__S_MOVRELS_B32(MachInst)
Definition: decoder.cc:10858
gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64
Definition: instructions.hh:12875
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ORN2_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ORN2_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10822
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F32(MachInst)
Definition: decoder.cc:4988
gem5::VegaISA::Inst_VOP3__V_SUBREV_F32
Definition: instructions.hh:24131
gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64
Definition: instructions.hh:20695
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_USHORT
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_USHORT(MachInst)
Definition: decoder.cc:8534
gem5::VegaISA::Inst_DS__DS_MIN_U64
Definition: instructions.hh:33315
gem5::VegaISA::Decoder::decode_OP_DS__DS_INC_RTN_U32
GPUStaticInst * decode_OP_DS__DS_INC_RTN_U32(MachInst)
Definition: decoder.cc:7462
gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64
Definition: instructions.hh:20151
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIX_F32
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIX_F32(MachInst)
Definition: decoder.cc:13054
gem5::VegaISA::Inst_VOP2__V_MUL_HI_I32_I24
Definition: instructions.hh:6447
gem5::VegaISA::Inst_SOP1__S_BCNT0_I32_B64
Definition: instructions.hh:2601
gem5::VegaISA::Inst_VOP2__V_MAC_F32
Definition: instructions.hh:6957
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64
Definition: instructions.hh:12909
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP_PCK
Definition: instructions.hh:39021
gem5::VegaISA::Inst_VOP1__V_FLOOR_F32
Definition: instructions.hh:9089
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32
Definition: instructions.hh:15323
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN_X2
Definition: instructions.hh:43111
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F16
Definition: instructions.hh:10971
gem5::VegaISA::Decoder::decode_OP_VOP2__V_XOR_B32
GPUStaticInst * decode_OP_VOP2__V_XOR_B32(MachInst)
Definition: decoder.cc:3971
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:9821
gem5::VegaISA::Decoder::decode_OP_SOP1__S_XNOR_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_XNOR_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10840
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_AND
Definition: instructions.hh:37441
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_NGE_F32(MachInst)
Definition: decoder.cc:4964
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_SCC1
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_SCC1(MachInst)
Definition: decoder.cc:11085
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD(MachInst)
Definition: decoder.cc:8675
gem5::VegaISA::Inst_VOPC__V_CMP_F_F16
Definition: instructions.hh:10665
gem5::VegaISA::Inst_VOP3__V_MIN_U32
Definition: instructions.hh:24505
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_F32
GPUStaticInst * decode_OPU_VOP3__V_MAX3_F32(MachInst)
Definition: decoder.cc:6728
gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16
Definition: instructions.hh:14303
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B16
GPUStaticInst * decode_OP_DS__DS_WRITE_B16(MachInst)
Definition: decoder.cc:7438
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_COS_F32
GPUStaticInst * decode_OPU_VOP3__V_COS_F32(MachInst)
Definition: decoder.cc:6422
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F32(MachInst)
Definition: decoder.cc:4928
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MUL_HI_I32_I24
GPUStaticInst * decode_OP_VOP2__V_MUL_HI_I32_I24(MachInst)
Definition: decoder.cc:3887
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_B_O
Definition: instructions.hh:41225
gem5::VegaISA::Inst_MIMG__IMAGE_GET_RESINFO
Definition: instructions.hh:39057
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GE_U32(MachInst)
Definition: decoder.cc:5666
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SMIN
Definition: instructions.hh:42583
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG2ST64_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG2ST64_RTN_B32(MachInst)
Definition: decoder.cc:7534
gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32
Definition: instructions.hh:19539
gem5::VegaISA::Inst_VOP2__V_MUL_U32_U24
Definition: instructions.hh:6481
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I32(MachInst)
Definition: decoder.cc:12579
gem5::VegaISA::Inst_VOPC__V_CMP_F_I16
Definition: instructions.hh:13929
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F32(MachInst)
Definition: decoder.cc:5060
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LL_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LL_B32_B16(MachInst)
Definition: decoder.cc:4528
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_L_O(MachInst)
Definition: decoder.cc:9083
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_FMA_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_FMA_F16(MachInst)
Definition: decoder.cc:13019
gem5::VegaISA::Decoder::decode_OP_VOP2__V_AND_B32
GPUStaticInst * decode_OP_VOP2__V_AND_B32(MachInst)
Definition: decoder.cc:3959
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_TRU_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_TRU_F32(MachInst)
Definition: decoder.cc:12147
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_DWORDX2
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_DWORDX2(MachInst)
Definition: decoder.cc:8306
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32
Definition: instructions.hh:22769
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8699
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32
Definition: instructions.hh:12739
gem5::VegaISA::Inst_VOP2__V_SUBREV_F16
Definition: instructions.hh:7349
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_INC
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_INC(MachInst)
Definition: decoder.cc:10501
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F32_UBYTE1
GPUStaticInst * decode_OP_VOP1__V_CVT_F32_UBYTE1(MachInst)
Definition: decoder.cc:11362
gem5::VegaISA::Inst_DS__DS_MSKOR_B64
Definition: instructions.hh:33475
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P2_LEGACY_F16(MachInst)
Definition: decoder.cc:7087
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_FLR_I32_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_FLR_I32_F32(MachInst)
Definition: decoder.cc:11332
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_HI_U32
GPUStaticInst * decode_OP_SOP2__S_MUL_HI_U32(MachInst)
Definition: decoder.cc:4488
gem5::VegaISA::Inst_VOP1__V_SIN_F32
Definition: instructions.hh:9409
gem5::VegaISA::Inst_VOP3__V_FMA_F32
Definition: instructions.hh:28541
gem5::VegaISA::Decoder::decode_OP_SMEM__S_STORE_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_STORE_DWORDX2(MachInst)
Definition: decoder.cc:10080
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RCP_F32
GPUStaticInst * decode_OPU_VOP3__V_RCP_F32(MachInst)
Definition: decoder.cc:6374
gem5::VegaISA::Inst_SOPP__S_WAKEUP
Definition: instructions.hh:4577
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4H_PCK
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4H_PCK(MachInst)
Definition: decoder.cc:9210
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U16(MachInst)
Definition: decoder.cc:5468
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F16
Definition: instructions.hh:18077
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8558
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_U32
GPUStaticInst * decode_OP_VOP2__V_MIN_U32(MachInst)
Definition: decoder.cc:3929
gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I16_F16
Definition: instructions.hh:27825
gem5::VegaISA::Decoder::tableDecodePrimary
static IsaDecodeMethod tableDecodePrimary[512]
Definition: gpu_decoder.hh:61
gem5::VegaISA::Decoder::decode_OP_SMEM__S_DCACHE_INV_VOL
GPUStaticInst * decode_OP_SMEM__S_DCACHE_INV_VOL(MachInst)
Definition: decoder.cc:10192
gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4
Definition: instructions.hh:5823
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_SUB
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_SUB(MachInst)
Definition: decoder.cc:10445
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_XYZW
Definition: instructions.hh:36475
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GT_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_GT_U32(MachInst)
Definition: decoder.cc:12609
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE_BUFFER
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE_BUFFER(MachInst)
Definition: decoder.cc:10222
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATOMIC_XOR
GPUStaticInst * decode_OP_SMEM__S_ATOMIC_XOR(MachInst)
Definition: decoder.cc:10494
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:9986
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_UMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:9725
gem5::VegaISA::InstFormat
Definition: gpu_decoder.hh:1911
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64
Definition: instructions.hh:17057
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9392
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_O(MachInst)
Definition: decoder.cc:9266
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_O(MachInst)
Definition: decoder.cc:9302
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16
Definition: instructions.hh:21341
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MIN_SRC2_I64(MachInst)
Definition: decoder.cc:8142
gem5::VegaISA::Inst_VOP3__V_MUL_U32_U24
Definition: instructions.hh:24301
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B_CL(MachInst)
Definition: decoder.cc:8999
gem5::VegaISA::Inst_SOPP__S_BRANCH
Definition: instructions.hh:4547
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_XOR_X2
Definition: instructions.hh:37981
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9549
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I8
Definition: instructions.hh:2953
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_XY(MachInst)
Definition: decoder.cc:9380
gem5::VegaISA::Decoder::decode_OP_SOP2__S_PACK_LH_B32_B16
GPUStaticInst * decode_OP_SOP2__S_PACK_LH_B32_B16(MachInst)
Definition: decoder.cc:4535
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_O(MachInst)
Definition: decoder.cc:9248
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F16
Definition: instructions.hh:11617
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_UMAX
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_UMAX(MachInst)
Definition: decoder.cc:8927
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_U16
GPUStaticInst * decode_OP_VOP2__V_ADD_U16(MachInst)
Definition: decoder.cc:4073
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRXCHG_RTN_B32
GPUStaticInst * decode_OP_DS__DS_WRXCHG_RTN_B32(MachInst)
Definition: decoder.cc:7522
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_F16_F32
GPUStaticInst * decode_OP_VOP1__V_CVT_F16_F32(MachInst)
Definition: decoder.cc:11314
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ABS_I32
GPUStaticInst * decode_OP_SOP1__S_ABS_I32(MachInst)
Definition: decoder.cc:10888
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_UBYTE_D16_HI(MachInst)
Definition: decoder.cc:10137
gem5::VegaISA::Inst_DS__DS_WRXCHG2_RTN_B32
Definition: instructions.hh:32481
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHRREV_B32
GPUStaticInst * decode_OPU_VOP3__V_LSHRREV_B32(MachInst)
Definition: decoder.cc:5966
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_I32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_I32_F64(MachInst)
Definition: decoder.cc:6188
gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64
Definition: instructions.hh:16241
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_U16(MachInst)
Definition: decoder.cc:12513
gem5::VegaISA::Inst_SOPC__S_BITCMP0_B64
Definition: instructions.hh:4295
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B32
Definition: instructions.hh:3655
gem5::VegaISA::InFmt_MUBUF::OP
unsigned int OP
Definition: gpu_decoder.hh:1719
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F64(MachInst)
Definition: decoder.cc:5108
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:8468
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U64(MachInst)
Definition: decoder.cc:5726
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_B_O
Definition: instructions.hh:41441
gem5::VegaISA::Decoder::decode_OP_SOPK__S_GETREG_B32
GPUStaticInst * decode_OP_SOPK__S_GETREG_B32(MachInst)
Definition: decoder.cc:4651
gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32
Definition: instructions.hh:18927
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX_I16(MachInst)
Definition: decoder.cc:6134
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_NE_U16
GPUStaticInst * decode_OP_VOPC__V_CMP_NE_U16(MachInst)
Definition: decoder.cc:12423
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32
Definition: instructions.hh:19233
gem5::VegaISA::Inst_DS__DS_RSUB_U32
Definition: instructions.hh:31251
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_VCCZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_VCCZ(MachInst)
Definition: decoder.cc:11091
gem5::VegaISA::Inst_VOP3__V_MOV_FED_B32
Definition: instructions.hh:26069
gem5::VegaISA::Inst_DS__DS_READ_B64
Definition: instructions.hh:34421
gem5::VegaISA::Decoder::subDecode_OP_DS
GPUStaticInst * subDecode_OP_DS(MachInst)
Definition: decoder.cc:3792
gem5::VegaISA::Inst_SOP1__S_SWAPPC_B64
Definition: instructions.hh:3207
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4
Definition: instructions.hh:42170
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16
Definition: instructions.hh:14813
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_DEC
Definition: instructions.hh:39499
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U64(MachInst)
Definition: decoder.cc:5732
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F64(MachInst)
Definition: decoder.cc:12285
gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64
Definition: instructions.hh:12977
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMAX
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:8402
gem5::VegaISA::Inst_VOP1__V_FRACT_F64
Definition: instructions.hh:9697
gem5::VegaISA::Inst_VOP2__V_MADAK_F16
Definition: instructions.hh:7487
gem5::VegaISA::Decoder::decode_OP_VOP1__V_CVT_OFF_F32_I4
GPUStaticInst * decode_OP_VOP1__V_CVT_OFF_F32_I4(MachInst)
Definition: decoder.cc:11338
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAC_F16
GPUStaticInst * decode_OPU_VOP3__V_MAC_F16(MachInst)
Definition: decoder.cc:6068
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_I64(MachInst)
Definition: decoder.cc:12855
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_SHORT
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_SHORT(MachInst)
Definition: decoder.cc:9628
gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32
Definition: instructions.hh:12059
gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32
Definition: instructions.hh:22497
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ALIGNBIT_B32
GPUStaticInst * decode_OPU_VOP3__V_ALIGNBIT_B32(MachInst)
Definition: decoder.cc:6698
gem5::VegaISA::Inst_VOP3__V_MIN_U16
Definition: instructions.hh:25613
gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F16
Definition: instructions.hh:18349
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:12279
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:12249
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_V
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_V(MachInst)
Definition: decoder.cc:8063
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_CL_O(MachInst)
Definition: decoder.cc:9065
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64
Definition: instructions.hh:13453
gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32
Definition: instructions.hh:16071
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGT_F64(MachInst)
Definition: decoder.cc:5264
gem5::VegaISA::Inst_SOPP__S_TTRACEDATA
Definition: instructions.hh:5151
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_LSHLREV_B16
GPUStaticInst * decode_OP_VOP3P__V_PK_LSHLREV_B16(MachInst)
Definition: decoder.cc:12949
gem5::VegaISA::Inst_SOP2__S_AND_B32
Definition: instructions.hh:453
gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64
Definition: instructions.hh:22973
gem5::VegaISA::Decoder::decode_OP_SOPP__S_INCPERFLEVEL
GPUStaticInst * decode_OP_SOPP__S_INCPERFLEVEL(MachInst)
Definition: decoder.cc:11175
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NLE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NLE_F16(MachInst)
Definition: decoder.cc:4790
gem5::VegaISA::Inst_DS__DS_SUB_RTN_U64
Definition: instructions.hh:33775
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SIN_F32
GPUStaticInst * decode_OP_VOP1__V_SIN_F32(MachInst)
Definition: decoder.cc:11500
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_U32(MachInst)
Definition: decoder.cc:5540
gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32
Definition: instructions.hh:15119
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64
Definition: instructions.hh:16717
gem5::VegaISA::Inst_VOP3__V_INTERP_P2_F16
Definition: instructions.hh:30333
gem5::VegaISA::Inst_VOP1__V_CVT_F16_I16
Definition: instructions.hh:9853
gem5::VegaISA::InstFormat::iFmt_SMEM
InFmt_SMEM iFmt_SMEM
Definition: gpu_decoder.hh:1925
gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE0
Definition: instructions.hh:8641
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_T_I16(MachInst)
Definition: decoder.cc:12387
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUB_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:4001
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I64_I32
GPUStaticInst * decode_OPU_VOP3__V_MAD_I64_I32(MachInst)
Definition: decoder.cc:6860
gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64
Definition: instructions.hh:19709
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64
Definition: instructions.hh:23007
gem5::VegaISA::Inst_VOP3__V_BFE_I32
Definition: instructions.hh:28469
gem5::VegaISA::Inst_SOP2__S_NAND_B32
Definition: instructions.hh:793
gem5::VegaISA::InFmt_VOP1
Definition: gpu_decoder.hh:1795
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SWAP_X2(MachInst)
Definition: decoder.cc:10333
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMAX_X2
Definition: instructions.hh:43185
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD
Definition: instructions.hh:41585
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_TRU_F16(MachInst)
Definition: decoder.cc:4904
gem5::VegaISA::Inst_DS__DS_GWS_INIT
Definition: instructions.hh:35067
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY(MachInst)
Definition: decoder.cc:9428
gem5::VegaISA::InstFormat::iFmt_EXP
InFmt_EXP iFmt_EXP
Definition: gpu_decoder.hh:1914
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2
Definition: instructions.hh:42096
gem5::VegaISA::Inst_VOP2__V_SUBREV_CO_U32
Definition: instructions.hh:7131
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_UMIN
Definition: instructions.hh:42622
gem5::VegaISA::Inst_VOP3__V_CVT_PK_U16_U32
Definition: instructions.hh:31117
gem5::VegaISA::Inst_VOPC__V_CMP_T_U64
Definition: instructions.hh:16615
gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32
Definition: instructions.hh:11855
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64
Definition: instructions.hh:19743
gem5::VegaISA::Decoder::tableSubDecode_OP_VOP3P
static IsaDecodeMethod tableSubDecode_OP_VOP3P[128]
Definition: gpu_decoder.hh:77
gem5::VegaISA::Inst_DS__DS_INC_U32
Definition: instructions.hh:31283
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GT_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:12273
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I32
GPUStaticInst * decode_OP_DS__DS_MAX_I32(MachInst)
Definition: decoder.cc:7329
gem5::VegaISA::Inst_SOP1__S_SEXT_I32_I16
Definition: instructions.hh:2985
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_UMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:8396
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_LZ
Definition: instructions.hh:39785
gem5::VegaISA::Inst_SOP1__S_NOT_B64
Definition: instructions.hh:2409
gem5::VegaISA::Inst_VOP3__V_ADD_U16
Definition: instructions.hh:25239
gem5::VegaISA::Decoder::decode_OP_VOP2__V_DOT2C_F32_F16
GPUStaticInst * decode_OP_VOP2__V_DOT2C_F32_F16(MachInst)
Definition: decoder.cc:4175
gem5::VegaISA::Inst_VOP3__V_MAD_U64_U32
Definition: instructions.hh:29591
gem5::VegaISA::Inst_VOP3__V_CVT_F16_I16
Definition: instructions.hh:27537
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_SUB_X2(MachInst)
Definition: decoder.cc:10354
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_F32(MachInst)
Definition: decoder.cc:4946
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_I32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_I32(MachInst)
Definition: decoder.cc:12555
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_I16(MachInst)
Definition: decoder.cc:5294
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NE_U32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:5660
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_U32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_U32(MachInst)
Definition: decoder.cc:6302
gem5::VegaISA::Inst_DS__DS_ORDERED_COUNT
Definition: instructions.hh:35287
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL
Definition: instructions.hh:40037
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F16
Definition: instructions.hh:18383
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:4724
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORD
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORD(MachInst)
Definition: decoder.cc:9867
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64
Definition: instructions.hh:23925
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD
Definition: instructions.hh:36909
gem5::VegaISA::Inst_DS__DS_ADD_RTN_F32
Definition: instructions.hh:32719
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XY
Definition: instructions.hh:38431
gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16
Definition: instructions.hh:14745
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FFBH_I32
GPUStaticInst * decode_OPU_VOP3__V_FFBH_I32(MachInst)
Definition: decoder.cc:6452
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NGE_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:5252
gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32
Definition: instructions.hh:12705
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9543
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8656
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16
Definition: instructions.hh:14643
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MIN_I32
GPUStaticInst * decode_OP_SOP2__S_MIN_I32(MachInst)
Definition: decoder.cc:4260
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_I16(MachInst)
Definition: decoder.cc:12477
gem5::VegaISA::Decoder::decode_OP_DS__DS_RSUB_RTN_U64
GPUStaticInst * decode_OP_DS__DS_RSUB_RTN_U64(MachInst)
Definition: decoder.cc:7823
gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64
Definition: instructions.hh:20729
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_F64
GPUStaticInst * decode_OPU_VOP3__V_MUL_F64(MachInst)
Definition: decoder.cc:7106
gem5::VegaISA::Inst_VOP3__V_MIN_I32
Definition: instructions.hh:24437
gem5::VegaISA::Decoder::decode_OP_VOP1__V_MOV_B32
GPUStaticInst * decode_OP_VOP1__V_MOV_B32(MachInst)
Definition: decoder.cc:11266
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F16
GPUStaticInst * decode_OP_VOP2__V_MADMK_F16(MachInst)
Definition: decoder.cc:4061
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32
Definition: instructions.hh:15357
gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64
Definition: instructions.hh:13827
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MUL_LO_U16
GPUStaticInst * decode_OP_VOP3P__V_PK_MUL_LO_U16(MachInst)
Definition: decoder.cc:12928
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I64(MachInst)
Definition: decoder.cc:5720
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U32(MachInst)
Definition: decoder.cc:12603
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_O
Definition: instructions.hh:40109
gem5::VegaISA::Inst_DS__DS_WRXCHG2ST64_RTN_B32
Definition: instructions.hh:32515
gem5::VegaISA::Inst_VOP3__V_CVT_FLR_I32_F32
Definition: instructions.hh:26197
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B(MachInst)
Definition: decoder.cc:9230
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_T_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_T_U64(MachInst)
Definition: decoder.cc:5864
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_D_CL(MachInst)
Definition: decoder.cc:8981
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_D_CL_O
Definition: instructions.hh:40217
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F32(MachInst)
Definition: decoder.cc:6614
gem5::VegaISA::Inst_SOP1__S_NAND_SAVEEXEC_B64
Definition: instructions.hh:3431
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_FORMAT_D16_X
Definition: instructions.hh:36361
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_UBYTE0
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_UBYTE0(MachInst)
Definition: decoder.cc:6272
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MOV_B32
GPUStaticInst * decode_OPU_VOP3__V_MOV_B32(MachInst)
Definition: decoder.cc:6182
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGUSER
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGUSER(MachInst)
Definition: decoder.cc:11199
gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32
Definition: instructions.hh:15901
gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F16
Definition: instructions.hh:11005
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_I16(MachInst)
Definition: decoder.cc:6878
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LT_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_LT_F16(MachInst)
Definition: decoder.cc:11775
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_D16_XYZ
Definition: instructions.hh:38621
gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64
Definition: instructions.hh:23245
gem5::VegaISA::InFmt_SOP1
Definition: gpu_decoder.hh:1751
gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE
Definition: instructions.hh:41911
gem5::VegaISA::Inst_VOP3__V_MIN_F32
Definition: instructions.hh:24369
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_CL(MachInst)
Definition: decoder.cc:9161
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_I64(MachInst)
Definition: decoder.cc:7841
gem5::VegaISA::Inst_VOP3__V_FLOOR_F16
Definition: instructions.hh:27857
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMP_T_U32(MachInst)
Definition: decoder.cc:12627
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SMAX_X2(MachInst)
Definition: decoder.cc:8777
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F32
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F32(MachInst)
Definition: decoder.cc:11434
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_SRC2_U64
GPUStaticInst * decode_OP_DS__DS_DEC_SRC2_U64(MachInst)
Definition: decoder.cc:8136
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LT_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LT_U32(MachInst)
Definition: decoder.cc:10995
gem5::VegaISA::Inst_VOP3__V_MAX_U16
Definition: instructions.hh:25545
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U64
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U64(MachInst)
Definition: decoder.cc:7853
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_CO_U32
GPUStaticInst * decode_OPU_VOP3__V_SUB_CO_U32(MachInst)
Definition: decoder.cc:6014
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F64
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F64(MachInst)
Definition: decoder.cc:4694
gem5::VegaISA::Inst_SOPK__S_CBRANCH_I_FORK
Definition: instructions.hh:2121
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_NEQ_F16(MachInst)
Definition: decoder.cc:4796
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LSHLREV_B64
GPUStaticInst * decode_OPU_VOP3__V_LSHLREV_B64(MachInst)
Definition: decoder.cc:7184
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4
Definition: instructions.hh:37023
gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64
Definition: instructions.hh:23279
gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32
Definition: instructions.hh:22905
gem5::VegaISA::Inst_DS__DS_PERMUTE_B32
Definition: instructions.hh:33021
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_F64
Definition: instructions.hh:35739
gem5::VegaISA::Inst_VINTRP__V_INTERP_MOV_F32
Definition: instructions.hh:17261
gem5::VegaISA::Decoder::decode_OP_VOP2__V_OR_B32
GPUStaticInst * decode_OP_VOP2__V_OR_B32(MachInst)
Definition: decoder.cc:3965
gem5::VegaISA::Inst_DS__DS_MIN_RTN_I32
Definition: instructions.hh:32175
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET0_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET0_B64(MachInst)
Definition: decoder.cc:10756
gem5::VegaISA::Inst_VOP3__V_TRUNC_F64
Definition: instructions.hh:26517
gem5::VegaISA::Inst_MUBUF__BUFFER_WBINVL1_VOL
Definition: instructions.hh:37123
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMAX
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMAX(MachInst)
Definition: decoder.cc:9719
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_RSQ_F32
GPUStaticInst * decode_OPU_VOP3__V_RSQ_F32(MachInst)
Definition: decoder.cc:6386
gem5::VegaISA::Decoder::tableSubDecode_OP_GLOBAL
static IsaDecodeMethod tableSubDecode_OP_GLOBAL[128]
Definition: gpu_decoder.hh:65
gem5::VegaISA::Inst_SOPP__S_SETHALT
Definition: instructions.hh:4881
gem5::VegaISA::Inst_DS__DS_MIN_F32
Definition: instructions.hh:31775
gem5::VegaISA::InFmt_VOPC
Definition: gpu_decoder.hh:1835
gem5::VegaISA::Inst_DS__DS_DEC_RTN_U32
Definition: instructions.hh:32141
gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_FORMAT_XYZW
Definition: instructions.hh:36019
gem5::VegaISA::Inst_DS__DS_MAX_F32
Definition: instructions.hh:31807
gem5::VegaISA::Decoder::decode_OP_SOP1__S_NAND_SAVEEXEC_B64
GPUStaticInst * decode_OP_SOP1__S_NAND_SAVEEXEC_B64(MachInst)
Definition: decoder.cc:10828
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F32(MachInst)
Definition: decoder.cc:5000
gem5::VegaISA::Decoder::decode_OP_DS__DS_DEC_U32
GPUStaticInst * decode_OP_DS__DS_DEC_U32(MachInst)
Definition: decoder.cc:7317
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_MIN_F16
GPUStaticInst * decode_OP_VOP3P__V_PK_MIN_F16(MachInst)
Definition: decoder.cc:13040
gem5::VegaISA::Inst_DS__DS_MAX_SRC2_I64
Definition: instructions.hh:35499
gem5::VegaISA::Inst_DS__DS_MIN_RTN_F32
Definition: instructions.hh:32617
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_O
Definition: instructions.hh:40577
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_ATOMIC_AND
GPUStaticInst * decode_OP_MIMG__IMAGE_ATOMIC_AND(MachInst)
Definition: decoder.cc:8933
gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64
Definition: instructions.hh:23483
gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64
Definition: instructions.hh:23075
gem5::VegaISA::Decoder::decode_OP_SOP1__S_ANDN2_WREXEC_B64
GPUStaticInst * decode_OP_SOP1__S_ANDN2_WREXEC_B64(MachInst)
Definition: decoder.cc:10921
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CD
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CD(MachInst)
Definition: decoder.cc:9338
gem5::VegaISA::Inst_DS__DS_MIN_I32
Definition: instructions.hh:31347
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_GE_I64
GPUStaticInst * decode_OPU_VOP3__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:5714
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_CLASS_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_CLASS_F32(MachInst)
Definition: decoder.cc:4682
gem5::VegaISA::Inst_DS__DS_MAX_I32
Definition: instructions.hh:31379
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B128
GPUStaticInst * decode_OP_DS__DS_READ_B128(MachInst)
Definition: decoder.cc:8220
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I64(MachInst)
Definition: decoder.cc:12765
gem5::VegaISA::Decoder::decode_OP_SMEM__S_LOAD_DWORDX16
GPUStaticInst * decode_OP_SMEM__S_LOAD_DWORDX16(MachInst)
Definition: decoder.cc:10017
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_CLASS_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_CLASS_F32(MachInst)
Definition: decoder.cc:11739
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_MAD_MIXHI_F16
GPUStaticInst * decode_OP_VOP3P__V_MAD_MIXHI_F16(MachInst)
Definition: decoder.cc:13068
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_DIV_FIXUP_F16
GPUStaticInst * decode_OPU_VOP3__V_DIV_FIXUP_F16(MachInst)
Definition: decoder.cc:7051
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_XYZW(MachInst)
Definition: decoder.cc:9416
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_I32_I16
GPUStaticInst * decode_OPU_VOP3__V_MAD_I32_I16(MachInst)
Definition: decoder.cc:6915
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L(MachInst)
Definition: decoder.cc:9174
gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64
Definition: instructions.hh:23653
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBREV_CO_U32(MachInst)
Definition: decoder.cc:4007
gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64
Definition: instructions.hh:19811
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_LZ_O
Definition: instructions.hh:40649
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORD
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORD(MachInst)
Definition: decoder.cc:8546
gem5::VegaISA::Decoder::decode_OP_VOP2__V_LSHRREV_B16
GPUStaticInst * decode_OP_VOP2__V_LSHRREV_B16(MachInst)
Definition: decoder.cc:4103
gem5::VegaISA::InFmt_VOP3P::OP
unsigned int OP
Definition: gpu_decoder.hh:1899
gem5::VegaISA::Inst_DS__DS_READ2ST64_B32
Definition: instructions.hh:32821
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_U32(MachInst)
Definition: decoder.cc:12723
gem5::VegaISA::Inst_DS__DS_CMPST_B64
Definition: instructions.hh:33613
gem5::VegaISA::Inst_SOPC__S_CMP_GT_I32
Definition: instructions.hh:3911
gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64
Definition: instructions.hh:20219
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX3_I16
GPUStaticInst * decode_OPU_VOP3__V_MAX3_I16(MachInst)
Definition: decoder.cc:6956
gem5::VegaISA::Decoder::subDecode_OP_SOPC
GPUStaticInst * subDecode_OP_SOPC(MachInst)
Definition: decoder.cc:3752
gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4
Definition: instructions.hh:5463
gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64
Definition: instructions.hh:16649
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F32_I32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F32_I32(MachInst)
Definition: decoder.cc:6200
gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32
Definition: instructions.hh:19471
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUBREV_F32
GPUStaticInst * decode_OPU_VOP3__V_SUBREV_F32(MachInst)
Definition: decoder.cc:5888
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B96
GPUStaticInst * decode_OP_DS__DS_WRITE_B96(MachInst)
Definition: decoder.cc:8202
gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F16
Definition: instructions.hh:11515
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2
Definition: instructions.hh:36947
gem5::VegaISA::Decoder::decode_OP_VOP1__V_EXP_LEGACY_F32
GPUStaticInst * decode_OP_VOP1__V_EXP_LEGACY_F32(MachInst)
Definition: decoder.cc:11693
gem5::VegaISA::Inst_VOP3__V_CMP_U_F16
Definition: instructions.hh:17771
gem5::VegaISA::Decoder::decode_OP_SOP1__S_BITSET1_B64
GPUStaticInst * decode_OP_SOP1__S_BITSET1_B64(MachInst)
Definition: decoder.cc:10768
gem5::VegaISA::Inst_DS__DS_CMPST_F64
Definition: instructions.hh:33645
gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16
Definition: instructions.hh:21579
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_F_U32
GPUStaticInst * decode_OPU_VOP3__V_CMP_F_U32(MachInst)
Definition: decoder.cc:5534
gem5::VegaISA::Inst_VOP3__V_CVT_PKNORM_U16_F32
Definition: instructions.hh:31049
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_I64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_I64(MachInst)
Definition: decoder.cc:12831
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64
Definition: instructions.hh:13385
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_LE_F16(MachInst)
Definition: decoder.cc:4736
gem5::VegaISA::Inst_VOP1__V_RSQ_F16
Definition: instructions.hh:10013
gem5::VegaISA::Inst_SOP2__S_ORN2_B64
Definition: instructions.hh:759
gem5::VegaISA::Inst_MTBUF__TBUFFER_STORE_FORMAT_XYZW
Definition: instructions.hh:38355
gem5::VegaISA::Inst_VOP3__V_CMP_O_F64
Definition: instructions.hh:19913
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_I64
GPUStaticInst * decode_OP_DS__DS_MIN_I64(MachInst)
Definition: decoder.cc:7666
gem5::VegaISA::Inst_VOP1__V_RCP_F16
Definition: instructions.hh:9949
gem5::VegaISA::Decoder::decode_OP_SOP1__S_MOV_B32
GPUStaticInst * decode_OP_SOP1__S_MOV_B32(MachInst)
Definition: decoder.cc:10606
gem5::VegaISA::Inst_VOP3__V_EXP_F16
Definition: instructions.hh:27761
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NEQ_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:11943
gem5::VegaISA::Inst_VOP1__V_CVT_F64_U32
Definition: instructions.hh:8801
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F16
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F16(MachInst)
Definition: decoder.cc:6560
gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32
Definition: instructions.hh:21953
gem5::VegaISA::Inst_DS__DS_MIN_U32
Definition: instructions.hh:31411
gem5::VegaISA::Inst_DS__DS_MAX_U32
Definition: instructions.hh:31443
gem5::VegaISA::Inst_VOP3__V_MIN_I16
Definition: instructions.hh:25647
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_ADD_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_ADD_I16(MachInst)
Definition: decoder.cc:12935
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LG_F32
GPUStaticInst * decode_OP_VOPC__V_CMPX_LG_F32(MachInst)
Definition: decoder.cc:12087
gem5::VegaISA::Inst_DS__DS_MSKOR_B32
Definition: instructions.hh:31573
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2
Definition: instructions.hh:43370
gem5::VegaISA::InFmt_SOPC
Definition: gpu_decoder.hh:1766
gem5::VegaISA::Inst_VOP1__V_BFREV_B32
Definition: instructions.hh:9505
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_B_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_B_CL(MachInst)
Definition: decoder.cc:9186
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F16
GPUStaticInst * decode_OP_VOP1__V_SQRT_F16(MachInst)
Definition: decoder.cc:11615
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_STORE_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9446
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMP_LE_U64(MachInst)
Definition: decoder.cc:12795
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ASHRREV_I16
GPUStaticInst * decode_OP_VOP2__V_ASHRREV_I16(MachInst)
Definition: decoder.cc:4109
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MAX_U32
GPUStaticInst * decode_OP_VOP2__V_MAX_U32(MachInst)
Definition: decoder.cc:3935
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_CD_O
Definition: instructions.hh:41801
gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32
Definition: instructions.hh:18689
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NGE_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_NGE_F64(MachInst)
Definition: decoder.cc:12303
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FREXP_MANT_F32
GPUStaticInst * decode_OPU_VOP3__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:6482
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_T_I16
GPUStaticInst * decode_OPU_VOP3__V_CMP_T_I16(MachInst)
Definition: decoder.cc:5336
gem5::VegaISA::Inst_SOPC__S_CMP_GT_U32
Definition: instructions.hh:4103
gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16
Definition: instructions.hh:14779
gem5::VegaISA::Inst_VOP3__V_RCP_IFLAG_F32
Definition: instructions.hh:26901
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_F64_F32
GPUStaticInst * decode_OPU_VOP3__V_CVT_F64_F32(MachInst)
Definition: decoder.cc:6266
gem5::VegaISA::Inst_VOP3__V_CVT_F64_U32
Definition: instructions.hh:26485
gem5::VegaISA::Inst_VOP3__V_MIN_F16
Definition: instructions.hh:25511
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_ADD_X2(MachInst)
Definition: decoder.cc:8753
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP_X2
Definition: instructions.hh:37657
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBREV_F16
GPUStaticInst * decode_OP_VOP2__V_SUBREV_F16(MachInst)
Definition: decoder.cc:4043
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F16(MachInst)
Definition: decoder.cc:11811
gem5::VegaISA::Inst_VOP1__V_RNDNE_F32
Definition: instructions.hh:9057
gem5::VegaISA::Inst_VOP3__V_LDEXP_F16
Definition: instructions.hh:25681
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_U64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_U64(MachInst)
Definition: decoder.cc:5822
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_F16(MachInst)
Definition: decoder.cc:4730
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_U_F64
GPUStaticInst * decode_OP_VOPC__V_CMPX_U_F64(MachInst)
Definition: decoder.cc:12297
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LG_F32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LG_F32(MachInst)
Definition: decoder.cc:4940
gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64
Definition: instructions.hh:23347
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_EXECNZ
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_EXECNZ(MachInst)
Definition: decoder.cc:11109
gem5::VegaISA::Inst_DS__DS_WRITE_B16
Definition: instructions.hh:31971
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_ADD3_U32
GPUStaticInst * decode_OPU_VOP3__V_ADD3_U32(MachInst)
Definition: decoder.cc:7003
gem5::VegaISA::Decoder::decode
GPUStaticInst * decode(MachInst mach_inst)
Definition: decoder.cc:3712
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:8649
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_O
Definition: instructions.hh:41729
gem5::VegaISA::Inst_DS__DS_AND_SRC2_B32
Definition: instructions.hh:34827
gem5::VegaISA::Inst_SMEM__S_DCACHE_WB
Definition: instructions.hh:5995
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMPX_GE_F16(MachInst)
Definition: decoder.cc:11901
gem5::VegaISA::Inst_SOP1__S_GETPC_B64
Definition: instructions.hh:3145
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_B_CL_O(MachInst)
Definition: decoder.cc:9308
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN_I16
GPUStaticInst * decode_OPU_VOP3__V_MIN_I16(MachInst)
Definition: decoder.cc:6146
gem5::VegaISA::Inst_SOP1__S_NOR_SAVEEXEC_B64
Definition: instructions.hh:3463
gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F16
Definition: instructions.hh:17873
gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32
Definition: instructions.hh:18995
gem5::VegaISA::Inst_VOP1__V_SQRT_F16
Definition: instructions.hh:9981
gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD
Definition: instructions.hh:42281
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_LOAD_DWORDX2(MachInst)
Definition: decoder.cc:10050
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_CL_O(MachInst)
Definition: decoder.cc:9113
gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64
Definition: instructions.hh:13895
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_TRU_F16
GPUStaticInst * decode_OPU_VOP3__V_CMP_TRU_F16(MachInst)
Definition: decoder.cc:4808
gem5::VegaISA::Inst_MTBUF__TBUFFER_LOAD_FORMAT_D16_XYZW
Definition: instructions.hh:38507
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_PCK_SGN
Definition: instructions.hh:38805
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SQRT_F64
GPUStaticInst * decode_OP_VOP1__V_SQRT_F64(MachInst)
Definition: decoder.cc:11494
gem5::VegaISA::Inst_VOP3__V_ADD_F16
Definition: instructions.hh:25069
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_FLOOR_F64
GPUStaticInst * decode_OPU_VOP3__V_FLOOR_F64(MachInst)
Definition: decoder.cc:6326
gem5::VegaISA::Inst_VOP1__V_CEIL_F64
Definition: instructions.hh:8865
gem5::VegaISA::Inst_DS__DS_DEC_SRC2_U32
Definition: instructions.hh:34677
gem5::VegaISA::Inst_SOP1__S_BITSET1_B32
Definition: instructions.hh:3081
gem5::VegaISA::Decoder::decode_OP_DS__DS_ADD_SRC2_F32
GPUStaticInst * decode_OP_DS__DS_ADD_SRC2_F32(MachInst)
Definition: decoder.cc:8045
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_INTERP_P1LV_F16
GPUStaticInst * decode_OPU_VOP3__V_INTERP_P1LV_F16(MachInst)
Definition: decoder.cc:7081
gem5::VegaISA::Inst_VOPC__V_CMP_U_F32
Definition: instructions.hh:12025
gem5::VegaISA::Inst_VOP3__V_MUL_LO_U16
Definition: instructions.hh:25341
gem5::VegaISA::Decoder::subDecode_OP_MIMG
GPUStaticInst * subDecode_OP_MIMG(MachInst)
Definition: decoder.cc:3837
gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32
Definition: instructions.hh:15935
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_XOR
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_XOR(MachInst)
Definition: decoder.cc:9743
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F64
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F64(MachInst)
Definition: decoder.cc:12189
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CMPK_GT_I32
GPUStaticInst * decode_OP_SOPK__S_CMPK_GT_I32(MachInst)
Definition: decoder.cc:4573
gem5::VegaISA::Decoder::decode_OP_SOPK__S_MULK_I32
GPUStaticInst * decode_OP_SOPK__S_MULK_I32(MachInst)
Definition: decoder.cc:4639
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFE_U32
GPUStaticInst * decode_OPU_VOP3__V_BFE_U32(MachInst)
Definition: decoder.cc:6662
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_O
Definition: instructions.hh:41117
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI
GPUStaticInst * decode_OP_FLAT__FLAT_STORE_SHORT_D16_HI(MachInst)
Definition: decoder.cc:8293
gem5::VegaISA::Inst_DS__DS_WRITE_B128
Definition: instructions.hh:35803
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAD_LEGACY_F16
GPUStaticInst * decode_OPU_VOP3__V_MAD_LEGACY_F16(MachInst)
Definition: decoder.cc:6866
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_CMPSWAP_X2(MachInst)
Definition: decoder.cc:8747
gem5::VegaISA::InstFormat::iFmt_VOP3A
InFmt_VOP3A iFmt_VOP3A
Definition: gpu_decoder.hh:1935
gem5::VegaISA::Decoder::decode_OP_VOP2__V_SUBBREV_CO_U32
GPUStaticInst * decode_OP_VOP2__V_SUBBREV_CO_U32(MachInst)
Definition: decoder.cc:4025
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F32
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F32(MachInst)
Definition: decoder.cc:11566
gem5::VegaISA::Inst_VOP3__V_MQSAD_U32_U8
Definition: instructions.hh:29555
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MIN3_U32
GPUStaticInst * decode_OPU_VOP3__V_MIN3_U32(MachInst)
Definition: decoder.cc:6722
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FFBH_I32
GPUStaticInst * decode_OP_VOP1__V_FFBH_I32(MachInst)
Definition: decoder.cc:11536
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U32
Definition: instructions.hh:32005
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE2ST64_B64
GPUStaticInst * decode_OP_DS__DS_WRITE2ST64_B64(MachInst)
Definition: decoder.cc:7726
gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32
Definition: instructions.hh:22225
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_F16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_F16(MachInst)
Definition: decoder.cc:11805
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_O_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_O_F16(MachInst)
Definition: decoder.cc:4856
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LE_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LE_U64(MachInst)
Definition: decoder.cc:12891
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B64(MachInst)
Definition: decoder.cc:7877
gem5::VegaISA::Inst_MIMG__IMAGE_STORE_MIP
Definition: instructions.hh:38949
gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32
Definition: instructions.hh:19369
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_GE_I16
GPUStaticInst * decode_OP_VOPC__V_CMP_GE_I16(MachInst)
Definition: decoder.cc:12381
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F32(MachInst)
Definition: decoder.cc:5030
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_GT_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_GT_F64(MachInst)
Definition: decoder.cc:5222
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_SRC2_I64
GPUStaticInst * decode_OP_DS__DS_MAX_SRC2_I64(MachInst)
Definition: decoder.cc:8148
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_XOR
Definition: instructions.hh:39431
gem5::VegaISA::Decoder::decode_OP_SOPP__S_CBRANCH_CDBGSYS
GPUStaticInst * decode_OP_SOPP__S_CBRANCH_CDBGSYS(MachInst)
Definition: decoder.cc:11193
gem5::VegaISA::Inst_VOP3__V_ADD_LSHL_U32
Definition: instructions.hh:29739
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_F_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_F_F64(MachInst)
Definition: decoder.cc:5198
gem5::VegaISA::InFmt_SOPC::OP
unsigned int OP
Definition: gpu_decoder.hh:1769
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_LT_I32
GPUStaticInst * decode_OPU_VOP3__V_CMP_LT_I32(MachInst)
Definition: decoder.cc:5492
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_DWORDX3
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:8262
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_C_D_CL(MachInst)
Definition: decoder.cc:9029
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LG_F64
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LG_F64(MachInst)
Definition: decoder.cc:5228
gem5::VegaISA::Inst_SOP1__S_BREV_B64
Definition: instructions.hh:2537
gem5::VegaISA::Inst_VOP3__V_MAX_I16
Definition: instructions.hh:25579
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN_X2(MachInst)
Definition: decoder.cc:10368
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4
Definition: instructions.hh:40685
gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32
Definition: instructions.hh:12535
gem5::VegaISA::Decoder::decode_OP_DS__DS_OR_RTN_B64
GPUStaticInst * decode_OP_DS__DS_OR_RTN_B64(MachInst)
Definition: decoder.cc:7871
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_CD_CL
Definition: instructions.hh:41621
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_LOAD_SSHORT
GPUStaticInst * decode_OP_FLAT__FLAT_LOAD_SSHORT(MachInst)
Definition: decoder.cc:8244
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_F16(MachInst)
Definition: decoder.cc:4832
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LT_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LT_F16(MachInst)
Definition: decoder.cc:4820
gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32
Definition: instructions.hh:11923
gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE
Definition: instructions.hh:36825
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_U16(MachInst)
Definition: decoder.cc:12489
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_BARRIER
GPUStaticInst * decode_OP_DS__DS_GWS_BARRIER(MachInst)
Definition: decoder.cc:8081
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_EQ_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_EQ_U64(MachInst)
Definition: decoder.cc:12885
gem5::VegaISA::Decoder::decode_OP_SOPP__S_BRANCH
GPUStaticInst * decode_OP_SOPP__S_BRANCH(MachInst)
Definition: decoder.cc:11067
gem5::VegaISA::Inst_SOP2__S_RFE_RESTORE_B64
Definition: instructions.hh:1507
gem5::VegaISA::Inst_SOPC__S_CMP_GE_I32
Definition: instructions.hh:3943
gem5::VegaISA::Inst_VOP3__V_ALIGNBIT_B32
Definition: instructions.hh:28649
gem5::VegaISA::Decoder::decode_OP_DS__DS_CMPST_RTN_F32
GPUStaticInst * decode_OP_DS__DS_CMPST_RTN_F32(MachInst)
Definition: decoder.cc:7546
gem5::VegaISA::Inst_SOPP__S_CBRANCH_CDBGSYS_AND_USER
Definition: instructions.hh:5271
gem5::VegaISA::Inst_SMEM__S_MEMREALTIME
Definition: instructions.hh:6109
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MED3_F32
GPUStaticInst * decode_OPU_VOP3__V_MED3_F32(MachInst)
Definition: decoder.cc:6746
gem5::VegaISA::Decoder::decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN
GPUStaticInst * decode_OP_SMEM__S_BUFFER_ATOMIC_UMIN(MachInst)
Definition: decoder.cc:10277
gem5::VegaISA::Inst_DS__DS_MIN_SRC2_U64
Definition: instructions.hh:35529
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL
GPUStaticInst * decode_OP_DS__DS_GWS_SEMA_RELEASE_ALL(MachInst)
Definition: decoder.cc:8051
gem5::VegaISA::Inst_VOP3__V_MAX_F16
Definition: instructions.hh:25477
gem5::VegaISA::Inst_DS__DS_WRITE_B8_D16_HI
Definition: instructions.hh:31937
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_BFREV_B32
GPUStaticInst * decode_OPU_VOP3__V_BFREV_B32(MachInst)
Definition: decoder.cc:6434
gem5::VegaISA::InstFormat::iFmt_SOPK
InFmt_SOPK iFmt_SOPK
Definition: gpu_decoder.hh:1930
gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F32
Definition: instructions.hh:29225
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64
Definition: instructions.hh:23789
gem5::VegaISA::Decoder::decode_OP_VOP1__V_FREXP_MANT_F16
GPUStaticInst * decode_OP_VOP1__V_FREXP_MANT_F16(MachInst)
Definition: decoder.cc:11639
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_XOR(MachInst)
Definition: decoder.cc:8723
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U16
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U16(MachInst)
Definition: decoder.cc:12495
gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F16
Definition: instructions.hh:11583
gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32
Definition: instructions.hh:19573
gem5::VegaISA::Decoder::decode_OP_SOPC__S_BITCMP1_B64
GPUStaticInst * decode_OP_SOPC__S_BITCMP1_B64(MachInst)
Definition: decoder.cc:11025
gem5::VegaISA::Decoder::decode_OP_SOP2__S_ORN2_B32
GPUStaticInst * decode_OP_SOP2__S_ORN2_B32(MachInst)
Definition: decoder.cc:4344
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MADMK_F32
GPUStaticInst * decode_OP_VOP2__V_MADMK_F32(MachInst)
Definition: decoder.cc:3983
gem5::VegaISA::Decoder::decode_OP_VOP2__V_ADD_F32
GPUStaticInst * decode_OP_VOP2__V_ADD_F32(MachInst)
Definition: decoder.cc:3851
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_SMIN
Definition: instructions.hh:37297
gem5::VegaISA::Inst_DS__DS_AND_RTN_B64
Definition: instructions.hh:34047
gem5::VegaISA::Inst_VOP3__V_SIN_F32
Definition: instructions.hh:27093
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_C_LZ_O(MachInst)
Definition: decoder.cc:9314
gem5::VegaISA::Inst_SOP1__S_WQM_B32
Definition: instructions.hh:2441
gem5::VegaISA::Inst_DS__DS_APPEND
Definition: instructions.hh:35255
gem5::VegaISA::Decoder::decode_OP_VOP2__V_MIN_I16
GPUStaticInst * decode_OP_VOP2__V_MIN_I16(MachInst)
Definition: decoder.cc:4145
gem5::VegaISA::Inst_DS__DS_MIN_RTN_U32
Definition: instructions.hh:32243
gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64
Definition: instructions.hh:16411
gem5::VegaISA::Decoder::decode_OP_SOPK__S_CALL_B64
GPUStaticInst * decode_OP_SOPK__S_CALL_B64(MachInst)
Definition: decoder.cc:4669
gem5::VegaISA::Inst_MIMG__IMAGE_ATOMIC_SUB
Definition: instructions.hh:39193
gem5::VegaISA::Decoder::decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X
GPUStaticInst * decode_OP_MTBUF__TBUFFER_LOAD_FORMAT_D16_X(MachInst)
Definition: decoder.cc:9422
gem5::VegaISA::Inst_VOP3__V_CUBETC_F32
Definition: instructions.hh:28361
gem5::VegaISA::Inst_SOPK__S_GETREG_B32
Definition: instructions.hh:2153
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_B
Definition: instructions.hh:39713
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_NOP
GPUStaticInst * decode_OPU_VOP3__V_NOP(MachInst)
Definition: decoder.cc:6176
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I16
GPUStaticInst * decode_OP_DS__DS_READ_I16(MachInst)
Definition: decoder.cc:7606
gem5::VegaISA::Inst_VOP3__V_CVT_PK_I16_I32
Definition: instructions.hh:31151
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_I8_D16
GPUStaticInst * decode_OP_DS__DS_READ_I8_D16(MachInst)
Definition: decoder.cc:7783
gem5::VegaISA::Decoder::tableSubDecode_OP_DS
static IsaDecodeMethod tableSubDecode_OP_DS[256]
Definition: gpu_decoder.hh:63
gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F16
Definition: instructions.hh:11073
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_SMIN
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_SMIN(MachInst)
Definition: decoder.cc:8390
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_LE_I16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_LE_I16(MachInst)
Definition: decoder.cc:5408
gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64
Definition: instructions.hh:16445
gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32
Definition: instructions.hh:12263
gem5::VegaISA::Inst_SOPK__S_MOVK_I32
Definition: instructions.hh:1609
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_DWORDX3(MachInst)
Definition: decoder.cc:9881
gem5::VegaISA::Decoder::decode_OP_DS__DS_BPERMUTE_B32
GPUStaticInst * decode_OP_DS__DS_BPERMUTE_B32(MachInst)
Definition: decoder.cc:7630
gem5::VegaISA::Inst_VOP3__V_MAC_F32
Definition: instructions.hh:24813
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_STORE_DWORD
GPUStaticInst * decode_OP_MUBUF__BUFFER_STORE_DWORD(MachInst)
Definition: decoder.cc:9641
gem5::VegaISA::Inst_VOPC__V_CMP_U_F16
Definition: instructions.hh:10937
gem5::VegaISA::Inst_DS__DS_ADD_U64
Definition: instructions.hh:33089
gem5::VegaISA::Inst_SOPC__S_CMP_GE_U32
Definition: instructions.hh:4135
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MUL_LEGACY_F32
GPUStaticInst * decode_OPU_VOP3__V_MUL_LEGACY_F32(MachInst)
Definition: decoder.cc:5894
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_STORE_DWORDX3(MachInst)
Definition: decoder.cc:9937
gem5::VegaISA::Decoder::decode_OP_DS__DS_XOR_RTN_B32
GPUStaticInst * decode_OP_DS__DS_XOR_RTN_B32(MachInst)
Definition: decoder.cc:7510
gem5::VegaISA::Decoder::decode_OP_VOP2__V_DOT8C_I32_I4
GPUStaticInst * decode_OP_VOP2__V_DOT8C_I32_I4(MachInst)
Definition: decoder.cc:4196
gem5::VegaISA::InFmt_FLAT
Definition: gpu_decoder.hh:1643
gem5::VegaISA::Inst_MIMG__IMAGE_LOAD_MIP
Definition: instructions.hh:38733
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C
Definition: instructions.hh:40901
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_SMIN_X2(MachInst)
Definition: decoder.cc:9785
gem5::VegaISA::Inst_SOP2__S_BFM_B64
Definition: instructions.hh:1235
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_T_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_T_I16(MachInst)
Definition: decoder.cc:12483
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_F_I16
GPUStaticInst * decode_OP_VOPC__V_CMPX_F_I16(MachInst)
Definition: decoder.cc:12441
gem5::VegaISA::Inst_DS__DS_OR_SRC2_B32
Definition: instructions.hh:34857
gem5::VegaISA::InstFormat::iFmt_MUBUF
InFmt_MUBUF iFmt_MUBUF
Definition: gpu_decoder.hh:1923
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_XOR_X2
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_XOR_X2(MachInst)
Definition: decoder.cc:8504
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_ATOMIC_DEC
GPUStaticInst * decode_OP_MUBUF__BUFFER_ATOMIC_DEC(MachInst)
Definition: decoder.cc:9755
gem5::VegaISA::Inst_VOP1__V_COS_F16
Definition: instructions.hh:10365
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CVT_U32_F64
GPUStaticInst * decode_OPU_VOP3__V_CVT_U32_F64(MachInst)
Definition: decoder.cc:6296
gem5::VegaISA::Decoder::decode_OP_SOP2__S_AND_B32
GPUStaticInst * decode_OP_SOP2__S_AND_B32(MachInst)
Definition: decoder.cc:4296
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F64
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F64(MachInst)
Definition: decoder.cc:7124
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_LT_U64
GPUStaticInst * decode_OP_VOPC__V_CMPX_LT_U64(MachInst)
Definition: decoder.cc:12879
gem5::VegaISA::Inst_VOP1__V_RSQ_F64
Definition: instructions.hh:9313
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_U32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_U32(MachInst)
Definition: decoder.cc:7486
gem5::VegaISA::Decoder::decode_OP_SOP2__S_NAND_B32
GPUStaticInst * decode_OP_SOP2__S_NAND_B32(MachInst)
Definition: decoder.cc:4356
gem5::VegaISA::Inst_VOP1__V_TRUNC_F64
Definition: instructions.hh:8833
gem5::VegaISA::Decoder::decode_OP_SMEM__S_ATC_PROBE
GPUStaticInst * decode_OP_SMEM__S_ATC_PROBE(MachInst)
Definition: decoder.cc:10216
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RNDNE_F16
GPUStaticInst * decode_OP_VOP1__V_RNDNE_F16(MachInst)
Definition: decoder.cc:11669
gem5::VegaISA::Decoder::decode_OP_DS__DS_GWS_INIT
GPUStaticInst * decode_OP_DS__DS_GWS_INIT(MachInst)
Definition: decoder.cc:8057
gem5::VegaISA::Decoder::decode_OP_VOP1__V_SAT_PK_U8_I16
GPUStaticInst * decode_OP_VOP1__V_SAT_PK_U8_I16(MachInst)
Definition: decoder.cc:11719
gem5::VegaISA::Decoder::decode_OP_SOP2__S_MUL_I32
GPUStaticInst * decode_OP_SOP2__S_MUL_I32(MachInst)
Definition: decoder.cc:4440
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMPX_NE_U32
GPUStaticInst * decode_OP_VOPC__V_CMPX_NE_U32(MachInst)
Definition: decoder.cc:12711
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_LOAD_DWORDX4(MachInst)
Definition: decoder.cc:8564
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64
Definition: instructions.hh:20253
gem5::VegaISA::Decoder::decode_OP_VOPC__V_CMP_O_F32
GPUStaticInst * decode_OP_VOPC__V_CMP_O_F32(MachInst)
Definition: decoder.cc:12003
gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32
Definition: instructions.hh:30573
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_SUB_F16
GPUStaticInst * decode_OPU_VOP3__V_SUB_F16(MachInst)
Definition: decoder.cc:6050
gem5::VegaISA::Inst_SOPP__S_CBRANCH_VCCNZ
Definition: instructions.hh:4699
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_MAX_I32
GPUStaticInst * decode_OPU_VOP3__V_MAX_I32(MachInst)
Definition: decoder.cc:5948
gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE1
Definition: instructions.hh:26357
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_I64
GPUStaticInst * decode_OP_DS__DS_MAX_I64(MachInst)
Definition: decoder.cc:7672
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_SAMPLE_B
GPUStaticInst * decode_OP_MIMG__IMAGE_SAMPLE_B(MachInst)
Definition: decoder.cc:8993
gem5::VegaISA::Decoder::decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16
GPUStaticInst * decode_OP_SCRATCH__SCRATCH_LOAD_SHORT_D16(MachInst)
Definition: decoder.cc:9979
gem5::VegaISA::Inst_VOP3__V_INTERP_P1_F32
Definition: instructions.hh:30161
gem5::VegaISA::Inst_VOP1__V_NOP
Definition: instructions.hh:8101
gem5::VegaISA::Decoder::decode_OP_VOP3P__V_PK_SUB_I16
GPUStaticInst * decode_OP_VOP3P__V_PK_SUB_I16(MachInst)
Definition: decoder.cc:12942
gem5::VegaISA::Inst_VOPC__V_CMP_T_I64
Definition: instructions.hh:16343
gem5::VegaISA::Inst_MIMG__IMAGE_GATHER4_C_LZ
Definition: instructions.hh:41081
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_NEQ_F16
GPUStaticInst * decode_OPU_VOP3__V_CMPX_NEQ_F16(MachInst)
Definition: decoder.cc:4892
gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64
Definition: instructions.hh:17091
gem5::VegaISA::Decoder::decode_OP_DS__DS_WRITE_B8
GPUStaticInst * decode_OP_DS__DS_WRITE_B8(MachInst)
Definition: decoder.cc:7432
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_LDEXP_F16
GPUStaticInst * decode_OPU_VOP3__V_LDEXP_F16(MachInst)
Definition: decoder.cc:6152
gem5::VegaISA::Decoder::decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP
GPUStaticInst * decode_OP_GLOBAL__GLOBAL_ATOMIC_SWAP(MachInst)
Definition: decoder.cc:8663
gem5::VegaISA::Decoder::decode_OP_DS__DS_READ_B32
GPUStaticInst * decode_OP_DS__DS_READ_B32(MachInst)
Definition: decoder.cc:7576
gem5::VegaISA::Decoder::decode_OP_DS__DS_MAX_U32
GPUStaticInst * decode_OP_DS__DS_MAX_U32(MachInst)
Definition: decoder.cc:7341
gem5::VegaISA::Inst_VOP3__V_LOG_LEGACY_F32
Definition: instructions.hh:28113
gem5::VegaISA::Decoder::decode_OP_MIMG__IMAGE_GATHER4_L_O
GPUStaticInst * decode_OP_MIMG__IMAGE_GATHER4_L_O(MachInst)
Definition: decoder.cc:9260
gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64
Definition: instructions.hh:23517
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_F64
GPUStaticInst * decode_OP_DS__DS_MIN_F64(MachInst)
Definition: decoder.cc:7744
gem5::VegaISA::Decoder::decode_OP_SOP1__S_SWAPPC_B64
GPUStaticInst * decode_OP_SOP1__S_SWAPPC_B64(MachInst)
Definition: decoder.cc:10786
gem5::VegaISA::Inst_VOP3__V_MED3_U32
Definition: instructions.hh:29009
gem5::VegaISA::Decoder::decode_OP_SOPC__S_CMP_LE_U32
GPUStaticInst * decode_OP_SOPC__S_CMP_LE_U32(MachInst)
Definition: decoder.cc:11001
gem5::VegaISA::Decoder::decode_OP_DS__DS_MIN_RTN_F32
GPUStaticInst * decode_OP_DS__DS_MIN_RTN_F32(MachInst)
Definition: decoder.cc:7552
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_DEC_X2
Definition: instructions.hh:38053
gem5::VegaISA::Inst_VOP2__V_MUL_F32
Definition: instructions.hh:6379
gem5::VegaISA::Inst_MIMG__IMAGE_SAMPLE_C_B_CL_O
Definition: instructions.hh:40613
gem5::VegaISA::Decoder::decode_OP_VOP1__V_RSQ_F64
GPUStaticInst * decode_OP_VOP1__V_RSQ_F64(MachInst)
Definition: decoder.cc:11482
gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD
Definition: instructions.hh:42507
gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F16
Definition: instructions.hh:18417
gem5::VegaISA::Inst_SOP1__S_MOVRELD_B64
Definition: instructions.hh:3687
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMPX_EQ_F32
GPUStaticInst * decode_OPU_VOP3__V_CMPX_EQ_F32(MachInst)
Definition: decoder.cc:5018
gem5::VegaISA::Decoder::decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI
GPUStaticInst * decode_OP_MUBUF__BUFFER_LOAD_SHORT_D16_HI(MachInst)
Definition: decoder.cc:10161
gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64
Definition: instructions.hh:13521
gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16
Definition: instructions.hh:21715
gem5::VegaISA::Decoder::decode_OP_FLAT__FLAT_ATOMIC_INC
GPUStaticInst * decode_OP_FLAT__FLAT_ATOMIC_INC(MachInst)
Definition: decoder.cc:8432
gem5::VegaISA::Inst_VOP3__V_RNDNE_F16
Definition: instructions.hh:27953
gem5::VegaISA::Inst_SOP1__S_FF1_I32_B64
Definition: instructions.hh:2793
gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_INC
Definition: instructions.hh:37549
gem5::VegaISA::Decoder::decode_OPU_VOP3__V_CMP_EQ_U64
GPUStaticInst * decode_OPU_VOP3__V_CMP_EQ_U64(MachInst)
Definition: decoder.cc:5738
gem5::VegaISA::Inst_DS__DS_ADD_RTN_U64
Definition: instructions.hh:33741

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