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isa.cc
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27 
28 #include "arch/arm/fastmodel/iris/isa.hh"
29 
30 #include "arch/arm/regs/misc.hh"
31 #include "base/logging.hh"
32 #include "cpu/thread_context.hh"
33 #include "sim/serialize.hh"
34 
35 namespace gem5
36 {
37 
38 void
39 Iris::ISA::serialize(CheckpointOut &cp) const
40 {
41  RegVal miscRegs[ArmISA::NUM_PHYS_MISCREGS];
42  for (int i = 0; i < ArmISA::NUM_PHYS_MISCREGS; i++)
43  miscRegs[i] = tc->readMiscRegNoEffect(i);
44  SERIALIZE_ARRAY(miscRegs, ArmISA::NUM_PHYS_MISCREGS);
45 }
46 
47 void
48 Iris::ISA::copyRegsFrom(ThreadContext *src)
49 {
50  panic("copyRegsFrom not implemented");
51 }
52 
53 } // namespace gem5
isa.hh
gem5::BaseISA::tc
ThreadContext * tc
Definition: isa.hh:66
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
serialize.hh
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:67
gem5::Iris::ThreadContext
Definition: thread_context.hh:54
gem5::Iris::ISA::copyRegsFrom
void copyRegsFrom(ThreadContext *src) override
Definition: isa.cc:48
SERIALIZE_ARRAY
#define SERIALIZE_ARRAY(member, size)
Definition: serialize.hh:610
gem5::ThreadContext::readMiscRegNoEffect
virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const =0
misc.hh
logging.hh
gem5::Iris::ISA::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: isa.cc:39
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::ArmISA::NUM_PHYS_MISCREGS
@ NUM_PHYS_MISCREGS
Definition: misc.hh:1104
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
thread_context.hh
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:188
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