gem5  [DEVELOP-FOR-23.0]
•All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
fs_workload.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3  * All rights reserved.
4  *
5  * This software was developed by the University of Cambridge Computer
6  * Laboratory as part of the CTSRD Project, with support from the UK Higher
7  * Education Innovation Fund (HEIF).
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions are
11  * met: redistributions of source code must retain the above copyright
12  * notice, this list of conditions and the following disclaimer;
13  * redistributions in binary form must reproduce the above copyright
14  * notice, this list of conditions and the following disclaimer in the
15  * documentation and/or other materials provided with the distribution;
16  * neither the name of the copyright holders nor the names of its
17  * contributors may be used to endorse or promote products derived from
18  * this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef __ARCH_ARM_FREEBSD_FS_WORKLOAD_HH__
34 #define __ARCH_ARM_FREEBSD_FS_WORKLOAD_HH__
35 
36 #include <map>
37 
38 #include "arch/arm/fs_workload.hh"
39 #include "kern/freebsd/events.hh"
40 #include "params/ArmFsFreebsd.hh"
41 
42 namespace gem5
43 {
44 
45 namespace ArmISA
46 {
47 
48 class FsFreebsd : public ArmISA::FsWorkload
49 {
50  public:
52  PARAMS(ArmFsFreebsd);
53 
56  bool enableContextSwitchStatsDump;
57 
62  std::map<uint32_t, uint32_t> taskMap;
63 
66  std::ostream* taskFile;
67 
68  FsFreebsd(const Params &p);
69  ~FsFreebsd();
70 
71  void initState() override;
72 
75  void mapPid(ThreadContext* tc, uint32_t pid);
76 
77  private:
79  PCEvent *kernelPanic = nullptr;
80 
82  PCEvent *kernelOops = nullptr;
83 
89  PCEvent *skipUDelay = nullptr;
90 
96  Addr secDataPtrAddr;
97  Addr secDataAddr;
98  Addr penReleaseAddr;
99  Addr pen64ReleaseAddr;
100  Addr bootReleaseAddr;
101 };
102 
103 } // namespace ArmISA
104 } // namespace gem5
105 
106 #endif // __ARCH_ARM_FREEBSD_FS_WORKLOAD_HH__
gem5::ArmISA::FsFreebsd::bootReleaseAddr
Addr bootReleaseAddr
Definition: fs_workload.hh:100
gem5::ArmISA::FsWorkload
Definition: fs_workload.hh:68
fs_workload.hh
events.hh
gem5::ArmISA::FsFreebsd::FsFreebsd
FsFreebsd(const Params &p)
Definition: fs_workload.cc:56
gem5::ArmISA::FsFreebsd
Definition: fs_workload.hh:48
gem5::ArmISA::FsFreebsd::PARAMS
PARAMS(ArmFsFreebsd)
Boilerplate params code.
gem5::ArmISA::FsFreebsd::taskFile
std::ostream * taskFile
This is a file that is placed in the run directory that prints out mappings between taskIds and OS pr...
Definition: fs_workload.hh:66
gem5::SimObject::Params
SimObjectParams Params
Definition: sim_object.hh:170
gem5::ArmISA::FsFreebsd::secDataPtrAddr
Addr secDataPtrAddr
These variables store addresses of important data structures that are normaly kept coherent at boot w...
Definition: fs_workload.hh:96
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::ArmISA::FsFreebsd::~FsFreebsd
~FsFreebsd()
Definition: fs_workload.cc:124
gem5::ArmISA::FsFreebsd::kernelOops
PCEvent * kernelOops
Event to halt the simulator if the kernel calls oopses
Definition: fs_workload.hh:82
gem5::PCEvent
Definition: pc_event.hh:45
gem5::ArmISA::FsFreebsd::pen64ReleaseAddr
Addr pen64ReleaseAddr
Definition: fs_workload.hh:99
gem5::ArmISA::FsFreebsd::mapPid
void mapPid(ThreadContext *tc, uint32_t pid)
This function creates a new task Id for the given pid.
gem5::ArmISA::FsFreebsd::kernelPanic
PCEvent * kernelPanic
Event to halt the simulator if the kernel calls panic()
Definition: fs_workload.hh:79
gem5::ArmISA::FsFreebsd::penReleaseAddr
Addr penReleaseAddr
Definition: fs_workload.hh:98
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ArmISA::FsFreebsd::initState
void initState() override
initState() is called on each SimObject when not restoring from a checkpoint.
Definition: fs_workload.cc:77
gem5::ArmISA::FsFreebsd::enableContextSwitchStatsDump
bool enableContextSwitchStatsDump
When enabled, dump stats/task info on context switches for Streamline and per-thread cache occupancy ...
Definition: fs_workload.hh:56
gem5::ArmISA::FsFreebsd::taskMap
std::map< uint32_t, uint32_t > taskMap
This map stores a mapping of OS process IDs to internal Task IDs.
Definition: fs_workload.hh:62
gem5::ArmISA::FsFreebsd::skipUDelay
PCEvent * skipUDelay
PC based event to skip udelay(<time>) calls and quiesce the processor for the appropriate amount of t...
Definition: fs_workload.hh:89
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::FsFreebsd::secDataAddr
Addr secDataAddr
Definition: fs_workload.hh:97
Generated on Sun Jul 30 2023 01:56:47 for gem5 by doxygen 1.8.17