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interrupts.cc
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37 
38 #include "arch/arm/interrupts.hh"
39 
40 #include "arch/arm/system.hh"
41 
42 namespace gem5
43 {
44 
45 bool
46 ArmISA::Interrupts::takeInt(InterruptTypes int_type) const
47 {
48  // Table G1-17~19 of ARM V8 ARM
49  InterruptMask mask;
50  bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
51 
52  CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
53  SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);;
54  HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
55  ExceptionLevel el = currEL(tc);
56  bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
57  bool is_secure = isSecure(tc);
58 
59  switch(int_type) {
60  case INT_FIQ:
61  cpsr_mask_bit = cpsr.f;
62  scr_routing_bit = scr.fiq;
63  scr_fwaw_bit = scr.fw;
64  hcr_mask_override_bit = hcr.fmo;
65  break;
66  case INT_IRQ:
67  cpsr_mask_bit = cpsr.i;
68  scr_routing_bit = scr.irq;
69  scr_fwaw_bit = 1;
70  hcr_mask_override_bit = hcr.imo;
71  break;
72  case INT_ABT:
73  cpsr_mask_bit = cpsr.a;
74  scr_routing_bit = scr.ea;
75  scr_fwaw_bit = scr.aw;
76  hcr_mask_override_bit = hcr.amo;
77  break;
78  default:
79  panic("Unhandled interrupt type!");
80  }
81 
82  if (hcr.tge)
83  hcr_mask_override_bit = 1;
84 
85  if (!highest_el_is_64) {
86  // AArch32
87  if (!scr_routing_bit) {
88  // SCR IRQ == 0
89  if (!hcr_mask_override_bit)
90  mask = INT_MASK_M;
91  else {
92  if (!is_secure && (el == EL0 || el == EL1))
93  mask = INT_MASK_T;
94  else
95  mask = INT_MASK_M;
96  }
97  } else {
98  // SCR IRQ == 1
99  if ((!is_secure) &&
100  (hcr_mask_override_bit ||
101  (!scr_fwaw_bit && !hcr_mask_override_bit)))
102  mask = INT_MASK_T;
103  else
104  mask = INT_MASK_M;
105  }
106  } else {
107  // AArch64
108  if (!scr_routing_bit) {
109  // SCR IRQ == 0
110  if (!scr.rw) {
111  // SCR RW == 0
112  if (!hcr_mask_override_bit) {
113  if (el == EL3)
114  mask = INT_MASK_P;
115  else
116  mask = INT_MASK_M;
117  } else {
118  if (el == EL3)
119  mask = INT_MASK_T;
120  else if (is_secure || el == EL2)
121  mask = INT_MASK_M;
122  else
123  mask = INT_MASK_T;
124  }
125  } else {
126  // SCR RW == 1
127  if (!hcr_mask_override_bit) {
128  if (el == EL3 || el == EL2)
129  mask = INT_MASK_P;
130  else
131  mask = INT_MASK_M;
132  } else {
133  if (el == EL3)
134  mask = INT_MASK_P;
135  else if (is_secure || el == EL2)
136  mask = INT_MASK_M;
137  else
138  mask = INT_MASK_T;
139  }
140  }
141  } else {
142  // SCR IRQ == 1
143  if (el == EL3)
144  mask = INT_MASK_M;
145  else
146  mask = INT_MASK_T;
147  }
148  }
149 
150  return ((mask == INT_MASK_T) ||
151  ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
152  (mask != INT_MASK_P);
153 }
154 
155 } // namespace gem5
gem5::ArmISA::Interrupts::INT_MASK_M
@ INT_MASK_M
Definition: interrupts.hh:126
gem5::ArmISA::MISCREG_CPSR
@ MISCREG_CPSR
Definition: misc.hh:66
gem5::ThreadContext::readMiscReg
virtual RegVal readMiscReg(RegIndex misc_reg)=0
gem5::ArmSystem::highestELIs64
bool highestELIs64() const
Returns true if the register width of the highest implemented exception level is 64 bits (ARMv8)
Definition: system.hh:187
gem5::ArmISA::el
Bitfield< 3, 2 > el
Definition: misc_types.hh:73
gem5::BaseInterrupts::tc
ThreadContext * tc
Definition: interrupts.hh:44
gem5::ArmISA::MISCREG_SCR_EL3
@ MISCREG_SCR_EL3
Definition: misc.hh:599
sc_dt::int_type
int64 int_type
Definition: sc_nbdefs.hh:240
gem5::ArmISA::INT_FIQ
@ INT_FIQ
Definition: interrupts.hh:64
gem5::ArmISA::EL1
@ EL1
Definition: types.hh:274
system.hh
gem5::ArmISA::Interrupts::InterruptMask
InterruptMask
Definition: interrupts.hh:124
gem5::ArmISA::INT_ABT
@ INT_ABT
Definition: interrupts.hh:62
interrupts.hh
gem5::ArmISA::Interrupts::INT_MASK_P
@ INT_MASK_P
Definition: interrupts.hh:128
gem5::ArmISA::Interrupts::takeInt
bool takeInt(InterruptTypes int_type) const
Definition: interrupts.cc:46
gem5::ArmISA::EL2
@ EL2
Definition: types.hh:275
gem5::ArmISA::mask
Bitfield< 3, 0 > mask
Definition: pcstate.hh:63
gem5::ArmISA::InterruptTypes
InterruptTypes
Definition: interrupts.hh:59
gem5::ArmISA::EL3
@ EL3
Definition: types.hh:276
gem5::ArmISA::isSecure
bool isSecure(ThreadContext *tc)
Definition: utility.cc:74
gem5::ArmISA::currEL
ExceptionLevel currEL(const ThreadContext *tc)
Returns the current Exception Level (EL) of the provided ThreadContext.
Definition: utility.cc:124
gem5::ArmISA::EL0
@ EL0
Definition: types.hh:273
gem5::ArmISA::INT_IRQ
@ INT_IRQ
Definition: interrupts.hh:63
gem5::ArmISA::MISCREG_HCR_EL2
@ MISCREG_HCR_EL2
Definition: misc.hh:591
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::Interrupts::INT_MASK_T
@ INT_MASK_T
Definition: interrupts.hh:127
gem5::ArmISA::ExceptionLevel
ExceptionLevel
Definition: types.hh:271
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:188
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