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ccr.hh
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37 
38 #ifndef __ARCH_X86_REGS_CCR_HH__
39 #define __ARCH_X86_REGS_CCR_HH__
40 
41 #include "cpu/reg_class.hh"
42 #include "debug/CCRegs.hh"
43 
44 namespace gem5
45 {
46 namespace X86ISA
47 {
48 namespace cc_reg
49 {
50 
51 enum : RegIndex
52 {
58 
60 };
61 
62 } // namespace cc_reg
63 
65  cc_reg::NumRegs, debug::CCRegs);
66 
67 namespace cc_reg
68 {
69 
70 inline constexpr RegId
76 
77 } // namespace cc_reg
78 
79 } // namespace X86ISA
80 } // namespace gem5
81 
82 #endif // __ARCH_X86_REGS_CCR_HH__
gem5::X86ISA::cc_reg::Ezf
constexpr RegId Ezf
Definition: ccr.hh:75
gem5::X86ISA::cc_reg::_CfofIdx
@ _CfofIdx
Definition: ccr.hh:54
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:68
gem5::X86ISA::cc_reg::Ecf
constexpr RegId Ecf
Definition: ccr.hh:74
gem5::X86ISA::cc_reg::Cfof
constexpr RegId Cfof
Definition: ccr.hh:72
gem5::X86ISA::cc_reg::_EcfIdx
@ _EcfIdx
Definition: ccr.hh:56
gem5::X86ISA::cc_reg::_EzfIdx
@ _EzfIdx
Definition: ccr.hh:57
gem5::RegClass
Definition: reg_class.hh:184
gem5::CCRegClassName
constexpr char CCRegClassName[]
Definition: reg_class.hh:80
gem5::X86ISA::cc_reg::_ZapsIdx
@ _ZapsIdx
Definition: ccr.hh:53
gem5::X86ISA::cc_reg::Df
constexpr RegId Df
Definition: ccr.hh:73
gem5::X86ISA::cc_reg::NumRegs
@ NumRegs
Definition: ccr.hh:59
gem5::X86ISA::cc_reg::_DfIdx
@ _DfIdx
Definition: ccr.hh:55
gem5::X86ISA::ccRegClass
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
reg_class.hh
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::cc_reg::Zaps
constexpr RegId Zaps
Definition: ccr.hh:71
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:92

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