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41 #ifndef __CPU__REG_CLASS_HH__
42 #define __CPU__REG_CLASS_HH__
52 #include "debug/InvalidReg.hh"
103 inline constexpr
RegId();
123 return !(*
this==that);
156 inline constexpr
const char*
className()
const;
158 inline constexpr
bool isFlat()
const;
173 virtual std::string
valString(
const void *
val,
size_t size)
const;
182 class RegClassIterator;
213 reg_class.
_flat =
false;
221 reg_class.
_ops = &new_ops;
225 template <
class RegType>
329 return id == other.
id;
335 return id != other.
id;
354 return RegId(*
this, idx);
357 template <
typename ValueType>
364 assert(size ==
sizeof(ValueType));
369 template <
typename ValueType>
385 return csprintf(
"v%d[%d]", reg_idx, elem_idx);
464 pinned = (numWrites != 0);
502 const size_t index =
static_cast<size_t>(reg_id.
index());
503 const size_t class_num =
static_cast<size_t>(reg_id.
classValue());
505 const size_t shifted_class_num =
510 const size_t concatenated_hash =
index | shifted_class_num;
516 "sizeof(RegIndex) should be less than sizeof(size_t)");
518 return concatenated_hash;
523 #endif // __CPU__REG_CLASS_HH__
RegId flatten(const BaseISA &isa) const
constexpr bool operator!=(const RegId &that) const
constexpr bool isRenameable() const
Return true if this register can be renamed.
int getNumPinnedWrites() const
const RegClass * _regClass
size_t operator()(const gem5::RegId ®_id) const
@ VecElemClass
Vector Register Native Elem lane.
constexpr char VecRegClassName[]
constexpr RegId(const RegClass ®_class, RegIndex reg_idx)
@ CCRegClass
Condition-code register.
int getNumPinnedWrites() const
constexpr char VecPredRegClassName[]
static std::ostream & operator<<(std::ostream &os, const DummyMatRegContainer &d)
friend std::ostream & operator<<(std::ostream &os, const RegId &rid)
std::string valString(const void *val) const
constexpr size_t regBytes() const
virtual std::string valString(const void *val, size_t size) const
Print the value of a register pointed to by val of size size.
const debug::Flag & debugFlag
std::string csprintf(const char *format, const Args &...args)
virtual std::string regName(const RegId &id) const
Print the name of the register specified in id.
constexpr RegClass invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg)
constexpr bool isFlat() const
void decrNumPinnedWritesToComplete()
std::string regName(const RegId &id) const
constexpr RegId operator[](RegIndex idx) const
std::forward_iterator_tag iterator_category
RegClassIterator operator++(int)
std::string valString(const void *val, size_t size) const override
Print the value of a register pointed to by val of size size.
@ FloatRegClass
Floating-point register.
VecElemRegClassOps(size_t elems_per_vec)
void decrNumPinnedWrites()
void setNumPinnedWrites(int num_writes)
const RegIndex & flatIndex() const
Flat index accessor.
constexpr RegClass regType() const
bool operator!=(const RegClassIterator &other) const
@ MatRegClass
Matrix Register.
void incrNumPinnedWritesToComplete()
constexpr bool operator==(const RegId &that) const
bool operator!=(const PhysRegId &that) const
constexpr bool operator<(const RegId &that) const
Order operator.
constexpr char IntRegClassName[]
constexpr char MatRegClassName[]
constexpr const char * className() const
Return a const char* with the register class name.
constexpr RegClassType type() const
int getNumPinnedWritesToComplete() const
constexpr char VecElemClassName[]
int numPinnedWritesToComplete
constexpr const char * name() const
constexpr char CCRegClassName[]
PhysRegId(const RegClass ®_class, RegIndex _regIdx, RegIndex _flatIdx)
Scalar PhysRegId constructor.
bool operator<(const PhysRegId &that) const
Explicit forward methods, to prevent comparisons of PhysRegId with RegIds.
@ IntRegClass
Integer register.
constexpr char MiscRegClassName[]
constexpr size_t regShift() const
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
static constexpr int ceilLog2(const T &n)
constexpr RegClass needsFlattening() const
RegClassType
Enumerate the classes of registers.
constexpr RegClass ops(const RegClassOps &new_ops) const
static RegClassOps defaultOps
bool operator==(const RegClassIterator &other) const
@ MiscRegClass
Control (misc) register.
Overload hash function for BasicBlockRange type.
constexpr RegClass(RegClassType type, const char *new_name, size_t num_regs, const debug::Flag &debug_flag)
virtual RegId flatten(const BaseISA &isa, const RegId &id) const
Flatten register id id using information in the ISA object isa.
void incrNumPinnedWrites()
RegId flatten(const BaseISA &isa, const RegId &id) const
void setNumPinnedWrites(int numWrites)
void setNumPinnedWritesToComplete(int numWrites)
RegClassIterator & operator++()
bool isFixedMapping() const
Returns true if this register is always associated to the same architectural register.
@ VecRegClass
Vector Register.
reference operator*() const
constexpr RegIndex index() const
Index accessors.
constexpr bool isFlat() const
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
constexpr RegClassType classValue() const
constexpr char FloatRegClassName[]
RegClassIterator(const RegClass ®_class, RegIndex idx)
constexpr bool is(RegClassType reg_class) const
constexpr const RegClass & regClass() const
Class accessor.
constexpr const debug::Flag & debug() const
bool operator==(const PhysRegId &that) const
Register ID: describe an architectural register with its class and index.
std::size_t difference_type
constexpr size_t numRegs() const
Generated on Sun Jul 30 2023 01:56:53 for gem5 by doxygen 1.8.17