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reg_class.hh
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40 
41 #ifndef __CPU__REG_CLASS_HH__
42 #define __CPU__REG_CLASS_HH__
43 
44 #include <cstddef>
45 #include <iterator>
46 #include <string>
47 
48 #include "base/cprintf.hh"
49 #include "base/debug.hh"
50 #include "base/intmath.hh"
51 #include "base/types.hh"
52 #include "debug/InvalidReg.hh"
53 
54 namespace gem5
55 {
56 
59 {
62 
71 };
72 
73 // "Standard" register class names. Using these is encouraged but optional.
74 inline constexpr char IntRegClassName[] = "integer";
75 inline constexpr char FloatRegClassName[] = "floating_point";
76 inline constexpr char VecRegClassName[] = "vector";
77 inline constexpr char VecElemClassName[] = "vector_element";
78 inline constexpr char VecPredRegClassName[] = "vector_predicate";
79 inline constexpr char MatRegClassName[] = "matrix";
80 inline constexpr char CCRegClassName[] = "condition_code";
81 inline constexpr char MiscRegClassName[] = "miscellaneous";
82 
83 class RegClass;
84 class RegClassIterator;
85 class BaseISA;
86 
92 class RegId
93 {
94  protected:
95  const RegClass *_regClass = nullptr;
98 
99  friend struct std::hash<RegId>;
100  friend class RegClassIterator;
101 
102  public:
103  inline constexpr RegId();
104 
105  constexpr RegId(const RegClass &reg_class, RegIndex reg_idx)
106  : _regClass(&reg_class), regIdx(reg_idx), numPinnedWrites(0)
107  {}
108 
109  constexpr operator RegIndex() const
110  {
111  return index();
112  }
113 
114  constexpr bool
115  operator==(const RegId& that) const
116  {
117  return classValue() == that.classValue() && regIdx == that.index();
118  }
119 
120  constexpr bool
121  operator!=(const RegId& that) const
122  {
123  return !(*this==that);
124  }
125 
129  constexpr bool
130  operator<(const RegId& that) const
131  {
132  return classValue() < that.classValue() ||
133  (classValue() == that.classValue() && (regIdx < that.index()));
134  }
135 
139  constexpr bool
140  isRenameable() const
141  {
143  }
144 
146  inline constexpr bool is(RegClassType reg_class) const;
147 
150  constexpr RegIndex index() const { return regIdx; }
151 
153  constexpr const RegClass &regClass() const { return *_regClass; }
154  inline constexpr RegClassType classValue() const;
156  inline constexpr const char* className() const;
157 
158  inline constexpr bool isFlat() const;
159  inline RegId flatten(const BaseISA &isa) const;
160 
161  int getNumPinnedWrites() const { return numPinnedWrites; }
162  void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
163 
164  friend inline std::ostream& operator<<(std::ostream& os, const RegId& rid);
165 };
166 
168 {
169  public:
171  virtual std::string regName(const RegId &id) const;
173  virtual std::string valString(const void *val, size_t size) const;
175  virtual RegId
176  flatten(const BaseISA &isa, const RegId &id) const
177  {
178  return id;
179  }
180 };
181 
182 class RegClassIterator;
183 
184 class RegClass
185 {
186  private:
188  const char *_name;
189 
190  size_t _numRegs;
191  size_t _regBytes = sizeof(RegVal);
192  // This is how much to shift an index by to get an offset of a register in
193  // a register file from the register index, which would otherwise need to
194  // be calculated with a multiply.
195  size_t _regShift = ceilLog2(sizeof(RegVal));
196 
197  static inline RegClassOps defaultOps;
200 
201  bool _flat = true;
202 
203  public:
204  constexpr RegClass(RegClassType type, const char *new_name,
205  size_t num_regs, const debug::Flag &debug_flag) :
206  _type(type), _name(new_name), _numRegs(num_regs), debugFlag(debug_flag)
207  {}
208 
209  constexpr RegClass
211  {
212  RegClass reg_class = *this;
213  reg_class._flat = false;
214  return reg_class;
215  }
216 
217  constexpr RegClass
218  ops(const RegClassOps &new_ops) const
219  {
220  RegClass reg_class = *this;
221  reg_class._ops = &new_ops;
222  return reg_class;
223  }
224 
225  template <class RegType>
226  constexpr RegClass
227  regType() const
228  {
229  RegClass reg_class = *this;
230  reg_class._regBytes = sizeof(RegType);
231  reg_class._regShift = ceilLog2(reg_class._regBytes);
232  return reg_class;
233  }
234 
235  constexpr RegClassType type() const { return _type; }
236  constexpr const char *name() const { return _name; }
237  constexpr size_t numRegs() const { return _numRegs; }
238  constexpr size_t regBytes() const { return _regBytes; }
239  constexpr size_t regShift() const { return _regShift; }
240  constexpr const debug::Flag &debug() const { return debugFlag; }
241  constexpr bool isFlat() const { return _flat; }
242 
243  std::string regName(const RegId &id) const { return _ops->regName(id); }
244  std::string
245  valString(const void *val) const
246  {
247  return _ops->valString(val, regBytes());
248  }
249  RegId
250  flatten(const BaseISA &isa, const RegId &id) const
251  {
252  return isFlat() ? id : _ops->flatten(isa, id);
253  }
254 
256 
257  inline iterator begin() const;
258  inline iterator end() const;
259 
260  inline constexpr RegId operator[](RegIndex idx) const;
261 };
262 
263 inline constexpr RegClass
264  invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg);
265 
266 constexpr RegId::RegId() : RegId(invalidRegClass, 0) {}
267 
268 constexpr bool
269 RegId::is(RegClassType reg_class) const
270 {
271  return _regClass->type() == reg_class;
272 }
273 
274 constexpr RegClassType RegId::classValue() const { return _regClass->type(); }
275 constexpr const char* RegId::className() const { return _regClass->name(); }
276 
277 constexpr bool RegId::isFlat() const { return _regClass->isFlat(); }
278 RegId
279 RegId::flatten(const BaseISA &isa) const
280 {
281  return _regClass->flatten(isa, *this);
282 }
283 
284 std::ostream&
285 operator<<(std::ostream& os, const RegId& rid)
286 {
287  return os << rid.regClass().regName(rid);
288 }
289 
291 {
292  private:
294 
295  RegClassIterator(const RegClass &reg_class, RegIndex idx) :
296  id(reg_class, idx)
297  {}
298 
299  friend class RegClass;
300 
301  public:
302  using iterator_category = std::forward_iterator_tag;
303  using difference_type = std::size_t;
304  using value_type = const RegId;
305  using pointer = value_type *;
307 
308  reference operator*() const { return id; }
309  pointer operator->() { return &id; }
310 
313  {
314  id.regIdx++;
315  return *this;
316  }
317 
320  {
321  auto tmp = *this;
322  ++(*this);
323  return tmp;
324  }
325 
326  bool
327  operator==(const RegClassIterator &other) const
328  {
329  return id == other.id;
330  }
331 
332  bool
333  operator!=(const RegClassIterator &other) const
334  {
335  return id != other.id;
336  }
337 };
338 
339 RegClassIterator
341 {
342  return RegClassIterator(*this, 0);
343 }
344 
347 {
348  return RegClassIterator(*this, numRegs());
349 }
350 
351 constexpr RegId
353 {
354  return RegId(*this, idx);
355 }
356 
357 template <typename ValueType>
359 {
360  public:
361  std::string
362  valString(const void *val, size_t size) const override
363  {
364  assert(size == sizeof(ValueType));
365  return csprintf("%s", *(const ValueType *)val);
366  }
367 };
368 
369 template <typename ValueType>
370 class VecElemRegClassOps : public TypedRegClassOps<ValueType>
371 {
372  protected:
373  size_t elemsPerVec;
374 
375  public:
376  explicit VecElemRegClassOps(size_t elems_per_vec) :
377  elemsPerVec(elems_per_vec)
378  {}
379 
380  std::string
381  regName(const RegId &id) const override
382  {
383  RegIndex reg_idx = id.index() / elemsPerVec;
384  RegIndex elem_idx = id.index() % elemsPerVec;
385  return csprintf("v%d[%d]", reg_idx, elem_idx);
386  }
387 };
388 
393 class PhysRegId : private RegId
394 {
395  private:
398  bool pinned;
399 
400  public:
401  explicit PhysRegId() : RegId(invalidRegClass, -1), flatIdx(-1),
403  {}
404 
406  explicit PhysRegId(const RegClass &reg_class, RegIndex _regIdx,
407  RegIndex _flatIdx)
408  : RegId(reg_class, _regIdx), flatIdx(_flatIdx),
410  {}
411 
414  using RegId::index;
415  using RegId::regClass;
416  using RegId::classValue;
417  using RegId::className;
418  using RegId::is;
425  bool
426  operator<(const PhysRegId& that) const
427  {
428  return RegId::operator<(that);
429  }
430 
431  bool
432  operator==(const PhysRegId& that) const
433  {
434  return RegId::operator==(that);
435  }
436 
437  bool
438  operator!=(const PhysRegId& that) const
439  {
440  return RegId::operator!=(that);
441  }
448  bool isFixedMapping() const { return !isRenameable(); }
449 
451  const RegIndex& flatIndex() const { return flatIdx; }
452 
453  int getNumPinnedWrites() const { return numPinnedWrites; }
454 
455  void
456  setNumPinnedWrites(int numWrites)
457  {
458  // An instruction with a pinned destination reg can get
459  // squashed. The numPinnedWrites counter may be zero when
460  // the squash happens but we need to know if the dest reg
461  // was pinned originally in order to reset counters properly
462  // for a possible re-rename using the same physical reg (which
463  // may be required in case of a mem access order violation).
464  pinned = (numWrites != 0);
465  numPinnedWrites = numWrites;
466  }
467 
470 
471  bool isPinned() const { return pinned; }
472 
473  int
475  {
477  }
478 
479  void
481  {
482  numPinnedWritesToComplete = numWrites;
483  }
484 
487 };
488 
490 
491 } // namespace gem5
492 
493 namespace std
494 {
495 template<>
496 struct hash<gem5::RegId>
497 {
498  size_t
499  operator()(const gem5::RegId& reg_id) const
500  {
501  // Extract unique integral values for the effective fields of a RegId.
502  const size_t index = static_cast<size_t>(reg_id.index());
503  const size_t class_num = static_cast<size_t>(reg_id.classValue());
504 
505  const size_t shifted_class_num =
506  class_num << (sizeof(gem5::RegIndex) << 3);
507 
508  // Concatenate the class_num to the end of the flat_index, in order to
509  // maximize information retained.
510  const size_t concatenated_hash = index | shifted_class_num;
511 
512  // If RegIndex is larger than size_t, then class_num will not be
513  // considered by this hash function, so we may wish to perform a
514  // different operation to include that information in the hash.
515  static_assert(sizeof(gem5::RegIndex) < sizeof(size_t),
516  "sizeof(RegIndex) should be less than sizeof(size_t)");
517 
518  return concatenated_hash;
519  }
520 };
521 } // namespace std
522 
523 #endif // __CPU__REG_CLASS_HH__
gem5::debug::Flag
Definition: debug.hh:61
gem5::RegId::flatten
RegId flatten(const BaseISA &isa) const
Definition: reg_class.hh:279
gem5::RegClass::_flat
bool _flat
Definition: reg_class.hh:201
gem5::PhysRegId::isPinned
bool isPinned() const
Definition: reg_class.hh:471
gem5::PhysRegId::PhysRegId
PhysRegId()
Definition: reg_class.hh:401
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::RegId::operator!=
constexpr bool operator!=(const RegId &that) const
Definition: reg_class.hh:121
gem5::RegId::isRenameable
constexpr bool isRenameable() const
Return true if this register can be renamed.
Definition: reg_class.hh:140
gem5::RegClass::_type
RegClassType _type
Definition: reg_class.hh:187
gem5::RegClass::_regShift
size_t _regShift
Definition: reg_class.hh:195
gem5::RegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:161
gem5::RegId::_regClass
const RegClass * _regClass
Definition: reg_class.hh:95
gem5::VecElemRegClassOps::elemsPerVec
size_t elemsPerVec
Definition: reg_class.hh:373
std::hash< gem5::RegId >::operator()
size_t operator()(const gem5::RegId &reg_id) const
Definition: reg_class.hh:499
gem5::VecElemClass
@ VecElemClass
Vector Register Native Elem lane.
Definition: reg_class.hh:65
gem5::VecRegClassName
constexpr char VecRegClassName[]
Definition: reg_class.hh:76
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::InvalidRegClass
@ InvalidRegClass
Definition: reg_class.hh:70
gem5::RegId::RegId
constexpr RegId(const RegClass &reg_class, RegIndex reg_idx)
Definition: reg_class.hh:105
gem5::CCRegClass
@ CCRegClass
Condition-code register.
Definition: reg_class.hh:68
gem5::PhysRegId::getNumPinnedWrites
int getNumPinnedWrites() const
Definition: reg_class.hh:453
gem5::VecPredRegClassName
constexpr char VecPredRegClassName[]
Definition: reg_class.hh:78
gem5::operator<<
static std::ostream & operator<<(std::ostream &os, const DummyMatRegContainer &d)
Definition: matrix.hh:564
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:776
gem5::RegId::operator<<
friend std::ostream & operator<<(std::ostream &os, const RegId &rid)
Definition: reg_class.hh:285
gem5::RegClass::valString
std::string valString(const void *val) const
Definition: reg_class.hh:245
gem5::RegClass::regBytes
constexpr size_t regBytes() const
Definition: reg_class.hh:238
gem5::RegClassOps::valString
virtual std::string valString(const void *val, size_t size) const
Print the value of a register pointed to by val of size size.
Definition: reg_class.cc:59
gem5::RegClass::debugFlag
const debug::Flag & debugFlag
Definition: reg_class.hh:199
gem5::csprintf
std::string csprintf(const char *format, const Args &...args)
Definition: cprintf.hh:161
gem5::RegClassOps::regName
virtual std::string regName(const RegId &id) const
Print the name of the register specified in id.
Definition: reg_class.cc:53
gem5::TypedRegClassOps
Definition: reg_class.hh:358
gem5::RegClassIterator::id
RegId id
Definition: reg_class.hh:293
gem5::invalidRegClass
constexpr RegClass invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg)
gem5::RegClass::isFlat
constexpr bool isFlat() const
Definition: reg_class.hh:241
gem5::PhysRegId::decrNumPinnedWritesToComplete
void decrNumPinnedWritesToComplete()
Definition: reg_class.hh:485
gem5::VecPredRegClass
@ VecPredRegClass
Definition: reg_class.hh:66
gem5::RegClass::regName
std::string regName(const RegId &id) const
Definition: reg_class.hh:243
gem5::RegClass::operator[]
constexpr RegId operator[](RegIndex idx) const
Definition: reg_class.hh:352
gem5::RegClassIterator::iterator_category
std::forward_iterator_tag iterator_category
Definition: reg_class.hh:302
gem5::RegClassIterator::operator++
RegClassIterator operator++(int)
Definition: reg_class.hh:319
gem5::TypedRegClassOps::valString
std::string valString(const void *val, size_t size) const override
Print the value of a register pointed to by val of size size.
Definition: reg_class.hh:362
gem5::FloatRegClass
@ FloatRegClass
Floating-point register.
Definition: reg_class.hh:61
gem5::VecElemRegClassOps::VecElemRegClassOps
VecElemRegClassOps(size_t elems_per_vec)
Definition: reg_class.hh:376
gem5::PhysRegId::decrNumPinnedWrites
void decrNumPinnedWrites()
Definition: reg_class.hh:468
gem5::RegId::setNumPinnedWrites
void setNumPinnedWrites(int num_writes)
Definition: reg_class.hh:162
gem5::PhysRegId::flatIndex
const RegIndex & flatIndex() const
Flat index accessor.
Definition: reg_class.hh:451
gem5::RegClass::regType
constexpr RegClass regType() const
Definition: reg_class.hh:227
gem5::PhysRegId::pinned
bool pinned
Definition: reg_class.hh:398
gem5::RegClassIterator::operator!=
bool operator!=(const RegClassIterator &other) const
Definition: reg_class.hh:333
gem5::MatRegClass
@ MatRegClass
Matrix Register.
Definition: reg_class.hh:67
gem5::PhysRegId::incrNumPinnedWritesToComplete
void incrNumPinnedWritesToComplete()
Definition: reg_class.hh:486
gem5::RegId::operator==
constexpr bool operator==(const RegId &that) const
Definition: reg_class.hh:115
gem5::PhysRegId::operator!=
bool operator!=(const PhysRegId &that) const
Definition: reg_class.hh:438
gem5::RegClass::_ops
const RegClassOps * _ops
Definition: reg_class.hh:198
gem5::RegId::operator<
constexpr bool operator<(const RegId &that) const
Order operator.
Definition: reg_class.hh:130
gem5::IntRegClassName
constexpr char IntRegClassName[]
Definition: reg_class.hh:74
debug.hh
gem5::MatRegClassName
constexpr char MatRegClassName[]
Definition: reg_class.hh:79
gem5::RegId::regIdx
RegIndex regIdx
Definition: reg_class.hh:96
gem5::RegId::className
constexpr const char * className() const
Return a const char* with the register class name.
Definition: reg_class.hh:275
cprintf.hh
gem5::RegClass::type
constexpr RegClassType type() const
Definition: reg_class.hh:235
gem5::PhysRegId::getNumPinnedWritesToComplete
int getNumPinnedWritesToComplete() const
Definition: reg_class.hh:474
gem5::VecElemClassName
constexpr char VecElemClassName[]
Definition: reg_class.hh:77
gem5::PhysRegId::numPinnedWritesToComplete
int numPinnedWritesToComplete
Definition: reg_class.hh:397
gem5::RegClass
Definition: reg_class.hh:184
gem5::RegClass::name
constexpr const char * name() const
Definition: reg_class.hh:236
gem5::CCRegClassName
constexpr char CCRegClassName[]
Definition: reg_class.hh:80
gem5::PhysRegId::PhysRegId
PhysRegId(const RegClass &reg_class, RegIndex _regIdx, RegIndex _flatIdx)
Scalar PhysRegId constructor.
Definition: reg_class.hh:406
gem5::PhysRegId::operator<
bool operator<(const PhysRegId &that) const
Explicit forward methods, to prevent comparisons of PhysRegId with RegIds.
Definition: reg_class.hh:426
gem5::RegClassIterator::operator->
pointer operator->()
Definition: reg_class.hh:309
gem5::RegClass::_name
const char * _name
Definition: reg_class.hh:188
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:60
gem5::MiscRegClassName
constexpr char MiscRegClassName[]
Definition: reg_class.hh:81
gem5::RegClass::regShift
constexpr size_t regShift() const
Definition: reg_class.hh:239
gem5::VecElemRegClassOps::regName
std::string regName(const RegId &id) const override
Print the name of the register specified in id.
Definition: reg_class.hh:381
gem5::ceilLog2
static constexpr int ceilLog2(const T &n)
Definition: intmath.hh:84
gem5::RegId::numPinnedWrites
int numPinnedWrites
Definition: reg_class.hh:97
gem5::RegClass::needsFlattening
constexpr RegClass needsFlattening() const
Definition: reg_class.hh:210
gem5::RegClass::end
iterator end() const
Definition: reg_class.hh:346
gem5::RegClassType
RegClassType
Enumerate the classes of registers.
Definition: reg_class.hh:58
gem5::RegClass::ops
constexpr RegClass ops(const RegClassOps &new_ops) const
Definition: reg_class.hh:218
gem5::RegClass::defaultOps
static RegClassOps defaultOps
Definition: reg_class.hh:197
gem5::RegClassIterator::operator==
bool operator==(const RegClassIterator &other) const
Definition: reg_class.hh:327
gem5::MiscRegClass
@ MiscRegClass
Control (misc) register.
Definition: reg_class.hh:69
std
Overload hash function for BasicBlockRange type.
Definition: misc.hh:2909
gem5::RegClass::RegClass
constexpr RegClass(RegClassType type, const char *new_name, size_t num_regs, const debug::Flag &debug_flag)
Definition: reg_class.hh:204
types.hh
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:810
gem5::RegClassOps::flatten
virtual RegId flatten(const BaseISA &isa, const RegId &id) const
Flatten register id id using information in the ISA object isa.
Definition: reg_class.hh:176
gem5::PhysRegId::incrNumPinnedWrites
void incrNumPinnedWrites()
Definition: reg_class.hh:469
gem5::PhysRegId::flatIdx
RegIndex flatIdx
Definition: reg_class.hh:396
gem5::RegClass::flatten
RegId flatten(const BaseISA &isa, const RegId &id) const
Definition: reg_class.hh:250
gem5::VecElemRegClassOps
Definition: reg_class.hh:370
gem5::PhysRegId::setNumPinnedWrites
void setNumPinnedWrites(int numWrites)
Definition: reg_class.hh:456
gem5::ArmISA::id
Bitfield< 33 > id
Definition: misc_types.hh:305
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:393
gem5::PhysRegId::setNumPinnedWritesToComplete
void setNumPinnedWritesToComplete(int numWrites)
Definition: reg_class.hh:480
gem5::RegClassIterator
Definition: reg_class.hh:290
gem5::RegClassIterator::operator++
RegClassIterator & operator++()
Definition: reg_class.hh:312
gem5::RegClass::begin
iterator begin() const
Definition: reg_class.hh:340
gem5::PhysRegId::isFixedMapping
bool isFixedMapping() const
Returns true if this register is always associated to the same architectural register.
Definition: reg_class.hh:448
gem5::VecRegClass
@ VecRegClass
Vector Register.
Definition: reg_class.hh:63
gem5::RegClassIterator::operator*
reference operator*() const
Definition: reg_class.hh:308
gem5::RegId::index
constexpr RegIndex index() const
Index accessors.
Definition: reg_class.hh:150
gem5::BaseISA
Definition: isa.hh:58
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
intmath.hh
gem5::RegId::isFlat
constexpr bool isFlat() const
Definition: reg_class.hh:277
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::RegId::classValue
constexpr RegClassType classValue() const
Definition: reg_class.hh:274
gem5::FloatRegClassName
constexpr char FloatRegClassName[]
Definition: reg_class.hh:75
gem5::RegClassIterator::RegClassIterator
RegClassIterator(const RegClass &reg_class, RegIndex idx)
Definition: reg_class.hh:295
gem5::RegId::is
constexpr bool is(RegClassType reg_class) const
Definition: reg_class.hh:269
gem5::RegClass::_numRegs
size_t _numRegs
Definition: reg_class.hh:190
gem5::RegId::regClass
constexpr const RegClass & regClass() const
Class accessor.
Definition: reg_class.hh:153
gem5::RegClassOps
Definition: reg_class.hh:167
gem5::RegClass::_regBytes
size_t _regBytes
Definition: reg_class.hh:191
gem5::RegClass::debug
constexpr const debug::Flag & debug() const
Definition: reg_class.hh:240
gem5::PhysRegId::operator==
bool operator==(const PhysRegId &that) const
Definition: reg_class.hh:432
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:92
gem5::RegClassIterator::difference_type
std::size_t difference_type
Definition: reg_class.hh:303
gem5::RegClass::numRegs
constexpr size_t numRegs() const
Definition: reg_class.hh:237
gem5::RegId::RegId
constexpr RegId()
Definition: reg_class.hh:266

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