gem5
[DEVELOP-FOR-23.0]
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We provide a base class for integer operations and then inherit for several other classes. More...
#include <integer.hh>
Protected Member Functions | |
IntOp (const char *mnem, MachInst _machInst, OpClass __opClass) | |
Constructor. More... | |
uint32_t | makeCRFieldSigned (int64_t a, int64_t b, bool so) const |
uint32_t | makeCRFieldUnsigned (uint64_t a, uint64_t b, bool so) const |
std::string | generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override |
Internal function to generate disassembly string. More... | |
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PowerStaticInst (const char *mnem, ExtMachInst _machInst, OpClass __opClass) | |
uint32_t | insertCRField (uint32_t cr, uint32_t bf, uint32_t value) const |
void | printReg (std::ostream &os, RegId reg) const |
Print a register name for disassembly given the unique dependence tag number (FP or int). More... | |
std::string | generateDisassembly (Addr pc, const loader::SymbolTable *symtab) const override |
Internal function to generate disassembly string. More... | |
void | advancePC (PCStateBase &pc_state) const override |
void | advancePC (ThreadContext *tc) const override |
std::unique_ptr< PCStateBase > | buildRetPC (const PCStateBase &cur_pc, const PCStateBase &call_pc) const override |
size_t | asBytes (void *buf, size_t max_size) override |
Instruction classes can override this function to return a a representation of themselves as a blob of bytes, generally assumed to be that instructions ExtMachInst. More... | |
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void | setRegIdxArrays (RegIdArrayPtr src, RegIdArrayPtr dest) |
Set the pointers which point to the arrays of source and destination register indices. More... | |
StaticInst (const char *_mnemonic, OpClass op_class) | |
Constructor. More... | |
template<typename T > | |
size_t | simpleAsBytes (void *buf, size_t max_size, const T &t) |
Protected Attributes | |
bool | rc |
bool | oe |
uint32_t | sh |
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ExtMachInst | machInst |
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std::bitset< Num_Flags > | flags |
Flag values for this instruction. More... | |
OpClass | _opClass |
See opClass(). More... | |
uint8_t | _numSrcRegs = 0 |
See numSrcRegs(). More... | |
uint8_t | _numDestRegs = 0 |
See numDestRegs(). More... | |
std::array< uint8_t, MiscRegClass+1 > | _numTypedDestRegs = {} |
const char * | mnemonic |
Base mnemonic (e.g., "add"). More... | |
std::unique_ptr< std::string > | cachedDisassembly |
String representation of disassembly (lazily evaluated via disassemble()). More... | |
Additional Inherited Members | |
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using | RegIdArrayPtr = RegId(StaticInst::*)[] |
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uint8_t | numSrcRegs () const |
Number of source registers. More... | |
uint8_t | numDestRegs () const |
Number of destination registers. More... | |
uint8_t | numDestRegs (RegClassType type) const |
Number of destination registers of a particular type. More... | |
bool | isNop () const |
bool | isMemRef () const |
bool | isLoad () const |
bool | isStore () const |
bool | isAtomic () const |
bool | isStoreConditional () const |
bool | isInstPrefetch () const |
bool | isDataPrefetch () const |
bool | isPrefetch () const |
bool | isInteger () const |
bool | isFloating () const |
bool | isVector () const |
bool | isMatrix () const |
bool | isControl () const |
bool | isCall () const |
bool | isReturn () const |
bool | isDirectCtrl () const |
bool | isIndirectCtrl () const |
bool | isCondCtrl () const |
bool | isUncondCtrl () const |
bool | isSerializing () const |
bool | isSerializeBefore () const |
bool | isSerializeAfter () const |
bool | isSquashAfter () const |
bool | isFullMemBarrier () const |
bool | isReadBarrier () const |
bool | isWriteBarrier () const |
bool | isNonSpeculative () const |
bool | isQuiesce () const |
bool | isUnverifiable () const |
bool | isSyscall () const |
bool | isMacroop () const |
bool | isMicroop () const |
bool | isDelayedCommit () const |
bool | isLastMicroop () const |
bool | isFirstMicroop () const |
bool | isHtmStart () const |
bool | isHtmStop () const |
bool | isHtmCancel () const |
bool | isHtmCmd () const |
void | setFirstMicroop () |
void | setLastMicroop () |
void | setDelayedCommit () |
void | setFlag (Flags f) |
OpClass | opClass () const |
Operation class. Used to select appropriate function unit in issue. More... | |
const RegId & | destRegIdx (int i) const |
Return logical index (architectural reg num) of i'th destination reg. More... | |
void | setDestRegIdx (int i, const RegId &val) |
const RegId & | srcRegIdx (int i) const |
Return logical index (architectural reg num) of i'th source reg. More... | |
void | setSrcRegIdx (int i, const RegId &val) |
virtual uint64_t | getEMI () const |
virtual | ~StaticInst () |
virtual Fault | execute (ExecContext *xc, trace::InstRecord *traceData) const =0 |
virtual Fault | initiateAcc (ExecContext *xc, trace::InstRecord *traceData) const |
virtual Fault | completeAcc (Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) const |
virtual StaticInstPtr | fetchMicroop (MicroPC upc) const |
Return the microop that goes with a particular micropc. More... | |
virtual std::unique_ptr< PCStateBase > | branchTarget (const PCStateBase &pc) const |
Return the target address for a PC-relative branch. More... | |
virtual std::unique_ptr< PCStateBase > | branchTarget (ThreadContext *tc) const |
Return the target address for an indirect branch (jump). More... | |
virtual const std::string & | disassemble (Addr pc, const loader::SymbolTable *symtab=nullptr) const |
Return string representation of disassembled instruction. More... | |
void | printFlags (std::ostream &outs, const std::string &separator) const |
Print a separator separated list of this instruction's set flag names on the given stream. More... | |
std::string | getName () |
Return name of machine instruction. More... | |
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RefCounted () | |
We initialize the reference count to zero and the first object to take ownership of it must increment it to one. More... | |
virtual | ~RefCounted () |
We make the destructor virtual because we're likely to have virtual functions on reference counted objects. More... | |
void | incref () const |
Increment the reference count. More... | |
void | decref () const |
Decrement the reference count and destroy the object if all references are gone. More... | |
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static StaticInstPtr | nullStaticInstPtr |
Pointer to a statically allocated "null" instruction object. More... | |
We provide a base class for integer operations and then inherit for several other classes.
These specialise for instructions using immediate values and also rotate instructions. We also need to have versions that consider the Rc and OE bits. Base class for integer operations.
Definition at line 54 of file integer.hh.
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inlineprotected |
Constructor.
Definition at line 65 of file integer.hh.
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overrideprotectedvirtual |
Internal function to generate disassembly string.
Implements gem5::StaticInst.
Reimplemented in gem5::PowerISA::IntImmTrapOp, gem5::PowerISA::IntTrapOp, gem5::PowerISA::IntConcatRotateOp, gem5::PowerISA::IntRotateOp, gem5::PowerISA::IntConcatShiftOp, gem5::PowerISA::IntShiftOp, gem5::PowerISA::IntImmLogicOp, gem5::PowerISA::IntLogicOp, gem5::PowerISA::IntImmCompLogicOp, gem5::PowerISA::IntImmCompOp, gem5::PowerISA::IntCompOp, gem5::PowerISA::IntDispArithOp, gem5::PowerISA::IntImmArithOp, gem5::PowerISA::IntArithOp, and gem5::PowerISA::IntImmOp.
Definition at line 38 of file integer.cc.
References gem5::StaticInst::_numDestRegs, gem5::StaticInst::_numSrcRegs, gem5::ccprintf(), gem5::StaticInst::destRegIdx(), gem5::StaticInst::mnemonic, oe, gem5::PowerISA::PowerStaticInst::printReg(), rc, gem5::StaticInst::srcRegIdx(), and ss.
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inlineprotected |
Definition at line 74 of file integer.hh.
References gem5::ArmISA::a, gem5::ArmISA::b, gem5::PowerISA::int_reg::Cr, gem5::X86ISA::misc_reg::cr(), and gem5::PowerISA::so.
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inlineprotected |
Definition at line 88 of file integer.hh.
References gem5::ArmISA::a, gem5::ArmISA::b, gem5::PowerISA::int_reg::Cr, gem5::X86ISA::misc_reg::cr(), and gem5::PowerISA::so.
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Definition at line 59 of file integer.hh.
Referenced by generateDisassembly(), and gem5::PowerISA::IntArithOp::generateDisassembly().
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Definition at line 58 of file integer.hh.
Referenced by generateDisassembly(), gem5::PowerISA::IntArithOp::generateDisassembly(), gem5::PowerISA::IntLogicOp::generateDisassembly(), gem5::PowerISA::IntShiftOp::generateDisassembly(), gem5::PowerISA::IntConcatShiftOp::generateDisassembly(), gem5::PowerISA::IntRotateOp::generateDisassembly(), gem5::PowerISA::IntConcatRotateOp::generateDisassembly(), and gem5::PowerISA::IntArithOp::multiplyAdd().
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Definition at line 62 of file integer.hh.