static_inst.hh

Go to the documentation of this file.

/*
 * Copyright (c) 2017, 2020 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2003-2005 The Regents of The University of Michigan
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __CPU_STATIC_INST_HH__
#define __CPU_STATIC_INST_HH__
 
#include <array>
#include <bitset>
#include <cstdint>
#include <memory>
#include <string>
 
#include "arch/generic/pcstate.hh"
#include "base/logging.hh"
#include "base/refcnt.hh"
#include "cpu/op_class.hh"
#include "cpu/reg_class.hh"
#include "cpu/static_inst_fwd.hh"
#include "enums/StaticInstFlags.hh"
#include "sim/byteswap.hh"
 
namespace gem5
{
 
// forward declarations
class Packet;
 
class ExecContext;
class ThreadContext;
 
namespace loader
{
class SymbolTable;
} // namespace loader
 
namespace trace
{
class InstRecord;
} // namespace trace
 
class StaticInst : public RefCounted, public StaticInstFlags
{
  public:
    using RegIdArrayPtr = RegId (StaticInst:: *)[];
 
  private:
    RegIdArrayPtr _srcRegIdxPtr = nullptr;
 
    RegIdArrayPtr _destRegIdxPtr = nullptr;
 
  protected:
 
    std::bitset<Num_Flags> flags;
 
    OpClass _opClass;
 
    uint8_t _numSrcRegs = 0;
 
    uint8_t _numDestRegs = 0;
 
    std::array<uint8_t, MiscRegClass + 1> _numTypedDestRegs = {};
 
  public:
 
 
    uint8_t numSrcRegs()  const { return _numSrcRegs; }
    uint8_t numDestRegs() const { return _numDestRegs; }
    uint8_t
    numDestRegs(RegClassType type) const
    {
        return _numTypedDestRegs[type];
    }
 
 
 
    bool isNop()          const { return flags[IsNop]; }
 
    bool
    isMemRef() const
    {
        return flags[IsLoad] || flags[IsStore] || flags[IsAtomic];
    }
    bool isLoad()         const { return flags[IsLoad]; }
    bool isStore()        const { return flags[IsStore]; }
    bool isAtomic()       const { return flags[IsAtomic]; }
    bool isStoreConditional()     const { return flags[IsStoreConditional]; }
    bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
    bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
    bool isPrefetch()     const { return isInstPrefetch() ||
                                         isDataPrefetch(); }
 
    bool isInteger()      const { return flags[IsInteger]; }
    bool isFloating()     const { return flags[IsFloating]; }
    bool isVector()       const { return flags[IsVector]; }
    bool isMatrix()       const { return flags[IsMatrix]; }
 
    bool isControl()      const { return flags[IsControl]; }
    bool isCall()         const { return flags[IsCall]; }
    bool isReturn()       const { return flags[IsReturn]; }
    bool isDirectCtrl()   const { return flags[IsDirectControl]; }
    bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
    bool isCondCtrl()     const { return flags[IsCondControl]; }
    bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 
    bool isSerializing()  const { return flags[IsSerializing] ||
                                      flags[IsSerializeBefore] ||
                                      flags[IsSerializeAfter]; }
    bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
    bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
    bool isSquashAfter() const { return flags[IsSquashAfter]; }
    bool
    isFullMemBarrier() const
    {
        return flags[IsReadBarrier] && flags[IsWriteBarrier];
    }
    bool isReadBarrier() const { return flags[IsReadBarrier]; }
    bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
    bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
    bool isQuiesce() const { return flags[IsQuiesce]; }
    bool isUnverifiable() const { return flags[IsUnverifiable]; }
    bool isSyscall() const { return flags[IsSyscall]; }
    bool isMacroop() const { return flags[IsMacroop]; }
    bool isMicroop() const { return flags[IsMicroop]; }
    bool isDelayedCommit() const { return flags[IsDelayedCommit]; }
    bool isLastMicroop() const { return flags[IsLastMicroop]; }
    bool isFirstMicroop() const { return flags[IsFirstMicroop]; }
    // hardware transactional memory
    // HtmCmds must be identified as such in order
    // to provide them with necessary memory ordering semantics.
    bool isHtmStart() const { return flags[IsHtmStart]; }
    bool isHtmStop() const { return flags[IsHtmStop]; }
    bool isHtmCancel() const { return flags[IsHtmCancel]; }
 
    bool
    isHtmCmd() const
    {
        return isHtmStart() || isHtmStop() || isHtmCancel();
    }
 
    void setFirstMicroop() { flags[IsFirstMicroop] = true; }
    void setLastMicroop() { flags[IsLastMicroop] = true; }
    void setDelayedCommit() { flags[IsDelayedCommit] = true; }
    void setFlag(Flags f) { flags[f] = true; }
 
    OpClass opClass() const { return _opClass; }
 
 
    const RegId &destRegIdx(int i) const { return (this->*_destRegIdxPtr)[i]; }
 
    void
    setDestRegIdx(int i, const RegId &val)
    {
        (this->*_destRegIdxPtr)[i] = val;
    }
 
    const RegId &srcRegIdx(int i) const { return (this->*_srcRegIdxPtr)[i]; }
 
    void
    setSrcRegIdx(int i, const RegId &val)
    {
        (this->*_srcRegIdxPtr)[i] = val;
    }
 
    static StaticInstPtr nullStaticInstPtr;
 
    virtual uint64_t getEMI() const { return 0; }
 
  protected:
 
    void
    setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)
    {
        _srcRegIdxPtr = src;
        _destRegIdxPtr = dest;
    }
 
    const char *mnemonic;
 
    mutable std::unique_ptr<std::string> cachedDisassembly;
 
    virtual std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const = 0;
 
    StaticInst(const char *_mnemonic, OpClass op_class)
        : _opClass(op_class), mnemonic(_mnemonic)
    {}
 
  public:
    virtual ~StaticInst() {};
 
    virtual Fault execute(ExecContext *xc,
            trace::InstRecord *traceData) const = 0;
 
    virtual Fault
    initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const
    {
        panic("initiateAcc not defined!");
    }
 
    virtual Fault
    completeAcc(Packet *pkt, ExecContext *xc,
            trace::InstRecord *trace_data) const
    {
        panic("completeAcc not defined!");
    }
 
    virtual void advancePC(PCStateBase &pc_state) const = 0;
    virtual void advancePC(ThreadContext *tc) const;
 
    virtual std::unique_ptr<PCStateBase>
    buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const
    {
        panic("buildRetPC not defined!");
    }
 
    virtual StaticInstPtr fetchMicroop(MicroPC upc) const;
 
    virtual std::unique_ptr<PCStateBase> branchTarget(
            const PCStateBase &pc) const;
 
    virtual std::unique_ptr<PCStateBase> branchTarget(
            ThreadContext *tc) const;
 
    virtual const std::string &disassemble(Addr pc,
        const loader::SymbolTable *symtab=nullptr) const;
 
    void printFlags(std::ostream &outs, const std::string &separator) const;
 
    std::string getName() { return mnemonic; }
 
  protected:
    template<typename T>
    size_t
    simpleAsBytes(void *buf, size_t max_size, const T &t)
    {
        size_t size = sizeof(T);
        if (size <= max_size)
            *reinterpret_cast<T *>(buf) = htole<T>(t);
        return size;
    }
 
  public:
    virtual size_t asBytes(void *buf, size_t max_size) { return 0; }
};
 
} // namespace gem5
 
#endif // __CPU_STATIC_INST_HH__