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thread_context.cc
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41 
42 #include "cpu/o3/thread_context.hh"
43 
44 #include "debug/O3CPU.hh"
45 
46 namespace gem5
47 {
48 
49 namespace o3
50 {
51 
52 void
54 {
55  gem5::takeOverFrom(*this, *old_context);
56 
57  getIsaPtr()->takeOverFrom(this, old_context);
58 
59  InstDecoder *newDecoder = getDecoderPtr();
60  InstDecoder *oldDecoder = old_context->getDecoderPtr();
61  newDecoder->takeOverFrom(oldDecoder);
62 
63  thread->noSquashFromTC = false;
64  thread->trapPending = false;
65 }
66 
67 void
69 {
70  DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
71  threadId());
72 
74  return;
75 
78 
79  // status() == Suspended
81 }
82 
83 void
85 {
86  DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
87  threadId());
88 
90  return;
91 
92  if (cpu->isDraining()) {
93  DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
94  return;
95  }
96 
99 
102 }
103 
104 void
106 {
107  DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());
108 
111  return;
112 
113  // the thread is not going to halt/terminate immediately in this cycle.
114  // The thread will be removed after an exit trap is processed
115  // (e.g., after trapLatency cycles). Until then, the thread's status
116  // will be Halting.
118 
119  // add this thread to the exiting list to mark that it is trying to exit.
121 }
122 
123 Tick
125 {
126  return thread->lastActivate;
127 }
128 
129 Tick
131 {
132  return thread->lastSuspend;
133 }
134 
135 void
137 {
138  // Prevent squashing
139  thread->noSquashFromTC = true;
140  getIsaPtr()->copyRegsFrom(tc);
141  thread->noSquashFromTC = false;
142 }
143 
144 void
146 {
147  cpu->isa[thread->threadId()]->clear();
148 }
149 
150 RegVal
152 {
153  return cpu->getArchReg(reg, thread->threadId());
154 }
155 
156 void *
158 {
160 }
161 
162 void
163 ThreadContext::getReg(const RegId &reg, void *val) const
164 {
166 }
167 
168 void
170 {
173 }
174 
175 void
176 ThreadContext::setReg(const RegId &reg, const void *val)
177 {
180 }
181 
182 void
184 {
185  cpu->pcState(val, thread->threadId());
186 
188 }
189 
190 void
192 {
193  cpu->pcState(val, thread->threadId());
194 
196 }
197 
198 void
200 {
201  cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
202 
204 }
205 
206 void
208 {
209  cpu->setMiscReg(misc_reg, val, thread->threadId());
210 
212 }
213 
214 // hardware transactional memory
215 void
217  HtmFailureFaultCause cause)
218 {
219  cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
220 
222 }
223 
226 {
227  return thread->htmCheckpoint;
228 }
229 
230 void
232 {
233  thread->htmCheckpoint = std::move(new_cpt);
234 }
235 
236 } // namespace o3
237 } // namespace gem5
gem5::curTick
Tick curTick()
The universal simulation clock.
Definition: cur_tick.hh:46
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1360
gem5::o3::CPU::getWritableArchReg
void * getWritableArchReg(const RegId &reg, ThreadID tid)
Definition: cpu.cc:1072
gem5::o3::ThreadContext::thread
ThreadState * thread
Pointer to the thread state that this TC corrseponds to.
Definition: thread_context.hh:101
gem5::ThreadContext::Active
@ Active
Running.
Definition: thread_context.hh:103
gem5::BaseHTMCheckpointPtr
std::unique_ptr< BaseHTMCheckpoint > BaseHTMCheckpointPtr
Definition: htm.hh:125
gem5::o3::ThreadContext::htmAbortTransaction
void htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: thread_context.cc:216
gem5::o3::ThreadContext::activate
void activate() override
Set the status to Active.
Definition: thread_context.cc:68
gem5::o3::ThreadContext::takeOverFrom
void takeOverFrom(gem5::ThreadContext *old_context) override
Takes over execution of a thread from another CPU.
Definition: thread_context.cc:53
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::ThreadContext::getHtmCheckpointPtr
BaseHTMCheckpointPtr & getHtmCheckpointPtr() override
Definition: thread_context.cc:225
gem5::BaseISA::copyRegsFrom
virtual void copyRegsFrom(ThreadContext *src)=0
gem5::ThreadContext::Halted
@ Halted
Permanently shut down.
Definition: thread_context.hh:116
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::InstDecoder::takeOverFrom
virtual void takeOverFrom(InstDecoder *old)
Take over the state from an old decoder when switching CPUs.
Definition: decoder.hh:89
gem5::o3::ThreadContext::getIsaPtr
BaseISA * getIsaPtr() const override
Definition: thread_context.hh:109
gem5::o3::ThreadContext::threadId
int threadId() const override
Returns this thread's ID number.
Definition: thread_context.hh:134
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
This function is used to instruct the memory subsystem that a transaction should be aborted and the s...
Definition: cpu.cc:1428
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:776
gem5::o3::ThreadContext::getWritableReg
void * getWritableReg(const RegId &reg) override
Definition: thread_context.cc:157
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:929
gem5::BaseISA::takeOverFrom
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
Definition: isa.hh:81
gem5::o3::ThreadContext::setReg
void setReg(const RegId &reg, RegVal val) override
Definition: thread_context.cc:169
gem5::o3::ThreadContext::conditionalSquash
void conditionalSquash()
check if the cpu is currently in state update mode and squash if not.
Definition: thread_context.hh:233
gem5::takeOverFrom
void takeOverFrom(ThreadContext &ntc, ThreadContext &otc)
Copy state between thread contexts in preparation for CPU handover.
Definition: thread_context.cc:252
gem5::o3::ThreadContext::getDecoderPtr
InstDecoder * getDecoderPtr() override
Definition: thread_context.hh:115
gem5::o3::ThreadState::htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
Definition: thread_state.hh:92
gem5::ThreadState::lastSuspend
Tick lastSuspend
Last time suspend was called on this thread.
Definition: thread_state.hh:128
gem5::o3::ThreadContext::suspend
void suspend() override
Set the status to Suspended.
Definition: thread_context.cc:84
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:535
gem5::InstDecoder
Definition: decoder.hh:42
gem5::ThreadContext::Suspended
@ Suspended
Temporarily inactive.
Definition: thread_context.hh:107
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:210
gem5::ThreadContext::getDecoderPtr
virtual InstDecoder * getDecoderPtr()=0
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1102
gem5::o3::ThreadContext::setMiscRegNoEffect
void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:199
gem5::o3::ThreadContext::setHtmCheckpointPtr
void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
Definition: thread_context.cc:231
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:923
gem5::ThreadState::threadId
ThreadID threadId() const
Definition: thread_state.hh:69
gem5::o3::ThreadContext::getReg
RegVal getReg(const RegId &reg) const override
Definition: thread_context.cc:151
gem5::ThreadState::setStatus
void setStatus(Status new_status)
Sets the status of this thread.
Definition: thread_state.hh:83
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition: thread_state.hh:84
gem5::ThreadState::lastActivate
Tick lastActivate
Last time activate was called on this thread.
Definition: thread_state.hh:125
gem5::o3::ThreadContext::halt
void halt() override
Set the status to Halted.
Definition: thread_context.cc:105
gem5::o3::ThreadContext::clearArchRegs
void clearArchRegs() override
Resets all architectural registers to 0.
Definition: thread_context.cc:145
gem5::o3::ThreadContext::copyArchRegs
void copyArchRegs(gem5::ThreadContext *tc) override
Copies the architectural registers from another TC into this TC.
Definition: thread_context.cc:136
gem5::o3::ThreadContext::readLastSuspend
Tick readLastSuspend() override
Reads the last tick that this thread was suspended on.
Definition: thread_context.cc:130
gem5::ThreadState::status
Status status() const
Returns the status of this thread.
Definition: thread_state.hh:80
gem5::ThreadContext::Halting
@ Halting
Trying to exit and waiting for an event to completely exit.
Definition: thread_context.hh:111
gem5::o3::CPU::setArchReg
void setArchReg(const RegId &reg, RegVal val, ThreadID tid)
Definition: cpu.cc:1080
gem5::o3::CPU::isDraining
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:235
gem5::o3::ThreadContext::pcState
const PCStateBase & pcState() const override
Reads this thread's PC state.
Definition: thread_context.hh:180
thread_context.hh
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::o3::ThreadContext::cpu
CPU * cpu
Pointer to the CPU.
Definition: thread_context.hh:71
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::o3::ThreadContext::pcStateNoRecord
void pcStateNoRecord(const PCStateBase &val) override
Definition: thread_context.cc:191
gem5::o3::CPU::isa
std::vector< BaseISA * > isa
Definition: cpu.hh:444
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:497
gem5::o3::CPU::getArchReg
RegVal getArchReg(const RegId &reg, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1056
gem5::o3::ThreadContext::readLastActivate
Tick readLastActivate() override
Reads the last tick that this thread was activated on.
Definition: thread_context.cc:124
gem5::o3::ThreadState::trapPending
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition: thread_state.hh:89
gem5::o3::ThreadContext::setMiscReg
void setMiscReg(RegIndex misc_reg, RegVal val) override
Sets a misc.
Definition: thread_context.cc:207
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:92

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