dramsys_wrapper.cc

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/*
 * Copyright (c) 2022 Fraunhofer IESE
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#include "dramsys_wrapper.hh"
 
namespace gem5
{
 
namespace memory
{
 
DRAMSysWrapper::DRAMSysWrapper(
    sc_core::sc_module_name name,
    DRAMSysConfiguration::Configuration const &config,
    bool recordable,
    AddrRange range) :
    sc_core::sc_module(name),
    dramsys(instantiateDRAMSys(recordable, config)),
    range(range)
{
    tSocket.register_nb_transport_fw(this, &DRAMSysWrapper::nb_transport_fw);
    tSocket.register_transport_dbg(this, &DRAMSysWrapper::transport_dbg);
    iSocket.register_nb_transport_bw(this, &DRAMSysWrapper::nb_transport_bw);
    iSocket.bind(dramsys->tSocket);
 
    // Register a callback to compensate for the destructor not
    // being called.
    registerExitCallback(
        [this]()
        {
            // Workaround for BUG GEM5-1233
            sc_gem5::Kernel::stop();
        });
}
 
std::shared_ptr<::DRAMSys>
DRAMSysWrapper::instantiateDRAMSys(
    bool recordable,
    DRAMSysConfiguration::Configuration const &config)
{
    return recordable
        ? std::make_shared<::DRAMSysRecordable>("DRAMSys", config)
        : std::make_shared<::DRAMSys>("DRAMSys", config);
}
 
tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_fw(
    tlm::tlm_generic_payload &payload,
    tlm::tlm_phase &phase,
    sc_core::sc_time &fwDelay)
{
    // Subtract base address offset
    payload.set_address(payload.get_address() - range.start());
 
    return iSocket->nb_transport_fw(payload, phase, fwDelay);
}
 
tlm::tlm_sync_enum DRAMSysWrapper::nb_transport_bw(
    tlm::tlm_generic_payload &payload,
    tlm::tlm_phase &phase,
    sc_core::sc_time &bwDelay)
{
    return tSocket->nb_transport_bw(payload, phase, bwDelay);
}
 
unsigned int DRAMSysWrapper::transport_dbg(tlm::tlm_generic_payload &trans)
{
    // Subtract base address offset
    trans.set_address(trans.get_address() - range.start());
 
    return iSocket->transport_dbg(trans);
}
 
} // namespace memory
} // namespace gem5