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dramsys_wrapper.hh
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28 
29 #ifndef __MEM_DRAMSYS_WRAPPER_HH__
30 #define __MEM_DRAMSYS_WRAPPER_HH__
31 
32 #include <iostream>
33 #include <memory>
34 
35 #include "DRAMSysConfiguration.h"
36 #include "mem/abstract_mem.hh"
37 #include "params/DRAMSys.hh"
38 #include "sim/core.hh"
39 #include "simulation/DRAMSysRecordable.h"
40 #include "systemc/core/kernel.hh"
42 #include "systemc/ext/systemc"
43 #include "systemc/ext/tlm"
46 
47 namespace gem5
48 {
49 
50 namespace memory
51 {
52 
54 {
55  friend class DRAMSys;
56 
57  public:
60  DRAMSysConfiguration::Configuration const &config,
61  bool recordable,
63 
64  private:
65  static std::shared_ptr<::DRAMSys>
66  instantiateDRAMSys(bool recordable,
67  DRAMSysConfiguration::Configuration const &config);
68 
70  tlm::tlm_phase &phase,
71  sc_core::sc_time &fwDelay);
72 
74  tlm::tlm_phase &phase,
75  sc_core::sc_time &bwDelay);
76 
77  unsigned int transport_dbg(tlm::tlm_generic_payload &trans);
78 
81 
82  std::shared_ptr<::DRAMSys> dramsys;
83 
85 };
86 
87 } // namespace memory
88 } // namespace gem5
89 
90 #endif // __MEM_DRAMSYS_WRAPPER_HH__
gem5::memory::DRAMSysWrapper::range
AddrRange range
Definition: dramsys_wrapper.hh:84
kernel.hh
sc_core::sc_module
Definition: sc_module.hh:101
tlm::tlm_phase
Definition: phase.hh:47
memory
Definition: mem.h:38
abstract_mem.hh
sc_module_name.hh
gem5::memory::DRAMSysWrapper::tSocket
tlm_utils::simple_target_socket< DRAMSysWrapper > tSocket
Definition: dramsys_wrapper.hh:80
gem5::memory::DRAMSysWrapper::dramsys
std::shared_ptr<::DRAMSys > dramsys
Definition: dramsys_wrapper.hh:82
gem5::memory::DRAMSysWrapper::SC_HAS_PROCESS
SC_HAS_PROCESS(DRAMSysWrapper)
gem5::memory::DRAMSysWrapper::DRAMSysWrapper
DRAMSysWrapper(sc_core::sc_module_name name, DRAMSysConfiguration::Configuration const &config, bool recordable, AddrRange range)
Definition: dramsys_wrapper.cc:37
sc_core::sc_time
Definition: sc_time.hh:49
tlm_utils::simple_initiator_socket
Definition: simple_initiator_socket.h:173
sc_core::sc_module_name
Definition: sc_module_name.hh:41
gem5::memory::DRAMSysWrapper::transport_dbg
unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
Definition: dramsys_wrapper.cc:90
gem5::memory::DRAMSysWrapper
Definition: dramsys_wrapper.hh:53
gem5::memory::DRAMSysWrapper::nb_transport_bw
tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &bwDelay)
Definition: dramsys_wrapper.cc:82
tlm_utils::simple_target_socket
Definition: simple_target_socket.h:605
tlm::tlm_generic_payload
Definition: gp.hh:133
gem5::memory::DRAMSys
Definition: dramsys.hh:43
core.hh
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
gem5::memory::DRAMSysWrapper::nb_transport_fw
tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload &payload, tlm::tlm_phase &phase, sc_core::sc_time &fwDelay)
Definition: dramsys_wrapper.cc:71
tlm::tlm_sync_enum
tlm_sync_enum
Definition: fw_bw_ifs.hh:48
tlm_port_wrapper.hh
gem5::memory::DRAMSysWrapper::iSocket
tlm_utils::simple_initiator_socket< DRAMSysWrapper > iSocket
Definition: dramsys_wrapper.hh:79
gem5::AddrRange
The AddrRange class encapsulates an address range, and supports a number of tests to check if two ran...
Definition: addr_range.hh:81
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
simple_target_socket.h
gem5::memory::DRAMSysWrapper::instantiateDRAMSys
static std::shared_ptr<::DRAMSys > instantiateDRAMSys(bool recordable, DRAMSysConfiguration::Configuration const &config)
Definition: dramsys_wrapper.cc:62

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