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exported_clock_rate_control.hh
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27 
28 #ifndef __ARCH_ARM_FASTMODEL_PROTOCOL_EXPORTED_CLOCK_RATE_CONTROL_HH__
29 #define __ARCH_ARM_FASTMODEL_PROTOCOL_EXPORTED_CLOCK_RATE_CONTROL_HH__
30 
31 #include <string>
32 #include <systemc>
33 #include <tlm>
34 
35 namespace gem5
36 {
37 
38 // This protocol is an exportable version of the clock rate protocol native to
39 // fast models. It's identical to the original, except it has some extra info
40 // which lets it be exported into systemc.
41 
43 
45 {
46  public:
47  virtual ~ClockRateControlFwIf() {}
48  virtual void set_mul_div(uint64_t mul, uint64_t div) = 0;
49 };
50 
52 {
53  public:
54  virtual ~ClockRateControlBwIf() {}
55 };
56 
58 {
59  public:
60  ClockRateControlSlaveBase(const std::string &name) {}
61 };
62 
64  public tlm::tlm_base_initiator_socket<64, ClockRateControlFwIf,
65  ClockRateControlBwIf>
66 {
67  private:
69 
70  public:
73 
74  using Base::bind;
75  using Base::operator();
76 
78  {
79  get_base_export().bind(dummyBwIf);
80  }
82  {
83  get_base_export().bind(dummyBwIf);
84  }
85 
86  const char *
87  kind() const override
88  {
89  return "ClockRateControlInitiatorSocket";
90  }
91 
92  std::type_index
93  get_protocol_types() const override
94  {
95  return typeid(ClockRateControlDummyProtocolType);
96  }
97 };
98 
100  public tlm::tlm_base_target_socket<64, ClockRateControlFwIf,
101  ClockRateControlBwIf>
102 {
103  public:
106 
107  using Base::bind;
108  using Base::operator();
109 
110  using Base::Base;
111 
112  const char *
113  kind() const override
114  {
115  return "ClockRateControlInitiatorSocket";
116  }
117 
118  std::type_index
119  get_protocol_types() const override
120  {
121  return typeid(ClockRateControlDummyProtocolType);
122  }
123 };
124 
125 } // namespace gem5
126 
127 #endif // __ARCH_ARM_FASTMODEL_PROTOCOL_EXPORTED_CLOCK_RATE_CONTROL_HH__
gem5::ClockRateControlInitiatorSocket::Base
tlm::tlm_base_initiator_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf > Base
Definition: exported_clock_rate_control.hh:72
gem5::ClockRateControlInitiatorSocket::kind
const char * kind() const override
Definition: exported_clock_rate_control.hh:87
gem5::ClockRateControlTargetSocket
Definition: exported_clock_rate_control.hh:99
gem5::RiscvISA::div
T div(T rs1, T rs2)
Definition: utility.hh:195
gem5::ClockRateControlFwIf
Definition: exported_clock_rate_control.hh:44
gem5::ClockRateControlTargetSocket::kind
const char * kind() const override
Definition: exported_clock_rate_control.hh:113
sc_core::sc_interface
Definition: sc_interface.hh:37
tlm::tlm_base_target_socket
Definition: initiator_socket.hh:69
gem5::ClockRateControlBwIf
Definition: exported_clock_rate_control.hh:51
gem5::ClockRateControlDummyProtocolType
Definition: exported_clock_rate_control.hh:42
gem5::ClockRateControlInitiatorSocket::get_protocol_types
std::type_index get_protocol_types() const override
Definition: exported_clock_rate_control.hh:93
gem5::ClockRateControlInitiatorSocket
Definition: exported_clock_rate_control.hh:63
gem5::ClockRateControlFwIf::set_mul_div
virtual void set_mul_div(uint64_t mul, uint64_t div)=0
gem5::ClockRateControlTargetSocket::get_protocol_types
std::type_index get_protocol_types() const override
Definition: exported_clock_rate_control.hh:119
gem5::auxv::Base
@ Base
Definition: aux_vector.hh:74
tlm::tlm_base_initiator_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf >::get_base_export
virtual sc_core::sc_export< ClockRateControlBwIf > & get_base_export()
Definition: initiator_socket.hh:184
gem5::ClockRateControlBwIf::~ClockRateControlBwIf
virtual ~ClockRateControlBwIf()
Definition: exported_clock_rate_control.hh:54
gem5::ClockRateControlTargetSocket::Base
tlm::tlm_base_target_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf > Base
Definition: exported_clock_rate_control.hh:105
gem5::ClockRateControlInitiatorSocket::ClockRateControlInitiatorSocket
ClockRateControlInitiatorSocket(const char *name)
Definition: exported_clock_rate_control.hh:81
name
const std::string & name()
Definition: trace.cc:48
gem5::ClockRateControlInitiatorSocket::ClockRateControlInitiatorSocket
ClockRateControlInitiatorSocket()
Definition: exported_clock_rate_control.hh:77
gem5::ClockRateControlFwIf::~ClockRateControlFwIf
virtual ~ClockRateControlFwIf()
Definition: exported_clock_rate_control.hh:47
tlm::tlm_base_initiator_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf >::bind
virtual void bind(base_target_socket_type &s)
Definition: initiator_socket.hh:121
sc_core::sc_object::name
const char * name() const
Definition: sc_object.cc:44
gem5::ClockRateControlSlaveBase::ClockRateControlSlaveBase
ClockRateControlSlaveBase(const std::string &name)
Definition: exported_clock_rate_control.hh:60
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
tlm::tlm_base_target_socket< 64, ClockRateControlFwIf, ClockRateControlBwIf >::bind
virtual void bind(base_initiator_socket_type &s)
Definition: target_socket.hh:112
gem5::ClockRateControlSlaveBase
Definition: exported_clock_rate_control.hh:57
tlm::tlm_base_initiator_socket
Definition: initiator_socket.hh:78
gem5::ClockRateControlInitiatorSocket::dummyBwIf
ClockRateControlBwIf dummyBwIf
Definition: exported_clock_rate_control.hh:68

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