gem5::RiscvISA Namespace Reference

Namespaces
	float_reg
	int_reg

Classes
class	AddressFault
class	AtomicGenericOp
	A generic atomic op class. More...
class	AtomicMemOp
class	AtomicMemOpMicro
class	BareMetal
class	BreakpointFault
class	BSOp
class	CompRegOp
	Base class for compressed operations that work only on registers. More...
struct	CSRMetadata
class	CSROp
	Base class for CSR operations. More...
class	Decoder
class	EmuLinux
class	FsLinux
class	IllegalFrmFault
class	IllegalInstFault
class	ImmOp
	Base class for operations with immediates (I is the type of immediate) More...
class	InstFault
class	InterruptFault
class	Interrupts
class	ISA
class	Load
class	LoadReserved
class	LoadReservedMicro
class	MemFenceMicro
class	MemInst
class	MmioVirtIO
class	MMU
class	NonMaskableInterruptFault
class	PCState
class	PseudoOp
struct	RegABI32
struct	RegABI64
class	RegOp
	Base class for operations that work only on registers. More...
class	RemoteGDB
class	Reset
class	RiscvFault
class	RiscvMacroInst
	Base class for all RISC-V Macroops. More...
class	RiscvMicroInst
	Base class for all RISC-V Microops. More...
class	RiscvStaticInst
	Base class for all RISC-V static instructions. More...
class	SEWorkload
class	StackTrace
class	Store
class	StoreCond
class	StoreCondMicro
class	SyscallFault
class	SystemOp
	Base class for system operations. More...
class	TLB
struct	TlbEntry
class	UnimplementedFault
class	Unknown
	Static instruction class for unknown (illegal) instructions. More...
class	UnknownInstFault
class	Walker

Typedefs
typedef Trie< Addr, TlbEntry >	TlbEntryTrie
using	RiscvType = enums::RiscvType
using	freg_t = float64_t
typedef uint32_t	MachInst

Enumerations
enum	FloatException : uint64_t {   FloatInexact = 0x1, FloatUnderflow = 0x2, FloatOverflow = 0x4, FloatDivZero = 0x8,   FloatInvalid = 0x10 }
enum	ExceptionCode : uint64_t {   INST_ADDR_MISALIGNED = 0, INST_ACCESS = 1, INST_ILLEGAL = 2, BREAKPOINT = 3,   LOAD_ADDR_MISALIGNED = 4, LOAD_ACCESS = 5, STORE_ADDR_MISALIGNED = 6, AMO_ADDR_MISALIGNED = 6,   STORE_ACCESS = 7, AMO_ACCESS = 7, ECALL_USER = 8, ECALL_SUPER = 9,   ECALL_MACHINE = 11, INST_PAGE = 12, LOAD_PAGE = 13, STORE_PAGE = 15,   AMO_PAGE = 15, INT_SOFTWARE_USER = 0, INT_SOFTWARE_SUPER = 1, INT_SOFTWARE_MACHINE = 3,   INT_TIMER_USER = 4, INT_TIMER_SUPER = 5, INT_TIMER_MACHINE = 7, INT_EXT_USER = 8,   INT_EXT_SUPER = 9, INT_EXT_MACHINE = 11, NumInterruptTypes, INT_NMI = NumInterruptTypes }
enum	FaultType { FaultType::INTERRUPT, FaultType::NON_MASKABLE_INTERRUPT, FaultType::OTHERS }
enum	PrivilegeMode { PRV_U = 0, PRV_S = 1, PRV_M = 3 }
enum	FPUStatus { OFF = 0, INITIAL = 1, CLEAN = 2, DIRTY = 3 }
enum	MiscRegIndex {   MISCREG_PRV = 0, MISCREG_ISA, MISCREG_VENDORID, MISCREG_ARCHID,   MISCREG_IMPID, MISCREG_HARTID, MISCREG_STATUS, MISCREG_IP,   MISCREG_IE, MISCREG_CYCLE, MISCREG_TIME, MISCREG_INSTRET,   MISCREG_HPMCOUNTER03, MISCREG_HPMCOUNTER04, MISCREG_HPMCOUNTER05, MISCREG_HPMCOUNTER06,   MISCREG_HPMCOUNTER07, MISCREG_HPMCOUNTER08, MISCREG_HPMCOUNTER09, MISCREG_HPMCOUNTER10,   MISCREG_HPMCOUNTER11, MISCREG_HPMCOUNTER12, MISCREG_HPMCOUNTER13, MISCREG_HPMCOUNTER14,   MISCREG_HPMCOUNTER15, MISCREG_HPMCOUNTER16, MISCREG_HPMCOUNTER17, MISCREG_HPMCOUNTER18,   MISCREG_HPMCOUNTER19, MISCREG_HPMCOUNTER20, MISCREG_HPMCOUNTER21, MISCREG_HPMCOUNTER22,   MISCREG_HPMCOUNTER23, MISCREG_HPMCOUNTER24, MISCREG_HPMCOUNTER25, MISCREG_HPMCOUNTER26,   MISCREG_HPMCOUNTER27, MISCREG_HPMCOUNTER28, MISCREG_HPMCOUNTER29, MISCREG_HPMCOUNTER30,   MISCREG_HPMCOUNTER31, MISCREG_HPMEVENT03, MISCREG_HPMEVENT04, MISCREG_HPMEVENT05,   MISCREG_HPMEVENT06, MISCREG_HPMEVENT07, MISCREG_HPMEVENT08, MISCREG_HPMEVENT09,   MISCREG_HPMEVENT10, MISCREG_HPMEVENT11, MISCREG_HPMEVENT12, MISCREG_HPMEVENT13,   MISCREG_HPMEVENT14, MISCREG_HPMEVENT15, MISCREG_HPMEVENT16, MISCREG_HPMEVENT17,   MISCREG_HPMEVENT18, MISCREG_HPMEVENT19, MISCREG_HPMEVENT20, MISCREG_HPMEVENT21,   MISCREG_HPMEVENT22, MISCREG_HPMEVENT23, MISCREG_HPMEVENT24, MISCREG_HPMEVENT25,   MISCREG_HPMEVENT26, MISCREG_HPMEVENT27, MISCREG_HPMEVENT28, MISCREG_HPMEVENT29,   MISCREG_HPMEVENT30, MISCREG_HPMEVENT31, MISCREG_TSELECT, MISCREG_TDATA1,   MISCREG_TDATA2, MISCREG_TDATA3, MISCREG_DCSR, MISCREG_DPC,   MISCREG_DSCRATCH, MISCREG_MEDELEG, MISCREG_MIDELEG, MISCREG_MTVEC,   MISCREG_MCOUNTEREN, MISCREG_MSCRATCH, MISCREG_MEPC, MISCREG_MCAUSE,   MISCREG_MTVAL, MISCREG_PMPCFG0, MISCREG_PMPCFG1, MISCREG_PMPCFG2,   MISCREG_PMPCFG3, MISCREG_PMPADDR00, MISCREG_PMPADDR01, MISCREG_PMPADDR02,   MISCREG_PMPADDR03, MISCREG_PMPADDR04, MISCREG_PMPADDR05, MISCREG_PMPADDR06,   MISCREG_PMPADDR07, MISCREG_PMPADDR08, MISCREG_PMPADDR09, MISCREG_PMPADDR10,   MISCREG_PMPADDR11, MISCREG_PMPADDR12, MISCREG_PMPADDR13, MISCREG_PMPADDR14,   MISCREG_PMPADDR15, MISCREG_SEDELEG, MISCREG_SIDELEG, MISCREG_STVEC,   MISCREG_SCOUNTEREN, MISCREG_SSCRATCH, MISCREG_SEPC, MISCREG_SCAUSE,   MISCREG_STVAL, MISCREG_SATP, MISCREG_UTVEC, MISCREG_USCRATCH,   MISCREG_UEPC, MISCREG_UCAUSE, MISCREG_UTVAL, MISCREG_FFLAGS,   MISCREG_FRM, MISCREG_NMIVEC, MISCREG_NMIE, MISCREG_NMIP,   MISCREG_MSTATUSH, MISCREG_CYCLEH, MISCREG_TIMEH, MISCREG_INSTRETH,   MISCREG_HPMCOUNTER03H, MISCREG_HPMCOUNTER04H, MISCREG_HPMCOUNTER05H, MISCREG_HPMCOUNTER06H,   MISCREG_HPMCOUNTER07H, MISCREG_HPMCOUNTER08H, MISCREG_HPMCOUNTER09H, MISCREG_HPMCOUNTER10H,   MISCREG_HPMCOUNTER11H, MISCREG_HPMCOUNTER12H, MISCREG_HPMCOUNTER13H, MISCREG_HPMCOUNTER14H,   MISCREG_HPMCOUNTER15H, MISCREG_HPMCOUNTER16H, MISCREG_HPMCOUNTER17H, MISCREG_HPMCOUNTER18H,   MISCREG_HPMCOUNTER19H, MISCREG_HPMCOUNTER20H, MISCREG_HPMCOUNTER21H, MISCREG_HPMCOUNTER22H,   MISCREG_HPMCOUNTER23H, MISCREG_HPMCOUNTER24H, MISCREG_HPMCOUNTER25H, MISCREG_HPMCOUNTER26H,   MISCREG_HPMCOUNTER27H, MISCREG_HPMCOUNTER28H, MISCREG_HPMCOUNTER29H, MISCREG_HPMCOUNTER30H,   MISCREG_HPMCOUNTER31H, NUM_MISCREGS }
enum	CSRIndex {   CSR_USTATUS = 0x000, CSR_UIE = 0x004, CSR_UTVEC = 0x005, CSR_USCRATCH = 0x040,   CSR_UEPC = 0x041, CSR_UCAUSE = 0x042, CSR_UTVAL = 0x043, CSR_UIP = 0x044,   CSR_FFLAGS = 0x001, CSR_FRM = 0x002, CSR_FCSR = 0x003, CSR_CYCLE = 0xC00,   CSR_TIME = 0xC01, CSR_INSTRET = 0xC02, CSR_HPMCOUNTER03 = 0xC03, CSR_HPMCOUNTER04 = 0xC04,   CSR_HPMCOUNTER05 = 0xC05, CSR_HPMCOUNTER06 = 0xC06, CSR_HPMCOUNTER07 = 0xC07, CSR_HPMCOUNTER08 = 0xC08,   CSR_HPMCOUNTER09 = 0xC09, CSR_HPMCOUNTER10 = 0xC0A, CSR_HPMCOUNTER11 = 0xC0B, CSR_HPMCOUNTER12 = 0xC0C,   CSR_HPMCOUNTER13 = 0xC0D, CSR_HPMCOUNTER14 = 0xC0E, CSR_HPMCOUNTER15 = 0xC0F, CSR_HPMCOUNTER16 = 0xC10,   CSR_HPMCOUNTER17 = 0xC11, CSR_HPMCOUNTER18 = 0xC12, CSR_HPMCOUNTER19 = 0xC13, CSR_HPMCOUNTER20 = 0xC14,   CSR_HPMCOUNTER21 = 0xC15, CSR_HPMCOUNTER22 = 0xC16, CSR_HPMCOUNTER23 = 0xC17, CSR_HPMCOUNTER24 = 0xC18,   CSR_HPMCOUNTER25 = 0xC19, CSR_HPMCOUNTER26 = 0xC1A, CSR_HPMCOUNTER27 = 0xC1B, CSR_HPMCOUNTER28 = 0xC1C,   CSR_HPMCOUNTER29 = 0xC1D, CSR_HPMCOUNTER30 = 0xC1E, CSR_HPMCOUNTER31 = 0xC1F, CSR_CYCLEH = 0xC80,   CSR_TIMEH = 0xC81, CSR_INSTRETH = 0xC82, CSR_HPMCOUNTER03H = 0xC83, CSR_HPMCOUNTER04H = 0xC84,   CSR_HPMCOUNTER05H = 0xC85, CSR_HPMCOUNTER06H = 0xC86, CSR_HPMCOUNTER07H = 0xC87, CSR_HPMCOUNTER08H = 0xC88,   CSR_HPMCOUNTER09H = 0xC89, CSR_HPMCOUNTER10H = 0xC8A, CSR_HPMCOUNTER11H = 0xC8B, CSR_HPMCOUNTER12H = 0xC8C,   CSR_HPMCOUNTER13H = 0xC8D, CSR_HPMCOUNTER14H = 0xC8E, CSR_HPMCOUNTER15H = 0xC8F, CSR_HPMCOUNTER16H = 0xC90,   CSR_HPMCOUNTER17H = 0xC91, CSR_HPMCOUNTER18H = 0xC92, CSR_HPMCOUNTER19H = 0xC93, CSR_HPMCOUNTER20H = 0xC94,   CSR_HPMCOUNTER21H = 0xC95, CSR_HPMCOUNTER22H = 0xC96, CSR_HPMCOUNTER23H = 0xC97, CSR_HPMCOUNTER24H = 0xC98,   CSR_HPMCOUNTER25H = 0xC99, CSR_HPMCOUNTER26H = 0xC9A, CSR_HPMCOUNTER27H = 0xC9B, CSR_HPMCOUNTER28H = 0xC9C,   CSR_HPMCOUNTER29H = 0xC9D, CSR_HPMCOUNTER30H = 0xC9E, CSR_HPMCOUNTER31H = 0xC9F, CSR_SSTATUS = 0x100,   CSR_SEDELEG = 0x102, CSR_SIDELEG = 0x103, CSR_SIE = 0x104, CSR_STVEC = 0x105,   CSR_SCOUNTEREN = 0x106, CSR_SSCRATCH = 0x140, CSR_SEPC = 0x141, CSR_SCAUSE = 0x142,   CSR_STVAL = 0x143, CSR_SIP = 0x144, CSR_SATP = 0x180, CSR_MVENDORID = 0xF11,   CSR_MARCHID = 0xF12, CSR_MIMPID = 0xF13, CSR_MHARTID = 0xF14, CSR_MSTATUS = 0x300,   CSR_MISA = 0x301, CSR_MEDELEG = 0x302, CSR_MIDELEG = 0x303, CSR_MIE = 0x304,   CSR_MTVEC = 0x305, CSR_MCOUNTEREN = 0x306, CSR_MSTATUSH = 0x310, CSR_MSCRATCH = 0x340,   CSR_MEPC = 0x341, CSR_MCAUSE = 0x342, CSR_MTVAL = 0x343, CSR_MIP = 0x344,   CSR_PMPCFG0 = 0x3A0, CSR_PMPCFG1 = 0x3A1, CSR_PMPCFG2 = 0x3A2, CSR_PMPCFG3 = 0x3A3,   CSR_PMPADDR00 = 0x3B0, CSR_PMPADDR01 = 0x3B1, CSR_PMPADDR02 = 0x3B2, CSR_PMPADDR03 = 0x3B3,   CSR_PMPADDR04 = 0x3B4, CSR_PMPADDR05 = 0x3B5, CSR_PMPADDR06 = 0x3B6, CSR_PMPADDR07 = 0x3B7,   CSR_PMPADDR08 = 0x3B8, CSR_PMPADDR09 = 0x3B9, CSR_PMPADDR10 = 0x3BA, CSR_PMPADDR11 = 0x3BB,   CSR_PMPADDR12 = 0x3BC, CSR_PMPADDR13 = 0x3BD, CSR_PMPADDR14 = 0x3BE, CSR_PMPADDR15 = 0x3BF,   CSR_MCYCLE = 0xB00, CSR_MINSTRET = 0xB02, CSR_MHPMCOUNTER03 = 0xB03, CSR_MHPMCOUNTER04 = 0xB04,   CSR_MHPMCOUNTER05 = 0xB05, CSR_MHPMCOUNTER06 = 0xB06, CSR_MHPMCOUNTER07 = 0xB07, CSR_MHPMCOUNTER08 = 0xB08,   CSR_MHPMCOUNTER09 = 0xB09, CSR_MHPMCOUNTER10 = 0xB0A, CSR_MHPMCOUNTER11 = 0xB0B, CSR_MHPMCOUNTER12 = 0xB0C,   CSR_MHPMCOUNTER13 = 0xB0D, CSR_MHPMCOUNTER14 = 0xB0E, CSR_MHPMCOUNTER15 = 0xB0F, CSR_MHPMCOUNTER16 = 0xB10,   CSR_MHPMCOUNTER17 = 0xB11, CSR_MHPMCOUNTER18 = 0xB12, CSR_MHPMCOUNTER19 = 0xB13, CSR_MHPMCOUNTER20 = 0xB14,   CSR_MHPMCOUNTER21 = 0xB15, CSR_MHPMCOUNTER22 = 0xB16, CSR_MHPMCOUNTER23 = 0xB17, CSR_MHPMCOUNTER24 = 0xB18,   CSR_MHPMCOUNTER25 = 0xB19, CSR_MHPMCOUNTER26 = 0xB1A, CSR_MHPMCOUNTER27 = 0xB1B, CSR_MHPMCOUNTER28 = 0xB1C,   CSR_MHPMCOUNTER29 = 0xB1D, CSR_MHPMCOUNTER30 = 0xB1E, CSR_MHPMCOUNTER31 = 0xB1F, CSR_MCYCLEH = 0xB80,   CSR_MINSTRETH = 0xB82, CSR_MHPMCOUNTER03H = 0xB83, CSR_MHPMCOUNTER04H = 0xB84, CSR_MHPMCOUNTER05H = 0xB85,   CSR_MHPMCOUNTER06H = 0xB86, CSR_MHPMCOUNTER07H = 0xB87, CSR_MHPMCOUNTER08H = 0xB88, CSR_MHPMCOUNTER09H = 0xB89,   CSR_MHPMCOUNTER10H = 0xB8A, CSR_MHPMCOUNTER11H = 0xB8B, CSR_MHPMCOUNTER12H = 0xB8C, CSR_MHPMCOUNTER13H = 0xB8D,   CSR_MHPMCOUNTER14H = 0xB8E, CSR_MHPMCOUNTER15H = 0xB8F, CSR_MHPMCOUNTER16H = 0xB90, CSR_MHPMCOUNTER17H = 0xB91,   CSR_MHPMCOUNTER18H = 0xB92, CSR_MHPMCOUNTER19H = 0xB93, CSR_MHPMCOUNTER20H = 0xB94, CSR_MHPMCOUNTER21H = 0xB95,   CSR_MHPMCOUNTER22H = 0xB96, CSR_MHPMCOUNTER23H = 0xB97, CSR_MHPMCOUNTER24H = 0xB98, CSR_MHPMCOUNTER25H = 0xB99,   CSR_MHPMCOUNTER26H = 0xB9A, CSR_MHPMCOUNTER27H = 0xB9B, CSR_MHPMCOUNTER28H = 0xB9C, CSR_MHPMCOUNTER29H = 0xB9D,   CSR_MHPMCOUNTER30H = 0xB9E, CSR_MHPMCOUNTER31H = 0xB9F, CSR_MHPMEVENT03 = 0x323, CSR_MHPMEVENT04 = 0x324,   CSR_MHPMEVENT05 = 0x325, CSR_MHPMEVENT06 = 0x326, CSR_MHPMEVENT07 = 0x327, CSR_MHPMEVENT08 = 0x328,   CSR_MHPMEVENT09 = 0x329, CSR_MHPMEVENT10 = 0x32A, CSR_MHPMEVENT11 = 0x32B, CSR_MHPMEVENT12 = 0x32C,   CSR_MHPMEVENT13 = 0x32D, CSR_MHPMEVENT14 = 0x32E, CSR_MHPMEVENT15 = 0x32F, CSR_MHPMEVENT16 = 0x330,   CSR_MHPMEVENT17 = 0x331, CSR_MHPMEVENT18 = 0x332, CSR_MHPMEVENT19 = 0x333, CSR_MHPMEVENT20 = 0x334,   CSR_MHPMEVENT21 = 0x335, CSR_MHPMEVENT22 = 0x336, CSR_MHPMEVENT23 = 0x337, CSR_MHPMEVENT24 = 0x338,   CSR_MHPMEVENT25 = 0x339, CSR_MHPMEVENT26 = 0x33A, CSR_MHPMEVENT27 = 0x33B, CSR_MHPMEVENT28 = 0x33C,   CSR_MHPMEVENT29 = 0x33D, CSR_MHPMEVENT30 = 0x33E, CSR_MHPMEVENT31 = 0x33F, CSR_TSELECT = 0x7A0,   CSR_TDATA1 = 0x7A1, CSR_TDATA2 = 0x7A2, CSR_TDATA3 = 0x7A3, CSR_DCSR = 0x7B0,   CSR_DPC = 0x7B1, CSR_DSCRATCH = 0x7B2 }

Functions
static SyscallReturn	unameFunc64 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler. More...
static SyscallReturn	unameFunc32 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler. More...
	BitUnion64 (SATP) Bitfield< 63
	EndBitUnion (SATP) enum AddrXlateMode
	BitUnion64 (PTESv39) Bitfield< 53
	EndBitUnion (PTESv39) struct TlbEntry
	BitUnion32 (IndexReg) Bitfield< 31 > p
	EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
	EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
	EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
	EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
	EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
	EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
	EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
	EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
	EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
	EndSubBitUnion (cu) Bitfield< 27 > rp
	SubBitUnion (im, 15, 8) Bitfield< 15 > im7
	EndSubBitUnion (im) Bitfield< 7 > kx
	EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
	EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
	EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
	EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
	SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
	EndSubBitUnion (ip)
	EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
	EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
	EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
	EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
	EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
	EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
	EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
	EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
	EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
	EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
	EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
static constexpr uint16_t	unboxF16 (uint64_t v)
static constexpr uint32_t	unboxF32 (uint64_t v)
static constexpr uint64_t	boxF16 (uint16_t v)
static constexpr uint64_t	boxF32 (uint32_t v)
static constexpr float16_t	f16 (uint16_t v)
static constexpr float32_t	f32 (uint32_t v)
static constexpr float64_t	f64 (uint64_t v)
static constexpr float16_t	f16 (freg_t r)
static constexpr float32_t	f32 (freg_t r)
static constexpr float64_t	f64 (freg_t r)
static constexpr freg_t	freg (float16_t f)
static constexpr freg_t	freg (float32_t f)
static constexpr freg_t	freg (float64_t f)
static constexpr freg_t	freg (uint_fast64_t f)
constexpr RegClass	floatRegClass (FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs)
constexpr RegClass	intRegClass (IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)
constexpr RegClass	miscRegClass (MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs)
template<typename... T>
constexpr uint64_t	rvTypeFlags (T... args)
	BitUnion64 (STATUS) Bitfield< 63 > rv64_sd
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org. More...
	EndBitUnion (STATUS) BitUnion64(MISA) Bitfield< 63
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, v1.11 and v1.12 in Figure 3.1, accessible at www.riscv.org. More...
	EndBitUnion (MISA) BitUnion64(INTERRUPT) Bitfield< 11 > mei
	These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. More...
	EndBitUnion (INTERRUPT) const off_t MXL_OFFSETS[enums
int32_t	_rvk_emu_sll_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_srl_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_sll_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_srl_64 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_rol_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_ror_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_rol_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_ror_64 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_grev_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_grev_64 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_brev8_32 (int32_t rs1)
int64_t	_rvk_emu_brev8_64 (int64_t rs1)
uint32_t	_rvk_emu_shuffle32_stage (uint32_t src, uint32_t maskL, uint32_t maskR, int N)
int32_t	_rvk_emu_shfl_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_unshfl_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_zip_32 (int32_t rs1)
int32_t	_rvk_emu_unzip_32 (int32_t rs1)
int32_t	_rvk_emu_clmul_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_clmulh_32 (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_clmul_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_clmulh_64 (int64_t rs1, int64_t rs2)
uint32_t	_rvk_emu_xperm32 (uint32_t rs1, uint32_t rs2, int sz_log2)
int32_t	_rvk_emu_xperm4_32 (int32_t rs1, int32_t rs2)
int32_t	_rvk_emu_xperm8_32 (int32_t rs1, int32_t rs2)
uint64_t	_rvk_emu_xperm64 (uint64_t rs1, uint64_t rs2, int sz_log2)
int64_t	_rvk_emu_xperm4_64 (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_xperm8_64 (int64_t rs1, int64_t rs2)
uint8_t	_rvk_emu_aes_xtime (uint8_t x)
uint32_t	_rvk_emu_aes_fwd_mc_8 (uint32_t x)
uint32_t	_rvk_emu_aes_fwd_mc_32 (uint32_t x)
uint32_t	_rvk_emu_aes_inv_mc_8 (uint32_t x)
uint32_t	_rvk_emu_aes_inv_mc_32 (uint32_t x)
int32_t	_rvk_emu_aes32dsi (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_aes32dsmi (int32_t rs1, int32_t rs2, uint8_t bs)
int64_t	_rvk_emu_aes64ds (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_aes64im (int64_t rs1)
int64_t	_rvk_emu_aes64dsm (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_aes64ks1i (int64_t rs1, int rnum)
int64_t	_rvk_emu_aes64ks2 (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_aes32esi (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_aes32esmi (int32_t rs1, int32_t rs2, uint8_t bs)
int64_t	_rvk_emu_aes64es (int64_t rs1, int64_t rs2)
int64_t	_rvk_emu_aes64esm (int64_t rs1, int64_t rs2)
int32_t	_rvk_emu_sha256sig0 (int32_t rs1)
int32_t	_rvk_emu_sha256sig1 (int32_t rs1)
int32_t	_rvk_emu_sha256sum0 (int32_t rs1)
int32_t	_rvk_emu_sha256sum1 (int32_t rs1)
static int32_t	_rvk_emu_sha512sig0h (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sig0l (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sig1h (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sig1l (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sum0r (int32_t rs1, int32_t rs2)
static int32_t	_rvk_emu_sha512sum1r (int32_t rs1, int32_t rs2)
int64_t	_rvk_emu_sha512sig0 (int64_t rs1)
int64_t	_rvk_emu_sha512sig1 (int64_t rs1)
int64_t	_rvk_emu_sha512sum0 (int64_t rs1)
int64_t	_rvk_emu_sha512sum1 (int64_t rs1)
int32_t	_rvk_emu_sm4ed (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_sm4ks (int32_t rs1, int32_t rs2, uint8_t bs)
int32_t	_rvk_emu_sm3p0 (int32_t rs1)
int32_t	_rvk_emu_sm3p1 (int32_t rs1)
	BitUnion64 (ExtMachInst) Bitfield< 63
	SubBitUnion (vtype8, 39, 32) Bitfield< 39 > vma
	EndSubBitUnion (vtype8) uint32_t instBits
template<typename T >
bool	isquietnan (T val)
template<>
bool	isquietnan< float > (float val)
template<>
bool	isquietnan< double > (double val)
template<typename T >
bool	issignalingnan (T val)
template<>
bool	issignalingnan< float > (float val)
template<>
bool	issignalingnan< double > (double val)
std::string	registerName (RegId reg)
uint32_t	mulhu_32 (uint32_t rs1, uint32_t rs2)
uint64_t	mulhu_64 (uint64_t rs1, uint64_t rs2)
int32_t	mulh_32 (int32_t rs1, int32_t rs2)
int64_t	mulh_64 (int64_t rs1, int64_t rs2)
int32_t	mulhsu_32 (int32_t rs1, uint32_t rs2)
int64_t	mulhsu_64 (int64_t rs1, uint64_t rs2)
template<typename T >
T	div (T rs1, T rs2)
template<typename T >
T	divu (T rs1, T rs2)
template<typename T >
T	rem (T rs1, T rs2)
template<typename T >
T	remu (T rs1, T rs2)

Variables
const std::array< const char *, NUM_MISCREGS >	MiscRegNames
const Addr	PageShift = 12
const Addr	PageBytes = 1ULL << PageShift
	mode
Bitfield< 59, 44 >	asid
Bitfield< 43, 0 >	ppn
const Addr	VADDR_BITS = 39
const Addr	LEVEL_BITS = 9
const Addr	LEVEL_MASK = (1 << LEVEL_BITS) - 1
Bitfield< 53, 28 >	ppn2
Bitfield< 27, 19 >	ppn1
Bitfield< 18, 10 >	ppn0
Bitfield< 7 >	d
Bitfield< 6 >	a
Bitfield< 5 >	g
Bitfield< 4 >	u
Bitfield< 3, 1 >	perm
Bitfield< 3 >	x
Bitfield< 2 >	w
Bitfield< 1 >	r
Bitfield< 0 >	v
constexpr enums::RiscvType	RV32 = enums::RV32
constexpr enums::RiscvType	RV64 = enums::RV64
Bitfield< 30, 0 >	index
	random
	fill
Bitfield< 29, 6 >	pfn
Bitfield< 5, 3 >	c
	pteBase
Bitfield< 22, 4 >	badVPN2
	mask
Bitfield< 12, 11 >	maskx
	aseUp
Bitfield< 29 >	elpa
Bitfield< 28 >	esp
Bitfield< 12, 8 >	aseDn
	wired
	impl
Bitfield< 39, 13 >	vpn2
Bitfield< 12, 11 >	vpn2x
Bitfield< 31 >	cu3
Bitfield< 30 >	cu2
Bitfield< 29 >	cu1
Bitfield< 28 >	cu0
Bitfield< 26 >	fr
Bitfield< 25 >	re
Bitfield< 24 >	mx
Bitfield< 23 >	px
Bitfield< 22 >	bev
Bitfield< 21 >	ts
Bitfield< 20 >	sr
Bitfield< 19 >	nmi
Bitfield< 15, 10 >	ipl
Bitfield< 14 >	im6
Bitfield< 13 >	im5
Bitfield< 12 >	im4
Bitfield< 11 >	im3
Bitfield< 10 >	im2
Bitfield< 9 >	im1
Bitfield< 8 >	im0
Bitfield< 6 >	sx
Bitfield< 5 >	ux
Bitfield< 4, 3 >	ksu
Bitfield< 4 >	um
Bitfield< 3 >	r0
Bitfield< 2 >	erl
Bitfield< 1 >	exl
Bitfield< 0 >	ie
	ipti
Bitfield< 28, 26 >	ippci
Bitfield< 9, 5 >	vs
	hss
Bitfield< 21, 18 >	eicss
Bitfield< 15, 12 >	ess
Bitfield< 9, 6 >	pss
Bitfield< 3, 0 >	css
	ssv7
Bitfield< 27, 24 >	ssv6
Bitfield< 23, 20 >	ssv5
Bitfield< 19, 16 >	ssv4
Bitfield< 15, 12 >	ssv3
Bitfield< 11, 8 >	ssv2
Bitfield< 7, 4 >	ssv1
Bitfield< 3, 0 >	ssv0
Bitfield< 30 >	ti
Bitfield< 29, 28 >	ce
Bitfield< 27 >	dc
Bitfield< 26 >	pci
Bitfield< 23 >	iv
Bitfield< 22 >	wp
Bitfield< 15, 10 >	ripl
Bitfield< 14 >	ip6
Bitfield< 13 >	ip5
Bitfield< 12 >	ip4
Bitfield< 11 >	ip3
Bitfield< 10 >	ip2
Bitfield< 9 >	ip1
Bitfield< 8 >	ip0
Bitfield< 6, 2 >	excCode
	coOp
Bitfield< 23, 16 >	coId
Bitfield< 15, 8 >	procId
Bitfield< 7, 0 >	rev
	exceptionBase
Bitfield< 9, 9 >	cpuNum
Bitfield< 30, 28 >	k23
Bitfield< 27, 25 >	ku
Bitfield< 15 >	be
Bitfield< 14, 13 >	at
Bitfield< 12, 10 >	ar
Bitfield< 9, 7 >	mt
Bitfield< 3 >	vi
Bitfield< 2, 0 >	k0
Bitfield< 30, 25 >	mmuSize
Bitfield< 24, 22 >	is
Bitfield< 21, 19 >	il
Bitfield< 18, 16 >	ia
Bitfield< 15, 13 >	ds
Bitfield< 12, 10 >	dl
Bitfield< 9, 7 >	da
Bitfield< 6 >	c2
Bitfield< 5 >	md
Bitfield< 4 >	pc
Bitfield< 3 >	wr
Bitfield< 2 >	ca
Bitfield< 1 >	ep
Bitfield< 0 >	fp
Bitfield< 30, 28 >	tu
Bitfield< 23, 20 >	tl
Bitfield< 19, 16 >	ta
Bitfield< 15, 12 >	su
Bitfield< 11, 8 >	ss
Bitfield< 7, 4 >	sl
Bitfield< 3, 0 >	sa
Bitfield< 10 >	dspp
Bitfield< 7 >	lpa
Bitfield< 6 >	veic
Bitfield< 5 >	vint
Bitfield< 4 >	sp
Bitfield< 1 >	sm
	vaddr
Bitfield< 2 >	i
Bitfield< 10, 5 >	event
Bitfield< 2 >	s
Bitfield< 1 >	k
Bitfield< 30 >	ec
Bitfield< 29 >	ed
Bitfield< 28 >	et
Bitfield< 27 >	es
Bitfield< 26 >	ee
Bitfield< 25 >	eb
	pTagLo
Bitfield< 7, 6 >	pState
Bitfield< 5 >	l
Bitfield< 0 >	p
constexpr auto &	ReturnAddrReg = int_reg::Ra
constexpr auto &	StackPointerReg = int_reg::Sp
constexpr auto &	ThreadPointerReg = int_reg::Tp
constexpr auto &	ReturnValueReg = int_reg::A0
constexpr auto &	AMOTempReg = int_reg::Ureg0
constexpr auto &	SyscallNumReg = int_reg::A7
constexpr RegId	ArgumentRegs []
const std::unordered_map< int, CSRMetadata >	CSRData
Bitfield< 35, 34 >	sxl
Bitfield< 33, 32 >	uxl
Bitfield< 31 >	rv32_sd
Bitfield< 22 >	tsr
Bitfield< 21 >	tw
Bitfield< 20 >	tvm
Bitfield< 19 >	mxr
Bitfield< 18 >	sum
Bitfield< 17 >	mprv
Bitfield< 16, 15 >	xs
Bitfield< 14, 13 >	fs
Bitfield< 12, 11 >	mpp
Bitfield< 8 >	spp
Bitfield< 7 >	mpie
Bitfield< 5 >	spie
Bitfield< 4 >	upie
Bitfield< 3 >	mie
Bitfield< 1 >	sie
Bitfield< 0 >	uie
	rv64_mxl
Bitfield< 31, 30 >	rv32_mxl
Bitfield< 23 >	rvx
Bitfield< 21 >	rvv
Bitfield< 20 >	rvu
Bitfield< 19 >	rvt
Bitfield< 18 >	rvs
Bitfield< 16 >	rvq
Bitfield< 15 >	rvp
Bitfield< 13 >	rvn
Bitfield< 12 >	rvm
Bitfield< 11 >	rvl
Bitfield< 10 >	rvk
Bitfield< 9 >	rvj
Bitfield< 8 >	rvi
Bitfield< 7 >	rvh
Bitfield< 6 >	rvg
Bitfield< 5 >	rvf
Bitfield< 4 >	rve
Bitfield< 3 >	rvd
Bitfield< 2 >	rvc
Bitfield< 1 >	rvb
Bitfield< 0 >	rva
Bitfield< 9 >	sei
Bitfield< 8 >	uei
Bitfield< 7 >	mti
Bitfield< 5 >	sti
Bitfield< 4 >	uti
Bitfield< 3 >	msi
Bitfield< 1 >	ssi
Bitfield< 0 >	usi
const off_t	MBE_OFFSET [enums::Num_RiscvType]
const off_t	SBE_OFFSET [enums::Num_RiscvType]
const off_t	SXL_OFFSET = 34
const off_t	UXL_OFFSET = 32
const off_t	FS_OFFSET = 13
const off_t	FRM_OFFSET = 5
const RegVal	ISA_MXL_MASKS [enums::Num_RiscvType]
const RegVal	ISA_EXT_MASK = mask(26)
const RegVal	ISA_EXT_C_MASK = 1UL << ('c' - 'a')
const RegVal	MISA_MASKS [enums::Num_RiscvType]
const RegVal	STATUS_SD_MASKS [enums::Num_RiscvType]
const RegVal	STATUS_MBE_MASK [enums::Num_RiscvType]
const RegVal	STATUS_SBE_MASK [enums::Num_RiscvType]
const RegVal	STATUS_SXL_MASK = 3ULL << SXL_OFFSET
const RegVal	STATUS_UXL_MASK = 3ULL << UXL_OFFSET
const RegVal	STATUS_TSR_MASK = 1ULL << 22
const RegVal	STATUS_TW_MASK = 1ULL << 21
const RegVal	STATUS_TVM_MASK = 1ULL << 20
const RegVal	STATUS_MXR_MASK = 1ULL << 19
const RegVal	STATUS_SUM_MASK = 1ULL << 18
const RegVal	STATUS_MPRV_MASK = 1ULL << 17
const RegVal	STATUS_XS_MASK = 3ULL << 15
const RegVal	STATUS_FS_MASK = 3ULL << FS_OFFSET
const RegVal	STATUS_MPP_MASK = 3ULL << 11
const RegVal	STATUS_VS_MASK = 3ULL << 9
const RegVal	STATUS_SPP_MASK = 1ULL << 8
const RegVal	STATUS_MPIE_MASK = 1ULL << 7
const RegVal	STATUS_SPIE_MASK = 1ULL << 5
const RegVal	STATUS_UPIE_MASK = 1ULL << 4
const RegVal	STATUS_MIE_MASK = 1ULL << 3
const RegVal	STATUS_SIE_MASK = 1ULL << 1
const RegVal	STATUS_UIE_MASK = 1ULL << 0
const RegVal	MSTATUS_MASKS [enums::Num_RiscvType]
const RegVal	MSTATUSH_MASKS = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32]
const RegVal	SSTATUS_MASKS [enums::Num_RiscvType]
const RegVal	USTATUS_MASKS [enums::Num_RiscvType]
const RegVal	MEI_MASK = 1ULL << 11
const RegVal	SEI_MASK = 1ULL << 9
const RegVal	UEI_MASK = 1ULL << 8
const RegVal	MTI_MASK = 1ULL << 7
const RegVal	STI_MASK = 1ULL << 5
const RegVal	UTI_MASK = 1ULL << 4
const RegVal	MSI_MASK = 1ULL << 3
const RegVal	SSI_MASK = 1ULL << 1
const RegVal	USI_MASK = 1ULL << 0
const RegVal	MI_MASK
const RegVal	SI_MASK
const RegVal	UI_MASK = UEI_MASK | UTI_MASK | USI_MASK
const RegVal	FFLAGS_MASK = (1 << FRM_OFFSET) - 1
const RegVal	FRM_MASK = 0x7
const RegVal	CAUSE_INTERRUPT_MASKS [enums::Num_RiscvType]
const std::unordered_map< int, RegVal >	CSRMasks [enums::Num_RiscvType]
const uint8_t	_rvk_emu_aes_fwd_sbox [256]
	Ref: https://github.com/rvkrypto/rvkrypto-fips. More...
const uint8_t	_rvk_emu_aes_inv_sbox [256]
const uint8_t	_rvk_emu_sm4_sbox [256]
	rv_type
Bitfield< 61 >	compressed
Bitfield< 57, 41 >	vl
Bitfield< 40 >	vill
Bitfield< 38 >	vta
Bitfield< 37, 35 >	vsew
Bitfield< 34, 32 >	vlmul
Bitfield< 1, 0 >	quadRant
Bitfield< 6, 2 >	opcode5
Bitfield< 6, 0 >	opcode
Bitfield< 31, 0 >	all
Bitfield< 11, 7 >	rd
Bitfield< 14, 12 >	funct3
Bitfield< 19, 15 >	rs1
Bitfield< 24, 20 >	rs2
Bitfield< 31, 25 >	funct7
Bitfield< 30 >	srType
Bitfield< 24, 20 >	shamt5
Bitfield< 25, 20 >	shamt6
Bitfield< 31, 20 >	imm12
Bitfield< 23, 20 >	succ
Bitfield< 27, 24 >	pred
Bitfield< 11, 7 >	imm5
Bitfield< 31, 25 >	imm7
Bitfield< 31, 12 >	imm20
Bitfield< 7 >	bimm12bit11
Bitfield< 11, 8 >	bimm12bits4to1
Bitfield< 30, 25 >	bimm12bits10to5
Bitfield< 31 >	immsign
Bitfield< 30, 21 >	ujimmbits10to1
Bitfield< 20 >	ujimmbit11
Bitfield< 19, 12 >	ujimmbits19to12
Bitfield< 31, 20 >	funct12
Bitfield< 19, 15 >	csrimm
Bitfield< 11, 7 >	fd
Bitfield< 19, 15 >	fs1
Bitfield< 24, 20 >	fs2
Bitfield< 31, 27 >	fs3
Bitfield< 14, 12 >	round_mode
Bitfield< 24, 20 >	conv_sgn
Bitfield< 26, 25 >	funct2
Bitfield< 31, 27 >	amofunct
Bitfield< 26 >	aq
Bitfield< 25 >	rl
Bitfield< 15, 13 >	copcode
Bitfield< 12 >	cfunct1
Bitfield< 11, 10 >	cfunct2high
Bitfield< 6, 5 >	cfunct2low
Bitfield< 11, 7 >	rc1
Bitfield< 6, 2 >	rc2
Bitfield< 9, 7 >	rp1
Bitfield< 4, 2 >	rp2
Bitfield< 11, 7 >	fc1
Bitfield< 6, 2 >	fc2
Bitfield< 4, 2 >	fp2
Bitfield< 12, 2 >	cjumpimm
Bitfield< 5, 3 >	cjumpimm3to1
Bitfield< 11, 11 >	cjumpimm4to4
Bitfield< 2, 2 >	cjumpimm5to5
Bitfield< 7, 7 >	cjumpimm6to6
Bitfield< 6, 6 >	cjumpimm7to7
Bitfield< 10, 9 >	cjumpimm9to8
Bitfield< 8, 8 >	cjumpimm10to10
Bitfield< 12 >	cjumpimmsign
Bitfield< 12, 5 >	cimm8
Bitfield< 12, 7 >	cimm6
Bitfield< 6, 2 >	cimm5
Bitfield< 12, 10 >	cimm3
Bitfield< 6, 5 >	cimm2
Bitfield< 12 >	cimm1
Bitfield< 31, 25 >	m5func
Bitfield< 31, 26 >	vfunct6
Bitfield< 31, 27 >	vfunct5
Bitfield< 27, 25 >	vfunct3
Bitfield< 26, 25 >	vfunct2
Bitfield< 31, 29 >	nf
Bitfield< 28 >	mew
Bitfield< 27, 26 >	mop
Bitfield< 25 >	vm
Bitfield< 24, 20 >	lumop
Bitfield< 24, 20 >	sumop
Bitfield< 14, 12 >	width
Bitfield< 24, 20 >	vs2
Bitfield< 19, 15 >	vs1
Bitfield< 11, 7 >	vd
Bitfield< 11, 7 >	vs3
Bitfield< 19, 15 >	vecimm
Bitfield< 17, 15 >	simm3
Bitfield< 31 >	bit31
Bitfield< 30 >	bit30
Bitfield< 30, 20 >	zimm_vsetvli
Bitfield< 31, 30 >	bit31_30
Bitfield< 29, 20 >	zimm_vsetivli
Bitfield< 19, 15 >	uimm_vsetivli
Bitfield< 31, 25 >	bit31_25

Typedef Documentation

freg_t

using gem5::RiscvISA::freg_t = typedef float64_t

Definition at line 69 of file float.hh.

MachInst

typedef uint32_t gem5::RiscvISA::MachInst

Definition at line 54 of file types.hh.

RiscvType

using gem5::RiscvISA::RiscvType = typedef enums::RiscvType

Definition at line 53 of file pcstate.hh.

TlbEntryTrie

typedef Trie<Addr, TlbEntry> gem5::RiscvISA::TlbEntryTrie

Definition at line 80 of file pagetable.hh.

Enumeration Type Documentation

CSRIndex

enum gem5::RiscvISA::CSRIndex

Enumerator
CSR_USTATUS
CSR_UIE
CSR_UTVEC
CSR_USCRATCH
CSR_UEPC
CSR_UCAUSE
CSR_UTVAL
CSR_UIP
CSR_FFLAGS
CSR_FRM
CSR_FCSR
CSR_CYCLE
CSR_TIME
CSR_INSTRET
CSR_HPMCOUNTER03
CSR_HPMCOUNTER04
CSR_HPMCOUNTER05
CSR_HPMCOUNTER06
CSR_HPMCOUNTER07
CSR_HPMCOUNTER08
CSR_HPMCOUNTER09
CSR_HPMCOUNTER10
CSR_HPMCOUNTER11
CSR_HPMCOUNTER12
CSR_HPMCOUNTER13
CSR_HPMCOUNTER14
CSR_HPMCOUNTER15
CSR_HPMCOUNTER16
CSR_HPMCOUNTER17
CSR_HPMCOUNTER18
CSR_HPMCOUNTER19
CSR_HPMCOUNTER20
CSR_HPMCOUNTER21
CSR_HPMCOUNTER22
CSR_HPMCOUNTER23
CSR_HPMCOUNTER24
CSR_HPMCOUNTER25
CSR_HPMCOUNTER26
CSR_HPMCOUNTER27
CSR_HPMCOUNTER28
CSR_HPMCOUNTER29
CSR_HPMCOUNTER30
CSR_HPMCOUNTER31
CSR_CYCLEH
CSR_TIMEH
CSR_INSTRETH
CSR_HPMCOUNTER03H
CSR_HPMCOUNTER04H
CSR_HPMCOUNTER05H
CSR_HPMCOUNTER06H
CSR_HPMCOUNTER07H
CSR_HPMCOUNTER08H
CSR_HPMCOUNTER09H
CSR_HPMCOUNTER10H
CSR_HPMCOUNTER11H
CSR_HPMCOUNTER12H
CSR_HPMCOUNTER13H
CSR_HPMCOUNTER14H
CSR_HPMCOUNTER15H
CSR_HPMCOUNTER16H
CSR_HPMCOUNTER17H
CSR_HPMCOUNTER18H
CSR_HPMCOUNTER19H
CSR_HPMCOUNTER20H
CSR_HPMCOUNTER21H
CSR_HPMCOUNTER22H
CSR_HPMCOUNTER23H
CSR_HPMCOUNTER24H
CSR_HPMCOUNTER25H
CSR_HPMCOUNTER26H
CSR_HPMCOUNTER27H
CSR_HPMCOUNTER28H
CSR_HPMCOUNTER29H
CSR_HPMCOUNTER30H
CSR_HPMCOUNTER31H
CSR_SSTATUS
CSR_SEDELEG
CSR_SIDELEG
CSR_SIE
CSR_STVEC
CSR_SCOUNTEREN
CSR_SSCRATCH
CSR_SEPC
CSR_SCAUSE
CSR_STVAL
CSR_SIP
CSR_SATP
CSR_MVENDORID
CSR_MARCHID
CSR_MIMPID
CSR_MHARTID
CSR_MSTATUS
CSR_MISA
CSR_MEDELEG
CSR_MIDELEG
CSR_MIE
CSR_MTVEC
CSR_MCOUNTEREN
CSR_MSTATUSH
CSR_MSCRATCH
CSR_MEPC
CSR_MCAUSE
CSR_MTVAL
CSR_MIP
CSR_PMPCFG0
CSR_PMPCFG1
CSR_PMPCFG2
CSR_PMPCFG3
CSR_PMPADDR00
CSR_PMPADDR01
CSR_PMPADDR02
CSR_PMPADDR03
CSR_PMPADDR04
CSR_PMPADDR05
CSR_PMPADDR06
CSR_PMPADDR07
CSR_PMPADDR08
CSR_PMPADDR09
CSR_PMPADDR10
CSR_PMPADDR11
CSR_PMPADDR12
CSR_PMPADDR13
CSR_PMPADDR14
CSR_PMPADDR15
CSR_MCYCLE
CSR_MINSTRET
CSR_MHPMCOUNTER03
CSR_MHPMCOUNTER04
CSR_MHPMCOUNTER05
CSR_MHPMCOUNTER06
CSR_MHPMCOUNTER07
CSR_MHPMCOUNTER08
CSR_MHPMCOUNTER09
CSR_MHPMCOUNTER10
CSR_MHPMCOUNTER11
CSR_MHPMCOUNTER12
CSR_MHPMCOUNTER13
CSR_MHPMCOUNTER14
CSR_MHPMCOUNTER15
CSR_MHPMCOUNTER16
CSR_MHPMCOUNTER17
CSR_MHPMCOUNTER18
CSR_MHPMCOUNTER19
CSR_MHPMCOUNTER20
CSR_MHPMCOUNTER21
CSR_MHPMCOUNTER22
CSR_MHPMCOUNTER23
CSR_MHPMCOUNTER24
CSR_MHPMCOUNTER25
CSR_MHPMCOUNTER26
CSR_MHPMCOUNTER27
CSR_MHPMCOUNTER28
CSR_MHPMCOUNTER29
CSR_MHPMCOUNTER30
CSR_MHPMCOUNTER31
CSR_MCYCLEH
CSR_MINSTRETH
CSR_MHPMCOUNTER03H
CSR_MHPMCOUNTER04H
CSR_MHPMCOUNTER05H
CSR_MHPMCOUNTER06H
CSR_MHPMCOUNTER07H
CSR_MHPMCOUNTER08H
CSR_MHPMCOUNTER09H
CSR_MHPMCOUNTER10H
CSR_MHPMCOUNTER11H
CSR_MHPMCOUNTER12H
CSR_MHPMCOUNTER13H
CSR_MHPMCOUNTER14H
CSR_MHPMCOUNTER15H
CSR_MHPMCOUNTER16H
CSR_MHPMCOUNTER17H
CSR_MHPMCOUNTER18H
CSR_MHPMCOUNTER19H
CSR_MHPMCOUNTER20H
CSR_MHPMCOUNTER21H
CSR_MHPMCOUNTER22H
CSR_MHPMCOUNTER23H
CSR_MHPMCOUNTER24H
CSR_MHPMCOUNTER25H
CSR_MHPMCOUNTER26H
CSR_MHPMCOUNTER27H
CSR_MHPMCOUNTER28H
CSR_MHPMCOUNTER29H
CSR_MHPMCOUNTER30H
CSR_MHPMCOUNTER31H
CSR_MHPMEVENT03
CSR_MHPMEVENT04
CSR_MHPMEVENT05
CSR_MHPMEVENT06
CSR_MHPMEVENT07
CSR_MHPMEVENT08
CSR_MHPMEVENT09
CSR_MHPMEVENT10
CSR_MHPMEVENT11
CSR_MHPMEVENT12
CSR_MHPMEVENT13
CSR_MHPMEVENT14
CSR_MHPMEVENT15
CSR_MHPMEVENT16
CSR_MHPMEVENT17
CSR_MHPMEVENT18
CSR_MHPMEVENT19
CSR_MHPMEVENT20
CSR_MHPMEVENT21
CSR_MHPMEVENT22
CSR_MHPMEVENT23
CSR_MHPMEVENT24
CSR_MHPMEVENT25
CSR_MHPMEVENT26
CSR_MHPMEVENT27
CSR_MHPMEVENT28
CSR_MHPMEVENT29
CSR_MHPMEVENT30
CSR_MHPMEVENT31
CSR_TSELECT
CSR_TDATA1
CSR_TDATA2
CSR_TDATA3
CSR_DCSR
CSR_DPC
CSR_DSCRATCH

Definition at line 246 of file misc.hh.

ExceptionCode

enum gem5::RiscvISA::ExceptionCode : uint64_t

Enumerator
INST_ADDR_MISALIGNED
INST_ACCESS
INST_ILLEGAL
BREAKPOINT
LOAD_ADDR_MISALIGNED
LOAD_ACCESS
STORE_ADDR_MISALIGNED
AMO_ADDR_MISALIGNED
STORE_ACCESS
AMO_ACCESS
ECALL_USER
ECALL_SUPER
ECALL_MACHINE
INST_PAGE
LOAD_PAGE
STORE_PAGE
AMO_PAGE
INT_SOFTWARE_USER
INT_SOFTWARE_SUPER
INT_SOFTWARE_MACHINE
INT_TIMER_USER
INT_TIMER_SUPER
INT_TIMER_MACHINE
INT_EXT_USER
INT_EXT_SUPER
INT_EXT_MACHINE
NumInterruptTypes
INT_NMI

Definition at line 67 of file faults.hh.

FaultType

enum gem5::RiscvISA::FaultType

strong

Enumerator
INTERRUPT
NON_MASKABLE_INTERRUPT
OTHERS

Definition at line 103 of file faults.hh.

FloatException

enum gem5::RiscvISA::FloatException : uint64_t

Enumerator
FloatInexact
FloatUnderflow
FloatOverflow
FloatDivZero
FloatInvalid

Definition at line 49 of file faults.hh.

FPUStatus

enum gem5::RiscvISA::FPUStatus

Enumerator
OFF
INITIAL
CLEAN
DIRTY

Definition at line 62 of file isa.hh.

MiscRegIndex

enum gem5::RiscvISA::MiscRegIndex

Enumerator
MISCREG_PRV
MISCREG_ISA
MISCREG_VENDORID
MISCREG_ARCHID
MISCREG_IMPID
MISCREG_HARTID
MISCREG_STATUS
MISCREG_IP
MISCREG_IE
MISCREG_CYCLE
MISCREG_TIME
MISCREG_INSTRET
MISCREG_HPMCOUNTER03
MISCREG_HPMCOUNTER04
MISCREG_HPMCOUNTER05
MISCREG_HPMCOUNTER06
MISCREG_HPMCOUNTER07
MISCREG_HPMCOUNTER08
MISCREG_HPMCOUNTER09
MISCREG_HPMCOUNTER10
MISCREG_HPMCOUNTER11
MISCREG_HPMCOUNTER12
MISCREG_HPMCOUNTER13
MISCREG_HPMCOUNTER14
MISCREG_HPMCOUNTER15
MISCREG_HPMCOUNTER16
MISCREG_HPMCOUNTER17
MISCREG_HPMCOUNTER18
MISCREG_HPMCOUNTER19
MISCREG_HPMCOUNTER20
MISCREG_HPMCOUNTER21
MISCREG_HPMCOUNTER22
MISCREG_HPMCOUNTER23
MISCREG_HPMCOUNTER24
MISCREG_HPMCOUNTER25
MISCREG_HPMCOUNTER26
MISCREG_HPMCOUNTER27
MISCREG_HPMCOUNTER28
MISCREG_HPMCOUNTER29
MISCREG_HPMCOUNTER30
MISCREG_HPMCOUNTER31
MISCREG_HPMEVENT03
MISCREG_HPMEVENT04
MISCREG_HPMEVENT05
MISCREG_HPMEVENT06
MISCREG_HPMEVENT07
MISCREG_HPMEVENT08
MISCREG_HPMEVENT09
MISCREG_HPMEVENT10
MISCREG_HPMEVENT11
MISCREG_HPMEVENT12
MISCREG_HPMEVENT13
MISCREG_HPMEVENT14
MISCREG_HPMEVENT15
MISCREG_HPMEVENT16
MISCREG_HPMEVENT17
MISCREG_HPMEVENT18
MISCREG_HPMEVENT19
MISCREG_HPMEVENT20
MISCREG_HPMEVENT21
MISCREG_HPMEVENT22
MISCREG_HPMEVENT23
MISCREG_HPMEVENT24
MISCREG_HPMEVENT25
MISCREG_HPMEVENT26
MISCREG_HPMEVENT27
MISCREG_HPMEVENT28
MISCREG_HPMEVENT29
MISCREG_HPMEVENT30
MISCREG_HPMEVENT31
MISCREG_TSELECT
MISCREG_TDATA1
MISCREG_TDATA2
MISCREG_TDATA3
MISCREG_DCSR
MISCREG_DPC
MISCREG_DSCRATCH
MISCREG_MEDELEG
MISCREG_MIDELEG
MISCREG_MTVEC
MISCREG_MCOUNTEREN
MISCREG_MSCRATCH
MISCREG_MEPC
MISCREG_MCAUSE
MISCREG_MTVAL
MISCREG_PMPCFG0
MISCREG_PMPCFG1
MISCREG_PMPCFG2
MISCREG_PMPCFG3
MISCREG_PMPADDR00
MISCREG_PMPADDR01
MISCREG_PMPADDR02
MISCREG_PMPADDR03
MISCREG_PMPADDR04
MISCREG_PMPADDR05
MISCREG_PMPADDR06
MISCREG_PMPADDR07
MISCREG_PMPADDR08
MISCREG_PMPADDR09
MISCREG_PMPADDR10
MISCREG_PMPADDR11
MISCREG_PMPADDR12
MISCREG_PMPADDR13
MISCREG_PMPADDR14
MISCREG_PMPADDR15
MISCREG_SEDELEG
MISCREG_SIDELEG
MISCREG_STVEC
MISCREG_SCOUNTEREN
MISCREG_SSCRATCH
MISCREG_SEPC
MISCREG_SCAUSE
MISCREG_STVAL
MISCREG_SATP
MISCREG_UTVEC
MISCREG_USCRATCH
MISCREG_UEPC
MISCREG_UCAUSE
MISCREG_UTVAL
MISCREG_FFLAGS
MISCREG_FRM
MISCREG_NMIVEC
MISCREG_NMIE
MISCREG_NMIP
MISCREG_MSTATUSH
MISCREG_CYCLEH
MISCREG_TIMEH
MISCREG_INSTRETH
MISCREG_HPMCOUNTER03H
MISCREG_HPMCOUNTER04H
MISCREG_HPMCOUNTER05H
MISCREG_HPMCOUNTER06H
MISCREG_HPMCOUNTER07H
MISCREG_HPMCOUNTER08H
MISCREG_HPMCOUNTER09H
MISCREG_HPMCOUNTER10H
MISCREG_HPMCOUNTER11H
MISCREG_HPMCOUNTER12H
MISCREG_HPMCOUNTER13H
MISCREG_HPMCOUNTER14H
MISCREG_HPMCOUNTER15H
MISCREG_HPMCOUNTER16H
MISCREG_HPMCOUNTER17H
MISCREG_HPMCOUNTER18H
MISCREG_HPMCOUNTER19H
MISCREG_HPMCOUNTER20H
MISCREG_HPMCOUNTER21H
MISCREG_HPMCOUNTER22H
MISCREG_HPMCOUNTER23H
MISCREG_HPMCOUNTER24H
MISCREG_HPMCOUNTER25H
MISCREG_HPMCOUNTER26H
MISCREG_HPMCOUNTER27H
MISCREG_HPMCOUNTER28H
MISCREG_HPMCOUNTER29H
MISCREG_HPMCOUNTER30H
MISCREG_HPMCOUNTER31H
NUM_MISCREGS

Definition at line 67 of file misc.hh.

PrivilegeMode

enum gem5::RiscvISA::PrivilegeMode

Enumerator
PRV_U
PRV_S
PRV_M

Definition at line 55 of file isa.hh.

Function Documentation

_rvk_emu_aes32dsi()

int32_t gem5::RiscvISA::_rvk_emu_aes32dsi ( int32_t  rs1, int32_t  rs2, uint8_t  bs  )

inline

Definition at line 361 of file rvk.hh.

References _rvk_emu_aes_inv_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes32dsmi()

int32_t gem5::RiscvISA::_rvk_emu_aes32dsmi ( int32_t  rs1, int32_t  rs2, uint8_t  bs  )

inline

Definition at line 372 of file rvk.hh.

References _rvk_emu_aes_inv_mc_8(), _rvk_emu_aes_inv_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes32esi()

int32_t gem5::RiscvISA::_rvk_emu_aes32esi ( int32_t  rs1, int32_t  rs2, uint8_t  bs  )

inline

Definition at line 447 of file rvk.hh.

References _rvk_emu_aes_fwd_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes32esmi()

int32_t gem5::RiscvISA::_rvk_emu_aes32esmi ( int32_t  rs1, int32_t  rs2, uint8_t  bs  )

inline

Definition at line 458 of file rvk.hh.

References _rvk_emu_aes_fwd_mc_8(), _rvk_emu_aes_fwd_sbox, _rvk_emu_rol_32(), gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_aes64ds()

int64_t gem5::RiscvISA::_rvk_emu_aes64ds ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 384 of file rvk.hh.

References _rvk_emu_aes_inv_sbox, rs1, and rs2.

Referenced by _rvk_emu_aes64dsm().

_rvk_emu_aes64dsm()

int64_t gem5::RiscvISA::_rvk_emu_aes64dsm ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 402 of file rvk.hh.

References _rvk_emu_aes64ds(), _rvk_emu_aes64im(), rs1, rs2, and x.

_rvk_emu_aes64es()

int64_t gem5::RiscvISA::_rvk_emu_aes64es ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 470 of file rvk.hh.

References _rvk_emu_aes_fwd_sbox, rs1, and rs2.

Referenced by _rvk_emu_aes64esm().

_rvk_emu_aes64esm()

int64_t gem5::RiscvISA::_rvk_emu_aes64esm ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 482 of file rvk.hh.

References _rvk_emu_aes64es(), _rvk_emu_aes_fwd_mc_32(), rs1, rs2, and x.

_rvk_emu_aes64im()

int64_t gem5::RiscvISA::_rvk_emu_aes64im ( int64_t  rs1 )

inline

Definition at line 396 of file rvk.hh.

References _rvk_emu_aes_inv_mc_32(), and rs1.

Referenced by _rvk_emu_aes64dsm().

_rvk_emu_aes64ks1i()

int64_t gem5::RiscvISA::_rvk_emu_aes64ks1i ( int64_t  rs1, int  rnum  )

inline

Definition at line 411 of file rvk.hh.

References _rvk_emu_aes_fwd_sbox, _rvk_emu_ror_32(), gem5::PowerISA::rc, rs1, and gem5::VegaISA::t.

_rvk_emu_aes64ks2()

int64_t gem5::RiscvISA::_rvk_emu_aes64ks2 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 437 of file rvk.hh.

References rs1, rs2, and gem5::VegaISA::t.

_rvk_emu_aes_fwd_mc_32()

uint32_t gem5::RiscvISA::_rvk_emu_aes_fwd_mc_32 ( uint32_t  x )

inline

Definition at line 326 of file rvk.hh.

References _rvk_emu_aes_fwd_mc_8(), _rvk_emu_rol_32(), and x.

Referenced by _rvk_emu_aes64esm().

_rvk_emu_aes_fwd_mc_8()

uint32_t gem5::RiscvISA::_rvk_emu_aes_fwd_mc_8 ( uint32_t  x )

inline

Definition at line 317 of file rvk.hh.

References _rvk_emu_aes_xtime(), and x.

Referenced by _rvk_emu_aes32esmi(), and _rvk_emu_aes_fwd_mc_32().

_rvk_emu_aes_inv_mc_32()

uint32_t gem5::RiscvISA::_rvk_emu_aes_inv_mc_32 ( uint32_t  x )

inline

Definition at line 352 of file rvk.hh.

References _rvk_emu_aes_inv_mc_8(), _rvk_emu_rol_32(), and x.

Referenced by _rvk_emu_aes64im().

_rvk_emu_aes_inv_mc_8()

uint32_t gem5::RiscvISA::_rvk_emu_aes_inv_mc_8 ( uint32_t  x )

inline

Definition at line 335 of file rvk.hh.

References _rvk_emu_aes_xtime(), and x.

Referenced by _rvk_emu_aes32dsmi(), and _rvk_emu_aes_inv_mc_32().

_rvk_emu_aes_xtime()

uint8_t gem5::RiscvISA::_rvk_emu_aes_xtime ( uint8_t  x )

inline

Definition at line 311 of file rvk.hh.

References x.

Referenced by _rvk_emu_aes_fwd_mc_8(), and _rvk_emu_aes_inv_mc_8().

_rvk_emu_brev8_32()

int32_t gem5::RiscvISA::_rvk_emu_brev8_32 ( int32_t  rs1 )

inline

Definition at line 182 of file rvk.hh.

References _rvk_emu_grev_32(), and rs1.

_rvk_emu_brev8_64()

int64_t gem5::RiscvISA::_rvk_emu_brev8_64 ( int64_t  rs1 )

inline

Definition at line 185 of file rvk.hh.

References _rvk_emu_grev_64(), and rs1.

_rvk_emu_clmul_32()

int32_t gem5::RiscvISA::_rvk_emu_clmul_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 229 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_clmul_64()

int64_t gem5::RiscvISA::_rvk_emu_clmul_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 249 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_clmulh_32()

int32_t gem5::RiscvISA::_rvk_emu_clmulh_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 239 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_clmulh_64()

int64_t gem5::RiscvISA::_rvk_emu_clmulh_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 260 of file rvk.hh.

References a, gem5::ArmISA::b, i, rs1, rs2, and x.

_rvk_emu_grev_32()

int32_t gem5::RiscvISA::_rvk_emu_grev_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 145 of file rvk.hh.

References rs1, rs2, and x.

Referenced by _rvk_emu_brev8_32().

_rvk_emu_grev_64()

int64_t gem5::RiscvISA::_rvk_emu_grev_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 157 of file rvk.hh.

References rs1, rs2, and x.

Referenced by _rvk_emu_brev8_64().

_rvk_emu_rol_32()

int32_t gem5::RiscvISA::_rvk_emu_rol_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 134 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes_fwd_mc_32(), _rvk_emu_aes_inv_mc_32(), _rvk_emu_sm3p0(), _rvk_emu_sm3p1(), _rvk_emu_sm4ed(), and _rvk_emu_sm4ks().

_rvk_emu_rol_64()

int64_t gem5::RiscvISA::_rvk_emu_rol_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 139 of file rvk.hh.

References _rvk_emu_sll_64(), _rvk_emu_srl_64(), rs1, and rs2.

_rvk_emu_ror_32()

int32_t gem5::RiscvISA::_rvk_emu_ror_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 136 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

Referenced by _rvk_emu_aes64ks1i(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha256sum0(), and _rvk_emu_sha256sum1().

_rvk_emu_ror_64()

int64_t gem5::RiscvISA::_rvk_emu_ror_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 141 of file rvk.hh.

References _rvk_emu_sll_64(), _rvk_emu_srl_64(), rs1, and rs2.

Referenced by _rvk_emu_sha512sig0(), _rvk_emu_sha512sig1(), _rvk_emu_sha512sum0(), and _rvk_emu_sha512sum1().

_rvk_emu_sha256sig0()

int32_t gem5::RiscvISA::_rvk_emu_sha256sig0 ( int32_t  rs1 )

inline

Definition at line 492 of file rvk.hh.

References _rvk_emu_ror_32(), _rvk_emu_srl_32(), rs1, and x.

_rvk_emu_sha256sig1()

int32_t gem5::RiscvISA::_rvk_emu_sha256sig1 ( int32_t  rs1 )

inline

Definition at line 501 of file rvk.hh.

References _rvk_emu_ror_32(), _rvk_emu_srl_32(), rs1, and x.

_rvk_emu_sha256sum0()

int32_t gem5::RiscvISA::_rvk_emu_sha256sum0 ( int32_t  rs1 )

inline

Definition at line 510 of file rvk.hh.

References _rvk_emu_ror_32(), rs1, and x.

_rvk_emu_sha256sum1()

int32_t gem5::RiscvISA::_rvk_emu_sha256sum1 ( int32_t  rs1 )

inline

Definition at line 519 of file rvk.hh.

References _rvk_emu_ror_32(), rs1, and x.

_rvk_emu_sha512sig0()

int64_t gem5::RiscvISA::_rvk_emu_sha512sig0 ( int64_t  rs1 )

inline

Definition at line 570 of file rvk.hh.

References _rvk_emu_ror_64(), _rvk_emu_srl_64(), and rs1.

_rvk_emu_sha512sig0h()

static int32_t gem5::RiscvISA::_rvk_emu_sha512sig0h ( int32_t  rs1, int32_t  rs2  )

inlinestatic

Definition at line 528 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sig0l()

static int32_t gem5::RiscvISA::_rvk_emu_sha512sig0l ( int32_t  rs1, int32_t  rs2  )

inlinestatic

Definition at line 535 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sig1()

int64_t gem5::RiscvISA::_rvk_emu_sha512sig1 ( int64_t  rs1 )

inline

Definition at line 576 of file rvk.hh.

References _rvk_emu_ror_64(), _rvk_emu_srl_64(), and rs1.

_rvk_emu_sha512sig1h()

static int32_t gem5::RiscvISA::_rvk_emu_sha512sig1h ( int32_t  rs1, int32_t  rs2  )

inlinestatic

Definition at line 542 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sig1l()

static int32_t gem5::RiscvISA::_rvk_emu_sha512sig1l ( int32_t  rs1, int32_t  rs2  )

inlinestatic

Definition at line 549 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sum0()

int64_t gem5::RiscvISA::_rvk_emu_sha512sum0 ( int64_t  rs1 )

inline

Definition at line 582 of file rvk.hh.

References _rvk_emu_ror_64(), and rs1.

_rvk_emu_sha512sum0r()

static int32_t gem5::RiscvISA::_rvk_emu_sha512sum0r ( int32_t  rs1, int32_t  rs2  )

inlinestatic

Definition at line 556 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_sha512sum1()

int64_t gem5::RiscvISA::_rvk_emu_sha512sum1 ( int64_t  rs1 )

inline

Definition at line 588 of file rvk.hh.

References _rvk_emu_ror_64(), and rs1.

_rvk_emu_sha512sum1r()

static int32_t gem5::RiscvISA::_rvk_emu_sha512sum1r ( int32_t  rs1, int32_t  rs2  )

inlinestatic

Definition at line 563 of file rvk.hh.

References _rvk_emu_sll_32(), _rvk_emu_srl_32(), rs1, and rs2.

_rvk_emu_shfl_32()

int32_t gem5::RiscvISA::_rvk_emu_shfl_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 196 of file rvk.hh.

References _rvk_emu_shuffle32_stage(), rs1, rs2, and x.

Referenced by _rvk_emu_zip_32().

_rvk_emu_shuffle32_stage()

uint32_t gem5::RiscvISA::_rvk_emu_shuffle32_stage ( uint32_t  src, uint32_t  maskL, uint32_t  maskR, int  N  )

inline

Definition at line 188 of file rvk.hh.

References x.

Referenced by _rvk_emu_shfl_32(), and _rvk_emu_unshfl_32().

_rvk_emu_sll_32()

int32_t gem5::RiscvISA::_rvk_emu_sll_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 124 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_32(), _rvk_emu_ror_32(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0r(), and _rvk_emu_sha512sum1r().

_rvk_emu_sll_64()

int64_t gem5::RiscvISA::_rvk_emu_sll_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 128 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_64(), and _rvk_emu_ror_64().

_rvk_emu_sm3p0()

int32_t gem5::RiscvISA::_rvk_emu_sm3p0 ( int32_t  rs1 )

inline

Definition at line 624 of file rvk.hh.

References _rvk_emu_rol_32(), rs1, and x.

_rvk_emu_sm3p1()

int32_t gem5::RiscvISA::_rvk_emu_sm3p1 ( int32_t  rs1 )

inline

Definition at line 632 of file rvk.hh.

References _rvk_emu_rol_32(), rs1, and x.

_rvk_emu_sm4ed()

int32_t gem5::RiscvISA::_rvk_emu_sm4ed ( int32_t  rs1, int32_t  rs2, uint8_t  bs  )

inline

Definition at line 595 of file rvk.hh.

References _rvk_emu_rol_32(), _rvk_emu_sm4_sbox, gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_sm4ks()

int32_t gem5::RiscvISA::_rvk_emu_sm4ks ( int32_t  rs1, int32_t  rs2, uint8_t  bs  )

inline

Definition at line 609 of file rvk.hh.

References _rvk_emu_rol_32(), _rvk_emu_sm4_sbox, gem5::X86ISA::bs, rs1, rs2, and x.

_rvk_emu_srl_32()

int32_t gem5::RiscvISA::_rvk_emu_srl_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 126 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_32(), _rvk_emu_ror_32(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0r(), and _rvk_emu_sha512sum1r().

_rvk_emu_srl_64()

int64_t gem5::RiscvISA::_rvk_emu_srl_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 130 of file rvk.hh.

References rs1, and rs2.

Referenced by _rvk_emu_rol_64(), _rvk_emu_ror_64(), _rvk_emu_sha512sig0(), and _rvk_emu_sha512sig1().

_rvk_emu_unshfl_32()

int32_t gem5::RiscvISA::_rvk_emu_unshfl_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 209 of file rvk.hh.

References _rvk_emu_shuffle32_stage(), rs1, rs2, and x.

Referenced by _rvk_emu_unzip_32().

_rvk_emu_unzip_32()

int32_t gem5::RiscvISA::_rvk_emu_unzip_32 ( int32_t  rs1 )

inline

Definition at line 225 of file rvk.hh.

References _rvk_emu_unshfl_32(), and rs1.

_rvk_emu_xperm32()

uint32_t gem5::RiscvISA::_rvk_emu_xperm32 ( uint32_t  rs1, uint32_t  rs2, int  sz_log2  )

inline

Definition at line 272 of file rvk.hh.

References i, mask, r, rs1, and rs2.

Referenced by _rvk_emu_xperm4_32(), and _rvk_emu_xperm8_32().

_rvk_emu_xperm4_32()

int32_t gem5::RiscvISA::_rvk_emu_xperm4_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 285 of file rvk.hh.

References _rvk_emu_xperm32(), rs1, and rs2.

_rvk_emu_xperm4_64()

int64_t gem5::RiscvISA::_rvk_emu_xperm4_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 304 of file rvk.hh.

References _rvk_emu_xperm64(), rs1, and rs2.

_rvk_emu_xperm64()

uint64_t gem5::RiscvISA::_rvk_emu_xperm64 ( uint64_t  rs1, uint64_t  rs2, int  sz_log2  )

inline

Definition at line 291 of file rvk.hh.

References i, mask, r, rs1, and rs2.

Referenced by _rvk_emu_xperm4_64(), and _rvk_emu_xperm8_64().

_rvk_emu_xperm8_32()

int32_t gem5::RiscvISA::_rvk_emu_xperm8_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 288 of file rvk.hh.

References _rvk_emu_xperm32(), rs1, and rs2.

_rvk_emu_xperm8_64()

int64_t gem5::RiscvISA::_rvk_emu_xperm8_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 307 of file rvk.hh.

References _rvk_emu_xperm64(), rs1, and rs2.

_rvk_emu_zip_32()

int32_t gem5::RiscvISA::_rvk_emu_zip_32 ( int32_t  rs1 )

inline

Definition at line 222 of file rvk.hh.

References _rvk_emu_shfl_32(), and rs1.

BitUnion32()

gem5::RiscvISA::BitUnion32

(

IndexReg

)

BitUnion64() [1/4]

gem5::RiscvISA::BitUnion64

(

ExtMachInst

)

BitUnion64() [2/4]

gem5::RiscvISA::BitUnion64

(

PTESv39

)

BitUnion64() [3/4]

gem5::RiscvISA::BitUnion64

(

SATP

)

BitUnion64() [4/4]

gem5::RiscvISA::BitUnion64

(

STATUS

)

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org.

in Figure 3.7. The main register that uses these fields is the MSTATUS register, which is shadowed by two others accessible at lower privilege levels (SSTATUS and USTATUS) that can't see the fields for higher privileges.

boxF16()

static constexpr uint64_t gem5::RiscvISA::boxF16 ( uint16_t  v )

staticconstexpr

Definition at line 93 of file float.hh.

References mask, and v.

Referenced by freg().

boxF32()

static constexpr uint64_t gem5::RiscvISA::boxF32 ( uint32_t  v )

staticconstexpr

Definition at line 94 of file float.hh.

References mask, and v.

Referenced by freg().

div()

template<typename T >

T gem5::RiscvISA::div ( T  rs1, T  rs2  )

inline

Definition at line 195 of file utility.hh.

References rs1, and rs2.

Referenced by gem5::free_bsd::onUDelay(), gem5::linux::onUDelay(), gem5::printSize(), and gem5::BaseIndexingPolicy::setEntry().

divu()

template<typename T >

T gem5::RiscvISA::divu ( T  rs1, T  rs2  )

inline

Definition at line 208 of file utility.hh.

References rs1, and rs2.

EndBitUnion() [1/29]

gem5::RiscvISA::EndBitUnion

(

CacheErrReg

)

EndBitUnion() [2/29]

gem5::RiscvISA::EndBitUnion

(

CauseReg

)

EndBitUnion() [3/29]

gem5::RiscvISA::EndBitUnion

(

Config1Reg

)

EndBitUnion() [4/29]

gem5::RiscvISA::EndBitUnion

(

Config2Reg

)

EndBitUnion() [5/29]

gem5::RiscvISA::EndBitUnion

(

Config3Reg

)

EndBitUnion() [6/29]

gem5::RiscvISA::EndBitUnion

(

ConfigReg

)

EndBitUnion() [7/29]

gem5::RiscvISA::EndBitUnion

(

ContextReg

)

EndBitUnion() [8/29]

gem5::RiscvISA::EndBitUnion

(

EBaseReg

)

EndBitUnion() [9/29]

gem5::RiscvISA::EndBitUnion

(

EntryHiReg

)

EndBitUnion() [10/29]

gem5::RiscvISA::EndBitUnion

(

EntryLoReg

)

EndBitUnion() [11/29]

gem5::RiscvISA::EndBitUnion

(

HWREnaReg

)

EndBitUnion() [12/29]

gem5::RiscvISA::EndBitUnion

(

IndexReg

)

EndBitUnion() [13/29]

gem5::RiscvISA::EndBitUnion

(

IntCtlReg

)

EndBitUnion() [14/29]

gem5::RiscvISA::EndBitUnion

(

INTERRUPT

)

const

Definition at line 802 of file misc.hh.

References RV32, and RV64.

EndBitUnion() [15/29]

gem5::RiscvISA::EndBitUnion

(

MISA

)

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org.

Both the MIP and MIE registers have the same fields, so accesses to either should use this bit union.

EndBitUnion() [16/29]

gem5::RiscvISA::EndBitUnion

(

PageGrainReg

)

EndBitUnion() [17/29]

gem5::RiscvISA::EndBitUnion

(

PageMaskReg

)

EndBitUnion() [18/29]

gem5::RiscvISA::EndBitUnion

(

PerfCntCtlReg

)

EndBitUnion() [19/29]

gem5::RiscvISA::EndBitUnion

(

PRIdReg

)

EndBitUnion() [20/29]

gem5::RiscvISA::EndBitUnion

(

PTESv39

)

EndBitUnion() [21/29]

gem5::RiscvISA::EndBitUnion

(

RandomReg

)

EndBitUnion() [22/29]

gem5::RiscvISA::EndBitUnion

(

SATP

)

Definition at line 49 of file pagetable.hh.

EndBitUnion() [23/29]

gem5::RiscvISA::EndBitUnion

(

SRSCtlReg

)

EndBitUnion() [24/29]

gem5::RiscvISA::EndBitUnion

(

SRSMapReg

)

EndBitUnion() [25/29]

gem5::RiscvISA::EndBitUnion

(

STATUS

)

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, v1.11 and v1.12 in Figure 3.1, accessible at www.riscv.org.

The register is used to control instruction extensions.

EndBitUnion() [26/29]

gem5::RiscvISA::EndBitUnion

(

StatusReg

)

EndBitUnion() [27/29]

gem5::RiscvISA::EndBitUnion

(

WatchHiReg

)

EndBitUnion() [28/29]

gem5::RiscvISA::EndBitUnion

(

WatchLoReg

)

EndBitUnion() [29/29]

gem5::RiscvISA::EndBitUnion

(

WiredReg

)

EndSubBitUnion() [1/4]

gem5::RiscvISA::EndSubBitUnion

(

cu

)

EndSubBitUnion() [2/4]

gem5::RiscvISA::EndSubBitUnion

(

im

)

EndSubBitUnion() [3/4]

gem5::RiscvISA::EndSubBitUnion

(

ip

)

EndSubBitUnion() [4/4]

gem5::RiscvISA::EndSubBitUnion

(

vtype8

)

f16() [1/2]

static constexpr float16_t gem5::RiscvISA::f16 ( freg_t  r )

staticconstexpr

Definition at line 100 of file float.hh.

References r, and unboxF16().

f16() [2/2]

static constexpr float16_t gem5::RiscvISA::f16 ( uint16_t  v )

staticconstexpr

Definition at line 97 of file float.hh.

References v.

f32() [1/2]

static constexpr float32_t gem5::RiscvISA::f32 ( freg_t  r )

staticconstexpr

Definition at line 101 of file float.hh.

References r, and unboxF32().

f32() [2/2]

static constexpr float32_t gem5::RiscvISA::f32 ( uint32_t  v )

staticconstexpr

Definition at line 98 of file float.hh.

References v.

f64() [1/2]

static constexpr float64_t gem5::RiscvISA::f64 ( freg_t  r )

staticconstexpr

Definition at line 102 of file float.hh.

References r.

f64() [2/2]

static constexpr float64_t gem5::RiscvISA::f64 ( uint64_t  v )

staticconstexpr

Definition at line 99 of file float.hh.

References v.

floatRegClass()

constexpr RegClass gem5::RiscvISA::floatRegClass ( FloatRegClass  , FloatRegClassName  , float_reg::NumRegs  , debug::FloatRegs    )

inlineconstexpr

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), and gem5::RiscvISA::ISA::ISA().

freg() [1/4]

static constexpr freg_t gem5::RiscvISA::freg ( float16_t  f )

staticconstexpr

Definition at line 105 of file float.hh.

References boxF16(), and gem5::VegaISA::f.

freg() [2/4]

static constexpr freg_t gem5::RiscvISA::freg ( float32_t  f )

staticconstexpr

Definition at line 106 of file float.hh.

References boxF32(), and gem5::VegaISA::f.

freg() [3/4]

static constexpr freg_t gem5::RiscvISA::freg ( float64_t  f )

staticconstexpr

Definition at line 107 of file float.hh.

References gem5::VegaISA::f.

freg() [4/4]

static constexpr freg_t gem5::RiscvISA::freg ( uint_fast64_t  f )

staticconstexpr

Definition at line 108 of file float.hh.

References gem5::VegaISA::f.

intRegClass()

constexpr RegClass gem5::RiscvISA::intRegClass ( IntRegClass  , IntRegClassName  , int_reg::NumRegs  , debug::IntRegs    )

inlineconstexpr

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), and gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs().

isquietnan()

template<typename T >

bool gem5::RiscvISA::isquietnan ( T  val )

inline

Definition at line 68 of file utility.hh.

isquietnan< double >()

template<>

bool gem5::RiscvISA::isquietnan< double > ( double  val )

inline

Definition at line 81 of file utility.hh.

References gem5::X86ISA::val.

isquietnan< float >()

template<>

bool gem5::RiscvISA::isquietnan< float > ( float  val )

inline

Definition at line 74 of file utility.hh.

References gem5::X86ISA::val.

issignalingnan()

template<typename T >

bool gem5::RiscvISA::issignalingnan ( T  val )

inline

Definition at line 88 of file utility.hh.

issignalingnan< double >()

template<>

bool gem5::RiscvISA::issignalingnan< double > ( double  val )

inline

Definition at line 101 of file utility.hh.

References gem5::X86ISA::val.

issignalingnan< float >()

template<>

bool gem5::RiscvISA::issignalingnan< float > ( float  val )

inline

Definition at line 94 of file utility.hh.

References gem5::X86ISA::val.

miscRegClass()

constexpr RegClass gem5::RiscvISA::miscRegClass ( MiscRegClass  , MiscRegClassName  , NUM_MISCREGS  , debug::MiscRegs    )

inlineconstexpr

Referenced by gem5::RiscvISA::ISA::ISA().

mulh_32()

int32_t gem5::RiscvISA::mulh_32 ( int32_t  rs1, int32_t  rs2  )

inline

Definition at line 167 of file utility.hh.

References rs1, and rs2.

mulh_64()

int64_t gem5::RiscvISA::mulh_64 ( int64_t  rs1, int64_t  rs2  )

inline

Definition at line 173 of file utility.hh.

References mulhu_64(), rs1, and rs2.

mulhsu_32()

int32_t gem5::RiscvISA::mulhsu_32 ( int32_t  rs1, uint32_t  rs2  )

inline

Definition at line 181 of file utility.hh.

References rs1, and rs2.

mulhsu_64()

int64_t gem5::RiscvISA::mulhsu_64 ( int64_t  rs1, uint64_t  rs2  )

inline

Definition at line 187 of file utility.hh.

References mulhu_64(), rs1, and rs2.

mulhu_32()

uint32_t gem5::RiscvISA::mulhu_32 ( uint32_t  rs1, uint32_t  rs2  )

inline

Definition at line 142 of file utility.hh.

References rs1, and rs2.

mulhu_64()

uint64_t gem5::RiscvISA::mulhu_64 ( uint64_t  rs1, uint64_t  rs2  )

inline

Definition at line 148 of file utility.hh.

References gem5::ArmISA::lo, rs1, and rs2.

Referenced by mulh_64(), and mulhsu_64().

registerName()

std::string gem5::RiscvISA::registerName ( RegId  reg )

inline

Definition at line 108 of file utility.hh.

References gem5::FloatRegClass, gem5::IntRegClass, gem5::RiscvISA::int_reg::NumArchRegs, gem5::RiscvISA::float_reg::NumRegs, gem5::X86ISA::reg, gem5::RiscvISA::int_reg::RegNames, and gem5::RiscvISA::float_reg::RegNames.

Referenced by gem5::RiscvISA::BSOp::generateDisassembly(), gem5::RiscvISA::CompRegOp::generateDisassembly(), gem5::RiscvISA::RegOp::generateDisassembly(), gem5::RiscvISA::Load::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::Store::generateDisassembly(), gem5::RiscvISA::LoadReservedMicro::generateDisassembly(), gem5::RiscvISA::SystemOp::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::StoreCondMicro::generateDisassembly(), gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), and gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly().

rem()

template<typename T >

T gem5::RiscvISA::rem ( T  rs1, T  rs2  )

inline

Definition at line 218 of file utility.hh.

References rs1, and rs2.

remu()

template<typename T >

T gem5::RiscvISA::remu ( T  rs1, T  rs2  )

inline

Definition at line 231 of file utility.hh.

References rs1, and rs2.

rvTypeFlags()

template<typename... T>

constexpr uint64_t gem5::RiscvISA::rvTypeFlags ( T...  args )

constexpr

Definition at line 490 of file misc.hh.

SubBitUnion() [1/3]

gem5::RiscvISA::SubBitUnion	(	im	,
		15	,
		8
	)

SubBitUnion() [2/3]

gem5::RiscvISA::SubBitUnion	(	ip	,
		15	,
		8
	)

SubBitUnion() [3/3]

gem5::RiscvISA::SubBitUnion	(	vtype8	,
		39	,
		32
	)

unameFunc32()

static SyscallReturn gem5::RiscvISA::unameFunc32 ( SyscallDesc *  desc, ThreadContext *  tc, VPtr< Linux::utsname >  name  )

static

Target uname() handler.

Definition at line 113 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

unameFunc64()

static SyscallReturn gem5::RiscvISA::unameFunc64 ( SyscallDesc *  desc, ThreadContext *  tc, VPtr< Linux::utsname >  name  )

static

Target uname() handler.

Definition at line 98 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

unboxF16()

static constexpr uint16_t gem5::RiscvISA::unboxF16 ( uint64_t  v )

staticconstexpr

Definition at line 73 of file float.hh.

References gem5::bits(), mask, and v.

Referenced by f16().

unboxF32()

static constexpr uint32_t gem5::RiscvISA::unboxF32 ( uint64_t  v )

staticconstexpr

Definition at line 84 of file float.hh.

References gem5::bits(), mask, and v.

Referenced by f32().

Variable Documentation

_rvk_emu_aes_fwd_sbox

const uint8_t gem5::RiscvISA::_rvk_emu_aes_fwd_sbox[256]

Initial value:

= {
    0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, 0x30, 0x01, 0x67, 0x2B,
    0xFE, 0xD7, 0xAB, 0x76, 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
    0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, 0xB7, 0xFD, 0x93, 0x26,
    0x36, 0x3F, 0xF7, 0xCC, 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
    0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, 0x07, 0x12, 0x80, 0xE2,
    0xEB, 0x27, 0xB2, 0x75, 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
    0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, 0x53, 0xD1, 0x00, 0xED,
    0x20, 0xFC, 0xB1, 0x5B, 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
    0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, 0x45, 0xF9, 0x02, 0x7F,
    0x50, 0x3C, 0x9F, 0xA8, 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
    0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, 0xCD, 0x0C, 0x13, 0xEC,
    0x5F, 0x97, 0x44, 0x17, 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
    0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, 0x46, 0xEE, 0xB8, 0x14,
    0xDE, 0x5E, 0x0B, 0xDB, 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
    0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, 0xE7, 0xC8, 0x37, 0x6D,
    0x8D, 0xD5, 0x4E, 0xA9, 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
    0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, 0xE8, 0xDD, 0x74, 0x1F,
    0x4B, 0xBD, 0x8B, 0x8A, 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
    0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, 0xE1, 0xF8, 0x98, 0x11,
    0x69, 0xD9, 0x8E, 0x94, 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
    0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, 0x41, 0x99, 0x2D, 0x0F,
    0xB0, 0x54, 0xBB, 0x16
}

Ref: https://github.com/rvkrypto/rvkrypto-fips.

Definition at line 47 of file rvk.hh.

Referenced by _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64es(), and _rvk_emu_aes64ks1i().

_rvk_emu_aes_inv_sbox

const uint8_t gem5::RiscvISA::_rvk_emu_aes_inv_sbox[256]

Initial value:

= {
    0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, 0xBF, 0x40, 0xA3, 0x9E,
    0x81, 0xF3, 0xD7, 0xFB, 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
    0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, 0x54, 0x7B, 0x94, 0x32,
    0xA6, 0xC2, 0x23, 0x3D, 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
    0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, 0x76, 0x5B, 0xA2, 0x49,
    0x6D, 0x8B, 0xD1, 0x25, 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
    0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, 0x6C, 0x70, 0x48, 0x50,
    0xFD, 0xED, 0xB9, 0xDA, 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
    0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, 0xF7, 0xE4, 0x58, 0x05,
    0xB8, 0xB3, 0x45, 0x06, 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
    0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, 0x3A, 0x91, 0x11, 0x41,
    0x4F, 0x67, 0xDC, 0xEA, 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
    0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, 0xE2, 0xF9, 0x37, 0xE8,
    0x1C, 0x75, 0xDF, 0x6E, 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
    0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, 0xFC, 0x56, 0x3E, 0x4B,
    0xC6, 0xD2, 0x79, 0x20, 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
    0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, 0xB1, 0x12, 0x10, 0x59,
    0x27, 0x80, 0xEC, 0x5F, 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
    0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, 0xA0, 0xE0, 0x3B, 0x4D,
    0xAE, 0x2A, 0xF5, 0xB0, 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
    0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, 0xE1, 0x69, 0x14, 0x63,
    0x55, 0x21, 0x0C, 0x7D
}

Definition at line 73 of file rvk.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), and _rvk_emu_aes64ds().

_rvk_emu_sm4_sbox

const uint8_t gem5::RiscvISA::_rvk_emu_sm4_sbox[256]

Initial value:

= {
    0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2,
    0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3,
    0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4,
    0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62,
    0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA,
    0x75, 0x8F, 0x3F, 0xA6, 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA,
    0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2,
    0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35,
    0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B,
    0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52,
    0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, 0x8A, 0xD2,
    0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1,
    0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30,
    0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60,
    0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45,
    0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51,
    0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41,
    0x1F, 0x10, 0x5A, 0xD8, 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD,
    0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A,
    0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84,
    0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E,
    0xD7, 0xCB, 0x39, 0x48
}

Definition at line 99 of file rvk.hh.

Referenced by _rvk_emu_sm4ed(), and _rvk_emu_sm4ks().

a

Bitfield<6> gem5::RiscvISA::a

Definition at line 69 of file pagetable.hh.

Referenced by _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), and _rvk_emu_clmulh_64().

all

Bitfield<31, 0> gem5::RiscvISA::all

Definition at line 77 of file types.hh.

Referenced by gem5::BaseRemoteGDB::cmdIsThreadAlive(), gem5::BaseRemoteGDB::cmdSetThread(), gem5::networking::Ip6Hdr::extensionLength(), gem5::networking::Ip6Hdr::getExt(), gem5::networking::IpHdr::options(), gem5::networking::TcpHdr::options(), gem5::networking::Ip6Hdr::proto(), gem5::System::remove(), gem5::System::schedule(), gem5::ArmISA::VldSingleOp::VldSingleOp(), and gem5::ArmISA::VstSingleOp::VstSingleOp().

amofunct

Bitfield<31, 27> gem5::RiscvISA::amofunct

Definition at line 118 of file types.hh.

AMOTempReg

constexpr auto & gem5::RiscvISA::AMOTempReg = int_reg::Ureg0

Definition at line 144 of file int.hh.

aq

Bitfield<26> gem5::RiscvISA::aq

Definition at line 119 of file types.hh.

ar

Bitfield<12, 10> gem5::RiscvISA::ar

Definition at line 225 of file pra_constants.hh.

ArgumentRegs

constexpr RegId gem5::RiscvISA::ArgumentRegs[]

inlineconstexpr

Initial value:

= {
    int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
    int_reg::A4, int_reg::A5, int_reg::A6, int_reg::A7
}

Definition at line 147 of file int.hh.

Referenced by gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< ArmISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< RiscvISA::RegABI32, ABI > &&std::is_integral_v< Arg > &&ABI::template IsWideV< Arg > > >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_base_of_v< GenericSyscallABI64, ABI > &&std::is_integral_v< Arg > > >::get(), gem5::guest_abi::Argument< ABI, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&!ABI::template IsWideV< Arg > > >::get(), gem5::guest_abi::Argument< X86ISA::EmuLinux::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&X86ISA::EmuLinux::SyscallABI32::IsWideV< Arg > > >::get(), and gem5::guest_abi::Argument< SparcISA::SEWorkload::SyscallABI32, Arg, typename std::enable_if_t< std::is_integral_v< Arg > &&SparcISA::SEWorkload::SyscallABI32::IsWideV< Arg > > >::get().

aseDn

Bitfield<12, 8> gem5::RiscvISA::aseDn

Definition at line 83 of file pra_constants.hh.

aseUp

gem5::RiscvISA::aseUp

Definition at line 79 of file pra_constants.hh.

asid

Bitfield< 23, 16 > gem5::RiscvISA::asid

Definition at line 47 of file pagetable.hh.

Referenced by gem5::buildKey().

at

Bitfield<14, 13> gem5::RiscvISA::at

Definition at line 224 of file pra_constants.hh.

badVPN2

Bitfield<22, 4> gem5::RiscvISA::badVPN2

Definition at line 67 of file pra_constants.hh.

be

Bitfield<15> gem5::RiscvISA::be

Definition at line 223 of file pra_constants.hh.

bev

Bitfield<22> gem5::RiscvISA::bev

Definition at line 117 of file pra_constants.hh.

bimm12bit11

Bitfield<7> gem5::RiscvISA::bimm12bit11

Definition at line 98 of file types.hh.

bimm12bits10to5

Bitfield<30, 25> gem5::RiscvISA::bimm12bits10to5

Definition at line 100 of file types.hh.

bimm12bits4to1

Bitfield<11, 8> gem5::RiscvISA::bimm12bits4to1

Definition at line 99 of file types.hh.

bit30

Bitfield<30> gem5::RiscvISA::bit30

Definition at line 170 of file types.hh.

bit31

Bitfield<31> gem5::RiscvISA::bit31

Definition at line 169 of file types.hh.

bit31_25

Bitfield<31, 25> gem5::RiscvISA::bit31_25

Definition at line 177 of file types.hh.

bit31_30

Bitfield<31, 30> gem5::RiscvISA::bit31_30

Definition at line 173 of file types.hh.

c

Bitfield<5, 3> gem5::RiscvISA::c

Definition at line 59 of file pra_constants.hh.

Referenced by gem5::RiscvISA::PCState::compressed().

c2

Bitfield<6> gem5::RiscvISA::c2

Definition at line 241 of file pra_constants.hh.

ca

Bitfield<2> gem5::RiscvISA::ca

Definition at line 245 of file pra_constants.hh.

CAUSE_INTERRUPT_MASKS

const RegVal gem5::RiscvISA::CAUSE_INTERRUPT_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = (1ULL << 31),
    [RV64] = (1ULL << 63),
}

Definition at line 920 of file misc.hh.

Referenced by gem5::RiscvISA::RiscvFault::invoke().

ce

Bitfield<29, 28> gem5::RiscvISA::ce

Definition at line 180 of file pra_constants.hh.

cfunct1

Bitfield<12> gem5::RiscvISA::cfunct1

Definition at line 123 of file types.hh.

cfunct2high

Bitfield<11, 10> gem5::RiscvISA::cfunct2high

Definition at line 124 of file types.hh.

cfunct2low

Bitfield< 6, 5> gem5::RiscvISA::cfunct2low

Definition at line 125 of file types.hh.

cimm1

Bitfield<12> gem5::RiscvISA::cimm1

Definition at line 147 of file types.hh.

cimm2

Bitfield< 6, 5> gem5::RiscvISA::cimm2

Definition at line 146 of file types.hh.

cimm3

Bitfield<12, 10> gem5::RiscvISA::cimm3

Definition at line 145 of file types.hh.

cimm5

Bitfield< 6, 2> gem5::RiscvISA::cimm5

Definition at line 144 of file types.hh.

cimm6

Bitfield<12, 7> gem5::RiscvISA::cimm6

Definition at line 143 of file types.hh.

cimm8

Bitfield<12, 5> gem5::RiscvISA::cimm8

Definition at line 142 of file types.hh.

cjumpimm

Bitfield<12, 2> gem5::RiscvISA::cjumpimm

Definition at line 133 of file types.hh.

cjumpimm10to10

Bitfield< 8, 8> gem5::RiscvISA::cjumpimm10to10

Definition at line 140 of file types.hh.

cjumpimm3to1

Bitfield< 5, 3> gem5::RiscvISA::cjumpimm3to1

Definition at line 134 of file types.hh.

cjumpimm4to4

Bitfield<11, 11> gem5::RiscvISA::cjumpimm4to4

Definition at line 135 of file types.hh.

cjumpimm5to5

Bitfield< 2, 2> gem5::RiscvISA::cjumpimm5to5

Definition at line 136 of file types.hh.

cjumpimm6to6

Bitfield< 7, 7> gem5::RiscvISA::cjumpimm6to6

Definition at line 137 of file types.hh.

cjumpimm7to7

Bitfield< 6, 6> gem5::RiscvISA::cjumpimm7to7

Definition at line 138 of file types.hh.

cjumpimm9to8

Bitfield<10, 9> gem5::RiscvISA::cjumpimm9to8

Definition at line 139 of file types.hh.

cjumpimmsign

Bitfield<12> gem5::RiscvISA::cjumpimmsign

Definition at line 141 of file types.hh.

coId

Bitfield<23, 16> gem5::RiscvISA::coId

Definition at line 205 of file pra_constants.hh.

compressed

Bitfield<61> gem5::RiscvISA::compressed

Definition at line 61 of file types.hh.

conv_sgn

Bitfield<24, 20> gem5::RiscvISA::conv_sgn

Definition at line 115 of file types.hh.

coOp

gem5::RiscvISA::coOp

Definition at line 204 of file pra_constants.hh.

copcode

Bitfield<15, 13> gem5::RiscvISA::copcode

Definition at line 122 of file types.hh.

cpuNum

Bitfield<9, 9> gem5::RiscvISA::cpuNum

Definition at line 215 of file pra_constants.hh.

CSRData

const std::unordered_map<int, CSRMetadata> gem5::RiscvISA::CSRData

Definition at line 494 of file misc.hh.

Referenced by gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::ISA::getCSRDataMap(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::setRegNoEffectWithMask(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), and gem5::setRegWithMask().

csrimm

Bitfield<19, 15> gem5::RiscvISA::csrimm

Definition at line 108 of file types.hh.

CSRMasks

const std::unordered_map<int, RegVal> gem5::RiscvISA::CSRMasks[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = {{CSR_USTATUS, USTATUS_MASKS[RV32]},
              {CSR_UIE, UI_MASK},
              {CSR_UIP, UI_MASK},
              {CSR_FFLAGS, FFLAGS_MASK},
              {CSR_FRM, FRM_MASK},
              {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
              {CSR_SSTATUS, SSTATUS_MASKS[RV32]},
              {CSR_SIE, SI_MASK},
              {CSR_SIP, SI_MASK},
              {CSR_MSTATUS, MSTATUS_MASKS[RV32]},
              {CSR_MISA, MISA_MASKS[RV32]},
              {CSR_MIE, MI_MASK},
              {CSR_MSTATUSH, MSTATUSH_MASKS},
              {CSR_MIP, MI_MASK}},
    [RV64] = {{CSR_USTATUS, USTATUS_MASKS[RV64]},
              {CSR_UIE, UI_MASK},
              {CSR_UIP, UI_MASK},
              {CSR_FFLAGS, FFLAGS_MASK},
              {CSR_FRM, FRM_MASK},
              {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
              {CSR_SSTATUS, SSTATUS_MASKS[RV64]},
              {CSR_SIE, SI_MASK},
              {CSR_SIP, SI_MASK},
              {CSR_MSTATUS, MSTATUS_MASKS[RV64]},
              {CSR_MISA, MISA_MASKS[RV64]},
              {CSR_MIE, MI_MASK},
              {CSR_MIP, MI_MASK}},
}

Definition at line 925 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::getCSRMaskMap(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::setRegNoEffectWithMask(), and gem5::setRegWithMask().

css

Bitfield<3, 0> gem5::RiscvISA::css

Definition at line 163 of file pra_constants.hh.

cu0

Bitfield<28> gem5::RiscvISA::cu0

Definition at line 110 of file pra_constants.hh.

cu1

Bitfield<29> gem5::RiscvISA::cu1

Definition at line 109 of file pra_constants.hh.

cu2

Bitfield<30> gem5::RiscvISA::cu2

Definition at line 108 of file pra_constants.hh.

cu3

Bitfield<31> gem5::RiscvISA::cu3

Definition at line 106 of file pra_constants.hh.

d

Bitfield< 2 > gem5::RiscvISA::d

Definition at line 68 of file pagetable.hh.

da

Bitfield<9, 7> gem5::RiscvISA::da

Definition at line 240 of file pra_constants.hh.

dc

Bitfield<27> gem5::RiscvISA::dc

Definition at line 181 of file pra_constants.hh.

dl

Bitfield<12, 10> gem5::RiscvISA::dl

Definition at line 239 of file pra_constants.hh.

ds

Bitfield<15, 13> gem5::RiscvISA::ds

Definition at line 238 of file pra_constants.hh.

dspp

Bitfield<10> gem5::RiscvISA::dspp

Definition at line 265 of file pra_constants.hh.

eb

Bitfield<25> gem5::RiscvISA::eb

Definition at line 315 of file pra_constants.hh.

ec

Bitfield<30> gem5::RiscvISA::ec

Definition at line 310 of file pra_constants.hh.

ed

Bitfield<29> gem5::RiscvISA::ed

Definition at line 311 of file pra_constants.hh.

ee

Bitfield<26> gem5::RiscvISA::ee

Definition at line 314 of file pra_constants.hh.

eicss

Bitfield<21, 18> gem5::RiscvISA::eicss

Definition at line 157 of file pra_constants.hh.

elpa

Bitfield<29> gem5::RiscvISA::elpa

Definition at line 80 of file pra_constants.hh.

ep

Bitfield<1> gem5::RiscvISA::ep

Definition at line 246 of file pra_constants.hh.

erl

Bitfield<2> gem5::RiscvISA::erl

Definition at line 140 of file pra_constants.hh.

es

Bitfield<27> gem5::RiscvISA::es

Definition at line 313 of file pra_constants.hh.

esp

Bitfield<28> gem5::RiscvISA::esp

Definition at line 81 of file pra_constants.hh.

ess

Bitfield<15, 12> gem5::RiscvISA::ess

Definition at line 159 of file pra_constants.hh.

et

Bitfield<28> gem5::RiscvISA::et

Definition at line 312 of file pra_constants.hh.

event

Bitfield<10, 5> gem5::RiscvISA::event

Definition at line 300 of file pra_constants.hh.

excCode

Bitfield<6, 2> gem5::RiscvISA::excCode

Definition at line 199 of file pra_constants.hh.

exceptionBase

gem5::RiscvISA::exceptionBase

Definition at line 213 of file pra_constants.hh.

exl

Bitfield< 0 > gem5::RiscvISA::exl

Definition at line 141 of file pra_constants.hh.

fc1

Bitfield<11, 7> gem5::RiscvISA::fc1

Definition at line 130 of file types.hh.

fc2

Bitfield< 6, 2> gem5::RiscvISA::fc2

Definition at line 131 of file types.hh.

fd

Bitfield<11, 7> gem5::RiscvISA::fd

Definition at line 110 of file types.hh.

FFLAGS_MASK

const RegVal gem5::RiscvISA::FFLAGS_MASK = (1 << FRM_OFFSET) - 1

Definition at line 917 of file misc.hh.

fill

Bitfield< 61, 40 > gem5::RiscvISA::fill

Definition at line 57 of file pra_constants.hh.

fp

Bitfield<0> gem5::RiscvISA::fp

Definition at line 247 of file pra_constants.hh.

fp2

Bitfield< 4, 2> gem5::RiscvISA::fp2

Definition at line 132 of file types.hh.

fr

Bitfield<26> gem5::RiscvISA::fr

Definition at line 113 of file pra_constants.hh.

FRM_MASK

const RegVal gem5::RiscvISA::FRM_MASK = 0x7

Definition at line 918 of file misc.hh.

FRM_OFFSET

const off_t gem5::RiscvISA::FRM_OFFSET = 5

Definition at line 819 of file misc.hh.

fs

Bitfield<14, 13> gem5::RiscvISA::fs

Definition at line 743 of file misc.hh.

fs1

Bitfield<19, 15> gem5::RiscvISA::fs1

Definition at line 111 of file types.hh.

fs2

Bitfield<24, 20> gem5::RiscvISA::fs2

Definition at line 112 of file types.hh.

fs3

Bitfield<31, 27> gem5::RiscvISA::fs3

Definition at line 113 of file types.hh.

FS_OFFSET

const off_t gem5::RiscvISA::FS_OFFSET = 13

Definition at line 818 of file misc.hh.

funct12

Bitfield<31, 20> gem5::RiscvISA::funct12

Definition at line 107 of file types.hh.

funct2

Bitfield<26, 25> gem5::RiscvISA::funct2

Definition at line 116 of file types.hh.

funct3

Bitfield<14, 12> gem5::RiscvISA::funct3

Definition at line 79 of file types.hh.

funct7

Bitfield<31, 25> gem5::RiscvISA::funct7

Definition at line 82 of file types.hh.

g

Bitfield< 30 > gem5::RiscvISA::g

Definition at line 70 of file pagetable.hh.

hss

gem5::RiscvISA::hss

Definition at line 155 of file pra_constants.hh.

i

Bitfield< 2 > gem5::RiscvISA::i

Definition at line 279 of file pra_constants.hh.

Referenced by _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_xperm32(), _rvk_emu_xperm64(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::RiscvISA::ISA::setMiscReg(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), and gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs().

ia

Bitfield<18, 16> gem5::RiscvISA::ia

Definition at line 237 of file pra_constants.hh.

ie

Bitfield< 4 > gem5::RiscvISA::ie

Definition at line 142 of file pra_constants.hh.

il

Bitfield<21, 19> gem5::RiscvISA::il

Definition at line 236 of file pra_constants.hh.

im0

Bitfield<8> gem5::RiscvISA::im0

Definition at line 132 of file pra_constants.hh.

im1

Bitfield<9> gem5::RiscvISA::im1

Definition at line 131 of file pra_constants.hh.

im2

Bitfield<10> gem5::RiscvISA::im2

Definition at line 130 of file pra_constants.hh.

im3

Bitfield<11> gem5::RiscvISA::im3

Definition at line 129 of file pra_constants.hh.

im4

Bitfield<12> gem5::RiscvISA::im4

Definition at line 128 of file pra_constants.hh.

im5

Bitfield<13> gem5::RiscvISA::im5

Definition at line 127 of file pra_constants.hh.

im6

Bitfield<14> gem5::RiscvISA::im6

Definition at line 126 of file pra_constants.hh.

imm12

Bitfield<31, 20> gem5::RiscvISA::imm12

Definition at line 88 of file types.hh.

imm20

Bitfield<31, 12> gem5::RiscvISA::imm20

Definition at line 96 of file types.hh.

imm5

Bitfield<11, 7> gem5::RiscvISA::imm5

Definition at line 93 of file types.hh.

imm7

Bitfield<31, 25> gem5::RiscvISA::imm7

Definition at line 94 of file types.hh.

immsign

Bitfield<31> gem5::RiscvISA::immsign

Definition at line 101 of file types.hh.

impl

Bitfield< 4, 3 > gem5::RiscvISA::impl

Definition at line 93 of file pra_constants.hh.

index

Bitfield< 22, 0 > gem5::RiscvISA::index

Definition at line 47 of file pra_constants.hh.

Referenced by gem5::RiscvISA::Interrupts::clear(), and gem5::RiscvISA::Interrupts::post().

ip0

Bitfield<8> gem5::RiscvISA::ip0

Definition at line 196 of file pra_constants.hh.

ip1

Bitfield<9> gem5::RiscvISA::ip1

Definition at line 195 of file pra_constants.hh.

ip2

Bitfield<10> gem5::RiscvISA::ip2

Definition at line 194 of file pra_constants.hh.

ip3

Bitfield<11> gem5::RiscvISA::ip3

Definition at line 193 of file pra_constants.hh.

ip4

Bitfield<12> gem5::RiscvISA::ip4

Definition at line 192 of file pra_constants.hh.

ip5

Bitfield<13> gem5::RiscvISA::ip5

Definition at line 191 of file pra_constants.hh.

ip6

Bitfield<14> gem5::RiscvISA::ip6

Definition at line 190 of file pra_constants.hh.

ipl

Bitfield<15, 10> gem5::RiscvISA::ipl

Definition at line 123 of file pra_constants.hh.

ippci

Bitfield<28, 26> gem5::RiscvISA::ippci

Definition at line 147 of file pra_constants.hh.

ipti

gem5::RiscvISA::ipti

Definition at line 146 of file pra_constants.hh.

is

Bitfield<24, 22> gem5::RiscvISA::is

Definition at line 235 of file pra_constants.hh.

ISA_EXT_C_MASK

const RegVal gem5::RiscvISA::ISA_EXT_C_MASK = 1UL << ('c' - 'a')

Definition at line 826 of file misc.hh.

ISA_EXT_MASK

const RegVal gem5::RiscvISA::ISA_EXT_MASK = mask(26)

Definition at line 825 of file misc.hh.

ISA_MXL_MASKS

const RegVal gem5::RiscvISA::ISA_MXL_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 3ULL << MXL_OFFSETS[RV32],
    [RV64] = 3ULL << MXL_OFFSETS[RV64],
}

Definition at line 821 of file misc.hh.

iv

Bitfield<23> gem5::RiscvISA::iv

Definition at line 184 of file pra_constants.hh.

k

Bitfield<1> gem5::RiscvISA::k

Definition at line 304 of file pra_constants.hh.

k0

Bitfield<2, 0> gem5::RiscvISA::k0

Definition at line 229 of file pra_constants.hh.

k23

Bitfield<30, 28> gem5::RiscvISA::k23

Definition at line 220 of file pra_constants.hh.

ksu

Bitfield<4, 3> gem5::RiscvISA::ksu

Definition at line 137 of file pra_constants.hh.

ku

Bitfield<27, 25> gem5::RiscvISA::ku

Definition at line 221 of file pra_constants.hh.

l

Bitfield<5> gem5::RiscvISA::l

Definition at line 323 of file pra_constants.hh.

LEVEL_BITS

const Addr gem5::RiscvISA::LEVEL_BITS = 9

Definition at line 60 of file pagetable.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::setupWalk(), and gem5::RiscvISA::Walker::WalkerState::stepWalk().

LEVEL_MASK

const Addr gem5::RiscvISA::LEVEL_MASK = (1 << LEVEL_BITS) - 1

Definition at line 61 of file pagetable.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::setupWalk(), and gem5::RiscvISA::Walker::WalkerState::stepWalk().

lpa

Bitfield<7> gem5::RiscvISA::lpa

Definition at line 267 of file pra_constants.hh.

lumop

Bitfield<24, 20> gem5::RiscvISA::lumop

Definition at line 159 of file types.hh.

m5func

Bitfield<31, 25> gem5::RiscvISA::m5func

Definition at line 149 of file types.hh.

mask

Bitfield< 11, 3 > gem5::RiscvISA::mask

Definition at line 73 of file pra_constants.hh.

Referenced by _rvk_emu_xperm32(), _rvk_emu_xperm64(), boxF16(), boxF32(), gem5::RiscvISA::Interrupts::getInterrupt(), gem5::RiscvISA::Interrupts::globalMask(), gem5::setRegNoEffectWithMask(), gem5::setRegWithMask(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), unboxF16(), and unboxF32().

maskx

Bitfield<12, 11> gem5::RiscvISA::maskx

Definition at line 74 of file pra_constants.hh.

MBE_OFFSET

const off_t gem5::RiscvISA::MBE_OFFSET[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 5,
    [RV64] = 37,
}

Definition at line 808 of file misc.hh.

md

Bitfield<5> gem5::RiscvISA::md

Definition at line 242 of file pra_constants.hh.

MEI_MASK

const RegVal gem5::RiscvISA::MEI_MASK = 1ULL << 11

Definition at line 901 of file misc.hh.

mew

Bitfield<28> gem5::RiscvISA::mew

Definition at line 156 of file types.hh.

MI_MASK

const RegVal gem5::RiscvISA::MI_MASK

Initial value:

= MEI_MASK | SEI_MASK | UEI_MASK |
                       MTI_MASK | STI_MASK | UTI_MASK |
                       MSI_MASK | SSI_MASK | USI_MASK

Definition at line 910 of file misc.hh.

mie

Bitfield<3> gem5::RiscvISA::mie

Definition at line 750 of file misc.hh.

MISA_MASKS

const RegVal gem5::RiscvISA::MISA_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = ISA_MXL_MASKS[RV32] | ISA_EXT_MASK,
    [RV64] = ISA_MXL_MASKS[RV64] | ISA_EXT_MASK,
}

Definition at line 827 of file misc.hh.

MiscRegNames

const std::array<const char *, NUM_MISCREGS> gem5::RiscvISA::MiscRegNames

Definition at line 66 of file isa.cc.

Referenced by gem5::RiscvISA::ISA::readMiscRegNoEffect(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::RiscvISA::ISA::setMiscRegNoEffect().

mmuSize

Bitfield<30, 25> gem5::RiscvISA::mmuSize

Definition at line 234 of file pra_constants.hh.

mode

gem5::RiscvISA::mode

Definition at line 46 of file pagetable.hh.

Referenced by gem5::RiscvISA::MMU::getMemPriv(), gem5::RiscvISA::Walker::WalkerState::initState(), gem5::RiscvISA::Walker::WalkerState::pageFault(), gem5::RiscvISA::Walker::WalkerState::recvPacket(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), and gem5::RiscvISA::MMU::translateFunctional().

mop

Bitfield<27, 26> gem5::RiscvISA::mop

Definition at line 157 of file types.hh.

mpie

Bitfield<7> gem5::RiscvISA::mpie

Definition at line 747 of file misc.hh.

mpp

Bitfield<12, 11> gem5::RiscvISA::mpp

Definition at line 744 of file misc.hh.

mprv

Bitfield<17> gem5::RiscvISA::mprv

Definition at line 741 of file misc.hh.

msi

Bitfield<3> gem5::RiscvISA::msi

Definition at line 799 of file misc.hh.

MSI_MASK

const RegVal gem5::RiscvISA::MSI_MASK = 1ULL << 3

Definition at line 907 of file misc.hh.

MSTATUS_MASKS

const RegVal gem5::RiscvISA::MSTATUS_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = STATUS_SD_MASKS[RV32] | STATUS_TSR_MASK | STATUS_TW_MASK |
             STATUS_TVM_MASK | STATUS_MXR_MASK | STATUS_SUM_MASK |
             STATUS_MPRV_MASK | STATUS_XS_MASK | STATUS_FS_MASK |
             STATUS_VS_MASK | STATUS_MPP_MASK | STATUS_SPP_MASK |
             STATUS_MPIE_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK |
             STATUS_MIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK,
    [RV64] = STATUS_SD_MASKS[RV64] | STATUS_MBE_MASK[RV64] |
             STATUS_SBE_MASK[RV64] | STATUS_SXL_MASK | STATUS_UXL_MASK |
             STATUS_TSR_MASK | STATUS_TW_MASK | STATUS_TVM_MASK |
             STATUS_MXR_MASK | STATUS_SUM_MASK | STATUS_MPRV_MASK |
             STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK|
             STATUS_MPP_MASK | STATUS_SPP_MASK | STATUS_MPIE_MASK |
             STATUS_SPIE_MASK | STATUS_UPIE_MASK | STATUS_MIE_MASK |
             STATUS_SIE_MASK | STATUS_UIE_MASK,
}

Definition at line 864 of file misc.hh.

MSTATUSH_MASKS

const RegVal gem5::RiscvISA::MSTATUSH_MASKS = STATUS_MBE_MASK[RV32] | STATUS_SBE_MASK[RV32]

Definition at line 881 of file misc.hh.

mt

Bitfield< 2 > gem5::RiscvISA::mt

Definition at line 226 of file pra_constants.hh.

mti

Bitfield<7> gem5::RiscvISA::mti

Definition at line 796 of file misc.hh.

MTI_MASK

const RegVal gem5::RiscvISA::MTI_MASK = 1ULL << 7

Definition at line 904 of file misc.hh.

mx

Bitfield<24> gem5::RiscvISA::mx

Definition at line 115 of file pra_constants.hh.

mxr

Bitfield<19> gem5::RiscvISA::mxr

Definition at line 739 of file misc.hh.

nf

Bitfield<31, 29> gem5::RiscvISA::nf

Definition at line 155 of file types.hh.

nmi

Bitfield<19> gem5::RiscvISA::nmi

Definition at line 120 of file pra_constants.hh.

opcode

Bitfield< 6, 0> gem5::RiscvISA::opcode

Definition at line 75 of file types.hh.

opcode5

Bitfield< 6, 2> gem5::RiscvISA::opcode5

Definition at line 74 of file types.hh.

p

Bitfield<0> gem5::RiscvISA::p

Definition at line 326 of file pra_constants.hh.

Referenced by gem5::RiscvISA::BareMetal::BareMetal().

PageBytes

const Addr gem5::RiscvISA::PageBytes = 1ULL << PageShift

Definition at line 54 of file page_size.hh.

Referenced by gem5::RiscvISA::MMU::translateFunctional().

PageShift

const Addr gem5::RiscvISA::PageShift = 12

Definition at line 53 of file page_size.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::startFunctional(), and gem5::RiscvISA::Walker::WalkerState::stepWalk().

pc

Bitfield<4> gem5::RiscvISA::pc

Definition at line 243 of file pra_constants.hh.

Referenced by gem5::RiscvISA::RiscvStaticInst::advancePC(), gem5::RiscvISA::RiscvMicroInst::advancePC(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::RiscvISA::Decoder::moreBytes(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), and gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs().

pci

Bitfield<26> gem5::RiscvISA::pci

Definition at line 182 of file pra_constants.hh.

perm

Bitfield<3, 1> gem5::RiscvISA::perm

Definition at line 72 of file pagetable.hh.

Referenced by gem5::ruby::CacheMemory::recordCacheContents().

pfn

Bitfield<29, 6> gem5::RiscvISA::pfn

Definition at line 58 of file pra_constants.hh.

ppn

gem5::RiscvISA::ppn

Definition at line 48 of file pagetable.hh.

ppn0

Bitfield<18, 10> gem5::RiscvISA::ppn0

Definition at line 67 of file pagetable.hh.

ppn1

Bitfield<27, 19> gem5::RiscvISA::ppn1

Definition at line 66 of file pagetable.hh.

ppn2

Bitfield<53, 28> gem5::RiscvISA::ppn2

Definition at line 65 of file pagetable.hh.

pred

Bitfield<27, 24> gem5::RiscvISA::pred

Definition at line 91 of file types.hh.

Referenced by gem5::branch_prediction::TAGEBase::baseUpdate(), gem5::branch_prediction::TAGEBase::condBranchUpdate(), gem5::MSHR::promoteIf(), gem5::MSHR::promoteReadable(), gem5::MSHR::promoteWritable(), and gem5::branch_prediction::MultiperspectivePerceptron::train().

procId

Bitfield<15, 8> gem5::RiscvISA::procId

Definition at line 206 of file pra_constants.hh.

pss

Bitfield<9, 6> gem5::RiscvISA::pss

Definition at line 161 of file pra_constants.hh.

pState

Bitfield<7, 6> gem5::RiscvISA::pState

Definition at line 322 of file pra_constants.hh.

pTagLo

gem5::RiscvISA::pTagLo

Definition at line 321 of file pra_constants.hh.

pteBase

gem5::RiscvISA::pteBase

Definition at line 66 of file pra_constants.hh.

px

Bitfield<23> gem5::RiscvISA::px

Definition at line 116 of file pra_constants.hh.

quadRant

Bitfield< 1, 0> gem5::RiscvISA::quadRant

Definition at line 73 of file types.hh.

r

Bitfield< 1 > gem5::RiscvISA::r

Definition at line 75 of file pagetable.hh.

Referenced by _rvk_emu_xperm32(), _rvk_emu_xperm64(), f16(), f32(), f64(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), and gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs().

r0

Bitfield<3> gem5::RiscvISA::r0

Definition at line 139 of file pra_constants.hh.

random

gem5::RiscvISA::random

Definition at line 53 of file pra_constants.hh.

rc1

Bitfield<11, 7> gem5::RiscvISA::rc1

Definition at line 126 of file types.hh.

rc2

Bitfield< 6, 2> gem5::RiscvISA::rc2

Definition at line 127 of file types.hh.

rd

Bitfield<11, 7> gem5::RiscvISA::rd

Definition at line 78 of file types.hh.

re

Bitfield<25> gem5::RiscvISA::re

Definition at line 114 of file pra_constants.hh.

ReturnAddrReg

constexpr auto& gem5::RiscvISA::ReturnAddrReg = int_reg::Ra

inlineconstexpr

Definition at line 140 of file int.hh.

ReturnValueReg

constexpr auto & gem5::RiscvISA::ReturnValueReg = int_reg::A0

Definition at line 143 of file int.hh.

Referenced by gem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI64, SyscallReturn >::store(), and gem5::guest_abi::Result< RiscvISA::SEWorkload::SyscallABI32, SyscallReturn >::store().

rev

Bitfield<7, 0> gem5::RiscvISA::rev

Definition at line 207 of file pra_constants.hh.

ripl

Bitfield<15, 10> gem5::RiscvISA::ripl

Definition at line 187 of file pra_constants.hh.

rl

Bitfield<25> gem5::RiscvISA::rl

Definition at line 120 of file types.hh.

round_mode

Bitfield<14, 12> gem5::RiscvISA::round_mode

Definition at line 114 of file types.hh.

rp1

Bitfield< 9, 7> gem5::RiscvISA::rp1

Definition at line 128 of file types.hh.

rp2

Bitfield< 4, 2> gem5::RiscvISA::rp2

Definition at line 129 of file types.hh.

rs1

Bitfield<19, 15> gem5::RiscvISA::rs1

Definition at line 80 of file types.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64ds(), _rvk_emu_aes64dsm(), _rvk_emu_aes64es(), _rvk_emu_aes64esm(), _rvk_emu_aes64im(), _rvk_emu_aes64ks1i(), _rvk_emu_aes64ks2(), _rvk_emu_brev8_32(), _rvk_emu_brev8_64(), _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_grev_32(), _rvk_emu_grev_64(), _rvk_emu_rol_32(), _rvk_emu_rol_64(), _rvk_emu_ror_32(), _rvk_emu_ror_64(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha256sum0(), _rvk_emu_sha256sum1(), _rvk_emu_sha512sig0(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0(), _rvk_emu_sha512sum0r(), _rvk_emu_sha512sum1(), _rvk_emu_sha512sum1r(), _rvk_emu_shfl_32(), _rvk_emu_sll_32(), _rvk_emu_sll_64(), _rvk_emu_sm3p0(), _rvk_emu_sm3p1(), _rvk_emu_sm4ed(), _rvk_emu_sm4ks(), _rvk_emu_srl_32(), _rvk_emu_srl_64(), _rvk_emu_unshfl_32(), _rvk_emu_unzip_32(), _rvk_emu_xperm32(), _rvk_emu_xperm4_32(), _rvk_emu_xperm4_64(), _rvk_emu_xperm64(), _rvk_emu_xperm8_32(), _rvk_emu_xperm8_64(), _rvk_emu_zip_32(), div(), divu(), mulh_32(), mulh_64(), mulhsu_32(), mulhsu_64(), mulhu_32(), mulhu_64(), rem(), and remu().

rs2

Bitfield<24, 20> gem5::RiscvISA::rs2

Definition at line 81 of file types.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64ds(), _rvk_emu_aes64dsm(), _rvk_emu_aes64es(), _rvk_emu_aes64esm(), _rvk_emu_aes64ks2(), _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_grev_32(), _rvk_emu_grev_64(), _rvk_emu_rol_32(), _rvk_emu_rol_64(), _rvk_emu_ror_32(), _rvk_emu_ror_64(), _rvk_emu_sha512sig0h(), _rvk_emu_sha512sig0l(), _rvk_emu_sha512sig1h(), _rvk_emu_sha512sig1l(), _rvk_emu_sha512sum0r(), _rvk_emu_sha512sum1r(), _rvk_emu_shfl_32(), _rvk_emu_sll_32(), _rvk_emu_sll_64(), _rvk_emu_sm4ed(), _rvk_emu_sm4ks(), _rvk_emu_srl_32(), _rvk_emu_srl_64(), _rvk_emu_unshfl_32(), _rvk_emu_xperm32(), _rvk_emu_xperm4_32(), _rvk_emu_xperm4_64(), _rvk_emu_xperm64(), _rvk_emu_xperm8_32(), _rvk_emu_xperm8_64(), div(), divu(), mulh_32(), mulh_64(), mulhsu_32(), mulhsu_64(), mulhu_32(), mulhu_64(), rem(), and remu().

RV32

constexpr enums::RiscvType gem5::RiscvISA::RV32 = enums::RV32

constexpr

Definition at line 54 of file pcstate.hh.

Referenced by gem5::RiscvISA::ISA::clear(), EndBitUnion(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvProcess32::initState(), gem5::Clint::raiseInterruptPin(), gem5::RiscvISA::ISA::readMiscReg(), gem5::RiscvISA::RiscvStaticInst::rvSelect(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs().

rv32_mxl

Bitfield<31, 30> gem5::RiscvISA::rv32_mxl

Definition at line 762 of file misc.hh.

rv32_sd

Bitfield<31> gem5::RiscvISA::rv32_sd

Definition at line 735 of file misc.hh.

RV64

constexpr enums::RiscvType gem5::RiscvISA::RV64 = enums::RV64

constexpr

Definition at line 55 of file pcstate.hh.

Referenced by gem5::RiscvISA::ISA::clear(), EndBitUnion(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::RiscvProcess64::initState(), gem5::RiscvISA::ISA::readMiscReg(), gem5::RiscvISA::ISA::setMiscReg(), and gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs().

rv64_mxl

gem5::RiscvISA::rv64_mxl

Definition at line 761 of file misc.hh.

rv_type

gem5::RiscvISA::rv_type

Definition at line 60 of file types.hh.

Referenced by gem5::RiscvISA::PCState::rvType().

rva

Bitfield<0> gem5::RiscvISA::rva

Definition at line 783 of file misc.hh.

rvb

Bitfield<1> gem5::RiscvISA::rvb

Definition at line 782 of file misc.hh.

rvc

Bitfield<2> gem5::RiscvISA::rvc

Definition at line 781 of file misc.hh.

rvd

Bitfield<3> gem5::RiscvISA::rvd

Definition at line 780 of file misc.hh.

rve

Bitfield<4> gem5::RiscvISA::rve

Definition at line 779 of file misc.hh.

rvf

Bitfield<5> gem5::RiscvISA::rvf

Definition at line 778 of file misc.hh.

rvg

Bitfield<6> gem5::RiscvISA::rvg

Definition at line 777 of file misc.hh.

rvh

Bitfield<7> gem5::RiscvISA::rvh

Definition at line 776 of file misc.hh.

rvi

Bitfield<8> gem5::RiscvISA::rvi

Definition at line 775 of file misc.hh.

rvj

Bitfield<9> gem5::RiscvISA::rvj

Definition at line 774 of file misc.hh.

rvk

Bitfield<10> gem5::RiscvISA::rvk

Definition at line 773 of file misc.hh.

rvl

Bitfield<11> gem5::RiscvISA::rvl

Definition at line 772 of file misc.hh.

rvm

Bitfield<12> gem5::RiscvISA::rvm

Definition at line 771 of file misc.hh.

rvn

Bitfield<13> gem5::RiscvISA::rvn

Definition at line 770 of file misc.hh.

rvp

Bitfield<15> gem5::RiscvISA::rvp

Definition at line 769 of file misc.hh.

rvq

Bitfield<16> gem5::RiscvISA::rvq

Definition at line 768 of file misc.hh.

rvs

Bitfield<18> gem5::RiscvISA::rvs

Definition at line 767 of file misc.hh.

rvt

Bitfield<19> gem5::RiscvISA::rvt

Definition at line 766 of file misc.hh.

rvu

Bitfield<20> gem5::RiscvISA::rvu

Definition at line 765 of file misc.hh.

rvv

Bitfield<21> gem5::RiscvISA::rvv

Definition at line 764 of file misc.hh.

rvx

Bitfield<23> gem5::RiscvISA::rvx

Definition at line 763 of file misc.hh.

s

Bitfield<2> gem5::RiscvISA::s

Definition at line 303 of file pra_constants.hh.

sa

Bitfield<3, 0> gem5::RiscvISA::sa

Definition at line 259 of file pra_constants.hh.

SBE_OFFSET

const off_t gem5::RiscvISA::SBE_OFFSET[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 4,
    [RV64] = 36,
}

Definition at line 812 of file misc.hh.

sei

Bitfield<9> gem5::RiscvISA::sei

Definition at line 794 of file misc.hh.

SEI_MASK

const RegVal gem5::RiscvISA::SEI_MASK = 1ULL << 9

Definition at line 902 of file misc.hh.

shamt5

Bitfield<24, 20> gem5::RiscvISA::shamt5

Definition at line 85 of file types.hh.

shamt6

Bitfield<25, 20> gem5::RiscvISA::shamt6

Definition at line 86 of file types.hh.

SI_MASK

const RegVal gem5::RiscvISA::SI_MASK

Initial value:

= SEI_MASK | UEI_MASK |
                       STI_MASK | UTI_MASK |
                       SSI_MASK | USI_MASK

Definition at line 913 of file misc.hh.

sie

Bitfield<1> gem5::RiscvISA::sie

Definition at line 751 of file misc.hh.

simm3

Bitfield<17, 15> gem5::RiscvISA::simm3

Definition at line 167 of file types.hh.

sl

Bitfield<7, 4> gem5::RiscvISA::sl

Definition at line 258 of file pra_constants.hh.

sm

Bitfield<1> gem5::RiscvISA::sm

Definition at line 273 of file pra_constants.hh.

sp

Bitfield<4> gem5::RiscvISA::sp

Definition at line 270 of file pra_constants.hh.

spie

Bitfield<5> gem5::RiscvISA::spie

Definition at line 748 of file misc.hh.

spp

Bitfield<8> gem5::RiscvISA::spp

Definition at line 746 of file misc.hh.

sr

Bitfield<20> gem5::RiscvISA::sr

Definition at line 119 of file pra_constants.hh.

srType

Bitfield<30> gem5::RiscvISA::srType

Definition at line 84 of file types.hh.

ss

Bitfield<11, 8> gem5::RiscvISA::ss

Definition at line 257 of file pra_constants.hh.

Referenced by gem5::RiscvISA::BSOp::generateDisassembly(), gem5::RiscvISA::CompRegOp::generateDisassembly(), gem5::RiscvISA::RegOp::generateDisassembly(), gem5::RiscvISA::MemFenceMicro::generateDisassembly(), gem5::RiscvISA::Load::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::Store::generateDisassembly(), gem5::RiscvISA::LoadReservedMicro::generateDisassembly(), gem5::RiscvISA::SystemOp::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::RiscvISA::StoreCondMicro::generateDisassembly(), gem5::RiscvISA::CSROp::generateDisassembly(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), and gem5::RiscvISA::AtomicMemOpMicro::generateDisassembly().

ssi

Bitfield<1> gem5::RiscvISA::ssi

Definition at line 800 of file misc.hh.

SSI_MASK

const RegVal gem5::RiscvISA::SSI_MASK = 1ULL << 1

Definition at line 908 of file misc.hh.

SSTATUS_MASKS

const RegVal gem5::RiscvISA::SSTATUS_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | STATUS_SUM_MASK |
             STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
             STATUS_SPP_MASK | STATUS_SPIE_MASK | STATUS_UPIE_MASK |
             STATUS_SIE_MASK | STATUS_UIE_MASK,
    [RV64] = STATUS_SD_MASKS[RV64] | STATUS_UXL_MASK | STATUS_MXR_MASK |
             STATUS_SUM_MASK | STATUS_XS_MASK | STATUS_FS_MASK |
             STATUS_VS_MASK | STATUS_SPP_MASK | STATUS_SPIE_MASK |
             STATUS_UPIE_MASK | STATUS_SIE_MASK | STATUS_UIE_MASK,
}

Definition at line 882 of file misc.hh.

ssv0

Bitfield<3, 0> gem5::RiscvISA::ssv0

Definition at line 174 of file pra_constants.hh.

ssv1

Bitfield<7, 4> gem5::RiscvISA::ssv1

Definition at line 173 of file pra_constants.hh.

ssv2

Bitfield<11, 8> gem5::RiscvISA::ssv2

Definition at line 172 of file pra_constants.hh.

ssv3

Bitfield<15, 12> gem5::RiscvISA::ssv3

Definition at line 171 of file pra_constants.hh.

ssv4

Bitfield<19, 16> gem5::RiscvISA::ssv4

Definition at line 170 of file pra_constants.hh.

ssv5

Bitfield<23, 20> gem5::RiscvISA::ssv5

Definition at line 169 of file pra_constants.hh.

ssv6

Bitfield<27, 24> gem5::RiscvISA::ssv6

Definition at line 168 of file pra_constants.hh.

ssv7

gem5::RiscvISA::ssv7

Definition at line 167 of file pra_constants.hh.

StackPointerReg

constexpr auto & gem5::RiscvISA::StackPointerReg = int_reg::Sp

Definition at line 141 of file int.hh.

Referenced by gem5::RiscvLinux64::archClone(), and gem5::RiscvLinux32::archClone().

STATUS_FS_MASK

const RegVal gem5::RiscvISA::STATUS_FS_MASK = 3ULL << FS_OFFSET

Definition at line 854 of file misc.hh.

STATUS_MBE_MASK

const RegVal gem5::RiscvISA::STATUS_MBE_MASK[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 1ULL << MBE_OFFSET[RV32],
    [RV64] = 1ULL << MBE_OFFSET[RV64],
}

Definition at line 837 of file misc.hh.

STATUS_MIE_MASK

const RegVal gem5::RiscvISA::STATUS_MIE_MASK = 1ULL << 3

Definition at line 861 of file misc.hh.

STATUS_MPIE_MASK

const RegVal gem5::RiscvISA::STATUS_MPIE_MASK = 1ULL << 7

Definition at line 858 of file misc.hh.

STATUS_MPP_MASK

const RegVal gem5::RiscvISA::STATUS_MPP_MASK = 3ULL << 11

Definition at line 855 of file misc.hh.

STATUS_MPRV_MASK

const RegVal gem5::RiscvISA::STATUS_MPRV_MASK = 1ULL << 17

Definition at line 852 of file misc.hh.

STATUS_MXR_MASK

const RegVal gem5::RiscvISA::STATUS_MXR_MASK = 1ULL << 19

Definition at line 850 of file misc.hh.

STATUS_SBE_MASK

const RegVal gem5::RiscvISA::STATUS_SBE_MASK[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 1ULL << SBE_OFFSET[RV32],
    [RV64] = 1ULL << SBE_OFFSET[RV64],
}

Definition at line 841 of file misc.hh.

STATUS_SD_MASKS

const RegVal gem5::RiscvISA::STATUS_SD_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = 1ULL << ((sizeof(uint32_t) * 8) - 1),
    [RV64] = 1ULL << ((sizeof(uint64_t) * 8) - 1),
}

Definition at line 833 of file misc.hh.

STATUS_SIE_MASK

const RegVal gem5::RiscvISA::STATUS_SIE_MASK = 1ULL << 1

Definition at line 862 of file misc.hh.

STATUS_SPIE_MASK

const RegVal gem5::RiscvISA::STATUS_SPIE_MASK = 1ULL << 5

Definition at line 859 of file misc.hh.

STATUS_SPP_MASK

const RegVal gem5::RiscvISA::STATUS_SPP_MASK = 1ULL << 8

Definition at line 857 of file misc.hh.

STATUS_SUM_MASK

const RegVal gem5::RiscvISA::STATUS_SUM_MASK = 1ULL << 18

Definition at line 851 of file misc.hh.

STATUS_SXL_MASK

const RegVal gem5::RiscvISA::STATUS_SXL_MASK = 3ULL << SXL_OFFSET

Definition at line 845 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

STATUS_TSR_MASK

const RegVal gem5::RiscvISA::STATUS_TSR_MASK = 1ULL << 22

Definition at line 847 of file misc.hh.

STATUS_TVM_MASK

const RegVal gem5::RiscvISA::STATUS_TVM_MASK = 1ULL << 20

Definition at line 849 of file misc.hh.

STATUS_TW_MASK

const RegVal gem5::RiscvISA::STATUS_TW_MASK = 1ULL << 21

Definition at line 848 of file misc.hh.

STATUS_UIE_MASK

const RegVal gem5::RiscvISA::STATUS_UIE_MASK = 1ULL << 0

Definition at line 863 of file misc.hh.

STATUS_UPIE_MASK

const RegVal gem5::RiscvISA::STATUS_UPIE_MASK = 1ULL << 4

Definition at line 860 of file misc.hh.

STATUS_UXL_MASK

const RegVal gem5::RiscvISA::STATUS_UXL_MASK = 3ULL << UXL_OFFSET

Definition at line 846 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

STATUS_VS_MASK

const RegVal gem5::RiscvISA::STATUS_VS_MASK = 3ULL << 9

Definition at line 856 of file misc.hh.

STATUS_XS_MASK

const RegVal gem5::RiscvISA::STATUS_XS_MASK = 3ULL << 15

Definition at line 853 of file misc.hh.

sti

Bitfield<5> gem5::RiscvISA::sti

Definition at line 797 of file misc.hh.

STI_MASK

const RegVal gem5::RiscvISA::STI_MASK = 1ULL << 5

Definition at line 905 of file misc.hh.

su

Bitfield<15, 12> gem5::RiscvISA::su

Definition at line 256 of file pra_constants.hh.

succ

Bitfield<23, 20> gem5::RiscvISA::succ

Definition at line 90 of file types.hh.

Referenced by gem5::prefetch::PIF::CompactorEntry::getPredictedAddresses(), gem5::prefetch::PIF::CompactorEntry::hasAddress(), gem5::prefetch::PIF::CompactorEntry::inSameSpatialRegion(), gem5::RequestPort::sendTimingReq(), and gem5::ResponsePort::sendTimingResp().

sum

Bitfield<18> gem5::RiscvISA::sum

Definition at line 740 of file misc.hh.

Referenced by gem5::networking::__tu_cksum(), gem5::networking::__tu_cksum6(), gem5::PowerISA::IntArithOp::add(), gem5::X86ISA::ACPI::apic_checksum(), gem5::networking::cksum(), gem5::ruby::Throttle::getTotalLinkBandwidth(), gem5::TrafficGen::parseConfig(), gem5::popCount(), gem5::ruby::SimpleNetwork::regStats(), gem5::ruby::garnet::GarnetNetwork::regStats(), SC_MODULE(), and TEST().

sumop

Bitfield<24, 20> gem5::RiscvISA::sumop

Definition at line 160 of file types.hh.

sx

Bitfield<6> gem5::RiscvISA::sx

Definition at line 135 of file pra_constants.hh.

sxl

Bitfield<35, 34> gem5::RiscvISA::sxl

Definition at line 733 of file misc.hh.

SXL_OFFSET

const off_t gem5::RiscvISA::SXL_OFFSET = 34

Definition at line 816 of file misc.hh.

SyscallNumReg

constexpr auto & gem5::RiscvISA::SyscallNumReg = int_reg::A7

Definition at line 145 of file int.hh.

Referenced by gem5::RiscvISA::EmuLinux::syscall().

ta

Bitfield<19, 16> gem5::RiscvISA::ta

Definition at line 255 of file pra_constants.hh.

ThreadPointerReg

constexpr auto & gem5::RiscvISA::ThreadPointerReg = int_reg::Tp

Definition at line 142 of file int.hh.

Referenced by gem5::RiscvLinux64::archClone(), and gem5::RiscvLinux32::archClone().

ti

Bitfield<30> gem5::RiscvISA::ti

Definition at line 179 of file pra_constants.hh.

tl

Bitfield< 0 > gem5::RiscvISA::tl

Definition at line 254 of file pra_constants.hh.

ts

Bitfield< 27, 24 > gem5::RiscvISA::ts

Definition at line 118 of file pra_constants.hh.

tsr

Bitfield<22> gem5::RiscvISA::tsr

Definition at line 736 of file misc.hh.

tu

Bitfield<30, 28> gem5::RiscvISA::tu

Definition at line 252 of file pra_constants.hh.

tvm

Bitfield<20> gem5::RiscvISA::tvm

Definition at line 738 of file misc.hh.

tw

Bitfield<21> gem5::RiscvISA::tw

Definition at line 737 of file misc.hh.

u

Bitfield< 3 > gem5::RiscvISA::u

Definition at line 71 of file pagetable.hh.

uei

Bitfield<8> gem5::RiscvISA::uei

Definition at line 795 of file misc.hh.

UEI_MASK

const RegVal gem5::RiscvISA::UEI_MASK = 1ULL << 8

Definition at line 903 of file misc.hh.

UI_MASK

const RegVal gem5::RiscvISA::UI_MASK = UEI_MASK | UTI_MASK | USI_MASK

Definition at line 916 of file misc.hh.

uie

Bitfield<0> gem5::RiscvISA::uie

Definition at line 752 of file misc.hh.

uimm_vsetivli

Bitfield<19, 15> gem5::RiscvISA::uimm_vsetivli

Definition at line 175 of file types.hh.

ujimmbit11

Bitfield<20> gem5::RiscvISA::ujimmbit11

Definition at line 104 of file types.hh.

ujimmbits10to1

Bitfield<30, 21> gem5::RiscvISA::ujimmbits10to1

Definition at line 103 of file types.hh.

ujimmbits19to12

Bitfield<19, 12> gem5::RiscvISA::ujimmbits19to12

Definition at line 105 of file types.hh.

um

Bitfield<4> gem5::RiscvISA::um

Definition at line 138 of file pra_constants.hh.

upie

Bitfield<4> gem5::RiscvISA::upie

Definition at line 749 of file misc.hh.

usi

Bitfield<0> gem5::RiscvISA::usi

Definition at line 801 of file misc.hh.

USI_MASK

const RegVal gem5::RiscvISA::USI_MASK = 1ULL << 0

Definition at line 909 of file misc.hh.

USTATUS_MASKS

const RegVal gem5::RiscvISA::USTATUS_MASKS[enums::Num_RiscvType]

Initial value:

= {
    [RV32] = STATUS_SD_MASKS[RV32] | STATUS_MXR_MASK | STATUS_SUM_MASK |
             STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
             STATUS_UPIE_MASK | STATUS_UIE_MASK,
    [RV64] = STATUS_SD_MASKS[RV64] | STATUS_MXR_MASK | STATUS_SUM_MASK |
             STATUS_XS_MASK | STATUS_FS_MASK | STATUS_VS_MASK |
             STATUS_UPIE_MASK | STATUS_UIE_MASK,
}

Definition at line 892 of file misc.hh.

uti

Bitfield<4> gem5::RiscvISA::uti

Definition at line 798 of file misc.hh.

UTI_MASK

const RegVal gem5::RiscvISA::UTI_MASK = 1ULL << 4

Definition at line 906 of file misc.hh.

ux

Bitfield<5> gem5::RiscvISA::ux

Definition at line 136 of file pra_constants.hh.

uxl

Bitfield<33, 32> gem5::RiscvISA::uxl

Definition at line 734 of file misc.hh.

UXL_OFFSET

const off_t gem5::RiscvISA::UXL_OFFSET = 32

Definition at line 817 of file misc.hh.

v

Bitfield< 1 > gem5::RiscvISA::v

Definition at line 76 of file pagetable.hh.

Referenced by boxF16(), boxF32(), f16(), f32(), f64(), unboxF16(), and unboxF32().

vaddr

gem5::RiscvISA::vaddr

Definition at line 278 of file pra_constants.hh.

Referenced by gem5::RiscvISA::Walker::WalkerState::recvPacket(), and gem5::RiscvISA::Walker::WalkerState::setupWalk().

VADDR_BITS

const Addr gem5::RiscvISA::VADDR_BITS = 39

Definition at line 59 of file pagetable.hh.

vd

Bitfield<11, 7> gem5::RiscvISA::vd

Definition at line 164 of file types.hh.

Referenced by sc_dt::add_on_help(), sc_dt::compare_unsigned(), sc_dt::convert_unsigned_SM_to_2C_to_SM(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), sc_dt::operator%(), sc_dt::operator&(), sc_dt::operator*(), sc_dt::operator+(), sc_dt::operator-(), sc_dt::operator/(), sc_dt::operator<(), sc_dt::operator==(), sc_dt::operator^(), sc_dt::operator|(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::VoltageDomain::VoltageDomainStats::VoltageDomainStats(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

vecimm

Bitfield<19, 15> gem5::RiscvISA::vecimm

Definition at line 166 of file types.hh.

veic

Bitfield<6> gem5::RiscvISA::veic

Definition at line 268 of file pra_constants.hh.

vfunct2

Bitfield<26, 25> gem5::RiscvISA::vfunct2

Definition at line 154 of file types.hh.

vfunct3

Bitfield<27, 25> gem5::RiscvISA::vfunct3

Definition at line 153 of file types.hh.

vfunct5

Bitfield<31, 27> gem5::RiscvISA::vfunct5

Definition at line 152 of file types.hh.

vfunct6

Bitfield<31, 26> gem5::RiscvISA::vfunct6

Definition at line 151 of file types.hh.

vi

Bitfield<3> gem5::RiscvISA::vi

Definition at line 228 of file pra_constants.hh.

vill

Bitfield<40> gem5::RiscvISA::vill

Definition at line 64 of file types.hh.

vint

Bitfield<5> gem5::RiscvISA::vint

Definition at line 269 of file pra_constants.hh.

vl

Bitfield<57, 41> gem5::RiscvISA::vl

Definition at line 63 of file types.hh.

Referenced by sc_core::sc_report_handler::set_verbosity_level().

vlmul

Bitfield<34, 32> gem5::RiscvISA::vlmul

Definition at line 69 of file types.hh.

vm

Bitfield<25> gem5::RiscvISA::vm

Definition at line 158 of file types.hh.

vpn2

Bitfield<39, 13> gem5::RiscvISA::vpn2

Definition at line 100 of file pra_constants.hh.

vpn2x

Bitfield<12, 11> gem5::RiscvISA::vpn2x

Definition at line 101 of file pra_constants.hh.

vs

Bitfield< 10, 9 > gem5::RiscvISA::vs

Definition at line 149 of file pra_constants.hh.

vs1

Bitfield<19, 15> gem5::RiscvISA::vs1

Definition at line 163 of file types.hh.

vs2

Bitfield<24, 20> gem5::RiscvISA::vs2

Definition at line 162 of file types.hh.

vs3

Bitfield<11, 7> gem5::RiscvISA::vs3

Definition at line 165 of file types.hh.

vsew

Bitfield<37, 35> gem5::RiscvISA::vsew

Definition at line 68 of file types.hh.

vta

Bitfield<38> gem5::RiscvISA::vta

Definition at line 67 of file types.hh.

w

Bitfield< 30 > gem5::RiscvISA::w

Definition at line 74 of file pagetable.hh.

width

Bitfield<14, 12> gem5::RiscvISA::width

Definition at line 161 of file types.hh.

wired

gem5::RiscvISA::wired

Definition at line 89 of file pra_constants.hh.

wp

Bitfield<22> gem5::RiscvISA::wp

Definition at line 185 of file pra_constants.hh.

wr

Bitfield<3> gem5::RiscvISA::wr

Definition at line 244 of file pra_constants.hh.

x

Bitfield<3> gem5::RiscvISA::x

Definition at line 73 of file pagetable.hh.

Referenced by _rvk_emu_aes32dsi(), _rvk_emu_aes32dsmi(), _rvk_emu_aes32esi(), _rvk_emu_aes32esmi(), _rvk_emu_aes64dsm(), _rvk_emu_aes64esm(), _rvk_emu_aes_fwd_mc_32(), _rvk_emu_aes_fwd_mc_8(), _rvk_emu_aes_inv_mc_32(), _rvk_emu_aes_inv_mc_8(), _rvk_emu_aes_xtime(), _rvk_emu_clmul_32(), _rvk_emu_clmul_64(), _rvk_emu_clmulh_32(), _rvk_emu_clmulh_64(), _rvk_emu_grev_32(), _rvk_emu_grev_64(), _rvk_emu_sha256sig0(), _rvk_emu_sha256sig1(), _rvk_emu_sha256sum0(), _rvk_emu_sha256sum1(), _rvk_emu_shfl_32(), _rvk_emu_shuffle32_stage(), _rvk_emu_sm3p0(), _rvk_emu_sm3p1(), _rvk_emu_sm4ed(), _rvk_emu_sm4ks(), _rvk_emu_unshfl_32(), gem5::RiscvISA::RiscvStaticInst::rvExt(), gem5::RiscvISA::RiscvStaticInst::rvSext(), and gem5::RiscvISA::RiscvStaticInst::rvZext().

xs

Bitfield<16, 15> gem5::RiscvISA::xs

Definition at line 742 of file misc.hh.

Referenced by gem5::dumpFpuSpec().

zimm_vsetivli

Bitfield<29, 20> gem5::RiscvISA::zimm_vsetivli

Definition at line 174 of file types.hh.

zimm_vsetvli

Bitfield<30, 20> gem5::RiscvISA::zimm_vsetvli

Definition at line 171 of file types.hh.