mem64.hh

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 * All rights reserved
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 * property including but not limited to intellectual property relating
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#ifndef __ARCH_ARM_MEM64_HH__
#define __ARCH_ARM_MEM64_HH__
 
#include "arch/arm/insts/misc64.hh"
#include "arch/arm/insts/static_inst.hh"
#include "arch/arm/pcstate.hh"
#include "cpu/thread_context.hh"
 
namespace gem5
{
 
namespace ArmISA
{
 
class SysDC64 : public MiscRegOp64
{
  protected:
    RegIndex base;
    MiscRegIndex dest;
 
    // This is used for fault handling only
    mutable Addr faultAddr;
 
    SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
            RegIndex _base, MiscRegIndex _dest)
        : MiscRegOp64(mnem, _machInst, __opClass, false),
          base(_base), dest(_dest), faultAddr(0)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
 
    uint32_t iss() const override;
};
 
class MightBeMicro64 : public ArmStaticInst
{
  protected:
    MightBeMicro64(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
        : ArmStaticInst(mnem, _machInst, __opClass)
    {}
 
    void
    advancePC(PCStateBase &pcState) const override
    {
        auto &apc = pcState.as<PCState>();
        if (flags[IsLastMicroop]) {
            apc.uEnd();
        } else if (flags[IsMicroop]) {
            apc.uAdvance();
        } else {
            apc.advance();
        }
    }
 
    void
    advancePC(ThreadContext *tc) const override
    {
        PCState pc = tc->pcState().as<PCState>();
        if (flags[IsLastMicroop]) {
            pc.uEnd();
        } else if (flags[IsMicroop]) {
            pc.uAdvance();
        } else {
            pc.advance();
        }
        tc->pcState(pc);
    }
};
 
class Memory64 : public MightBeMicro64
{
  public:
    enum AddrMode
    {
        AddrMd_Offset,
        AddrMd_PreIndex,
        AddrMd_PostIndex
    };
 
  protected:
 
    RegIndex dest;
    RegIndex base;
    bool baseIsSP;
    static const unsigned numMicroops = 3;
 
    StaticInstPtr *uops;
 
    Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
             RegIndex _dest, RegIndex _base)
        : MightBeMicro64(mnem, _machInst, __opClass),
          dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
    {
        baseIsSP = isSP(_base);
    }
 
    virtual
    ~Memory64()
    {
        delete [] uops;
    }
 
    StaticInstPtr
    fetchMicroop(MicroPC microPC) const override
    {
        assert(uops != NULL && microPC < numMicroops);
        return uops[microPC];
    }
 
    void startDisassembly(std::ostream &os) const;
 
    unsigned memAccessFlags;
 
    void setExcAcRel(bool exclusive, bool acrel);
};
 
class MemoryImm64 : public Memory64
{
  protected:
    int64_t imm;
 
    MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                RegIndex _dest, RegIndex _base, int64_t _imm)
        : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryDImm64 : public MemoryImm64
{
  protected:
    RegIndex dest2;
 
    MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                RegIndex _dest, RegIndex _dest2, RegIndex _base,
                int64_t _imm)
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
          dest2(_dest2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryDImmEx64 : public MemoryDImm64
{
  protected:
    RegIndex result;
 
    MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
                 RegIndex _result, RegIndex _dest, RegIndex _dest2,
                 RegIndex _base, int32_t _imm)
        : MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
                     _base, _imm), result(_result)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryPreIndex64 : public MemoryImm64
{
  protected:
    MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
                     OpClass __opClass, RegIndex _dest, RegIndex _base,
                     int64_t _imm)
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryPostIndex64 : public MemoryImm64
{
  protected:
    MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
                      OpClass __opClass, RegIndex _dest, RegIndex _base,
                      int64_t _imm)
        : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryReg64 : public Memory64
{
  protected:
    RegIndex offset;
    ArmExtendType type;
    uint64_t shiftAmt;
 
    MemoryReg64(const char *mnem, ExtMachInst _machInst,
                OpClass __opClass, RegIndex _dest, RegIndex _base,
                RegIndex _offset, ArmExtendType _type,
                uint64_t _shiftAmt)
        : Memory64(mnem, _machInst, __opClass, _dest, _base),
          offset(_offset), type(_type), shiftAmt(_shiftAmt)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryRaw64 : public Memory64
{
  protected:
    MemoryRaw64(const char *mnem, ExtMachInst _machInst,
                OpClass __opClass, RegIndex _dest, RegIndex _base)
        : Memory64(mnem, _machInst, __opClass, _dest, _base)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryEx64 : public Memory64
{
  protected:
    RegIndex result;
 
    MemoryEx64(const char *mnem, ExtMachInst _machInst,
               OpClass __opClass, RegIndex _dest, RegIndex _base,
               RegIndex _result)
        : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryLiteral64 : public Memory64
{
  protected:
    int64_t imm;
 
    MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
                    OpClass __opClass, RegIndex _dest, int64_t _imm)
        : Memory64(mnem, _machInst, __opClass, _dest, int_reg::Zero), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class MemoryAtomicPair64 : public Memory64
{
  protected:
    RegIndex dest2;
    RegIndex result;
    RegIndex result2;
 
    MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst,
                       OpClass __opClass, RegIndex _dest, RegIndex _base,
                       RegIndex _result)
        : Memory64(mnem, _machInst, __opClass, _dest, _base),
          dest2((RegIndex)(_dest + (RegIndex)(1))),
          result(_result),
          result2((RegIndex)(_result + (RegIndex)(1)))
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
} // namespace ArmISA
} // namespace gem5
 
#endif //__ARCH_ARM_INSTS_MEM_HH__