mem_dep_unit.hh

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#ifndef __CPU_O3_MEM_DEP_UNIT_HH__
#define __CPU_O3_MEM_DEP_UNIT_HH__
 
#include <list>
#include <memory>
#include <set>
#include <unordered_map>
#include <unordered_set>
 
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/dyn_inst_ptr.hh"
#include "cpu/o3/limits.hh"
#include "cpu/o3/store_set.hh"
#include "debug/MemDepUnit.hh"
 
namespace gem5
{
 
struct SNHash
{
    size_t
    operator()(const InstSeqNum &seq_num) const
    {
        unsigned a = (unsigned)seq_num;
        unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
        return hash;
    }
};
 
struct BaseO3CPUParams;
 
namespace o3
{
 
class CPU;
class InstructionQueue;
 
class MemDepUnit
{
  protected:
    std::string _name;
 
  public:
    MemDepUnit();
 
    MemDepUnit(const BaseO3CPUParams &params);
 
    ~MemDepUnit();
 
    std::string name() const { return _name; }
 
    void init(const BaseO3CPUParams &params, ThreadID tid, CPU *cpu);
 
    bool isDrained() const;
 
    void drainSanityCheck() const;
 
    void takeOverFrom();
 
    void setIQ(InstructionQueue *iq_ptr);
 
    void insert(const DynInstPtr &inst);
 
    void insertNonSpec(const DynInstPtr &inst);
 
    void insertBarrier(const DynInstPtr &barr_inst);
 
    void regsReady(const DynInstPtr &inst);
 
    void nonSpecInstReady(const DynInstPtr &inst);
 
    void reschedule(const DynInstPtr &inst);
 
    void replay();
 
    void completeInst(const DynInstPtr &inst);
 
    void squash(const InstSeqNum &squashed_num, ThreadID tid);
 
    void violation(const DynInstPtr &store_inst,
                   const DynInstPtr &violating_load);
 
    void issue(const DynInstPtr &inst);
 
    void dumpLists();
 
  private:
 
    void completed(const DynInstPtr &inst);
 
    void wakeDependents(const DynInstPtr &inst);
 
    typedef typename std::list<DynInstPtr>::iterator ListIt;
 
    class MemDepEntry;
 
    typedef std::shared_ptr<MemDepEntry> MemDepEntryPtr;
 
    class MemDepEntry
    {
      public:
        MemDepEntry(const DynInstPtr &new_inst);
 
        ~MemDepEntry();
 
        std::string name() const { return "memdepentry"; }
 
        DynInstPtr inst;
 
        ListIt listIt;
 
        std::vector<MemDepEntryPtr> dependInsts;
 
        bool regsReady = false;
        int memDeps = 0;
        bool completed = false;
        bool squashed = false;
 
#ifdef GEM5_DEBUG
        static int memdep_count;
        static int memdep_insert;
        static int memdep_erase;
#endif
    };
 
    MemDepEntryPtr &findInHash(const DynInstConstPtr& inst);
 
    void moveToReady(MemDepEntryPtr &ready_inst_entry);
 
    typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
 
    typedef typename MemDepHash::iterator MemDepHashIt;
 
    MemDepHash memDepHash;
 
    std::list<DynInstPtr> instList[MaxThreads];
 
    std::list<DynInstPtr> instsToReplay;
 
    StoreSet depPred;
 
    std::unordered_set<InstSeqNum> loadBarrierSNs;
 
    std::unordered_set<InstSeqNum> storeBarrierSNs;
 
    bool hasLoadBarrier() const { return !loadBarrierSNs.empty(); }
 
    bool hasStoreBarrier() const { return !storeBarrierSNs.empty(); }
 
    void insertBarrierSN(const DynInstPtr &barr_inst);
 
    InstructionQueue *iqPtr;
 
    int id;
    struct MemDepUnitStats : public statistics::Group
    {
        MemDepUnitStats(statistics::Group *parent);
        statistics::Scalar insertedLoads;
        statistics::Scalar insertedStores;
        statistics::Scalar conflictingLoads;
        statistics::Scalar conflictingStores;
    } stats;
};
 
} // namespace o3
} // namespace gem5
 
#endif // __CPU_O3_MEM_DEP_UNIT_HH__