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memory_manager.hh
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31 
32 #ifndef __DEV_AMDGPU_MEMORY_MANAGER_HH__
33 #define __DEV_AMDGPU_MEMORY_MANAGER_HH__
34 
35 #include <deque>
36 #include <unordered_map>
37 
38 #include "base/callback.hh"
39 #include "mem/port.hh"
40 #include "params/AMDGPUMemoryManager.hh"
41 #include "sim/clocked_object.hh"
42 
43 namespace gem5
44 {
45 
47 {
48  class GPUMemPort : public RequestPort
49  {
50  public:
51  GPUMemPort(const std::string &_name, AMDGPUMemoryManager &_gpuMemMgr)
52  : RequestPort(_name), gpu_mem(_gpuMemMgr)
53  {
54  }
55 
56  bool recvTimingResp(PacketPtr pkt) override;
57  void recvReqRetry() override;
58 
60  {
61  SenderState(Event *callback, Addr addr, uint64_t requestId)
62  : _callback(callback), _addr(addr), _requestId(requestId)
63  {}
64 
67  uint64_t _requestId;
68  };
69 
72  };
73 
75  const int cacheLineSize;
77 
79  {
81  { }
82 
85  };
86 
87  uint64_t requestId = 0;
88  std::unordered_map<uint64_t, RequestStatus> requestStatus;
89 
90  public:
91  AMDGPUMemoryManager(const AMDGPUMemoryManagerParams &p);
93 
104  void writeRequest(Addr addr, uint8_t *data, int size,
105  Request::Flags flag, Event *callback);
106 
117  void readRequest(Addr addr, uint8_t *data, int size,
118  Request::Flags flag, Event *callback);
119 
127 
128  Port &
129  getPort(const std::string &if_name, PortID idx) override
130  {
131  if (if_name == "port") {
132  return _gpuMemPort;
133  } else {
134  return ClockedObject::getPort(if_name, idx);
135  }
136  }
137 };
138 
139 } // namespace gem5
140 
141 #endif // __DEV_AMDGPU_MEMORY_MANAGER_HH__
gem5::PortID
int16_t PortID
Port index/ID type, and a symbolic name for an invalid port id.
Definition: types.hh:245
gem5::AMDGPUMemoryManager::GPUMemPort::SenderState::_addr
Addr _addr
Definition: memory_manager.hh:66
gem5::SimObject::getPort
virtual Port & getPort(const std::string &if_name, PortID idx=InvalidPortID)
Get a port with a given name and index.
Definition: sim_object.cc:123
gem5::AMDGPUMemoryManager::GPUMemPort::SenderState::_callback
Event * _callback
Definition: memory_manager.hh:65
gem5::AMDGPUMemoryManager::GPUMemPort::SenderState::_requestId
uint64_t _requestId
Definition: memory_manager.hh:67
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::AMDGPUMemoryManager::readRequest
void readRequest(Addr addr, uint8_t *data, int size, Request::Flags flag, Event *callback)
Read size amount of data from device memory at addr using flags and callback.
Definition: memory_manager.cc:96
gem5::AMDGPUMemoryManager::writeRequest
void writeRequest(Addr addr, uint8_t *data, int size, Request::Flags flag, Event *callback)
Write size amount of data to device memory at addr using flags and callback.
Definition: memory_manager.cc:53
gem5::AMDGPUMemoryManager::AMDGPUMemoryManager
AMDGPUMemoryManager(const AMDGPUMemoryManagerParams &p)
Definition: memory_manager.cc:45
gem5::AMDGPUMemoryManager::GPUMemPort::recvReqRetry
void recvReqRetry() override
Called by the peer if sendTimingReq was called on this peer (causing recvTimingReq to be called on th...
Definition: memory_manager.cc:175
gem5::AMDGPUMemoryManager::getPort
Port & getPort(const std::string &if_name, PortID idx) override
Get a port with a given name and index.
Definition: memory_manager.hh:129
gem5::RequestPort
A RequestPort is a specialisation of a Port, which implements the default protocol for the three diff...
Definition: port.hh:118
gem5::AMDGPUMemoryManager::GPUMemPort::recvTimingResp
bool recvTimingResp(PacketPtr pkt) override
Receive a timing response from the peer.
Definition: memory_manager.cc:138
gem5::Flags< FlagsType >
gem5::AMDGPUMemoryManager::GPUMemPort::SenderState::SenderState
SenderState(Event *callback, Addr addr, uint64_t requestId)
Definition: memory_manager.hh:61
gem5::VegaISA::p
Bitfield< 54 > p
Definition: pagetable.hh:70
gem5::AMDGPUMemoryManager::requestId
uint64_t requestId
Definition: memory_manager.hh:87
gem5::AMDGPUMemoryManager::_requestorId
const RequestorID _requestorId
Definition: memory_manager.hh:76
gem5::AMDGPUMemoryManager::RequestStatus::sentLastChunk
bool sentLastChunk
Definition: memory_manager.hh:84
gem5::Event
Definition: eventq.hh:254
gem5::Packet
A Packet is used to encapsulate a transfer between two objects in the memory system (e....
Definition: packet.hh:294
gem5::AMDGPUMemoryManager::GPUMemPort::retries
std::deque< PacketPtr > retries
Definition: memory_manager.hh:70
gem5::AMDGPUMemoryManager::GPUMemPort::gpu_mem
AMDGPUMemoryManager & gpu_mem
Definition: memory_manager.hh:71
gem5::AMDGPUMemoryManager::RequestStatus
Definition: memory_manager.hh:78
port.hh
gem5::AMDGPUMemoryManager
Definition: memory_manager.hh:46
gem5::AMDGPUMemoryManager::GPUMemPort
Definition: memory_manager.hh:48
gem5::Packet::SenderState
A virtual base opaque structure used to hold state associated with the packet (e.g....
Definition: packet.hh:468
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::ClockedObject
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to ...
Definition: clocked_object.hh:234
gem5::AMDGPUMemoryManager::RequestStatus::outstandingChunks
uint64_t outstandingChunks
Definition: memory_manager.hh:83
gem5::AMDGPUMemoryManager::_gpuMemPort
GPUMemPort _gpuMemPort
Definition: memory_manager.hh:74
gem5::AMDGPUMemoryManager::getRequestorID
RequestorID getRequestorID() const
Get the requestorID for the memory manager.
Definition: memory_manager.hh:126
gem5::AMDGPUMemoryManager::requestStatus
std::unordered_map< uint64_t, RequestStatus > requestStatus
Definition: memory_manager.hh:88
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
clocked_object.hh
std::deque
STL deque class.
Definition: stl.hh:44
gem5::AMDGPUMemoryManager::RequestStatus::RequestStatus
RequestStatus()
Definition: memory_manager.hh:80
gem5::AMDGPUMemoryManager::~AMDGPUMemoryManager
~AMDGPUMemoryManager()
Definition: memory_manager.hh:92
gem5::RequestorID
uint16_t RequestorID
Definition: request.hh:95
gem5::AMDGPUMemoryManager::GPUMemPort::GPUMemPort
GPUMemPort(const std::string &_name, AMDGPUMemoryManager &_gpuMemMgr)
Definition: memory_manager.hh:51
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::AMDGPUMemoryManager::cacheLineSize
const int cacheLineSize
Definition: memory_manager.hh:75
gem5::AMDGPUMemoryManager::GPUMemPort::SenderState
Definition: memory_manager.hh:59
callback.hh
gem5::Named::_name
const std::string _name
Definition: named.hh:41
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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