gem5  [DEVELOP-FOR-23.0]
All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Friends Macros Modules Pages
register_manager.hh
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2016, 2017 Advanced Micro Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  * this list of conditions and the following disclaimer.
10  *
11  * 2. Redistributions in binary form must reproduce the above copyright notice,
12  * this list of conditions and the following disclaimer in the documentation
13  * and/or other materials provided with the distribution.
14  *
15  * 3. Neither the name of the copyright holder nor the names of its
16  * contributors may be used to endorse or promote products derived from this
17  * software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef __REGISTER_MANAGER_HH__
33 #define __REGISTER_MANAGER_HH__
34 
35 #include <cstdint>
36 #include <map>
37 #include <string>
38 #include <utility>
39 #include <vector>
40 
43 #include "sim/sim_object.hh"
44 #include "sim/stats.hh"
45 
46 namespace gem5
47 {
48 
49 class ComputeUnit;
50 class Wavefront;
51 
52 struct RegisterManagerParams;
53 
54 /*
55  * Rename stage.
56  */
57 class RegisterManager : public SimObject
58 {
59  public:
60  RegisterManager(const RegisterManagerParams &params);
62  void setParent(ComputeUnit *cu);
63  void exec();
64 
65  // lookup virtual to physical register translation
66  int mapVgpr(Wavefront* w, int vgprIndex);
67  int mapSgpr(Wavefront* w, int sgprIndex);
68 
69  // check if we can allocate registers
70  bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf);
71  bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf);
72 
73  // allocate registers
74  void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand);
75 
76  // free all registers used by the WF
77  void freeRegisters(Wavefront *w);
78 
81 
82  private:
84 
86 
87  std::string _name;
88 };
89 
90 } // namespace gem5
91 
92 #endif // __REGISTER_MANAGER_HH__
gem5::Wavefront
Definition: wavefront.hh:60
gem5::RegisterManager::setParent
void setParent(ComputeUnit *cu)
Definition: register_manager.cc:77
gem5::VegaISA::w
Bitfield< 6 > w
Definition: pagetable.hh:59
std::vector
STL vector class.
Definition: stl.hh:37
gem5::RegisterManager::vrfPoolMgrs
std::vector< PoolManager * > vrfPoolMgrs
Definition: register_manager.hh:80
gem5::RegisterManagerPolicy
Register Manager Policy abstract class.
Definition: register_manager_policy.hh:53
stats.hh
gem5::RegisterManager::mapSgpr
int mapSgpr(Wavefront *w, int sgprIndex)
Definition: register_manager.cc:102
gem5::ComputeUnit
Definition: compute_unit.hh:201
gem5::RegisterManager::freeRegisters
void freeRegisters(Wavefront *w)
Definition: register_manager.cc:129
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
sim_object.hh
gem5::RegisterManager::srfPoolMgrs
std::vector< PoolManager * > srfPoolMgrs
Definition: register_manager.hh:79
gem5::SimObject
Abstract superclass for simulation objects.
Definition: sim_object.hh:146
gem5::RegisterManager::policy
RegisterManagerPolicy * policy
Definition: register_manager.hh:83
gem5::RegisterManager::mapVgpr
int mapVgpr(Wavefront *w, int vgprIndex)
Definition: register_manager.cc:95
gem5::RegisterManager::exec
void exec()
Definition: register_manager.cc:71
gem5::RegisterManager::allocateRegisters
void allocateRegisters(Wavefront *w, int vectorDemand, int scalarDemand)
Definition: register_manager.cc:122
pool_manager.hh
gem5::RegisterManager::RegisterManager
RegisterManager(const RegisterManagerParams &params)
Definition: register_manager.cc:48
gem5::RegisterManager::canAllocateSgprs
bool canAllocateSgprs(int simdId, int nWfs, int demandPerWf)
Definition: register_manager.cc:115
gem5::RegisterManager
Definition: register_manager.hh:57
gem5::RegisterManager::_name
std::string _name
Definition: register_manager.hh:87
gem5::RegisterManager::~RegisterManager
~RegisterManager()
Definition: register_manager.cc:60
gem5::RegisterManager::canAllocateVgprs
bool canAllocateVgprs(int simdId, int nWfs, int demandPerWf)
Definition: register_manager.cc:109
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
register_manager_policy.hh
gem5::RegisterManager::computeUnit
ComputeUnit * computeUnit
Definition: register_manager.hh:85

Generated on Sun Jul 30 2023 01:56:57 for gem5 by doxygen 1.8.17