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interface.h
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3  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
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6  Accellera licenses this file to you under the Apache License, Version 2.0
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21 
22  interface.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 /* Common interface file for test cases
39  Author: PRP
40  */
41 
43 {
44  SC_HAS_PROCESS( t );
45 
46  sc_in_clk clk;
47 
48  const sc_signal<bool>& reset_sig;
49 
50  const sc_signal<int>& i1;
51  const sc_signal<int>& i2;
52  const sc_signal<int>& i3;
53  const sc_signal<int>& i4;
54  const sc_signal<int>& i5;
55 
56  sc_signal<int>& o1;
57  sc_signal<int>& o2;
58  sc_signal<int>& o3;
59  sc_signal<int>& o4;
60  sc_signal<int>& o5;
61 
62  // Constructor
63  t (
64  sc_module_name NAME,
65  sc_clock& CLK,
66 
67  const sc_signal<bool>& RESET_SIG,
68 
69  const sc_signal<int>& I1,
70  const sc_signal<int>& I2,
71  const sc_signal<int>& I3,
72  const sc_signal<int>& I4,
73  const sc_signal<int>& I5,
74 
75  sc_signal<int>& O1,
76  sc_signal<int>& O2,
77  sc_signal<int>& O3,
78  sc_signal<int>& O4,
79  sc_signal<int>& O5)
80  : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4),
81  i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
82  {
83  clk(CLK);
84  SC_CTHREAD( entry, clk.pos() );
85  reset_signal_is(reset_sig,true);
86  }
87 
88  void entry();
89 };
gem5::SparcISA::int_reg::I4
constexpr RegId I4
Definition: int.hh:125
SC_MODULE
SC_MODULE(t)
Definition: interface.h:42
gem5::SparcISA::int_reg::I3
constexpr RegId I3
Definition: int.hh:124
gem5::SparcISA::int_reg::O3
constexpr RegId O3
Definition: int.hh:104
gem5::VegaISA::t
Bitfield< 51 > t
Definition: pagetable.hh:56
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
gem5::SparcISA::int_reg::O4
constexpr RegId O4
Definition: int.hh:105
gem5::SparcISA::int_reg::O2
constexpr RegId O2
Definition: int.hh:103
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:301
gem5::SparcISA::int_reg::I1
constexpr RegId I1
Definition: int.hh:122
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:323
gem5::SparcISA::int_reg::I5
constexpr RegId I5
Definition: int.hh:126
gem5::SparcISA::int_reg::I2
constexpr RegId I2
Definition: int.hh:123
gem5::SparcISA::int_reg::O5
constexpr RegId O5
Definition: int.hh:106
gem5::SparcISA::int_reg::O1
constexpr RegId O1
Definition: int.hh:102

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