serial_link.hh

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/*
 * Copyright (c) 2011-2013 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Copyright (c) 2006 The Regents of The University of Michigan
 * Copyright (c) 2015 The University of Bologna
 * All rights reserved.
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 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * this software without specific prior written permission.
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#ifndef __MEM_SERIAL_LINK_HH__
#define __MEM_SERIAL_LINK_HH__
 
#include <deque>
 
#include "base/types.hh"
#include "mem/port.hh"
#include "params/SerialLink.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{
 
class SerialLink : public ClockedObject
{
  protected:
 
    class DeferredPacket
    {
 
      public:
 
        const Tick tick;
        const PacketPtr pkt;
 
        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
        { }
    };
 
    // Forward declaration to allow the CPU-side port to have a pointer
    class SerialLinkRequestPort;
 
    class SerialLinkResponsePort : public ResponsePort
    {
 
      private:
 
        SerialLink& serial_link;
 
        SerialLinkRequestPort& mem_side_port;
 
        const Cycles delay;
 
        const AddrRangeList ranges;
 
        std::deque<DeferredPacket> transmitList;
 
        unsigned int outstandingResponses;
 
        bool retryReq;
 
        unsigned int respQueueLimit;
 
        bool respQueueFull() const;
 
        void trySendTiming();
 
        EventFunctionWrapper sendEvent;
 
      public:
 
        SerialLinkResponsePort(const std::string& _name, SerialLink&
                        _serial_link, SerialLinkRequestPort& _mem_side_port,
                        Cycles _delay, int _resp_limit, const
                        std::vector<AddrRange>& _ranges);
 
        void schedTimingResp(PacketPtr pkt, Tick when);
 
        void retryStalledReq();
 
      protected:
 
        bool recvTimingReq(PacketPtr pkt);
 
        void recvRespRetry();
 
        Tick recvAtomic(PacketPtr pkt);
 
        void recvFunctional(PacketPtr pkt);
 
        AddrRangeList getAddrRanges() const;
    };
 
 
    class SerialLinkRequestPort : public RequestPort
    {
 
      private:
 
        SerialLink& serial_link;
 
        SerialLinkResponsePort& cpu_side_port;
 
        const Cycles delay;
 
        std::deque<DeferredPacket> transmitList;
 
        const unsigned int reqQueueLimit;
 
        void trySendTiming();
 
        EventFunctionWrapper sendEvent;
 
      public:
 
        SerialLinkRequestPort(const std::string& _name, SerialLink&
                         _serial_link, SerialLinkResponsePort& _cpu_side_port,
                         Cycles _delay, int _req_limit);
 
        bool reqQueueFull() const;
 
        void schedTimingReq(PacketPtr pkt, Tick when);
 
        bool trySatisfyFunctional(PacketPtr pkt);
 
      protected:
 
        bool recvTimingResp(PacketPtr pkt);
 
        void recvReqRetry();
    };
 
    SerialLinkResponsePort cpu_side_port;
 
    SerialLinkRequestPort mem_side_port;
 
    unsigned num_lanes;
 
    uint64_t link_speed;
 
  public:
 
    Port &getPort(const std::string &if_name,
                  PortID idx=InvalidPortID);
 
    virtual void init();
 
    typedef SerialLinkParams Params;
 
    SerialLink(const SerialLinkParams &p);
};
 
} // namespace gem5
 
#endif //__MEM_SERIAL_LINK_HH__