smmu_v3_deviceifc.hh

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/*
 * Copyright (c) 2013, 2018-2019 ARM Limited
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 *
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 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
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 * terms below provided that you ensure that this notice is replicated
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 * modified or unmodified, in source code or in binary form.
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 * met: redistributions of source code must retain the above copyright
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#ifndef __DEV_ARM_SMMU_V3_DEVICEIFC_HH__
#define __DEV_ARM_SMMU_V3_DEVICEIFC_HH__
 
#include <list>
 
#include "dev/arm/smmu_v3_caches.hh"
#include "dev/arm/smmu_v3_defs.hh"
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "params/SMMUv3DeviceInterface.hh"
#include "sim/clocked_object.hh"
 
namespace gem5
{
 
class SMMUTranslationProcess;
class SMMUv3;
class SMMUDevicePort;
 
class SMMUv3DeviceInterface : public ClockedObject
{
  protected:
    friend class SMMUTranslationProcess;
 
  public:
    SMMUv3 *smmu;
    SMMUTLB* microTLB;
    SMMUTLB* mainTLB;
 
    const bool microTLBEnable;
    const bool mainTLBEnable;
 
    SMMUSemaphore devicePortSem;
    SMMUSemaphore microTLBSem;
    SMMUSemaphore mainTLBSem;
 
    const Cycles microTLBLat;
    const Cycles mainTLBLat;
 
    SMMUDevicePort *devicePort;
    SMMUATSDevicePort  atsDevicePort;
    SMMUATSMemoryPort atsMemPort;
 
    // in bytes
    const unsigned portWidth;
 
    unsigned wrBufSlotsRemaining;
    unsigned xlateSlotsRemaining;
    unsigned pendingMemAccesses;
 
    const bool prefetchEnable;
    const bool prefetchReserveLastWay;
 
    std::list<SMMUTranslationProcess *> duplicateReqs;
    SMMUSignal duplicateReqRemoved;
 
    std::list<SMMUTranslationProcess *> dependentReads[SMMU_MAX_TRANS_ID];
    std::list<SMMUTranslationProcess *> dependentWrites[SMMU_MAX_TRANS_ID];
    SMMUSignal dependentReqRemoved;
 
    // Receiving translation requests from the requestor device
    Tick recvAtomic(PacketPtr pkt);
    bool recvTimingReq(PacketPtr pkt);
    void schedTimingResp(PacketPtr pkt);
 
    Tick atsRecvAtomic(PacketPtr pkt);
    bool atsRecvTimingReq(PacketPtr pkt);
    bool atsRecvTimingResp(PacketPtr pkt);
    void schedAtsTimingResp(PacketPtr pkt);
 
    void scheduleDeviceRetry();
    void sendDeviceRetry();
    void atsSendDeviceRetry();
 
    bool deviceNeedsRetry;
    bool atsDeviceNeedsRetry;
 
    SMMUDeviceRetryEvent sendDeviceRetryEvent;
    MemberEventWrapper<&SMMUv3DeviceInterface::atsSendDeviceRetry> atsSendDeviceRetryEvent;
 
    Port& getPort(const std::string &name, PortID id) override;
 
  public:
    PARAMS(SMMUv3DeviceInterface);
    SMMUv3DeviceInterface(const Params &p);
 
    ~SMMUv3DeviceInterface()
    {
        delete microTLB;
        delete mainTLB;
    }
 
    DrainState drain() override;
 
    void setSMMU(SMMUv3 *_smmu) { smmu = _smmu; }
    void sendRange();
};
 
} // namespace gem5
 
#endif /* __DEV_ARM_SMMU_V3_DEVICEIFC_HH__ */