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int.cc
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28 
29 #include "arch/sparc/regs/int.hh"
30 
31 #include "arch/sparc/isa.hh"
32 
33 namespace gem5
34 {
35 
36 namespace SparcISA
37 {
38 
39 RegId
40 IntRegClassOps::flatten(const BaseISA &isa, const RegId &id) const
41 {
42  auto &sparc_isa = static_cast<const SparcISA::ISA &>(isa);
43  return {flatIntRegClass, sparc_isa.mapIntRegId(id.index())};
44 }
45 
46 } // namespace SparcISA
47 } // namespace gem5
gem5::MipsISA::index
Bitfield< 30, 0 > index
Definition: pra_constants.hh:47
gem5::SparcISA::ISA
Definition: isa.hh:55
int.hh
gem5::SparcISA::flatIntRegClass
constexpr RegClass flatIntRegClass
Definition: int.hh:83
gem5::SparcISA::IntRegClassOps::flatten
RegId flatten(const BaseISA &isa, const RegId &id) const override
Flatten register id id using information in the ISA object isa.
Definition: int.cc:40
gem5::BaseISA
Definition: isa.hh:58
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
isa.hh
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:92

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