gem5::ArmISA::MiscRegLUTEntry Struct Reference

MiscReg metadata. More...

#include <misc.hh>

Public Types
using	FaultCB = std::function< Fault(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) >

Public Member Functions
Fault	checkFault (ThreadContext *tc, const MiscRegOp64 &inst, ExceptionLevel el)
	MiscRegLUTEntry ()
uint64_t	reset () const
uint64_t	res0 () const
uint64_t	res1 () const
uint64_t	raz () const
uint64_t	rao () const
uint64_t	wi () const

Public Attributes
uint32_t	lower
uint32_t	upper
uint64_t	_reset
uint64_t	_res0
uint64_t	_res1
uint64_t	_raz
uint64_t	_rao
std::bitset< NUM_MISCREG_INFOS >	info
std::array< FaultCB, EL3+1 >	faultRead
std::array< FaultCB, EL3+1 >	faultWrite

Static Protected Member Functions
template<MiscRegInfo Sec, MiscRegInfo NonSec>
static Fault	defaultFault (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)

Detailed Description

MiscReg metadata.

Definition at line 1189 of file misc.hh.

Member Typedef Documentation

FaultCB

using gem5::ArmISA::MiscRegLUTEntry::FaultCB = std::function< Fault(const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst) >

Definition at line 1203 of file misc.hh.

Constructor & Destructor Documentation

MiscRegLUTEntry()

gem5::ArmISA::MiscRegLUTEntry::MiscRegLUTEntry ( )

inline

Definition at line 1217 of file misc.hh.

Member Function Documentation

checkFault()

Fault gem5::ArmISA::MiscRegLUTEntry::checkFault	(	ThreadContext *	tc,
		const MiscRegOp64 &	inst,
		ExceptionLevel	el
	)

Definition at line 2199 of file misc.cc.

References gem5::ArmISA::el, faultRead, faultWrite, and gem5::MiscRegOp64::miscRead().

defaultFault()

template<MiscRegInfo Sec, MiscRegInfo NonSec>

Fault gem5::ArmISA::MiscRegLUTEntry::defaultFault ( const MiscRegLUTEntry &  entry, ThreadContext *  tc, const MiscRegOp64 &  inst  )

staticprotected

Definition at line 2208 of file misc.cc.

References info, gem5::ArmISA::isSecureBelowEL3(), gem5::NoFault, and gem5::ArmISA::ArmStaticInst::undefined().

rao()

uint64_t gem5::ArmISA::MiscRegLUTEntry::rao ( ) const

inline

Definition at line 1233 of file misc.hh.

References _rao.

raz()

uint64_t gem5::ArmISA::MiscRegLUTEntry::raz ( ) const

inline

Definition at line 1232 of file misc.hh.

References _raz.

res0()

uint64_t gem5::ArmISA::MiscRegLUTEntry::res0 ( ) const

inline

Definition at line 1230 of file misc.hh.

References _res0.

res1()

uint64_t gem5::ArmISA::MiscRegLUTEntry::res1 ( ) const

inline

Definition at line 1231 of file misc.hh.

References _res1.

reset()

uint64_t gem5::ArmISA::MiscRegLUTEntry::reset ( ) const

inline

Definition at line 1229 of file misc.hh.

References _reset.

wi()

uint64_t gem5::ArmISA::MiscRegLUTEntry::wi ( ) const

inline

Definition at line 1235 of file misc.hh.

References _rao, and _raz.

Member Data Documentation

_rao

uint64_t gem5::ArmISA::MiscRegLUTEntry::_rao

Definition at line 1197 of file misc.hh.

Referenced by rao(), gem5::ArmISA::MiscRegLUTEntryInitializer::rao(), and wi().

_raz

uint64_t gem5::ArmISA::MiscRegLUTEntry::_raz

Definition at line 1196 of file misc.hh.

Referenced by raz(), gem5::ArmISA::MiscRegLUTEntryInitializer::raz(), and wi().

_res0

uint64_t gem5::ArmISA::MiscRegLUTEntry::_res0

Definition at line 1194 of file misc.hh.

Referenced by res0(), and gem5::ArmISA::MiscRegLUTEntryInitializer::res0().

_res1

uint64_t gem5::ArmISA::MiscRegLUTEntry::_res1

Definition at line 1195 of file misc.hh.

Referenced by res1(), and gem5::ArmISA::MiscRegLUTEntryInitializer::res1().

_reset

uint64_t gem5::ArmISA::MiscRegLUTEntry::_reset

Definition at line 1193 of file misc.hh.

Referenced by reset(), and gem5::ArmISA::MiscRegLUTEntryInitializer::reset().

faultRead

std::array<FaultCB, EL3 + 1> gem5::ArmISA::MiscRegLUTEntry::faultRead

Definition at line 1205 of file misc.hh.

Referenced by checkFault(), and gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead().

faultWrite

std::array<FaultCB, EL3 + 1> gem5::ArmISA::MiscRegLUTEntry::faultWrite

Definition at line 1206 of file misc.hh.

Referenced by checkFault(), and gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite().

info

std::bitset<NUM_MISCREG_INFOS> gem5::ArmISA::MiscRegLUTEntry::info

Definition at line 1198 of file misc.hh.

Referenced by gem5::ArmISA::MiscRegLUTEntryInitializer::banked(), gem5::ArmISA::MiscRegLUTEntryInitializer::banked64(), gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild(), defaultFault(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::implemented(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::mutex(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::unserialize(), gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite(), and gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail().

lower

uint32_t gem5::ArmISA::MiscRegLUTEntry::lower

Definition at line 1191 of file misc.hh.

Referenced by gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo().

upper

uint32_t gem5::ArmISA::MiscRegLUTEntry::upper

Definition at line 1192 of file misc.hh.

Referenced by gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo().

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The documentation for this struct was generated from the following files:

• arch/arm/regs/misc.hh
• arch/arm/regs/misc.cc