sve.hh

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/*
 * Copyright (c) 2017-2019 ARM Limited
 * All rights reserved
 *
 * The license below extends only to copyright in the software and shall
 * not be construed as granting a license to any other intellectual
 * property including but not limited to intellectual property relating
 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
 * unmodified and in its entirety in all distributions of the software,
 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef __ARCH_ARM_INSTS_SVE_HH__
#define __ARCH_ARM_INSTS_SVE_HH__
 
#include "arch/arm/insts/static_inst.hh"
 
namespace gem5
{
 
namespace ArmISA {
 
enum class SvePredType
{
    NONE,
    MERGE,
    ZERO,
    SELECT
};
 
const char* svePredTypeToStr(SvePredType pt);
 
class SveIndexIIOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    int8_t imm1;
    int8_t imm2;
 
    SveIndexIIOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest,
            int8_t _imm1, int8_t _imm2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), imm1(_imm1), imm2(_imm2)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveIndexIROp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    int8_t imm1;
    RegIndex op2;
 
    SveIndexIROp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest,
            int8_t _imm1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
          dest(_dest), imm1(_imm1), op2(_op2)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveIndexRIOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    int8_t imm2;
 
    SveIndexRIOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest,
            RegIndex _op1, int8_t _imm2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), imm2(_imm2)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveIndexRROp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex op2;
 
    SveIndexRROp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest,
            RegIndex _op1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
// Predicate count SVE instruction.
class SvePredCountOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex gp;
    bool srcIs32b;
    bool destIsVec;
 
    SvePredCountOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _gp,
            bool _srcIs32b = false, bool _destIsVec = false) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), gp(_gp),
        srcIs32b(_srcIs32b), destIsVec(_destIsVec)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
// Predicate count SVE instruction (predicated).
class SvePredCountPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex gp;
 
    SvePredCountPredOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveWhileOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
    bool srcIs32b;
 
    SveWhileOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
               RegIndex _dest, RegIndex _op1, RegIndex _op2,
               bool _srcIs32b) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePselOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex gp;
    RegIndex op2;
    uint64_t imm;
 
    SvePselOp(const char *mnem, ExtMachInst _machInst,
              OpClass __opClass, RegIndex _dest,
              RegIndex _op1, RegIndex _gp,
              RegIndex _op2, uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp), op2(_op2), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveCompTermOp : public ArmStaticInst
{
  protected:
    RegIndex op1, op2;
 
    SveCompTermOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                  RegIndex _op1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        op1(_op1), op2(_op2)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnaryPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, gp;
 
    SveUnaryPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                   RegIndex _dest, RegIndex _op1, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnaryUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1;
 
    SveUnaryUnpredOp(const char* mnem, ExtMachInst _machInst,
                     OpClass __opClass, RegIndex _dest, RegIndex _op1) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnaryWideImmUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    uint64_t imm;
 
    SveUnaryWideImmUnpredOp(const char* mnem, ExtMachInst _machInst,
                            OpClass __opClass, RegIndex _dest,
                            uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnaryWideImmPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    uint64_t imm;
    RegIndex gp;
 
    bool isMerging;
 
    SveUnaryWideImmPredOp(const char* mnem, ExtMachInst _machInst,
                          OpClass __opClass, RegIndex _dest,
                          uint64_t _imm, RegIndex _gp, bool _isMerging) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), imm(_imm), gp(_gp), isMerging(_isMerging)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinImmUnpredConstrOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1;
    uint64_t imm;
 
    SveBinImmUnpredConstrOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinImmPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, gp;
    uint64_t imm;
 
    SveBinImmPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                    RegIndex _dest, uint64_t _imm, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), gp(_gp), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinWideImmUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    uint64_t imm;
 
    SveBinWideImmUnpredOp(const char* mnem, ExtMachInst _machInst,
                          OpClass __opClass, RegIndex _dest,
                          uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinDestrPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op2, gp;
 
    SveBinDestrPredOp(const char* mnem, ExtMachInst _machInst,
                      OpClass __opClass, RegIndex _dest, RegIndex _op2,
                      RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op2(_op2), gp(_gp)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinConstrPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2, gp;
    SvePredType predType;
 
    SveBinConstrPredOp(const char* mnem, ExtMachInst _machInst,
                       OpClass __opClass, RegIndex _dest, RegIndex _op1,
                       RegIndex _op2, RegIndex _gp,
                       SvePredType _predType) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), gp(_gp), predType(_predType)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
 
    SveBinUnpredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                   RegIndex _dest, RegIndex _op1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinIdxUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
    uint8_t index;
 
    SveBinIdxUnpredOp(const char* mnem, ExtMachInst _machInst,
                      OpClass __opClass, RegIndex _dest, RegIndex _op1,
                      RegIndex _op2, uint8_t _index) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), index(_index)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePredLogicalOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2, gp;
    bool isSel;
 
    SvePredLogicalOp(const char* mnem, ExtMachInst _machInst,
                     OpClass __opClass, RegIndex _dest, RegIndex _op1,
                     RegIndex _op2, RegIndex _gp, bool _isSel = false) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), gp(_gp), isSel(_isSel)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePredBinPermOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
 
    SvePredBinPermOp(const char* mnem, ExtMachInst _machInst,
                     OpClass __opClass, RegIndex _dest, RegIndex _op1,
                     RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveCmpOp : public ArmStaticInst
{
  protected:
    RegIndex dest, gp, op1, op2;
 
    SveCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
             RegIndex _dest, RegIndex _op1, RegIndex _op2,
             RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), gp(_gp), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveCmpImmOp : public ArmStaticInst
{
  protected:
    RegIndex dest, gp, op1;
    uint64_t imm;
 
    SveCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                RegIndex _dest, RegIndex _op1, uint64_t _imm,
                RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), gp(_gp), op1(_op1), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveTerPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2, gp;
 
    SveTerPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                 RegIndex _dest, RegIndex _op1, RegIndex _op2,
                 RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), gp(_gp)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveTerUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
 
    SveTerUnpredOp(const char* mnem, ExtMachInst _machInst,
                    OpClass __opClass, RegIndex _dest,
                    RegIndex _op1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveTerImmUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op2;
    uint64_t imm;
 
    SveTerImmUnpredOp(const char* mnem, ExtMachInst _machInst,
                      OpClass __opClass, RegIndex _dest, RegIndex _op2,
                      uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op2(_op2), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveReducOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, gp;
 
    SveReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
               RegIndex _dest, RegIndex _op1, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveOrdReducOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, gp;
 
    SveOrdReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
               RegIndex _dest, RegIndex _op1, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePtrueOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    uint8_t imm;
 
    SvePtrueOp(const char* mnem, ExtMachInst _machInst,
               OpClass __opClass, RegIndex _dest, uint8_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveIntCmpOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1, op2;
    RegIndex gp;
    bool op2IsWide;
 
    SveIntCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                  RegIndex _dest, RegIndex _op1, RegIndex _op2,
                  RegIndex _gp, bool _op2IsWide = false) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveIntCmpImmOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    int64_t imm;
    RegIndex gp;
 
    SveIntCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                  RegIndex _dest, RegIndex _op1, int64_t _imm,
                  RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), imm(_imm), gp(_gp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveAdrOp : public ArmStaticInst
{
  public:
    enum SveAdrOffsetFormat
    {
        SveAdrOffsetPacked,
        SveAdrOffsetUnpackedSigned,
        SveAdrOffsetUnpackedUnsigned
    };
 
  protected:
    RegIndex dest, op1, op2;
    uint8_t mult;
    SveAdrOffsetFormat offsetFormat;
 
    SveAdrOp(const char* mnem, ExtMachInst _machInst,
             OpClass __opClass, RegIndex _dest, RegIndex _op1,
             RegIndex _op2, uint8_t _mult,
             SveAdrOffsetFormat _offsetFormat) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), mult(_mult),
        offsetFormat(_offsetFormat)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveElemCountOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    uint8_t pattern;
    uint8_t imm;
    bool dstIsVec;
    bool dstIs32b;
    uint8_t esize;
 
    SveElemCountOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                  RegIndex _dest, uint8_t _pattern, uint8_t _imm,
                  bool _dstIsVec, bool _dstIs32b) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), pattern(_pattern), imm(_imm), dstIsVec(_dstIsVec),
        dstIs32b(_dstIs32b)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePartBrkOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex gp;
    RegIndex op1;
    bool isMerging;
 
    SvePartBrkOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                  RegIndex _dest, RegIndex _gp, RegIndex _op1,
                  bool _isMerging) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePartBrkPropOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex op2;
    RegIndex gp;
 
    SvePartBrkPropOp(const char* mnem, ExtMachInst _machInst,
                     OpClass __opClass, RegIndex _dest,
                     RegIndex _op1, RegIndex _op2, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), gp(_gp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveSelectOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex gp;
    bool conditional;
    bool scalar;
    bool simdFp;
    size_t scalar_width;
 
    SveSelectOp(const char* mnem, ExtMachInst _machInst,
                      OpClass __opClass, RegIndex _dest,
                      RegIndex _op1, RegIndex _gp,
                      bool _conditional, bool _scalar,
                      bool _simdFp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp), conditional(_conditional),
        scalar(_scalar), simdFp(_simdFp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnaryPredPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex gp;
 
    SveUnaryPredPredOp(const char* mnem, ExtMachInst _machInst,
                       OpClass __opClass, RegIndex _dest,
                       RegIndex _op1, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), gp(_gp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveTblOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex op2;
 
    SveTblOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
            RegIndex _dest, RegIndex _op1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnpackOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
 
    SveUnpackOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                RegIndex _dest, RegIndex _op1) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePredTestOp : public ArmStaticInst
{
  protected:
    RegIndex op1;
    RegIndex gp;
 
    SvePredTestOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
                RegIndex _op1, RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        op1(_op1), gp(_gp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePredUnaryWImplicitSrcOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
 
    SvePredUnaryWImplicitSrcOp(const char* mnem, ExtMachInst _machInst,
                               OpClass __opClass, RegIndex _dest) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex gp;
 
    SvePredUnaryWImplicitSrcPredOp(const char* mnem, ExtMachInst _machInst,
                                   OpClass __opClass, RegIndex _dest,
                                   RegIndex _gp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), gp(_gp)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SvePredUnaryWImplicitDstOp : public ArmStaticInst
{
  protected:
    RegIndex op1;
 
    SvePredUnaryWImplicitDstOp(const char* mnem, ExtMachInst _machInst,
                               OpClass __opClass, RegIndex _op1) :
        ArmStaticInst(mnem, _machInst, __opClass),
        op1(_op1)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveWImplicitSrcDstOp : public ArmStaticInst
{
  protected:
    SveWImplicitSrcDstOp(const char* mnem, ExtMachInst _machInst,
                         OpClass __opClass) :
        ArmStaticInst(mnem, _machInst, __opClass)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinImmUnpredDestrOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    uint64_t imm;
 
    SveBinImmUnpredDestrOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), imm(_imm)
    {}
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveBinImmIdxUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1;
    uint64_t imm;
 
    SveBinImmIdxUnpredOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveUnarySca2VecUnpredOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1;
    bool simdFp;
 
    SveUnarySca2VecUnpredOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            bool _simdFp) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), simdFp(_simdFp)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveDotProdIdxOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
    uint64_t imm;
    uint8_t esize;
 
  public:
    SveDotProdIdxOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            RegIndex _op2, uint64_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveDotProdOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
    uint8_t esize;
 
  public:
    SveDotProdOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveComplexOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2, gp;
    uint8_t rot;
 
  public:
    SveComplexOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            RegIndex _op2, RegIndex _gp, uint8_t _rot) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), gp(_gp), rot(_rot)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
class SveComplexIdxOp : public ArmStaticInst
{
  protected:
    RegIndex dest, op1, op2;
    uint8_t rot, imm;
 
  public:
    SveComplexIdxOp(const char* mnem, ExtMachInst _machInst,
            OpClass __opClass, RegIndex _dest, RegIndex _op1,
            RegIndex _op2, uint8_t _rot, uint8_t _imm) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2), rot(_rot), imm(_imm)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
// SVE2 SCLAMP/UCLAMP instructions
class SveClampOp : public ArmStaticInst
{
  protected:
    RegIndex dest;
    RegIndex op1;
    RegIndex op2;
 
    SveClampOp(const char *mnem, ExtMachInst _machInst,
                  OpClass __opClass, RegIndex _dest,
                  RegIndex _op1, RegIndex _op2) :
        ArmStaticInst(mnem, _machInst, __opClass),
        dest(_dest), op1(_op1), op2(_op2)
    {}
 
    std::string generateDisassembly(
            Addr pc, const loader::SymbolTable *symtab) const override;
};
 
 
std::string sveDisasmPredCountImm(uint8_t imm);
 
unsigned int sveDecodePredCount(uint8_t imm, unsigned int num_elems);
 
uint64_t sveExpandFpImmAddSub(uint8_t imm, uint8_t size);
 
uint64_t sveExpandFpImmMaxMin(uint8_t imm, uint8_t size);
 
uint64_t sveExpandFpImmMul(uint8_t imm, uint8_t size);
 
} // namespace ArmISA
} // namespace gem5
 
#endif  // __ARCH_ARM_INSTS_SVE_HH__