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36 #ifndef __ARCH_GENERIC_VEC_PRED_REG_HH__
37 #define __ARCH_GENERIC_VEC_PRED_REG_HH__
43 #include <type_traits>
53 template <
size_t NumBits,
bool Packed>
72 template <
typename VecElem,
size_t NumElems,
bool Packed,
bool Const>
77 static constexpr
size_t NUM_BITS = Packed ? NumElems :
82 using Container =
typename std::conditional_t<
97 template<
bool Condition = !Const>
101 template<
bool Condition = !Const>
104 template<
bool Condition = !Const>
105 std::enable_if_t<Condition, MyClass&>
118 template<
bool Condition = !Const>
119 std::enable_if_t<Condition, bool&>
131 (Packed ? 1 :
sizeof(
VecElem)));
135 template<
bool Condition = !Const>
136 std::enable_if_t<Condition>
144 template<
typename VE2,
size_t NE2,
bool P2,
bool C2>
152 template<
typename VE2,
size_t NE2,
bool P2,
bool C2>
176 size_t actual_num_elems)
const
178 assert(actual_num_elems <= NumElems);
179 for (
int i = 0;
i < actual_num_elems; ++
i) {
194 size_t actual_num_elems)
const
196 assert(actual_num_elems <= NumElems);
197 for (
int i = 0;
i < actual_num_elems; ++
i) {
198 if (
mask[
i] &&
operator[](
i)) {
212 size_t actual_num_elems)
const
214 assert(actual_num_elems <= NumElems);
215 for (
int i = actual_num_elems - 1;
i >= 0; --
i) {
230 template <
size_t NumBits,
bool Packed>
233 static_assert(NumBits > 0,
234 "Size of a predicate register must be > 0");
263 std::copy(that.begin(), that.end(),
container.begin());
282 template<
size_t N2,
bool P2>
286 return NumBits == N2 && Packed == P2 &&
container == that.container;
290 template<
size_t N2,
bool P2>
309 assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
311 idx = idx + nbits - 1;
312 for (
int i = 0;
i < nbits; ++
i, --idx) {
322 setBits(
size_t idx, uint8_t nbits, uint8_t bval)
324 assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits);
325 for (
int i = 0;
i < nbits; ++
i, ++idx) {
335 for (
int i = 0;
i < NumBits;
i++)
347 template <
typename VecElem>
351 static_assert(NumBits %
sizeof(
VecElem) == 0,
352 "Container size incompatible with view size.");
354 Packed ? NumBits : (NumBits /
sizeof(
VecElem)),
355 Packed,
true>(*this);
358 template <
typename VecElem>
362 static_assert(NumBits %
sizeof(
VecElem) == 0,
363 "Container size incompatible with view size.");
365 Packed ? NumBits : (NumBits /
sizeof(
VecElem)),
366 Packed,
false>(*this);
371 template <
size_t NumBits,
bool Packed>
378 for (
const auto&
c:
s)
379 value[
i++] = (
c ==
'1');
384 template <
size_t NumBits,
bool Packed>
390 for (
auto b: value.container)
403 template <
typename VecElem>
415 static_assert(
sizeof(DummyVecPredRegContainer) ==
sizeof(
RegVal));
416 static inline std::ostream &
425 #endif // __ARCH_GENERIC_VEC_PRED_REG_HH__
void setBits(size_t idx, uint8_t nbits, uint8_t bval)
Set a subset of bits starting from a specific element in the container.
bool operator!=(const VecPredRegContainer< N2, P2 > &that) const
Inequality operator, required to compare thread contexts.
Generic predicate register container.
VecPredReg::Container VecPredRegContainer
uint8_t getRaw(size_t idx) const
Return an element of the predicate register as it appears in the raw (untyped) internal representatio...
std::enable_if_t< Condition > setRaw(size_t idx, uint8_t val)
Write a raw value in an element of the predicate register.
static std::ostream & operator<<(std::ostream &os, const DummyMatRegContainer &d)
bool firstActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the first active element of the register is true.
const bool & operator[](size_t idx) const
bool operator!=(const DummyVecPredRegContainer &d) const
void ccprintf(cp::Print &print)
bool operator!=(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Inequality operator, required to compare thread contexts.
constexpr uint64_t mask(unsigned nbits)
Generate a 64-bit mask of 'nbits' 1s, right justified.
void set()
Sets the predicate register to an all-true value.
bool operator==(const VecPredRegT< VE2, NE2, P2, C2 > &that) const
Equality operator, required to compare thread contexts.
MyClass & operator=(const MyClass &that)
auto as() const
Create a view of this container.
const bool & operator[](size_t idx) const
Returns a const reference to a specific element of the internal container.
uint8_t getBits(size_t idx, uint8_t nbits) const
Returns a subset of bits starting from a specific element in the container.
std::enable_if_t< Condition > set()
Reset the register to an all-true value.
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
std::enable_if_t< Condition > reset()
Reset the register to an all-false value.
std::enable_if_t< Condition, bool & > operator[](size_t idx)
MyClass & operator=(const std::vector< uint8_t > &that)
Required for de-serialization.
static bool parse(const std::string &s, DummyVecPredRegContainer &value)
typename std::conditional_t< Const, const VecPredRegContainer< NUM_BITS, Packed >, VecPredRegContainer< NUM_BITS, Packed > > Container
Container type alias.
bool lastActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if the last active element of the register is true.
bool & operator[](size_t idx)
Returns a reference to a specific element of the internal container.
VecPredRegContainer< NumBits, Packed > MyClass
static constexpr size_t NUM_BITS
Container & container
Container corresponding to this view.
static constexpr size_t NUM_BITS
Size of the register in bits.
void reset()
Resets the predicate register to an all-false register.
Dummy type aliases and constants for architectures that do not implement vector predicate registers.
static bool parse(const std::string &s, VecPredRegContainer< NumBits, Packed > &value)
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
std::array< bool, NumBits > Container
VecPredRegT(Container &c)
friend std::ostream & operator<<(std::ostream &os, const MyClass &p)
bool operator==(const VecPredRegContainer< N2, P2 > &that) const
Equality operator, required to compare thread contexts.
bool noneActive(const VecPredRegT< VecElem, NumElems, Packed, MC > &mask, size_t actual_num_elems) const
Returns true if there are no active elements in the register.
static void show(std::ostream &os, const VecPredRegContainer< NumBits, Packed > &value)
bool operator==(const DummyVecPredRegContainer &d) const
std::enable_if_t< Condition, MyClass & > operator=(const MyClass &that)
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