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arch
x86
pseudo_inst_abi.hh
Go to the documentation of this file.
1
/*
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* Copyright (c) 2020 The Regents of the University of California.
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
6
* not be construed as granting a license to any other intellectual
7
* property including but not limited to intellectual property relating
8
* to a hardware implementation of the functionality of the software
9
* licensed hereunder. You may use the software subject to the license
10
* terms below provided that you ensure that this notice is replicated
11
* unmodified and in its entirety in all distributions of the software,
12
* modified or unmodified, in source code or in binary form.
13
*
14
* Redistribution and use in source and binary forms, with or without
15
* modification, are permitted provided that the following conditions are
16
* met: redistributions of source code must retain the above copyright
17
* notice, this list of conditions and the following disclaimer;
18
* redistributions in binary form must reproduce the above copyright
19
* notice, this list of conditions and the following disclaimer in the
20
* documentation and/or other materials provided with the distribution;
21
* neither the name of the copyright holders nor the names of its
22
* contributors may be used to endorse or promote products derived from
23
* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
*/
37
38
#include "
arch/x86/regs/int.hh
"
39
#include "
sim/guest_abi.hh
"
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namespace
gem5
42
{
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44
struct
X86PseudoInstABI
45
{
46
using
State
= int;
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};
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namespace
guest_abi
50
{
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52
template
<
typename
T>
53
struct
Result
<
X86PseudoInstABI
, T>
54
{
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static
void
56
store
(
ThreadContext
*tc,
const
T &ret)
57
{
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// This assumes that all pseudo ops have their return value set
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// by the pseudo op instruction. This may need to be revisited if we
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// modify the pseudo op ABI in util/m5/m5op_x86.S
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tc->
setReg
(
X86ISA::int_reg::Rax
, ret);
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}
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};
64
65
template
<>
66
struct
Argument
<
X86PseudoInstABI
, uint64_t>
67
{
68
static
uint64_t
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get
(
ThreadContext
*tc,
X86PseudoInstABI::State
&
state
)
70
{
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// The first 6 integer arguments are passed in registers, the rest
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// are passed on the stack.
73
74
panic_if
(
state
>= 6,
"Too many psuedo inst arguments."
);
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using namespace
X86ISA;
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78
constexpr
RegId
int_reg_map[] = {
79
int_reg::Rdi
,
int_reg::Rsi
,
int_reg::Rdx
,
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int_reg::Rcx
,
int_reg::R8
,
int_reg::R9
81
};
82
83
return
tc->
getReg
(int_reg_map[
state
++]);
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}
85
};
86
87
}
// namespace guest_abi
88
}
// namespace gem5
gem5::X86PseudoInstABI::State
int State
Definition:
pseudo_inst_abi.hh:46
gem5::X86ISA::int_reg::Rsi
constexpr RegId Rsi
Definition:
int.hh:138
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId ®) const
Definition:
thread_context.cc:180
gem5::X86ISA::int_reg::Rcx
constexpr RegId Rcx
Definition:
int.hh:133
gem5::ArmISA::int_reg::R8
constexpr RegId R8
Definition:
int.hh:194
gem5::guest_abi::Result< X86PseudoInstABI, T >::store
static void store(ThreadContext *tc, const T &ret)
Definition:
pseudo_inst_abi.hh:56
gem5::X86PseudoInstABI
Definition:
pseudo_inst_abi.hh:44
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition:
thread_context.hh:88
gem5::X86ISA::int_reg::Rdx
constexpr RegId Rdx
Definition:
int.hh:134
int.hh
gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get
static uint64_t get(ThreadContext *tc, X86PseudoInstABI::State &state)
Definition:
pseudo_inst_abi.hh:69
state
atomic_var_t state
Definition:
helpers.cc:188
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition:
logging.hh:214
gem5::X86ISA::int_reg::Rdi
constexpr RegId Rdi
Definition:
int.hh:139
gem5::X86ISA::int_reg::Rax
constexpr RegId Rax
Definition:
int.hh:132
guest_abi.hh
gem5::guest_abi::Argument
Definition:
definition.hh:98
gem5::guest_abi::Result
Definition:
definition.hh:63
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition:
gpu_translation_state.hh:37
gem5::ArmISA::int_reg::R9
constexpr RegId R9
Definition:
int.hh:195
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition:
reg_class.hh:92
gem5::ThreadContext::setReg
virtual void setReg(const RegId ®, RegVal val)
Definition:
thread_context.cc:188
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