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pseudo_inst_abi.hh
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37 
38 #include "arch/x86/regs/int.hh"
39 #include "sim/guest_abi.hh"
40 
41 namespace gem5
42 {
43 
45 {
46  using State = int;
47 };
48 
49 namespace guest_abi
50 {
51 
52 template <typename T>
54 {
55  static void
56  store(ThreadContext *tc, const T &ret)
57  {
58  // This assumes that all pseudo ops have their return value set
59  // by the pseudo op instruction. This may need to be revisited if we
60  // modify the pseudo op ABI in util/m5/m5op_x86.S
61  tc->setReg(X86ISA::int_reg::Rax, ret);
62  }
63 };
64 
65 template <>
66 struct Argument<X86PseudoInstABI, uint64_t>
67 {
68  static uint64_t
70  {
71  // The first 6 integer arguments are passed in registers, the rest
72  // are passed on the stack.
73 
74  panic_if(state >= 6, "Too many psuedo inst arguments.");
75 
76  using namespace X86ISA;
77 
78  constexpr RegId int_reg_map[] = {
81  };
82 
83  return tc->getReg(int_reg_map[state++]);
84  }
85 };
86 
87 } // namespace guest_abi
88 } // namespace gem5
gem5::X86PseudoInstABI::State
int State
Definition: pseudo_inst_abi.hh:46
gem5::X86ISA::int_reg::Rsi
constexpr RegId Rsi
Definition: int.hh:138
gem5::ThreadContext::getReg
virtual RegVal getReg(const RegId &reg) const
Definition: thread_context.cc:180
gem5::X86ISA::int_reg::Rcx
constexpr RegId Rcx
Definition: int.hh:133
gem5::ArmISA::int_reg::R8
constexpr RegId R8
Definition: int.hh:194
gem5::guest_abi::Result< X86PseudoInstABI, T >::store
static void store(ThreadContext *tc, const T &ret)
Definition: pseudo_inst_abi.hh:56
gem5::X86PseudoInstABI
Definition: pseudo_inst_abi.hh:44
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:88
gem5::X86ISA::int_reg::Rdx
constexpr RegId Rdx
Definition: int.hh:134
int.hh
gem5::guest_abi::Argument< X86PseudoInstABI, uint64_t >::get
static uint64_t get(ThreadContext *tc, X86PseudoInstABI::State &state)
Definition: pseudo_inst_abi.hh:69
state
atomic_var_t state
Definition: helpers.cc:188
panic_if
#define panic_if(cond,...)
Conditional panic macro that checks the supplied condition and only panics if the condition is true a...
Definition: logging.hh:214
gem5::X86ISA::int_reg::Rdi
constexpr RegId Rdi
Definition: int.hh:139
gem5::X86ISA::int_reg::Rax
constexpr RegId Rax
Definition: int.hh:132
guest_abi.hh
gem5::guest_abi::Argument
Definition: definition.hh:98
gem5::guest_abi::Result
Definition: definition.hh:63
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::int_reg::R9
constexpr RegId R9
Definition: int.hh:195
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:92
gem5::ThreadContext::setReg
virtual void setReg(const RegId &reg, RegVal val)
Definition: thread_context.cc:188

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