gem5 v24.0.0.0
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SimpleLTTarget2.h
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1/*****************************************************************************
2
3 Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
4 more contributor license agreements. See the NOTICE file distributed
5 with this work for additional information regarding copyright ownership.
6 Accellera licenses this file to you under the Apache License, Version 2.0
7 (the "License"); you may not use this file except in compliance with the
8 License. You may obtain a copy of the License at
9
10 http://www.apache.org/licenses/LICENSE-2.0
11
12 Unless required by applicable law or agreed to in writing, software
13 distributed under the License is distributed on an "AS IS" BASIS,
14 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 permissions and limitations under the License.
17
18 *****************************************************************************/
19
20#ifndef __SIMPLE_LT_TARGET2_H__
21#define __SIMPLE_LT_TARGET2_H__
22
23#include "tlm.h"
24#include "tlm_utils/passthrough_target_socket.h"
25#include <cassert>
26#include <vector>
27
29{
30public:
35
36
37public:
39
40public:
42 sc_core::sc_module(name),
43 socket("socket")
44 {
45 // register nb_transport method
49
50 // TODO: we don't register the transport_dbg callback here, so we
51 // can test if something bad happens
52 // REGISTER_DEBUGTRANSPORT(socket, transport_dbg, 0);
53 }
54
57 {
58 sc_dt::uint64 address = trans.get_address();
59 assert(address < 400);
60
61 unsigned int& data = *reinterpret_cast<unsigned int*>(trans.get_data_ptr());
62 if (trans.get_command() == tlm::TLM_WRITE_COMMAND) {
63 std::cout << name() << ": Received write request: A = 0x"
64 << std::hex << (unsigned int)address
65 << ", D = 0x" << data << std::dec
66 << " @ " << sc_core::sc_time_stamp() << std::endl;
67
68 *reinterpret_cast<unsigned int*>(&mMem[address]) = data;
70
71 } else {
72 std::cout << name() << ": Received read request: A = 0x"
73 << std::hex << (unsigned int)address << std::dec
74 << " @ " << sc_core::sc_time_stamp() << std::endl;
75
76 data = *reinterpret_cast<unsigned int*>(&mMem[address]);
78 }
79
81
82 trans.set_dmi_allowed(true);
83 }
84
86 phase_type& phase,
88 {
89 assert(phase == tlm::BEGIN_REQ);
90
91 // Never blocks, so call b_transport implementation
92 myBTransport(trans, t);
93 // LT target
94 // - always return TLM_COMPLETED
95 // - not necessary to update phase (if TLM_COMPLETED is returned)
96 return tlm::TLM_COMPLETED;
97 }
98
100 {
101 if (r.get_address() >= 400) return 0;
102
103 unsigned int tmp = (int)r.get_address();
104 unsigned int num_bytes;
105 if (tmp + r.get_data_length() >= 400) {
106 num_bytes = 400 - tmp;
107
108 } else {
109 num_bytes = r.get_data_length();
110 }
111 if (r.is_read()) {
112 for (unsigned int i = 0; i < num_bytes; ++i) {
113 r.get_data_ptr()[i] = mMem[i + tmp];
114 }
115
116 } else {
117 for (unsigned int i = 0; i < num_bytes; ++i) {
118 mMem[i + tmp] = r.get_data_ptr()[i];
119 }
120 }
121 return num_bytes;
122 }
123
125 tlm::tlm_dmi& dmi_data)
126 {
127 sc_dt::uint64 address = trans.get_address();
128 if (address < 400) {
129 dmi_data.allow_read_write();
130 dmi_data.set_start_address(0x0);
131 dmi_data.set_end_address(399);
132 dmi_data.set_dmi_ptr(mMem);
135 return true;
136
137 } else {
138 // should not happen
139 dmi_data.set_start_address(address);
140 dmi_data.set_end_address(address);
141 return false;
142
143 }
144 }
145private:
146 unsigned char mMem[400];
147};
148
149#endif
const char data[]
tlm::tlm_sync_enum sync_enum_type
target_socket_type socket
void myBTransport(transaction_type &trans, sc_core::sc_time &t)
SimpleLTTarget2(sc_core::sc_module_name name)
unsigned int transport_dbg(transaction_type &r)
sync_enum_type myNBTransport(transaction_type &trans, phase_type &phase, sc_core::sc_time &t)
bool myGetDMIPtr(transaction_type &trans, tlm::tlm_dmi &dmi_data)
tlm::tlm_phase phase_type
unsigned char mMem[400]
tlm_utils::passthrough_target_socket< SimpleLTTarget2 > target_socket_type
tlm::tlm_generic_payload transaction_type
const char * name() const
Definition sc_object.cc:44
void set_write_latency(sc_core::sc_time t)
Definition dmi.hh:85
void set_dmi_ptr(unsigned char *p)
Definition dmi.hh:81
void set_start_address(sc_dt::uint64 addr)
Definition dmi.hh:82
void set_end_address(sc_dt::uint64 addr)
Definition dmi.hh:83
void set_read_latency(sc_core::sc_time t)
Definition dmi.hh:84
void allow_read_write()
Definition dmi.hh:90
unsigned char * get_data_ptr() const
Definition gp.hh:188
void set_dmi_allowed(bool dmi_allowed)
Definition gp.hh:239
void set_response_status(const tlm_response_status response_status)
Definition gp.hh:204
sc_dt::uint64 get_address() const
Definition gp.hh:184
tlm_command get_command() const
Definition gp.hh:180
void register_get_direct_mem_ptr(MODULE *mod, bool(MODULE::*cb)(transaction_type &, tlm::tlm_dmi &))
void register_nb_transport_fw(MODULE *mod, sync_enum_type(MODULE::*cb)(transaction_type &, phase_type &, sc_core::sc_time &))
void register_b_transport(MODULE *mod, void(MODULE::*cb)(transaction_type &, sc_core::sc_time &))
@ SC_NS
Definition sc_time.hh:43
const sc_time & sc_time_stamp()
Definition sc_main.cc:127
uint64_t uint64
Definition sc_nbdefs.hh:172
@ BEGIN_REQ
Definition phase.hh:41
@ TLM_WRITE_COMMAND
Definition gp.hh:85
@ TLM_OK_RESPONSE
Definition gp.hh:91
tlm_sync_enum
Definition fw_bw_ifs.hh:31
@ TLM_COMPLETED
Definition fw_bw_ifs.hh:31

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