gem5  v21.1.0.2
dmi.hh
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19 
20 #ifndef __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__
21 #define __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__
22 
23 #include "../../../core/sc_time.hh"
24 #include "../../../dt/int/sc_nbdefs.hh"
25 
26 namespace tlm
27 {
28 
29 class tlm_dmi
30 {
31  public:
32  // Enum for indicating the access granted to the initiator.
33  // The initiator uses gp.m_command to indicate it intention (read/write)
34  // The target is allowed to promote DMI_ACCESS_READ or DMI_ACCESS_WRITE
35  // requests to dmi_access_read_write.
36 
37  enum dmi_access_e {
38  DMI_ACCESS_NONE = 0x00, // no access
39  DMI_ACCESS_READ = 0x01, // read access
40  DMI_ACCESS_WRITE = 0x02, // write access
42  // read/write access
43  };
44 
45  tlm_dmi() { init(); }
46 
47  void
48  init()
49  {
50  m_dmi_ptr = nullptr;
51  m_dmi_start_address = 0x0;
56  }
57 
58  unsigned char *get_dmi_ptr() const { return m_dmi_ptr; }
63  dmi_access_e get_granted_access() const { return m_dmi_access; }
64  bool is_none_allowed() const { return m_dmi_access == DMI_ACCESS_NONE; }
65  bool
66  is_read_allowed() const
67  {
69  }
70  bool
72  {
74  }
75  bool
76  is_read_write_allowed() const
77  {
79  }
80 
81  void set_dmi_ptr(unsigned char *p) { m_dmi_ptr = p; }
91 
92  private:
93  // If the forward call is successful, the target returns the dmi_ptr,
94  // which must point to the data element corresponding to the
95  // dmi_start_address. The data is organized as a byte array with the
96  // endianness of the target (endianness member of the tlm_dmi struct).
97 
98  unsigned char *m_dmi_ptr;
99 
100  // The absolute start and end addresses of the DMI region. If the decoder
101  // logic in the interconnect changes the address field e.g. by masking, the
102  // interconnect is responsible to transform the relative address back to an
103  // absolute address again.
104 
107 
108  // Granted access
109 
111 
112  // These members define the latency of read/write transactions. The
113  // initiator must initialize these members to zero before requesting a
114  // dmi pointer, because both the interconnect as well as the target can
115  // add to the total transaction latency.
116  // Depending on the 'type' attribute only one, or both of these attributes
117  // will be valid.
118 
121 };
122 
123 } // namespace tlm
124 
125 #endif /* __SYSTEMC_EXT_TLM_CORE_2_INTERFACES_DMI_HH__ */
tlm::tlm_dmi::get_read_latency
sc_core::sc_time get_read_latency() const
Definition: dmi.hh:95
tlm::tlm_dmi::allow_read_write
void allow_read_write()
Definition: dmi.hh:124
tlm::tlm_dmi::allow_read
void allow_read()
Definition: dmi.hh:122
gem5::ArmISA::a
Bitfield< 8 > a
Definition: misc_types.hh:65
sc_core::SC_ZERO_TIME
const sc_time SC_ZERO_TIME
Definition: sc_time.cc:290
tlm::tlm_dmi::DMI_ACCESS_READ
@ DMI_ACCESS_READ
Definition: dmi.hh:90
tlm::tlm_dmi::m_dmi_start_address
sc_dt::uint64 m_dmi_start_address
Definition: dmi.hh:139
tlm::tlm_dmi::get_granted_access
dmi_access_e get_granted_access() const
Definition: dmi.hh:97
tlm::tlm_dmi::m_dmi_end_address
sc_dt::uint64 m_dmi_end_address
Definition: dmi.hh:140
tlm::tlm_dmi::get_write_latency
sc_core::sc_time get_write_latency() const
Definition: dmi.hh:96
tlm::tlm_dmi::allow_none
void allow_none()
Definition: dmi.hh:121
tlm::tlm_dmi::set_end_address
void set_end_address(sc_dt::uint64 addr)
Definition: dmi.hh:117
tlm::tlm_dmi::is_read_allowed
bool is_read_allowed() const
Definition: dmi.hh:100
sc_dt::uint64
uint64_t uint64
Definition: sc_nbdefs.hh:206
tlm::tlm_dmi::set_read_latency
void set_read_latency(sc_core::sc_time t)
Definition: dmi.hh:118
tlm::tlm_dmi::m_dmi_read_latency
sc_core::sc_time m_dmi_read_latency
Definition: dmi.hh:153
gem5::MipsISA::p
Bitfield< 0 > p
Definition: pra_constants.hh:326
sc_core::sc_time
Definition: sc_time.hh:49
tlm::tlm_dmi::get_end_address
sc_dt::uint64 get_end_address() const
Definition: dmi.hh:94
tlm::tlm_dmi::is_write_allowed
bool is_write_allowed() const
Definition: dmi.hh:105
tlm::tlm_dmi::get_start_address
sc_dt::uint64 get_start_address() const
Definition: dmi.hh:93
gem5::ArmISA::t
Bitfield< 5 > t
Definition: misc_types.hh:70
tlm
Definition: analysis_fifo.hh:27
tlm::tlm_dmi::get_dmi_ptr
unsigned char * get_dmi_ptr() const
Definition: dmi.hh:92
tlm::tlm_dmi::m_dmi_write_latency
sc_core::sc_time m_dmi_write_latency
Definition: dmi.hh:154
tlm::tlm_dmi::set_write_latency
void set_write_latency(sc_core::sc_time t)
Definition: dmi.hh:119
tlm::tlm_dmi::DMI_ACCESS_READ_WRITE
@ DMI_ACCESS_READ_WRITE
Definition: dmi.hh:92
tlm::tlm_dmi::is_read_write_allowed
bool is_read_write_allowed() const
Definition: dmi.hh:110
tlm::tlm_dmi::init
void init()
Definition: dmi.hh:82
tlm::tlm_dmi::m_dmi_access
dmi_access_e m_dmi_access
Definition: dmi.hh:144
tlm::tlm_dmi::set_dmi_ptr
void set_dmi_ptr(unsigned char *p)
Definition: dmi.hh:115
tlm::tlm_dmi::DMI_ACCESS_NONE
@ DMI_ACCESS_NONE
Definition: dmi.hh:89
tlm::tlm_dmi::is_none_allowed
bool is_none_allowed() const
Definition: dmi.hh:98
tlm::tlm_dmi::set_start_address
void set_start_address(sc_dt::uint64 addr)
Definition: dmi.hh:116
tlm::tlm_dmi::dmi_access_e
dmi_access_e
Definition: dmi.hh:71
tlm::tlm_dmi::tlm_dmi
tlm_dmi()
Definition: dmi.hh:79
tlm::tlm_dmi::DMI_ACCESS_WRITE
@ DMI_ACCESS_WRITE
Definition: dmi.hh:91
tlm::tlm_dmi::set_granted_access
void set_granted_access(dmi_access_e a)
Definition: dmi.hh:120
tlm::tlm_dmi::allow_write
void allow_write()
Definition: dmi.hh:123
tlm::tlm_dmi::m_dmi_ptr
unsigned char * m_dmi_ptr
Definition: dmi.hh:132
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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