gem5  v22.0.0.2
se_workload.cc
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27 
29 
30 namespace gem5
31 {
32 
33 namespace PowerISA
34 {
35 
43 };
44 
45 } // namespace PowerISA
46 } // namespace gem5
gem5::PowerISA::ArgumentReg1
constexpr auto & ArgumentReg1
Definition: int.hh:146
std::vector< int >
gem5::PowerISA::ArgumentReg5
constexpr auto & ArgumentReg5
Definition: int.hh:150
gem5::PowerISA::ArgumentReg3
constexpr auto & ArgumentReg3
Definition: int.hh:148
gem5::PowerISA::ArgumentReg0
constexpr auto & ArgumentReg0
Definition: int.hh:145
se_workload.hh
gem5::PowerISA::SEWorkload::SyscallABI::ArgumentRegs
static const std::vector< int > ArgumentRegs
Definition: se_workload.hh:64
gem5::PowerISA::ArgumentReg4
constexpr auto & ArgumentReg4
Definition: int.hh:149
gem5::PowerISA::ArgumentReg2
constexpr auto & ArgumentReg2
Definition: int.hh:147
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37

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