gem5  v21.1.0.2
Classes | Typedefs | Enumerations | Functions | Variables
gem5::PowerISA Namespace Reference

Classes

class  AlignmentFault
 
class  BranchCondOp
 Base class for conditional branches. More...
 
class  BranchDispCondOp
 Base class for conditional, PC-relative or absolute address branches. More...
 
class  BranchOp
 Base class for unconditional, PC-relative or absolute address branches. More...
 
class  BranchRegCondOp
 Base class for conditional, register-based branches. More...
 
class  CondLogicOp
 Class for condition register logical operations. More...
 
class  CondMoveOp
 Class for condition register move operations. More...
 
class  Decoder
 
class  EmuLinux
 
class  FloatOp
 Base class for floating point operations. More...
 
class  IntArithOp
 Class for integer arithmetic operations. More...
 
class  IntCompOp
 Class for integer compare operations. More...
 
class  IntConcatRotateOp
 Class for integer rotate operations with a shift amount obtained from a register or by concatenating immediate fields and the first and last bits of a mask obtained by concatenating immediate fields. More...
 
class  IntConcatShiftOp
 Class for integer shift operations with a shift value obtained from a register or by concatenating immediates. More...
 
class  IntDispArithOp
 Class for integer arithmetic operations with displacement. More...
 
class  Interrupts
 
class  IntImmArithOp
 Class for integer immediate arithmetic operations. More...
 
class  IntImmCompLogicOp
 Class for integer immediate compare logical operations. More...
 
class  IntImmCompOp
 Class for integer immediate compare operations. More...
 
class  IntImmLogicOp
 Class for integer immediate logical operations. More...
 
class  IntImmOp
 Class for integer immediate (signed and unsigned) operations. More...
 
class  IntImmTrapOp
 Class for integer immediate trap operations. More...
 
class  IntLogicOp
 Class for integer logical operations. More...
 
class  IntOp
 We provide a base class for integer operations and then inherit for several other classes. More...
 
class  IntRotateOp
 Class for integer rotate operations with a shift amount obtained from a register or an immediate and the first and last bits of a mask obtained from immediates. More...
 
class  IntShiftOp
 Class for integer operations with a shift value obtained from a register or an instruction field. More...
 
class  IntTrapOp
 Class for integer trap operations. More...
 
class  ISA
 
class  MachineCheckFault
 
class  MemDispOp
 Class for memory operations with displacement. More...
 
class  MemDispShiftOp
 Class for memory operations with shifted displacement. More...
 
class  MemIndexOp
 Class for memory operations with register indexed addressing. More...
 
class  MemOp
 Base class for memory operations. More...
 
class  MiscOp
 Class for misc operations. More...
 
class  MMU
 
class  PCDependentDisassembly
 Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC). More...
 
class  PCState
 
class  PowerFault
 
class  PowerStaticInst
 
struct  PTE
 
class  RemoteGDB
 
class  SEWorkload
 
class  StackTrace
 
class  TLB
 
struct  TlbEntry
 
class  TrapFault
 
class  UnimplementedOpcodeFault
 

Typedefs

typedef uint32_t MachInst
 
using VecElem = ::gem5::DummyVecElem
 
using VecRegContainer = ::gem5::DummyVecRegContainer
 
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer
 

Enumerations

enum  MiscIntRegNums {
  INTREG_CR = NumIntArchRegs, INTREG_XER, INTREG_LR, INTREG_CTR,
  INTREG_TAR, INTREG_FPSCR, INTREG_MSR, INTREG_RSV,
  INTREG_RSV_LEN, INTREG_RSV_ADDR
}
 
enum  MiscRegIndex { NUM_MISCREGS = 0 }
 

Functions

static SyscallReturn unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
 BitUnion32 (Cr) SubBitUnion(cr0
 
 EndSubBitUnion (cr0) Bitfield< 27
 
 EndBitUnion (Cr) BitUnion32(Xer) Bitfield< 31 > so
 
 EndBitUnion (Xer) BitUnion32(Fpscr) Bitfield< 31 > fx
 
 SubBitUnion (fprf, 16, 12) Bitfield< 16 > c
 
 SubBitUnion (fpcc, 15, 12) Bitfield< 15 > fl
 
 EndSubBitUnion (fpcc) EndSubBitUnion(fprf) Bitfield< 10 > vxsqrt
 
 EndBitUnion (Fpscr) BitUnion64(Msr) Bitfield< 63 > sf
 
 BitUnion32 (ExtMachInst) Bitfield< 25
 

Variables

const Addr PageShift = 12
 
const Addr PageBytes = 1ULL << PageShift
 
const int NumFloatArchRegs = 32
 
const int NumFloatRegs = NumFloatArchRegs
 
const int NumIntArchRegs = 32
 
const int NumIntSpecialRegs = 11
 
const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs
 
const int ReturnValueReg = 3
 
const int ArgumentReg0 = 3
 
const int ArgumentReg1 = 4
 
const int ArgumentReg2 = 5
 
const int ArgumentReg3 = 6
 
const int ArgumentReg4 = 7
 
const int ArgumentReg5 = 8
 
const int StackPointerReg = 1
 
const int TOCPointerReg = 2
 
const int ThreadPointerReg = 13
 
const char *const miscRegName [NUM_MISCREGS]
 
Bitfield< 31 > lt
 
Bitfield< 30 > gt
 
Bitfield< 29 > eq
 
Bitfield< 28 > so
 
 cr1
 
Bitfield< 30 > ov
 
Bitfield< 29 > ca
 
Bitfield< 19 > ov32
 
Bitfield< 18 > ca32
 
Bitfield< 30 > fex
 
Bitfield< 29 > vx
 
Bitfield< 28 > ox
 
Bitfield< 27 > ux
 
Bitfield< 26 > zx
 
Bitfield< 25 > xx
 
Bitfield< 24 > vxsnan
 
Bitfield< 23 > vxisi
 
Bitfield< 22 > vxidi
 
Bitfield< 21 > vxzdz
 
Bitfield< 20 > vximz
 
Bitfield< 19 > vxvc
 
Bitfield< 18 > fr
 
Bitfield< 17 > fi
 
Bitfield< 14 > fg
 
Bitfield< 13 > fe
 
Bitfield< 12 > fu
 
Bitfield< 9 > vxcvi
 
Bitfield< 8 > ve
 
Bitfield< 7 > oe
 
Bitfield< 6 > ue
 
Bitfield< 5 > ze
 
Bitfield< 4 > xe
 
Bitfield< 3 > ni
 
Bitfield< 2, 1 > rn
 
Bitfield< 60 > hv
 
Bitfield< 34, 33 > ts
 
Bitfield< 32 > tm
 
Bitfield< 25 > vec
 
Bitfield< 23 > vsx
 
Bitfield< 15 > ee
 
Bitfield< 14 > pr
 
Bitfield< 13 > fp
 
Bitfield< 12 > me
 
Bitfield< 11 > fe0
 
Bitfield< 10, 9 > te
 
Bitfield< 8 > fe1
 
Bitfield< 5 > ir
 
Bitfield< 4 > dr
 
Bitfield< 2 > pmm
 
Bitfield< 1 > ri
 
Bitfield< 0 > le
 
 rs
 
Bitfield< 20, 16 > ra
 
Bitfield< 15, 11 > sh
 
Bitfield< 1 > shn
 
Bitfield< 10, 6 > mb
 
Bitfield< 5 > mbn
 
Bitfield< 5 > men
 
Bitfield< 15, 0 > si
 
Bitfield< 15, 0 > ui
 
Bitfield< 15, 0 > d
 
Bitfield< 15, 2 > ds
 
Bitfield< 15, 6 > d0
 
Bitfield< 20, 16 > d1
 
Bitfield< 1, 0 > d2
 
Bitfield< 21 > l
 
Bitfield< 20, 11 > spr
 
Bitfield< 25, 23 > bf
 
Bitfield< 20, 18 > bfa
 
Bitfield< 1 > aa
 
Bitfield< 15, 2 > bd
 
Bitfield< 20, 16 > bi
 
Bitfield< 12, 11 > bh
 
Bitfield< 25, 21 > bo
 
Bitfield< 25, 2 > li
 
Bitfield< 0 > lk
 
Bitfield< 0 > rc
 
Bitfield< 25, 21 > bt
 
Bitfield< 20, 16 > ba
 
Bitfield< 15, 11 > bb
 
Bitfield< 25, 21 > to
 
Bitfield< 19, 12 > fxm
 
constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
 

Typedef Documentation

◆ MachInst

typedef uint32_t gem5::PowerISA::MachInst

Definition at line 44 of file types.hh.

◆ VecElem

Definition at line 45 of file vecregs.hh.

◆ VecPredRegContainer

Definition at line 50 of file vecregs.hh.

◆ VecRegContainer

Definition at line 46 of file vecregs.hh.

Enumeration Type Documentation

◆ MiscIntRegNums

Enumerator
INTREG_CR 
INTREG_XER 
INTREG_LR 
INTREG_CTR 
INTREG_TAR 
INTREG_FPSCR 
INTREG_MSR 
INTREG_RSV 
INTREG_RSV_LEN 
INTREG_RSV_ADDR 

Definition at line 60 of file int.hh.

◆ MiscRegIndex

Enumerator
NUM_MISCREGS 

Definition at line 41 of file misc.hh.

Function Documentation

◆ BitUnion32() [1/2]

gem5::PowerISA::BitUnion32 ( Cr  )

◆ BitUnion32() [2/2]

gem5::PowerISA::BitUnion32 ( ExtMachInst  )

◆ EndBitUnion() [1/3]

gem5::PowerISA::EndBitUnion ( Cr  )

◆ EndBitUnion() [2/3]

gem5::PowerISA::EndBitUnion ( Fpscr  )

◆ EndBitUnion() [3/3]

gem5::PowerISA::EndBitUnion ( Xer  )

◆ EndSubBitUnion() [1/2]

gem5::PowerISA::EndSubBitUnion ( cr0  )

◆ EndSubBitUnion() [2/2]

gem5::PowerISA::EndSubBitUnion ( fpcc  )

◆ SubBitUnion() [1/2]

gem5::PowerISA::SubBitUnion ( fpcc  ,
15  ,
12   
)

◆ SubBitUnion() [2/2]

gem5::PowerISA::SubBitUnion ( fprf  ,
16  ,
12   
)

◆ unameFunc()

static SyscallReturn gem5::PowerISA::unameFunc ( SyscallDesc desc,
ThreadContext tc,
VPtr< Linux::utsname name 
)
static

Target uname() handler.

Definition at line 96 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

Variable Documentation

◆ aa

Bitfield<1> gem5::PowerISA::aa

◆ ArgumentReg0

const int gem5::PowerISA::ArgumentReg0 = 3

Definition at line 50 of file int.hh.

◆ ArgumentReg1

const int gem5::PowerISA::ArgumentReg1 = 4

Definition at line 51 of file int.hh.

◆ ArgumentReg2

const int gem5::PowerISA::ArgumentReg2 = 5

Definition at line 52 of file int.hh.

◆ ArgumentReg3

const int gem5::PowerISA::ArgumentReg3 = 6

Definition at line 53 of file int.hh.

◆ ArgumentReg4

const int gem5::PowerISA::ArgumentReg4 = 7

Definition at line 54 of file int.hh.

◆ ArgumentReg5

const int gem5::PowerISA::ArgumentReg5 = 8

Definition at line 55 of file int.hh.

◆ ba

Bitfield<20, 16> gem5::PowerISA::ba

Definition at line 92 of file types.hh.

◆ bb

Bitfield<15, 11> gem5::PowerISA::bb

Definition at line 93 of file types.hh.

Referenced by std::hash< gem5::BasicBlockRange >::operator()().

◆ bd

Bitfield<15, 2> gem5::PowerISA::bd

◆ bf

Bitfield<25, 23> gem5::PowerISA::bf

Definition at line 74 of file types.hh.

Referenced by gem5::PowerISA::PowerStaticInst::insertCRField().

◆ bfa

Bitfield<20, 18> gem5::PowerISA::bfa

Definition at line 75 of file types.hh.

◆ bh

Bitfield<12, 11> gem5::PowerISA::bh

Definition at line 81 of file types.hh.

◆ bi

Bitfield<20, 16> gem5::PowerISA::bi

Definition at line 80 of file types.hh.

Referenced by sc_dt::sc_bitref< X >::b_not(), gem5::branch_prediction::TAGEBase::baseUpdate(), gem5::branch_prediction::TAGE::btbUpdate(), gem5::branch_prediction::TAGEBase::btbUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE::calcDep(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateIndicesAndTags(), gem5::branch_prediction::TAGEBase::calculateIndicesAndTags(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::computePartialSum(), gem5::branch_prediction::MPP_StatisticalCorrector::condBranchUpdate(), gem5::branch_prediction::LoopPredictor::condBranchUpdate(), gem5::branch_prediction::StatisticalCorrector::condBranchUpdate(), gem5::branch_prediction::TAGEBase::condBranchUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE::extraAltCalc(), sc_dt::sc_lv_base::get_word(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::getBiasLSUM(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::getBiasLSUM(), gem5::branch_prediction::TAGE_SC_L_TAGE::getBimodePred(), gem5::branch_prediction::TAGEBase::getBimodePred(), gem5::branch_prediction::TAGEBase::getGHR(), gem5::branch_prediction::MPP_StatisticalCorrector::getIndBias(), gem5::branch_prediction::StatisticalCorrector::getIndBias(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::getIndBiasBank(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::getIndBiasBank(), gem5::branch_prediction::MPP_StatisticalCorrector::getIndBiasSK(), gem5::branch_prediction::StatisticalCorrector::getIndBiasSK(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::getIndex(), gem5::branch_prediction::MultiperspectivePerceptron::getIndex(), gem5::branch_prediction::LoopPredictor::getLoop(), gem5::branch_prediction::MPP_TAGE::getUseAltIdx(), gem5::branch_prediction::TAGE_SC_L_TAGE::getUseAltIdx(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gPredictions(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gPredictions(), gem5::branch_prediction::StatisticalCorrector::gUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gUpdates(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), gem5::branch_prediction::MPP_TAGE::handleAllocAndUReset(), gem5::branch_prediction::TAGEBase::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleTAGEUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleTAGEUpdate(), gem5::branch_prediction::MPP_TAGE::handleTAGEUpdate(), gem5::branch_prediction::TAGEBase::handleTAGEUpdate(), gem5::branch_prediction::MPP_TAGE::isHighConfidence(), gem5::branch_prediction::TAGE::lookup(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::lookup(), gem5::branch_prediction::MultiperspectivePerceptron::lookup(), gem5::branch_prediction::LoopPredictor::loopPredict(), gem5::branch_prediction::LoopPredictor::loopUpdate(), sc_dt::scfx_rep::o_extend(), sc_dt::scfx_rep::o_set_high(), sc_dt::scfx_rep::o_zero_left(), sc_dt::scfx_rep::o_zero_right(), gem5::branch_prediction::TAGE::predict(), gem5::branch_prediction::LTAGE::predict(), gem5::branch_prediction::TAGE_SC_L::predict(), sc_dt::scfx_rep::q_clear(), sc_dt::scfx_rep::q_incr(), sc_dt::quantization_scfx_rep(), sc_dt::scfx_rep::resize_to(), sc_dt::scfx_rep::round(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::scHistoryUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::scHistoryUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector::scPredict(), gem5::branch_prediction::StatisticalCorrector::scPredict(), sc_dt::sc_bitref< X >::set_bit(), gem5::branch_prediction::LoopPredictor::specLoopUpdate(), gem5::branch_prediction::LTAGE::squash(), gem5::branch_prediction::TAGE::squash(), gem5::branch_prediction::LoopPredictor::squash(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::squash(), gem5::branch_prediction::TAGEBase::squash(), gem5::branch_prediction::MultiperspectivePerceptron::squash(), gem5::branch_prediction::LoopPredictor::squashLoop(), gem5::branch_prediction::TAGEBase::tagePredict(), gem5::branch_prediction::MultiperspectivePerceptron::train(), gem5::branch_prediction::TAGE::uncondBranch(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::uncondBranch(), gem5::branch_prediction::MultiperspectivePerceptron::uncondBranch(), gem5::branch_prediction::LTAGE::update(), gem5::branch_prediction::TAGE::update(), gem5::branch_prediction::TAGE_SC_L::update(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::update(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::branch_prediction::TAGEBase::updateHistories(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updatePartial(), gem5::branch_prediction::LoopPredictor::updateStats(), gem5::branch_prediction::StatisticalCorrector::updateStats(), and gem5::branch_prediction::TAGEBase::updateStats().

◆ bo

Bitfield<25, 21> gem5::PowerISA::bo

◆ bt

Bitfield<25, 21> gem5::PowerISA::bt

Definition at line 91 of file types.hh.

◆ ca

Bitfield<29> gem5::PowerISA::ca

Definition at line 62 of file misc.hh.

◆ ca32

Bitfield<18> gem5::PowerISA::ca32

Definition at line 64 of file misc.hh.

◆ cr1

gem5::PowerISA::cr1

Definition at line 56 of file misc.hh.

Referenced by gem5::SMMUv3::writeControl().

◆ d

Bitfield<15, 0> gem5::PowerISA::d

Definition at line 63 of file types.hh.

◆ d0

Bitfield<15, 6> gem5::PowerISA::d0

Definition at line 65 of file types.hh.

Referenced by gem5::Iob::receiveJBusInterrupt().

◆ d1

Bitfield<20, 16> gem5::PowerISA::d1

Definition at line 66 of file types.hh.

Referenced by gem5::Iob::receiveJBusInterrupt(), and SC_MODULE().

◆ d2

Bitfield< 1, 0> gem5::PowerISA::d2

Definition at line 67 of file types.hh.

Referenced by SC_MODULE().

◆ dr

Bitfield<4> gem5::PowerISA::dr

Definition at line 118 of file misc.hh.

◆ ds

Bitfield<15, 2> gem5::PowerISA::ds

Definition at line 64 of file types.hh.

◆ ee

Bitfield<15> gem5::PowerISA::ee

Definition at line 110 of file misc.hh.

◆ eq

Bitfield<29> gem5::PowerISA::eq

◆ fe

Bitfield<13> gem5::PowerISA::fe

Definition at line 88 of file misc.hh.

◆ fe0

Bitfield<11> gem5::PowerISA::fe0

Definition at line 114 of file misc.hh.

◆ fe1

Bitfield<8> gem5::PowerISA::fe1

Definition at line 116 of file misc.hh.

◆ fex

Bitfield<30> gem5::PowerISA::fex

Definition at line 69 of file misc.hh.

◆ fg

Bitfield<14> gem5::PowerISA::fg

Definition at line 87 of file misc.hh.

◆ fi

Bitfield<17> gem5::PowerISA::fi

Definition at line 82 of file misc.hh.

◆ fp

Bitfield<13> gem5::PowerISA::fp

Definition at line 112 of file misc.hh.

◆ fr

Bitfield<18> gem5::PowerISA::fr

Definition at line 81 of file misc.hh.

◆ fu

Bitfield<12> gem5::PowerISA::fu

◆ fxm

Bitfield<19, 12> gem5::PowerISA::fxm

Definition at line 99 of file types.hh.

◆ gt

Bitfield<30> gem5::PowerISA::gt

Definition at line 52 of file misc.hh.

◆ hv

Bitfield<60> gem5::PowerISA::hv

Definition at line 105 of file misc.hh.

◆ ir

Bitfield<5> gem5::PowerISA::ir

Definition at line 117 of file misc.hh.

◆ l

Bitfield<21> gem5::PowerISA::l

Definition at line 70 of file types.hh.

◆ le

Bitfield<0> gem5::PowerISA::le

Definition at line 121 of file misc.hh.

Referenced by sc_gem5::DynamicSensitivityEventOrList::notifyWork().

◆ li

Bitfield<25, 2> gem5::PowerISA::li

Definition at line 83 of file types.hh.

◆ lk

Bitfield<0> gem5::PowerISA::lk

Definition at line 84 of file types.hh.

◆ lt

Bitfield<31> gem5::PowerISA::lt

Definition at line 50 of file misc.hh.

Referenced by gem5::ruby::MessageBuffer::reanalyzeList().

◆ mb

Bitfield<10, 6> gem5::PowerISA::mb

Definition at line 55 of file types.hh.

◆ mbn

Bitfield<5> gem5::PowerISA::mbn

Definition at line 56 of file types.hh.

◆ me

Bitfield< 5, 1 > gem5::PowerISA::me

Definition at line 113 of file misc.hh.

◆ men

Bitfield<5> gem5::PowerISA::men

Definition at line 58 of file types.hh.

◆ miscRegName

const char* const gem5::PowerISA::miscRegName[NUM_MISCREGS]
Initial value:
= {
}

Definition at line 46 of file misc.hh.

◆ ni

Bitfield<3> gem5::PowerISA::ni

◆ NumFloatArchRegs

const int gem5::PowerISA::NumFloatArchRegs = 32

Definition at line 38 of file float.hh.

◆ NumFloatRegs

const int gem5::PowerISA::NumFloatRegs = NumFloatArchRegs

◆ NumIntArchRegs

const int gem5::PowerISA::NumIntArchRegs = 32

◆ NumIntRegs

const int gem5::PowerISA::NumIntRegs = NumIntArchRegs + NumIntSpecialRegs

Definition at line 46 of file int.hh.

Referenced by gem5::PowerISA::ISA::copyRegsFrom(), and gem5::PowerISA::ISA::ISA().

◆ NumIntSpecialRegs

const int gem5::PowerISA::NumIntSpecialRegs = 11

Definition at line 44 of file int.hh.

◆ NumVecElemPerVecReg

constexpr unsigned gem5::PowerISA::NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
constexpr

Definition at line 47 of file vecregs.hh.

◆ oe

Bitfield< 10 > gem5::PowerISA::oe

Definition at line 95 of file misc.hh.

◆ ov

Bitfield<30> gem5::PowerISA::ov

Definition at line 61 of file misc.hh.

Referenced by gem5::PowerISA::IntArithOp::divide().

◆ ov32

Bitfield<19> gem5::PowerISA::ov32

Definition at line 63 of file misc.hh.

◆ ox

Bitfield<28> gem5::PowerISA::ox

Definition at line 71 of file misc.hh.

◆ PageBytes

const Addr gem5::PowerISA::PageBytes = 1ULL << PageShift

Definition at line 44 of file page_size.hh.

◆ PageShift

const Addr gem5::PowerISA::PageShift = 12

Definition at line 43 of file page_size.hh.

◆ pmm

Bitfield<2> gem5::PowerISA::pmm

Definition at line 119 of file misc.hh.

◆ pr

Bitfield<14> gem5::PowerISA::pr

Definition at line 111 of file misc.hh.

◆ ra

Bitfield<20, 16> gem5::PowerISA::ra

◆ rc

Bitfield<0> gem5::PowerISA::rc

◆ ReturnValueReg

const int gem5::PowerISA::ReturnValueReg = 3

◆ ri

Bitfield<1> gem5::PowerISA::ri

◆ rn

Bitfield<2,1> gem5::PowerISA::rn

Definition at line 100 of file misc.hh.

◆ rs

gem5::PowerISA::rs

◆ sh

Bitfield<15, 11> gem5::PowerISA::sh

Definition at line 53 of file types.hh.

◆ shn

Bitfield<1> gem5::PowerISA::shn

Definition at line 54 of file types.hh.

◆ si

Bitfield<15, 0> gem5::PowerISA::si

Definition at line 61 of file types.hh.

Referenced by gem5::PowerISA::Decoder::decode().

◆ so

Bitfield<28> gem5::PowerISA::so

◆ spr

Bitfield<20, 11> gem5::PowerISA::spr

Definition at line 73 of file types.hh.

◆ StackPointerReg

const int gem5::PowerISA::StackPointerReg = 1

Definition at line 56 of file int.hh.

Referenced by gem5::PowerLinux::archClone().

◆ te

Bitfield<10, 9> gem5::PowerISA::te

Definition at line 115 of file misc.hh.

◆ ThreadPointerReg

const int gem5::PowerISA::ThreadPointerReg = 13

Definition at line 58 of file int.hh.

Referenced by gem5::PowerLinux::archClone().

◆ tm

Bitfield<32> gem5::PowerISA::tm

◆ to

Bitfield<25, 21> gem5::PowerISA::to

◆ TOCPointerReg

const int gem5::PowerISA::TOCPointerReg = 2

Definition at line 57 of file int.hh.

Referenced by gem5::PowerProcess::initState().

◆ ts

Bitfield<34, 33> gem5::PowerISA::ts

Definition at line 106 of file misc.hh.

◆ ue

Bitfield<6> gem5::PowerISA::ue

Definition at line 96 of file misc.hh.

◆ ui

Bitfield<15, 0> gem5::PowerISA::ui

Definition at line 62 of file types.hh.

◆ ux

Bitfield<27> gem5::PowerISA::ux

Definition at line 72 of file misc.hh.

◆ ve

Bitfield<8> gem5::PowerISA::ve

Definition at line 94 of file misc.hh.

◆ vec

Bitfield<25> gem5::PowerISA::vec

◆ vsx

Bitfield<23> gem5::PowerISA::vsx

Definition at line 109 of file misc.hh.

◆ vx

Bitfield<29> gem5::PowerISA::vx

◆ vxcvi

Bitfield<9> gem5::PowerISA::vxcvi

Definition at line 93 of file misc.hh.

◆ vxidi

Bitfield<22> gem5::PowerISA::vxidi

Definition at line 77 of file misc.hh.

◆ vximz

Bitfield<20> gem5::PowerISA::vximz

Definition at line 79 of file misc.hh.

◆ vxisi

Bitfield<23> gem5::PowerISA::vxisi

Definition at line 76 of file misc.hh.

◆ vxsnan

Bitfield<24> gem5::PowerISA::vxsnan

Definition at line 75 of file misc.hh.

◆ vxvc

Bitfield<19> gem5::PowerISA::vxvc

Definition at line 80 of file misc.hh.

◆ vxzdz

Bitfield<21> gem5::PowerISA::vxzdz

Definition at line 78 of file misc.hh.

◆ xe

Bitfield<4> gem5::PowerISA::xe

Definition at line 98 of file misc.hh.

Referenced by TEST_F().

◆ xx

Bitfield<25> gem5::PowerISA::xx

Definition at line 74 of file misc.hh.

◆ ze

Bitfield<5> gem5::PowerISA::ze

Definition at line 97 of file misc.hh.

◆ zx

Bitfield<26> gem5::PowerISA::zx

Definition at line 73 of file misc.hh.


Generated on Tue Sep 21 2021 12:31:47 for gem5 by doxygen 1.8.17