|
gem5 v24.0.0.0
|
Namespaces | |
| namespace | float_reg |
| namespace | int_reg |
Classes | |
| class | AlignmentFault |
| class | BranchCondOp |
| Base class for conditional branches. More... | |
| class | BranchDispCondOp |
| Base class for conditional, PC-relative or absolute address branches. More... | |
| class | BranchOp |
| Base class for unconditional, PC-relative or absolute address branches. More... | |
| class | BranchRegCondOp |
| Base class for conditional, register-based branches. More... | |
| class | CondLogicOp |
| Class for condition register logical operations. More... | |
| class | CondMoveOp |
| Class for condition register move operations. More... | |
| class | Decoder |
| class | EmuLinux |
| class | FloatOp |
| Base class for floating point operations. More... | |
| class | IntArithOp |
| Class for integer arithmetic operations. More... | |
| class | IntCompOp |
| Class for integer compare operations. More... | |
| class | IntConcatRotateOp |
| Class for integer rotate operations with a shift amount obtained from a register or by concatenating immediate fields and the first and last bits of a mask obtained by concatenating immediate fields. More... | |
| class | IntConcatShiftOp |
| Class for integer shift operations with a shift value obtained from a register or by concatenating immediates. More... | |
| class | IntDispArithOp |
| Class for integer arithmetic operations with displacement. More... | |
| class | Interrupts |
| class | IntImmArithOp |
| Class for integer immediate arithmetic operations. More... | |
| class | IntImmCompLogicOp |
| Class for integer immediate compare logical operations. More... | |
| class | IntImmCompOp |
| Class for integer immediate compare operations. More... | |
| class | IntImmLogicOp |
| Class for integer immediate logical operations. More... | |
| class | IntImmOp |
| Class for integer immediate (signed and unsigned) operations. More... | |
| class | IntImmTrapOp |
| Class for integer immediate trap operations. More... | |
| class | IntLogicOp |
| Class for integer logical operations. More... | |
| class | IntOp |
| We provide a base class for integer operations and then inherit for several other classes. More... | |
| class | IntRotateOp |
| Class for integer rotate operations with a shift amount obtained from a register or an immediate and the first and last bits of a mask obtained from immediates. More... | |
| class | IntShiftOp |
| Class for integer operations with a shift value obtained from a register or an instruction field. More... | |
| class | IntTrapOp |
| Class for integer trap operations. More... | |
| class | ISA |
| class | MachineCheckFault |
| class | MemDispOp |
| Class for memory operations with displacement. More... | |
| class | MemDispShiftOp |
| Class for memory operations with shifted displacement. More... | |
| class | MemIndexOp |
| Class for memory operations with register indexed addressing. More... | |
| class | MemOp |
| Base class for memory operations. More... | |
| class | MiscOp |
| Class for misc operations. More... | |
| class | MMU |
| class | PCDependentDisassembly |
| Base class for instructions whose disassembly is not purely a function of the machine instruction (i.e., it depends on the PC). More... | |
| class | PCState |
| class | PowerFault |
| class | PowerStaticInst |
| struct | PTE |
| class | RemoteGDB |
| class | SEWorkload |
| class | StackTrace |
| class | TLB |
| struct | TlbEntry |
| class | TrapFault |
| class | UnimplementedOpcodeFault |
Typedefs | |
| typedef uint32_t | MachInst |
Enumerations | |
| enum | MiscRegIndex { NUM_MISCREGS = 0 } |
Functions | |
| static SyscallReturn | unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name) |
| Target uname() handler. | |
| constexpr RegClass | floatRegClass (FloatRegClass, FloatRegClassName, float_reg::NumRegs, debug::FloatRegs) |
| constexpr RegClass | intRegClass (IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs) |
| constexpr RegClass | miscRegClass (MiscRegClass, MiscRegClassName, NUM_MISCREGS, debug::MiscRegs) |
| BitUnion32 (Cr) SubBitUnion(cr0 | |
| EndSubBitUnion (cr0) Bitfield< 27 | |
| EndBitUnion (Cr) BitUnion32(Xer) Bitfield< 31 > so | |
| EndBitUnion (Xer) BitUnion32(Fpscr) Bitfield< 31 > fx | |
| SubBitUnion (fprf, 16, 12) Bitfield< 16 > c | |
| SubBitUnion (fpcc, 15, 12) Bitfield< 15 > fl | |
| EndSubBitUnion (fpcc) EndSubBitUnion(fprf) Bitfield< 10 > vxsqrt | |
| EndBitUnion (Fpscr) BitUnion64(Msr) Bitfield< 63 > sf | |
| BitUnion32 (ExtMachInst) Bitfield< 25 | |
Variables | |
| const Addr | PageShift = 12 |
| const Addr | PageBytes = 1ULL << PageShift |
| constexpr auto & | ReturnValueReg = int_reg::R3 |
| constexpr auto & | ArgumentReg0 = int_reg::R3 |
| constexpr auto & | ArgumentReg1 = int_reg::R4 |
| constexpr auto & | ArgumentReg2 = int_reg::R5 |
| constexpr auto & | ArgumentReg3 = int_reg::R6 |
| constexpr auto & | ArgumentReg4 = int_reg::R7 |
| constexpr auto & | ArgumentReg5 = int_reg::R8 |
| constexpr auto & | StackPointerReg = int_reg::R1 |
| constexpr auto & | TOCPointerReg = int_reg::R2 |
| constexpr auto & | ThreadPointerReg = int_reg::R13 |
| const char *const | miscRegName [NUM_MISCREGS] |
| Bitfield< 31 > | lt |
| Bitfield< 30 > | gt |
| Bitfield< 29 > | eq |
| Bitfield< 28 > | so |
| cr1 | |
| Bitfield< 30 > | ov |
| Bitfield< 29 > | ca |
| Bitfield< 19 > | ov32 |
| Bitfield< 18 > | ca32 |
| Bitfield< 30 > | fex |
| Bitfield< 29 > | vx |
| Bitfield< 28 > | ox |
| Bitfield< 27 > | ux |
| Bitfield< 26 > | zx |
| Bitfield< 25 > | xx |
| Bitfield< 24 > | vxsnan |
| Bitfield< 23 > | vxisi |
| Bitfield< 22 > | vxidi |
| Bitfield< 21 > | vxzdz |
| Bitfield< 20 > | vximz |
| Bitfield< 19 > | vxvc |
| Bitfield< 18 > | fr |
| Bitfield< 17 > | fi |
| Bitfield< 14 > | fg |
| Bitfield< 13 > | fe |
| Bitfield< 12 > | fu |
| Bitfield< 9 > | vxcvi |
| Bitfield< 8 > | ve |
| Bitfield< 7 > | oe |
| Bitfield< 6 > | ue |
| Bitfield< 5 > | ze |
| Bitfield< 4 > | xe |
| Bitfield< 3 > | ni |
| Bitfield< 2, 1 > | rn |
| Bitfield< 60 > | hv |
| Bitfield< 34, 33 > | ts |
| Bitfield< 32 > | tm |
| Bitfield< 25 > | vec |
| Bitfield< 23 > | vsx |
| Bitfield< 15 > | ee |
| Bitfield< 14 > | pr |
| Bitfield< 13 > | fp |
| Bitfield< 12 > | me |
| Bitfield< 11 > | fe0 |
| Bitfield< 10, 9 > | te |
| Bitfield< 8 > | fe1 |
| Bitfield< 5 > | ir |
| Bitfield< 4 > | dr |
| Bitfield< 2 > | pmm |
| Bitfield< 1 > | ri |
| Bitfield< 0 > | le |
| rs | |
| Bitfield< 20, 16 > | ra |
| Bitfield< 15, 11 > | sh |
| Bitfield< 1 > | shn |
| Bitfield< 10, 6 > | mb |
| Bitfield< 5 > | mbn |
| Bitfield< 5 > | men |
| Bitfield< 15, 0 > | si |
| Bitfield< 15, 0 > | ui |
| Bitfield< 15, 0 > | d |
| Bitfield< 15, 2 > | ds |
| Bitfield< 15, 6 > | d0 |
| Bitfield< 20, 16 > | d1 |
| Bitfield< 1, 0 > | d2 |
| Bitfield< 21 > | l |
| Bitfield< 20, 11 > | spr |
| Bitfield< 25, 23 > | bf |
| Bitfield< 20, 18 > | bfa |
| Bitfield< 1 > | aa |
| Bitfield< 15, 2 > | bd |
| Bitfield< 20, 16 > | bi |
| Bitfield< 12, 11 > | bh |
| Bitfield< 25, 21 > | bo |
| Bitfield< 25, 2 > | li |
| Bitfield< 0 > | lk |
| Bitfield< 0 > | rc |
| Bitfield< 25, 21 > | bt |
| Bitfield< 20, 16 > | ba |
| Bitfield< 15, 11 > | bb |
| Bitfield< 25, 21 > | to |
| Bitfield< 19, 12 > | fxm |
| typedef uint32_t gem5::PowerISA::MachInst |
| gem5::PowerISA::BitUnion32 | ( | Cr | ) |
| gem5::PowerISA::BitUnion32 | ( | ExtMachInst | ) |
| gem5::PowerISA::EndBitUnion | ( | Cr | ) |
| gem5::PowerISA::EndBitUnion | ( | Fpscr | ) |
| gem5::PowerISA::EndBitUnion | ( | Xer | ) |
| gem5::PowerISA::EndSubBitUnion | ( | cr0 | ) |
| gem5::PowerISA::EndSubBitUnion | ( | fpcc | ) |
|
inlineconstexpr |
|
inlineconstexpr |
|
inlineconstexpr |
| gem5::PowerISA::SubBitUnion | ( | fpcc | , |
| 15 | , | ||
| 12 | ) |
| gem5::PowerISA::SubBitUnion | ( | fprf | , |
| 16 | , | ||
| 12 | ) |
|
static |
Target uname() handler.
Definition at line 96 of file se_workload.cc.
References gem5::ThreadContext::getProcessPtr(), and name().
| auto & gem5::PowerISA::ArgumentReg0 = int_reg::R3 |
| auto & gem5::PowerISA::ArgumentReg1 = int_reg::R4 |
| auto & gem5::PowerISA::ArgumentReg2 = int_reg::R5 |
| auto & gem5::PowerISA::ArgumentReg3 = int_reg::R6 |
| auto & gem5::PowerISA::ArgumentReg4 = int_reg::R7 |
| auto & gem5::PowerISA::ArgumentReg5 = int_reg::R8 |
| Bitfield<15, 2> gem5::PowerISA::bd |
Definition at line 79 of file types.hh.
Referenced by gem5::NonCachingSimpleCPU::fetchInstMem(), gem5::DmaPort::sendAtomicBdReq(), and gem5::NonCachingSimpleCPU::sendPacket().
| Bitfield<25, 23> gem5::PowerISA::bf |
Definition at line 74 of file types.hh.
Referenced by gem5::PowerISA::PowerStaticInst::insertCRField().
| Bitfield<20, 16> gem5::PowerISA::bi |
Definition at line 80 of file types.hh.
Referenced by gem5::branch_prediction::TAGEBase::baseUpdate(), gem5::branch_prediction::TAGEBase::btbUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE::calcDep(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateIndicesAndTags(), gem5::branch_prediction::TAGEBase::calculateIndicesAndTags(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::computePartialSum(), gem5::branch_prediction::LoopPredictor::condBranchUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector::condBranchUpdate(), gem5::branch_prediction::StatisticalCorrector::condBranchUpdate(), gem5::branch_prediction::TAGEBase::condBranchUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE::extraAltCalc(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::getBiasLSUM(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::getBiasLSUM(), gem5::branch_prediction::TAGE_SC_L_TAGE::getBimodePred(), gem5::branch_prediction::TAGEBase::getBimodePred(), gem5::branch_prediction::TAGEBase::getGHR(), gem5::branch_prediction::MPP_StatisticalCorrector::getIndBias(), gem5::branch_prediction::StatisticalCorrector::getIndBias(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::getIndBiasBank(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::getIndBiasBank(), gem5::branch_prediction::MPP_StatisticalCorrector::getIndBiasSK(), gem5::branch_prediction::StatisticalCorrector::getIndBiasSK(), gem5::branch_prediction::MultiperspectivePerceptron::getIndex(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::getIndex(), gem5::branch_prediction::LoopPredictor::getLoop(), gem5::branch_prediction::MPP_TAGE::getUseAltIdx(), gem5::branch_prediction::TAGE_SC_L_TAGE::getUseAltIdx(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gPredictions(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gPredictions(), gem5::branch_prediction::StatisticalCorrector::gUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gUpdates(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::MPP_TAGE::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), gem5::branch_prediction::TAGEBase::handleAllocAndUReset(), gem5::branch_prediction::MPP_TAGE::handleTAGEUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleTAGEUpdate(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleTAGEUpdate(), gem5::branch_prediction::TAGEBase::handleTAGEUpdate(), gem5::branch_prediction::MPP_TAGE::isHighConfidence(), gem5::branch_prediction::MultiperspectivePerceptron::lookup(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::lookup(), gem5::branch_prediction::LoopPredictor::loopPredict(), gem5::branch_prediction::LoopPredictor::loopUpdate(), gem5::branch_prediction::LTAGE::predict(), gem5::branch_prediction::TAGE::predict(), gem5::branch_prediction::TAGE_SC_L::predict(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::scHistoryUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::scHistoryUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector::scPredict(), gem5::branch_prediction::StatisticalCorrector::scPredict(), gem5::branch_prediction::LoopPredictor::specLoopUpdate(), gem5::branch_prediction::LoopPredictor::squash(), gem5::branch_prediction::LTAGE::squash(), gem5::branch_prediction::MultiperspectivePerceptron::squash(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::squash(), gem5::branch_prediction::TAGE::squash(), gem5::branch_prediction::TAGEBase::squash(), gem5::branch_prediction::LoopPredictor::squashLoop(), gem5::branch_prediction::TAGEBase::tagePredict(), gem5::branch_prediction::MultiperspectivePerceptron::train(), gem5::branch_prediction::LTAGE::update(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::update(), gem5::branch_prediction::TAGE::update(), gem5::branch_prediction::TAGE_SC_L::update(), gem5::branch_prediction::MultiperspectivePerceptron::updateHistories(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::branch_prediction::TAGE::updateHistories(), gem5::branch_prediction::TAGEBase::updateHistories(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updatePartial(), gem5::branch_prediction::LoopPredictor::updateStats(), gem5::branch_prediction::StatisticalCorrector::updateStats(), and gem5::branch_prediction::TAGEBase::updateStats().
| Bitfield<25, 21> gem5::PowerISA::bo |
Definition at line 82 of file types.hh.
Referenced by gem5::copyOutStat64Buf(), gem5::copyOutStatBuf(), gem5::copyOutStatfsBuf(), gem5::copyOutStatxBuf(), gem5::copyStringArray(), gem5::getrlimitFunc(), gem5::prlimitFunc(), and gem5::VirtQueue::VirtQueue().
| gem5::PowerISA::cr1 |
Definition at line 61 of file misc.hh.
Referenced by gem5::EndBitUnion(), and gem5::SMMUv3::writeControl().
| Bitfield<15, 6> gem5::PowerISA::d0 |
Definition at line 65 of file types.hh.
Referenced by gem5::Iob::receiveJBusInterrupt().
| Bitfield<20, 16> gem5::PowerISA::d1 |
Definition at line 66 of file types.hh.
Referenced by gem5::Iob::receiveJBusInterrupt().
| Bitfield<29> gem5::PowerISA::eq |
Definition at line 58 of file misc.hh.
Referenced by gem5::abortHandler(), gem5::ThermalModel::doStep(), gem5::ThermalCapacitor::getEquation(), gem5::ThermalDomain::getEquation(), gem5::ThermalResistor::getEquation(), gem5::LinearSystem::operator[](), gem5::pybind_init_event(), gem5::SimulatorThreads::runUntilLocalExit(), and gem5::LinearSystem::toStr().
| Bitfield<12> gem5::PowerISA::fu |
Definition at line 94 of file misc.hh.
Referenced by gem5::minor::Execute::commit(), gem5::minor::Execute::evaluate(), gem5::minor::Execute::Execute(), gem5::FuncUnit::FuncUnit(), gem5::o3::FUPool::FUPool(), gem5::minor::Execute::getCommittingThread(), and gem5::minor::Execute::issue().
| Bitfield<31> gem5::PowerISA::lt |
Definition at line 56 of file misc.hh.
Referenced by gem5::ruby::MessageBuffer::reanalyzeList().
| Bitfield< 5, 1 > gem5::PowerISA::me |
Definition at line 118 of file misc.hh.
Referenced by gem5::PM4PacketProcessor::serialize(), and gem5::PM4PacketProcessor::unserialize().
| const char* const gem5::PowerISA::miscRegName[NUM_MISCREGS] |
| Bitfield<3> gem5::PowerISA::ni |
Definition at line 104 of file misc.hh.
Referenced by gem5::TCPIface::establishConnection(), gem5::ruby::garnet::GarnetNetwork::GarnetNetwork(), and gem5::TCPIface::TCPIface().
| Bitfield<30> gem5::PowerISA::ov |
Definition at line 66 of file misc.hh.
Referenced by gem5::PowerISA::IntArithOp::divide(), and gem5::PowerISA::IntArithOp::divide().
Definition at line 44 of file page_size.hh.
Referenced by gem5::PowerISA::MMU::translateFunctional().
| const Addr gem5::PowerISA::PageShift = 12 |
Definition at line 43 of file page_size.hh.
| Bitfield<14> gem5::PowerISA::pr |
Definition at line 116 of file misc.hh.
Referenced by gem5::ArmISA::MMU::s1PermBits64().
| Bitfield<20, 16> gem5::PowerISA::ra |
Definition at line 50 of file types.hh.
Referenced by gem5::PowerISA::IntArithOp::add(), gem5::PowerISA::IntArithOp::add(), gem5::PowerISA::IntArithOp::divide(), gem5::PowerISA::IntArithOp::divide(), gem5::ArmISA::FsFreebsd::initState(), gem5::PowerISA::IntArithOp::multiply(), gem5::PowerISA::IntArithOp::multiply(), gem5::PowerISA::IntArithOp::multiplyAdd(), and gem5::PowerISA::IntArithOp::multiplyAdd().
| Bitfield<0> gem5::PowerISA::rc |
Definition at line 87 of file types.hh.
Referenced by gem5::RiscvISA::_rvk_emu_aes64ks1i(), gem5::htmFailureToStr(), gem5::TimingSimpleCPU::htmSendAbortSignal(), and gem5::TimingSimpleCPU::initiateMemMgmtCmd().
|
inlineconstexpr |
Definition at line 153 of file int.hh.
Referenced by gem5::guest_abi::Result< PowerISA::SEWorkload::SyscallABI, SyscallReturn >::store().
| Bitfield<1> gem5::PowerISA::ri |
Definition at line 125 of file misc.hh.
Referenced by gem5::ArmV8KvmCPU::dump(), gem5::ArmKvmCPU::dumpKvmStateCore(), gem5::SimObject::serializeAll(), gem5::ArmV8KvmCPU::startup(), gem5::ArmISA::syncVecElemsToRegs(), gem5::ArmISA::syncVecRegsToElems(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateKvmStateCore(), gem5::ArmKvmCPU::updateTCStateCore(), and gem5::ArmV8KvmCPU::updateThreadContext().
| gem5::PowerISA::rs |
Definition at line 49 of file types.hh.
Referenced by gem5::PowerISA::IntLogicOp::findLeadingZeros(), gem5::PowerISA::IntLogicOp::findLeadingZeros(), gem5::PowerISA::IntLogicOp::findTrailingZeros(), and gem5::PowerISA::IntLogicOp::findTrailingZeros().
| Bitfield<15, 0> gem5::PowerISA::si |
Definition at line 61 of file types.hh.
Referenced by gem5::PowerISA::Decoder::decode().
| Bitfield<28> gem5::PowerISA::so |
Definition at line 59 of file misc.hh.
Referenced by gem5::PowerISA::IntOp::makeCRFieldSigned(), gem5::PowerISA::IntOp::makeCRFieldUnsigned(), and gem5::o3::DynInst::strictlyOrdered().
| auto & gem5::PowerISA::StackPointerReg = int_reg::R1 |
Definition at line 160 of file int.hh.
Referenced by gem5::PowerLinux::archClone().
| auto & gem5::PowerISA::ThreadPointerReg = int_reg::R13 |
Definition at line 162 of file int.hh.
Referenced by gem5::PowerLinux::archClone().
| Bitfield<32> gem5::PowerISA::tm |
Definition at line 112 of file misc.hh.
Referenced by gem5::BaseSemihosting::BaseSemihosting(), gem5::Time::date(), gem5::DumbTOD::DumbTOD(), and gem5::RealViewTemperatureSensor::read().
| Bitfield<25, 21> gem5::PowerISA::to |
Definition at line 96 of file types.hh.
Referenced by gem5::BaseSemihosting::callRename(), gem5::GicV2Registers::clearBankedDistRange(), gem5::GicV2Registers::clearDistRange(), gem5::Gicv3Registers::clearDistRange(), gem5::Gicv3Registers::clearRedistRegister(), gem5::Gicv3CPUInterface::copy(), gem5::Gicv3Distributor::copy(), gem5::Gicv3Redistributor::copy(), gem5::GicV2Registers::copyBankedDistRange(), gem5::GicV2Registers::copyCpuRegister(), gem5::Gicv3Registers::copyCpuRegister(), gem5::GicV2Registers::copyDistRange(), gem5::Gicv3Registers::copyDistRange(), gem5::GicV2Registers::copyDistRegister(), gem5::Gicv3Registers::copyDistRegister(), gem5::GicV2::copyGicState(), gem5::Gicv3::copyGicState(), gem5::Gicv3Registers::copyRedistRange(), gem5::Gicv3Registers::copyRedistRegister(), and gem5::replace().
| auto & gem5::PowerISA::TOCPointerReg = int_reg::R2 |
Definition at line 161 of file int.hh.
Referenced by gem5::PowerProcess::initState().
| Bitfield<25> gem5::PowerISA::vec |
Definition at line 113 of file misc.hh.
Referenced by gem5::RegisterBank< BankByteOrder >::addRegistersAt(), gem5::memory::MemCtrl::addToReadQueue(), gem5::composeBitVector(), gem5::RiscvISA::ISA::getFaultHandlerAddr(), gem5::networking::IpHdr::options(), gem5::networking::TcpHdr::options(), gem5::statistics::Formula::result(), gem5::statistics::VectorBase< Derived, Stor >::result(), TEST(), TEST(), TEST(), TEST(), gem5::statistics::BinaryNode< Op >::total(), gem5::statistics::UnaryNode< Op >::total(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::statistics::validateStatName(), gem5::statistics::VectorBase< Derived, Stor >::value(), and gem5::statistics::Formula::zero().
| Bitfield<29> gem5::PowerISA::vx |
Definition at line 75 of file misc.hh.
Referenced by gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().