gem5  v22.0.0.2
int.hh
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29 
30 #ifndef __ARCH_POWER_REGS_INT_HH__
31 #define __ARCH_POWER_REGS_INT_HH__
32 
33 #include "cpu/reg_class.hh"
34 
35 namespace gem5
36 {
37 
38 namespace PowerISA
39 {
40 
41 namespace int_reg
42 {
43 
44 enum : RegIndex
45 {
78 
80 
91 
93 };
94 
95 inline constexpr RegId
128 
139 
140 } // namespace int_reg
141 
142 // Semantically meaningful register indices
143 inline constexpr auto
154 
155 } // namespace PowerISA
156 } // namespace gem5
157 
158 #endif // __ARCH_POWER_REGS_INT_HH__
gem5::PowerISA::int_reg::_R19Idx
@ _R19Idx
Definition: int.hh:65
gem5::PowerISA::int_reg::Cr
constexpr RegId Cr(IntRegClass, _CrIdx)
gem5::PowerISA::int_reg::_R10Idx
@ _R10Idx
Definition: int.hh:56
gem5::PowerISA::int_reg::R14
constexpr RegId R14(IntRegClass, _R14Idx)
gem5::PowerISA::int_reg::_R11Idx
@ _R11Idx
Definition: int.hh:57
gem5::PowerISA::int_reg::_R7Idx
@ _R7Idx
Definition: int.hh:53
gem5::PowerISA::int_reg::R27
constexpr RegId R27(IntRegClass, _R27Idx)
gem5::PowerISA::int_reg::R3
constexpr RegId R3(IntRegClass, _R3Idx)
gem5::PowerISA::int_reg::R29
constexpr RegId R29(IntRegClass, _R29Idx)
gem5::PowerISA::int_reg::NumArchRegs
@ NumArchRegs
Definition: int.hh:79
gem5::PowerISA::int_reg::R30
constexpr RegId R30(IntRegClass, _R30Idx)
gem5::PowerISA::ArgumentReg1
constexpr auto & ArgumentReg1
Definition: int.hh:146
gem5::PowerISA::int_reg::R1
constexpr RegId R1(IntRegClass, _R1Idx)
gem5::PowerISA::int_reg::_MsrIdx
@ _MsrIdx
Definition: int.hh:87
gem5::PowerISA::int_reg::_R8Idx
@ _R8Idx
Definition: int.hh:54
gem5::PowerISA::int_reg::_CtrIdx
@ _CtrIdx
Definition: int.hh:84
gem5::PowerISA::int_reg::_R18Idx
@ _R18Idx
Definition: int.hh:64
gem5::PowerISA::int_reg::R28
constexpr RegId R28(IntRegClass, _R28Idx)
gem5::PowerISA::TOCPointerReg
constexpr auto & TOCPointerReg
Definition: int.hh:152
gem5::PowerISA::int_reg::_R5Idx
@ _R5Idx
Definition: int.hh:51
gem5::PowerISA::int_reg::Rsv
constexpr RegId Rsv(IntRegClass, _RsvIdx)
gem5::PowerISA::int_reg::_RsvLenIdx
@ _RsvLenIdx
Definition: int.hh:89
gem5::PowerISA::int_reg::Xer
constexpr RegId Xer(IntRegClass, _XerIdx)
gem5::PowerISA::int_reg::R6
constexpr RegId R6(IntRegClass, _R6Idx)
gem5::PowerISA::int_reg::R7
constexpr RegId R7(IntRegClass, _R7Idx)
gem5::PowerISA::int_reg::_R22Idx
@ _R22Idx
Definition: int.hh:68
gem5::PowerISA::int_reg::RsvAddr
constexpr RegId RsvAddr(IntRegClass, _RsvAddrIdx)
gem5::PowerISA::int_reg::_XerIdx
@ _XerIdx
Definition: int.hh:82
gem5::PowerISA::ReturnValueReg
constexpr auto & ReturnValueReg
Definition: int.hh:144
gem5::PowerISA::ThreadPointerReg
constexpr auto & ThreadPointerReg
Definition: int.hh:153
gem5::PowerISA::int_reg::_R20Idx
@ _R20Idx
Definition: int.hh:66
gem5::PowerISA::int_reg::R4
constexpr RegId R4(IntRegClass, _R4Idx)
gem5::PowerISA::int_reg::_TarIdx
@ _TarIdx
Definition: int.hh:85
gem5::PowerISA::int_reg::R31
constexpr RegId R31(IntRegClass, _R31Idx)
gem5::PowerISA::int_reg::_R30Idx
@ _R30Idx
Definition: int.hh:76
gem5::PowerISA::int_reg::_R26Idx
@ _R26Idx
Definition: int.hh:72
gem5::PowerISA::int_reg::_R9Idx
@ _R9Idx
Definition: int.hh:55
gem5::PowerISA::int_reg::R23
constexpr RegId R23(IntRegClass, _R23Idx)
gem5::PowerISA::int_reg::_R12Idx
@ _R12Idx
Definition: int.hh:58
gem5::PowerISA::int_reg::R10
constexpr RegId R10(IntRegClass, _R10Idx)
gem5::PowerISA::int_reg::Ctr
constexpr RegId Ctr(IntRegClass, _CtrIdx)
gem5::PowerISA::int_reg::_R14Idx
@ _R14Idx
Definition: int.hh:60
gem5::PowerISA::int_reg::R16
constexpr RegId R16(IntRegClass, _R16Idx)
gem5::PowerISA::int_reg::R17
constexpr RegId R17(IntRegClass, _R17Idx)
gem5::PowerISA::int_reg::NumRegs
@ NumRegs
Definition: int.hh:92
gem5::PowerISA::int_reg::R19
constexpr RegId R19(IntRegClass, _R19Idx)
gem5::PowerISA::int_reg::_R24Idx
@ _R24Idx
Definition: int.hh:70
gem5::PowerISA::int_reg::R25
constexpr RegId R25(IntRegClass, _R25Idx)
gem5::PowerISA::int_reg::R18
constexpr RegId R18(IntRegClass, _R18Idx)
gem5::PowerISA::int_reg::_R23Idx
@ _R23Idx
Definition: int.hh:69
gem5::PowerISA::int_reg::R8
constexpr RegId R8(IntRegClass, _R8Idx)
gem5::PowerISA::int_reg::Tar
constexpr RegId Tar(IntRegClass, _TarIdx)
gem5::PowerISA::ArgumentReg5
constexpr auto & ArgumentReg5
Definition: int.hh:150
gem5::PowerISA::int_reg::_RsvIdx
@ _RsvIdx
Definition: int.hh:88
gem5::PowerISA::int_reg::_CrIdx
@ _CrIdx
Definition: int.hh:81
gem5::PowerISA::ArgumentReg3
constexpr auto & ArgumentReg3
Definition: int.hh:148
gem5::PowerISA::int_reg::R2
constexpr RegId R2(IntRegClass, _R2Idx)
gem5::PowerISA::int_reg::R11
constexpr RegId R11(IntRegClass, _R11Idx)
gem5::PowerISA::int_reg::R22
constexpr RegId R22(IntRegClass, _R22Idx)
gem5::PowerISA::int_reg::R9
constexpr RegId R9(IntRegClass, _R9Idx)
gem5::PowerISA::int_reg::R0
constexpr RegId R0(IntRegClass, _R0Idx)
gem5::PowerISA::int_reg::R24
constexpr RegId R24(IntRegClass, _R24Idx)
gem5::PowerISA::int_reg::_R6Idx
@ _R6Idx
Definition: int.hh:52
gem5::PowerISA::int_reg::R21
constexpr RegId R21(IntRegClass, _R21Idx)
gem5::PowerISA::int_reg::_R1Idx
@ _R1Idx
Definition: int.hh:47
gem5::PowerISA::int_reg::_R28Idx
@ _R28Idx
Definition: int.hh:74
gem5::PowerISA::int_reg::_R16Idx
@ _R16Idx
Definition: int.hh:62
gem5::PowerISA::int_reg::_R4Idx
@ _R4Idx
Definition: int.hh:50
gem5::IntRegClass
@ IntRegClass
Integer register.
Definition: reg_class.hh:58
gem5::PowerISA::ArgumentReg0
constexpr auto & ArgumentReg0
Definition: int.hh:145
gem5::PowerISA::int_reg::_R0Idx
@ _R0Idx
Definition: int.hh:46
gem5::PowerISA::int_reg::_R13Idx
@ _R13Idx
Definition: int.hh:59
gem5::PowerISA::int_reg::_R3Idx
@ _R3Idx
Definition: int.hh:49
gem5::PowerISA::int_reg::_R15Idx
@ _R15Idx
Definition: int.hh:61
gem5::PowerISA::StackPointerReg
constexpr auto & StackPointerReg
Definition: int.hh:151
gem5::PowerISA::int_reg::R15
constexpr RegId R15(IntRegClass, _R15Idx)
gem5::PowerISA::int_reg::R26
constexpr RegId R26(IntRegClass, _R26Idx)
gem5::PowerISA::int_reg::Lr
constexpr RegId Lr(IntRegClass, _LrIdx)
gem5::PowerISA::int_reg::_FpscrIdx
@ _FpscrIdx
Definition: int.hh:86
reg_class.hh
gem5::PowerISA::ArgumentReg4
constexpr auto & ArgumentReg4
Definition: int.hh:149
gem5::PowerISA::ArgumentReg2
constexpr auto & ArgumentReg2
Definition: int.hh:147
gem5::PowerISA::int_reg::_R2Idx
@ _R2Idx
Definition: int.hh:48
gem5::PowerISA::int_reg::_R27Idx
@ _R27Idx
Definition: int.hh:73
gem5::PowerISA::int_reg::_R21Idx
@ _R21Idx
Definition: int.hh:67
gem5::PowerISA::int_reg::Fpscr
constexpr RegId Fpscr(IntRegClass, _FpscrIdx)
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::PowerISA::int_reg::_R29Idx
@ _R29Idx
Definition: int.hh:75
gem5::PowerISA::int_reg::R5
constexpr RegId R5(IntRegClass, _R5Idx)
gem5::PowerISA::int_reg::_R31Idx
@ _R31Idx
Definition: int.hh:77
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::PowerISA::int_reg::_R17Idx
@ _R17Idx
Definition: int.hh:63
gem5::PowerISA::int_reg::_RsvAddrIdx
@ _RsvAddrIdx
Definition: int.hh:90
gem5::PowerISA::int_reg::_R25Idx
@ _R25Idx
Definition: int.hh:71
gem5::PowerISA::int_reg::R20
constexpr RegId R20(IntRegClass, _R20Idx)
gem5::PowerISA::int_reg::R12
constexpr RegId R12(IntRegClass, _R12Idx)
gem5::PowerISA::int_reg::R13
constexpr RegId R13(IntRegClass, _R13Idx)
gem5::PowerISA::int_reg::RsvLen
constexpr RegId RsvLen(IntRegClass, _RsvLenIdx)
gem5::PowerISA::int_reg::Msr
constexpr RegId Msr(IntRegClass, _MsrIdx)
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
gem5::PowerISA::int_reg::_LrIdx
@ _LrIdx
Definition: int.hh:83

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