gem5  v21.1.0.2
int.hh
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29 
30 #ifndef __ARCH_POWER_REGS_INT_HH__
31 #define __ARCH_POWER_REGS_INT_HH__
32 
33 namespace gem5
34 {
35 
36 namespace PowerISA
37 {
38 
39 // Constants Related to the number of registers
40 const int NumIntArchRegs = 32;
41 
42 // CR, XER, LR, CTR, TAR, FPSCR, MSR, RSV, RSV-LEN, RSV-ADDR
43 // and zero register, which doesn't actually exist but needs a number
44 const int NumIntSpecialRegs = 11;
45 
47 
48 // Semantically meaningful register indices
49 const int ReturnValueReg = 3;
50 const int ArgumentReg0 = 3;
51 const int ArgumentReg1 = 4;
52 const int ArgumentReg2 = 5;
53 const int ArgumentReg3 = 6;
54 const int ArgumentReg4 = 7;
55 const int ArgumentReg5 = 8;
56 const int StackPointerReg = 1;
57 const int TOCPointerReg = 2;
58 const int ThreadPointerReg = 13;
59 
61 {
72 };
73 
74 } // namespace PowerISA
75 } // namespace gem5
76 
77 #endif // __ARCH_POWER_REGS_INT_HH__
gem5::PowerISA::INTREG_FPSCR
@ INTREG_FPSCR
Definition: int.hh:67
gem5::PowerISA::ArgumentReg5
const int ArgumentReg5
Definition: int.hh:55
gem5::PowerISA::ArgumentReg2
const int ArgumentReg2
Definition: int.hh:52
gem5::PowerISA::ArgumentReg0
const int ArgumentReg0
Definition: int.hh:50
gem5::PowerISA::TOCPointerReg
const int TOCPointerReg
Definition: int.hh:57
gem5::PowerISA::NumIntSpecialRegs
const int NumIntSpecialRegs
Definition: int.hh:44
gem5::PowerISA::ThreadPointerReg
const int ThreadPointerReg
Definition: int.hh:58
gem5::PowerISA::StackPointerReg
const int StackPointerReg
Definition: int.hh:56
gem5::PowerISA::INTREG_XER
@ INTREG_XER
Definition: int.hh:63
gem5::PowerISA::INTREG_MSR
@ INTREG_MSR
Definition: int.hh:68
gem5::PowerISA::INTREG_RSV
@ INTREG_RSV
Definition: int.hh:69
gem5::PowerISA::ArgumentReg1
const int ArgumentReg1
Definition: int.hh:51
gem5::PowerISA::ArgumentReg3
const int ArgumentReg3
Definition: int.hh:53
gem5::PowerISA::INTREG_LR
@ INTREG_LR
Definition: int.hh:64
gem5::PowerISA::INTREG_CR
@ INTREG_CR
Definition: int.hh:62
gem5::PowerISA::INTREG_RSV_ADDR
@ INTREG_RSV_ADDR
Definition: int.hh:71
gem5::PowerISA::ReturnValueReg
const int ReturnValueReg
Definition: int.hh:49
gem5::PowerISA::INTREG_TAR
@ INTREG_TAR
Definition: int.hh:66
gem5::PowerISA::INTREG_RSV_LEN
@ INTREG_RSV_LEN
Definition: int.hh:70
gem5::PowerISA::INTREG_CTR
@ INTREG_CTR
Definition: int.hh:65
gem5::PowerISA::ArgumentReg4
const int ArgumentReg4
Definition: int.hh:54
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::PowerISA::MiscIntRegNums
MiscIntRegNums
Definition: int.hh:60
gem5::PowerISA::NumIntArchRegs
const int NumIntArchRegs
Definition: int.hh:40
gem5::PowerISA::NumIntRegs
const int NumIntRegs
Definition: int.hh:46

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