gem5  v21.1.0.2
gem5::McrMrcMiscInst Member List

This is the complete list of members for gem5::McrMrcMiscInst, including all inherited members.

_destRegIdxPtrgem5::StaticInstprivate
_numCCDestRegsgem5::StaticInstprotected
_numDestRegsgem5::StaticInstprotected
_numFPDestRegsgem5::StaticInstprotected
_numIntDestRegsgem5::StaticInstprotected
_numSrcRegsgem5::StaticInstprotected
_numVecDestRegsgem5::StaticInstprotected
_numVecElemDestRegsgem5::StaticInstprotected
_numVecPredDestRegsgem5::StaticInstprotected
_opClassgem5::StaticInstprotected
_srcRegIdxPtrgem5::StaticInstprivate
aarch64gem5::ArmISA::ArmStaticInstprotected
activateBreakpoint(ThreadContext *tc)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
advancePC(PCState &pcState) const overridegem5::ArmISA::ArmStaticInstinlineprotected
gem5::StaticInst::advancePC(TheISA::PCState &pc_state) const =0gem5::StaticInstpure virtual
advSIMDFPAccessTrap64(ExceptionLevel el) constgem5::ArmISA::ArmStaticInstprotected
annotateFault(ArmFault *fault)gem5::ArmISA::ArmStaticInstinlinevirtual
ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)gem5::ArmISA::ArmStaticInstinlineprotected
asBytes(void *buf, size_t max_size) overridegem5::ArmISA::ArmStaticInstinlinevirtual
branchTarget(const TheISA::PCState &pc) constgem5::StaticInstvirtual
branchTarget(ThreadContext *tc) constgem5::StaticInstvirtual
buildRetPC(const PCState &curPC, const PCState &callPC) const overridegem5::ArmISA::ArmStaticInstinlineprotected
gem5::StaticInst::buildRetPC(const TheISA::PCState &cur_pc, const TheISA::PCState &call_pc) constgem5::StaticInstinlinevirtual
cachedDisassemblygem5::StaticInstmutableprotected
checkAdvSIMDOrFPEnabled32(ThreadContext *tc, CPSR cpsr, CPACR cpacr, NSACR nsacr, FPEXC fpexc, bool fpexc_check, bool advsimd) constgem5::ArmISA::ArmStaticInstprotected
checkForWFxTrap32(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) constgem5::ArmISA::ArmStaticInstprotected
checkForWFxTrap64(ThreadContext *tc, ExceptionLevel tgtEl, bool isWfe) constgem5::ArmISA::ArmStaticInstprotected
checkFPAdvSIMDEnabled64(ThreadContext *tc, CPSR cpsr, CPACR cpacr) constgem5::ArmISA::ArmStaticInstprotected
checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) constgem5::ArmISA::ArmStaticInstprotected
checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) constgem5::ArmISA::ArmStaticInstprotected
checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) constgem5::ArmISA::ArmStaticInstprotected
completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *trace_data) constgem5::StaticInstinlinevirtual
countgem5::RefCountedmutableprivate
cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
cSwap(T val, bool big)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
cSwap(T val, bool big)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
decref() constgem5::RefCountedinline
destRegIdx(int i) constgem5::StaticInstinline
disabledFault() constgem5::ArmISA::ArmStaticInstinlineprotected
disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) constgem5::StaticInstvirtual
encoding() constgem5::ArmISA::ArmStaticInstinline
execute(ExecContext *xc, Trace::InstRecord *traceData) const overridegem5::McrMrcMiscInstvirtual
extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) constgem5::ArmISA::ArmStaticInstprotected
fetchMicroop(MicroPC upc) constgem5::StaticInstvirtual
flagsgem5::StaticInstprotected
generalExceptionsToAArch64(ThreadContext *tc, ExceptionLevel pstateEL) constgem5::ArmISA::ArmStaticInstprotected
generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const overridegem5::McrMrcMiscInstvirtual
getCurSveVecLen(ThreadContext *tc)gem5::ArmISA::ArmStaticInstinlinestatic
getCurSveVecLenInBits(ThreadContext *tc)gem5::ArmISA::ArmStaticInststatic
getCurSveVecLenInQWords(ThreadContext *tc)gem5::ArmISA::ArmStaticInstinlinestatic
getEMI() const overridegem5::ArmISA::ArmStaticInstinlineprotectedvirtual
getIntWidth() constgem5::ArmISA::ArmStaticInstinline
getName()gem5::StaticInstinline
getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) constgem5::ArmISA::ArmStaticInstprotected
hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, TheISA::PCState &tgt) constgem5::StaticInst
incref() constgem5::RefCountedinline
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) constgem5::StaticInstinlinevirtual
instSize() constgem5::ArmISA::ArmStaticInstinline
intWidthgem5::ArmISA::ArmStaticInstprotected
isAtomic() constgem5::StaticInstinline
isCall() constgem5::StaticInstinline
isCondCtrl() constgem5::StaticInstinline
isControl() constgem5::StaticInstinline
isDataPrefetch() constgem5::StaticInstinline
isDelayedCommit() constgem5::StaticInstinline
isDirectCtrl() constgem5::StaticInstinline
isFirstMicroop() constgem5::StaticInstinline
isFloating() constgem5::StaticInstinline
isFullMemBarrier() constgem5::StaticInstinline
isHtmCancel() constgem5::StaticInstinline
isHtmCmd() constgem5::StaticInstinline
isHtmStart() constgem5::StaticInstinline
isHtmStop() constgem5::StaticInstinline
isIndirectCtrl() constgem5::StaticInstinline
isInstPrefetch() constgem5::StaticInstinline
isInteger() constgem5::StaticInstinline
isLastMicroop() constgem5::StaticInstinline
isLoad() constgem5::StaticInstinline
isMacroop() constgem5::StaticInstinline
isMemRef() constgem5::StaticInstinline
isMicroop() constgem5::StaticInstinline
isNonSpeculative() constgem5::StaticInstinline
isNop() constgem5::StaticInstinline
isPrefetch() constgem5::StaticInstinline
isQuiesce() constgem5::StaticInstinline
isReadBarrier() constgem5::StaticInstinline
isReturn() constgem5::StaticInstinline
issgem5::McrMrcMiscInstprotected
isSerializeAfter() constgem5::StaticInstinline
isSerializeBefore() constgem5::StaticInstinline
isSerializing() constgem5::StaticInstinline
isSquashAfter() constgem5::StaticInstinline
isStore() constgem5::StaticInstinline
isStoreConditional() constgem5::StaticInstinline
isSyscall() constgem5::StaticInstinline
isUncondCtrl() constgem5::StaticInstinline
isUnverifiable() constgem5::StaticInstinline
isVector() constgem5::StaticInstinline
isWFxTrapping(ThreadContext *tc, ExceptionLevel targetEL, bool isWfe) constgem5::ArmISA::ArmStaticInstinlineprotected
isWriteBarrier() constgem5::StaticInstinline
machInstgem5::ArmISA::ArmStaticInstprotected
McrMrcMiscInst(const char *_mnemonic, ArmISA::ExtMachInst _machInst, uint64_t _iss, ArmISA::MiscRegIndex _miscReg)gem5::McrMrcMiscInst
miscReggem5::McrMrcMiscInstprotected
mnemonicgem5::StaticInstprotected
nullStaticInstPtrgem5::StaticInststatic
numCCDestRegs() constgem5::StaticInstinline
numDestRegs() constgem5::StaticInstinline
numFPDestRegs() constgem5::StaticInstinline
numIntDestRegs() constgem5::StaticInstinline
numSrcRegs() constgem5::StaticInstinline
numVecDestRegs() constgem5::StaticInstinline
numVecElemDestRegs() constgem5::StaticInstinline
numVecPredDestRegs() constgem5::StaticInstinline
opClass() constgem5::StaticInstinline
operator=(const RefCounted &)gem5::RefCountedprivate
printCCReg(std::ostream &os, RegIndex reg_idx) constgem5::ArmISA::ArmStaticInstprotected
printCondition(std::ostream &os, unsigned code, bool noImplicit=false) constgem5::ArmISA::ArmStaticInstprotected
printDataInst(std::ostream &os, bool withImm) constgem5::ArmISA::ArmStaticInstprotected
printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, uint64_t imm) constgem5::ArmISA::ArmStaticInstprotected
printExtendOperand(bool firstOperand, std::ostream &os, IntRegIndex rm, ArmExtendType type, int64_t shiftAmt) constgem5::ArmISA::ArmStaticInstprotected
printFlags(std::ostream &outs, const std::string &separator) constgem5::StaticInst
printFloatReg(std::ostream &os, RegIndex reg_idx) constgem5::ArmISA::ArmStaticInstprotected
printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth=0) constgem5::ArmISA::ArmStaticInstprotected
printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab, const std::string &prefix, const Addr addr, const std::string &suffix) constgem5::ArmISA::ArmStaticInstprotected
printMiscReg(std::ostream &os, RegIndex reg_idx) constgem5::ArmISA::ArmStaticInstprotected
printMnemonic(std::ostream &os, const std::string &suffix="", bool withPred=true, bool withCond64=false, ConditionCode cond64=COND_UC) constgem5::ArmISA::ArmStaticInstprotected
printPFflags(std::ostream &os, int flag) constgem5::ArmISA::ArmStaticInstprotected
printShiftOperand(std::ostream &os, IntRegIndex rm, bool immShift, uint32_t shiftAmt, IntRegIndex rs, ArmShiftType type) constgem5::ArmISA::ArmStaticInstprotected
printTarget(std::ostream &os, Addr target, const loader::SymbolTable *symtab) constgem5::ArmISA::ArmStaticInstprotected
printVecPredReg(std::ostream &os, RegIndex reg_idx) constgem5::ArmISA::ArmStaticInstprotected
printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg=false) constgem5::ArmISA::ArmStaticInstprotected
readPC(ExecContext *xc)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
RefCounted(const RefCounted &)gem5::RefCountedprivate
RefCounted()gem5::RefCountedinline
RegIdArrayPtr typedefgem5::StaticInst
satInt(int32_t &res, int64_t op, int width)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
setAIWNextPC(ExecContext *xc, Addr val)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
setDelayedCommit()gem5::StaticInstinline
setDestRegIdx(int i, const RegId &val)gem5::StaticInstinline
setFirstMicroop()gem5::StaticInstinline
setFlag(Flags f)gem5::StaticInstinline
setIWNextPC(ExecContext *xc, Addr val)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
setLastMicroop()gem5::StaticInstinline
setNextPC(ExecContext *xc, Addr val)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest)gem5::StaticInstinlineprotected
setSrcRegIdx(int i, const RegId &val)gem5::StaticInstinline
shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constgem5::ArmISA::ArmStaticInstprotected
shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constgem5::ArmISA::ArmStaticInstprotected
shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constgem5::ArmISA::ArmStaticInstprotected
shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) constgem5::ArmISA::ArmStaticInstprotected
shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) constgem5::ArmISA::ArmStaticInstprotected
simpleAsBytes(void *buf, size_t max_size, const T &t)gem5::StaticInstinlineprotected
softwareBreakpoint32(ExecContext *xc, uint16_t imm) constgem5::ArmISA::ArmStaticInstprotected
spsrWriteByInstr(uint32_t spsr, uint32_t val, uint8_t byteMask, bool affectState)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
srcRegIdx(int i) constgem5::StaticInstinline
StaticInst(const char *_mnemonic, OpClass op_class)gem5::StaticInstinlineprotected
sveAccessTrap(ExceptionLevel el) constgem5::ArmISA::ArmStaticInstprotected
trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) constgem5::ArmISA::ArmStaticInstprotected
undefinedFault32(ThreadContext *tc, ExceptionLevel el) constgem5::ArmISA::ArmStaticInstprotected
undefinedFault64(ThreadContext *tc, ExceptionLevel el) constgem5::ArmISA::ArmStaticInstprotected
uSatInt(int32_t &res, int64_t op, int width)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)gem5::ArmISA::ArmStaticInstinlineprotectedstatic
~RefCounted()gem5::RefCountedinlinevirtual
~StaticInst()gem5::StaticInstinlinevirtual

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