| _destRegIdxPtr | gem5::StaticInst | private |
| _numDestRegs | gem5::StaticInst | protected |
| _numSrcRegs | gem5::StaticInst | protected |
| _numTypedDestRegs | gem5::StaticInst | protected |
| _opClass | gem5::StaticInst | protected |
| _size | gem5::StaticInst | protected |
| _srcRegIdxPtr | gem5::StaticInst | private |
| advancePC(PCStateBase &pcState) const override | gem5::RiscvISA::RiscvMicroInst | protectedvirtual |
| advancePC(ThreadContext *tc) const override | gem5::RiscvISA::RiscvMicroInst | protectedvirtual |
| asBytes(void *buf, size_t size) override | gem5::RiscvISA::RiscvStaticInst | inlinevirtual |
| branchTarget(const PCStateBase &pc) const | gem5::StaticInst | virtual |
| branchTarget(ThreadContext *tc) const | gem5::StaticInst | virtual |
| buildRetPC(const PCStateBase &cur_pc, const PCStateBase &call_pc) const override | gem5::RiscvISA::RiscvStaticInst | inlinevirtual |
| cachedDisassembly | gem5::StaticInst | mutableprotected |
| completeAcc(Packet *pkt, ExecContext *xc, trace::InstRecord *trace_data) const | gem5::StaticInst | inlinevirtual |
| count | gem5::RefCounted | mutableprivate |
| decref() const | gem5::RefCounted | inline |
| destRegIdx(int i) const | gem5::StaticInst | inline |
| disassemble(Addr pc, const loader::SymbolTable *symtab=nullptr) const | gem5::StaticInst | virtual |
| execute(ExecContext *xc, trace::InstRecord *traceData) const =0 | gem5::StaticInst | pure virtual |
| fetchMicroop(MicroPC upc) const | gem5::StaticInst | virtual |
| flags | gem5::StaticInst | protected |
| generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const override | gem5::RiscvISA::VlSegMicroInst | protectedvirtual |
| getEMI() const | gem5::StaticInst | inlinevirtual |
| getName() | gem5::StaticInst | inline |
| incref() const | gem5::RefCounted | inline |
| initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const | gem5::StaticInst | inlinevirtual |
| isAtomic() const | gem5::StaticInst | inline |
| isCall() const | gem5::StaticInst | inline |
| isCondCtrl() const | gem5::StaticInst | inline |
| isControl() const | gem5::StaticInst | inline |
| isDataPrefetch() const | gem5::StaticInst | inline |
| isDelayedCommit() const | gem5::StaticInst | inline |
| isDirectCtrl() const | gem5::StaticInst | inline |
| isFirstMicroop() const | gem5::StaticInst | inline |
| isFloating() const | gem5::StaticInst | inline |
| isFullMemBarrier() const | gem5::StaticInst | inline |
| isHtmCancel() const | gem5::StaticInst | inline |
| isHtmCmd() const | gem5::StaticInst | inline |
| isHtmStart() const | gem5::StaticInst | inline |
| isHtmStop() const | gem5::StaticInst | inline |
| isIndirectCtrl() const | gem5::StaticInst | inline |
| isInstPrefetch() const | gem5::StaticInst | inline |
| isInteger() const | gem5::StaticInst | inline |
| isInvalid() const | gem5::StaticInst | inline |
| isLastMicroop() const | gem5::StaticInst | inline |
| isLoad() const | gem5::StaticInst | inline |
| isMacroop() const | gem5::StaticInst | inline |
| isMatrix() const | gem5::StaticInst | inline |
| isMemRef() const | gem5::StaticInst | inline |
| isMicroop() const | gem5::StaticInst | inline |
| isNonSpeculative() const | gem5::StaticInst | inline |
| isNop() const | gem5::StaticInst | inline |
| isPrefetch() const | gem5::StaticInst | inline |
| isPseudo() const | gem5::StaticInst | inline |
| isQuiesce() const | gem5::StaticInst | inline |
| isReadBarrier() const | gem5::StaticInst | inline |
| isReturn() const | gem5::StaticInst | inline |
| isSerializeAfter() const | gem5::StaticInst | inline |
| isSerializeBefore() const | gem5::StaticInst | inline |
| isSerializing() const | gem5::StaticInst | inline |
| isSquashAfter() const | gem5::StaticInst | inline |
| isStore() const | gem5::StaticInst | inline |
| isStoreConditional() const | gem5::StaticInst | inline |
| isSyscall() const | gem5::StaticInst | inline |
| isUncondCtrl() const | gem5::StaticInst | inline |
| isUnverifiable() const | gem5::StaticInst | inline |
| isVector() const | gem5::StaticInst | inline |
| isWriteBarrier() const | gem5::StaticInst | inline |
| machInst | gem5::RiscvISA::RiscvStaticInst | |
| memAccessFlags | gem5::RiscvISA::VlSegMicroInst | protected |
| microIdx | gem5::RiscvISA::VectorMicroInst | protected |
| microVl | gem5::RiscvISA::VectorMicroInst | protected |
| mnemonic | gem5::StaticInst | protected |
| nullStaticInstPtr | gem5::StaticInst | static |
| numDestRegs() const | gem5::StaticInst | inline |
| numDestRegs(RegClassType type) const | gem5::StaticInst | inline |
| numSrcRegs() const | gem5::StaticInst | inline |
| opClass() const | gem5::StaticInst | inline |
| operator=(const RefCounted &) | gem5::RefCounted | private |
| printFlags(std::ostream &outs, const std::string &separator) const | gem5::StaticInst | |
| RefCounted(const RefCounted &) | gem5::RefCounted | private |
| RefCounted() | gem5::RefCounted | inline |
| RegIdArrayPtr typedef | gem5::StaticInst | |
| regIdx | gem5::RiscvISA::VlSegMicroInst | protected |
| RiscvMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass) | gem5::RiscvISA::RiscvMicroInst | inlineprotected |
| RiscvStaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass) | gem5::RiscvISA::RiscvStaticInst | inlineprotected |
| rvExt(T64 x) const | gem5::RiscvISA::RiscvStaticInst | inlineprotected |
| rvSelect(T v32, T v64) const | gem5::RiscvISA::RiscvStaticInst | inlineprotected |
| rvSext(int64_t x) const | gem5::RiscvISA::RiscvStaticInst | inlineprotected |
| rvZext(uint64_t x) const | gem5::RiscvISA::RiscvStaticInst | inlineprotected |
| setDelayedCommit() | gem5::StaticInst | inline |
| setDestRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| setFirstMicroop() | gem5::StaticInst | inline |
| setFlag(Flags f) | gem5::StaticInst | inline |
| setLastMicroop() | gem5::StaticInst | inline |
| setRegIdxArrays(RegIdArrayPtr src, RegIdArrayPtr dest) | gem5::StaticInst | inlineprotected |
| setSrcRegIdx(int i, const RegId &val) | gem5::StaticInst | inline |
| simpleAsBytes(void *buf, size_t max_size, const T &t) | gem5::StaticInst | inlineprotected |
| size() const | gem5::StaticInst | inline |
| size(size_t newSize) | gem5::StaticInst | inlinevirtual |
| srcRegIdx(int i) const | gem5::StaticInst | inline |
| StaticInst(const char *_mnemonic, OpClass op_class) | gem5::StaticInst | inlineprotected |
| VectorMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _microVl, uint32_t _microIdx, uint32_t _vlen=256) | gem5::RiscvISA::VectorMicroInst | inlineprotected |
| vlen | gem5::RiscvISA::VectorMicroInst | protected |
| VlSegMicroInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass, uint32_t _microVl, uint32_t _microIdx, uint32_t _numMicroops, uint32_t _field, uint32_t _numFields, uint32_t _vlen) | gem5::RiscvISA::VlSegMicroInst | inlineprotected |
| vtype | gem5::RiscvISA::VectorMicroInst | protected |
| ~RefCounted() | gem5::RefCounted | inlinevirtual |
| ~StaticInst() | gem5::StaticInst | inlinevirtual |