gem5  v21.1.0.2
Classes | Typedefs | Enumerations | Functions | Variables
gem5::RiscvISA Namespace Reference

Classes

class  AddressFault
 
class  AtomicGenericOp
 A generic atomic op class. More...
 
class  AtomicMemOp
 
class  AtomicMemOpMicro
 
class  BareMetal
 
class  BreakpointFault
 
class  CompRegOp
 Base class for compressed operations that work only on registers. More...
 
struct  CSRMetadata
 
class  CSROp
 Base class for CSR operations. More...
 
class  Decoder
 
class  EmuLinux
 
class  FsLinux
 
class  IllegalFrmFault
 
class  IllegalInstFault
 
class  ImmOp
 Base class for operations with immediates (I is the type of immediate) More...
 
class  InstFault
 
class  InterruptFault
 
class  Interrupts
 
class  ISA
 
class  Load
 
class  LoadReserved
 
class  LoadReservedMicro
 
class  MemFenceMicro
 
class  MemInst
 
class  MMU
 
class  PCState
 
class  PseudoOp
 
struct  RegABI64
 
class  RegOp
 Base class for operations that work only on registers. More...
 
class  RemoteGDB
 
class  Reset
 
class  RiscvFault
 
class  RiscvMacroInst
 Base class for all RISC-V Macroops. More...
 
class  RiscvMicroInst
 Base class for all RISC-V Microops. More...
 
class  RiscvStaticInst
 Base class for all RISC-V static instructions. More...
 
class  SEWorkload
 
class  StackTrace
 
class  Store
 
class  StoreCond
 
class  StoreCondMicro
 
class  SyscallFault
 
class  SystemOp
 Base class for system operations. More...
 
class  TLB
 
struct  TlbEntry
 
class  UnimplementedFault
 
class  Unknown
 Static instruction class for unknown (illegal) instructions. More...
 
class  UnknownInstFault
 
class  Walker
 

Typedefs

typedef Trie< Addr, TlbEntryTlbEntryTrie
 
using freg_t = float64_t
 
typedef uint32_t MachInst
 
typedef uint64_t ExtMachInst
 
using VecElem = ::gem5::DummyVecElem
 
using VecRegContainer = ::gem5::DummyVecRegContainer
 
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer
 

Enumerations

enum  FloatException : uint64_t {
  FloatInexact = 0x1, FloatUnderflow = 0x2, FloatOverflow = 0x4, FloatDivZero = 0x8,
  FloatInvalid = 0x10
}
 
enum  ExceptionCode : uint64_t {
  INST_ADDR_MISALIGNED = 0, INST_ACCESS = 1, INST_ILLEGAL = 2, BREAKPOINT = 3,
  LOAD_ADDR_MISALIGNED = 4, LOAD_ACCESS = 5, STORE_ADDR_MISALIGNED = 6, AMO_ADDR_MISALIGNED = 6,
  STORE_ACCESS = 7, AMO_ACCESS = 7, ECALL_USER = 8, ECALL_SUPER = 9,
  ECALL_MACHINE = 11, INST_PAGE = 12, LOAD_PAGE = 13, STORE_PAGE = 15,
  AMO_PAGE = 15, INT_SOFTWARE_USER = 0, INT_SOFTWARE_SUPER = 1, INT_SOFTWARE_MACHINE = 3,
  INT_TIMER_USER = 4, INT_TIMER_SUPER = 5, INT_TIMER_MACHINE = 7, INT_EXT_USER = 8,
  INT_EXT_SUPER = 9, INT_EXT_MACHINE = 11, NumInterruptTypes
}
 
enum  PrivilegeMode { PRV_U = 0, PRV_S = 1, PRV_M = 3 }
 
enum  FPUStatus { OFF = 0, INITIAL = 1, CLEAN = 2, DIRTY = 3 }
 
enum  MiscRegIndex {
  MISCREG_PRV = 0, MISCREG_ISA, MISCREG_VENDORID, MISCREG_ARCHID,
  MISCREG_IMPID, MISCREG_HARTID, MISCREG_STATUS, MISCREG_IP,
  MISCREG_IE, MISCREG_CYCLE, MISCREG_TIME, MISCREG_INSTRET,
  MISCREG_HPMCOUNTER03, MISCREG_HPMCOUNTER04, MISCREG_HPMCOUNTER05, MISCREG_HPMCOUNTER06,
  MISCREG_HPMCOUNTER07, MISCREG_HPMCOUNTER08, MISCREG_HPMCOUNTER09, MISCREG_HPMCOUNTER10,
  MISCREG_HPMCOUNTER11, MISCREG_HPMCOUNTER12, MISCREG_HPMCOUNTER13, MISCREG_HPMCOUNTER14,
  MISCREG_HPMCOUNTER15, MISCREG_HPMCOUNTER16, MISCREG_HPMCOUNTER17, MISCREG_HPMCOUNTER18,
  MISCREG_HPMCOUNTER19, MISCREG_HPMCOUNTER20, MISCREG_HPMCOUNTER21, MISCREG_HPMCOUNTER22,
  MISCREG_HPMCOUNTER23, MISCREG_HPMCOUNTER24, MISCREG_HPMCOUNTER25, MISCREG_HPMCOUNTER26,
  MISCREG_HPMCOUNTER27, MISCREG_HPMCOUNTER28, MISCREG_HPMCOUNTER29, MISCREG_HPMCOUNTER30,
  MISCREG_HPMCOUNTER31, MISCREG_HPMEVENT03, MISCREG_HPMEVENT04, MISCREG_HPMEVENT05,
  MISCREG_HPMEVENT06, MISCREG_HPMEVENT07, MISCREG_HPMEVENT08, MISCREG_HPMEVENT09,
  MISCREG_HPMEVENT10, MISCREG_HPMEVENT11, MISCREG_HPMEVENT12, MISCREG_HPMEVENT13,
  MISCREG_HPMEVENT14, MISCREG_HPMEVENT15, MISCREG_HPMEVENT16, MISCREG_HPMEVENT17,
  MISCREG_HPMEVENT18, MISCREG_HPMEVENT19, MISCREG_HPMEVENT20, MISCREG_HPMEVENT21,
  MISCREG_HPMEVENT22, MISCREG_HPMEVENT23, MISCREG_HPMEVENT24, MISCREG_HPMEVENT25,
  MISCREG_HPMEVENT26, MISCREG_HPMEVENT27, MISCREG_HPMEVENT28, MISCREG_HPMEVENT29,
  MISCREG_HPMEVENT30, MISCREG_HPMEVENT31, MISCREG_TSELECT, MISCREG_TDATA1,
  MISCREG_TDATA2, MISCREG_TDATA3, MISCREG_DCSR, MISCREG_DPC,
  MISCREG_DSCRATCH, MISCREG_MEDELEG, MISCREG_MIDELEG, MISCREG_MTVEC,
  MISCREG_MCOUNTEREN, MISCREG_MSCRATCH, MISCREG_MEPC, MISCREG_MCAUSE,
  MISCREG_MTVAL, MISCREG_PMPCFG0, MISCREG_PMPCFG2, MISCREG_PMPADDR00,
  MISCREG_PMPADDR01, MISCREG_PMPADDR02, MISCREG_PMPADDR03, MISCREG_PMPADDR04,
  MISCREG_PMPADDR05, MISCREG_PMPADDR06, MISCREG_PMPADDR07, MISCREG_PMPADDR08,
  MISCREG_PMPADDR09, MISCREG_PMPADDR10, MISCREG_PMPADDR11, MISCREG_PMPADDR12,
  MISCREG_PMPADDR13, MISCREG_PMPADDR14, MISCREG_PMPADDR15, MISCREG_SEDELEG,
  MISCREG_SIDELEG, MISCREG_STVEC, MISCREG_SCOUNTEREN, MISCREG_SSCRATCH,
  MISCREG_SEPC, MISCREG_SCAUSE, MISCREG_STVAL, MISCREG_SATP,
  MISCREG_UTVEC, MISCREG_USCRATCH, MISCREG_UEPC, MISCREG_UCAUSE,
  MISCREG_UTVAL, MISCREG_FFLAGS, MISCREG_FRM, NUM_MISCREGS
}
 
enum  CSRIndex {
  CSR_USTATUS = 0x000, CSR_UIE = 0x004, CSR_UTVEC = 0x005, CSR_USCRATCH = 0x040,
  CSR_UEPC = 0x041, CSR_UCAUSE = 0x042, CSR_UTVAL = 0x043, CSR_UIP = 0x044,
  CSR_FFLAGS = 0x001, CSR_FRM = 0x002, CSR_FCSR = 0x003, CSR_CYCLE = 0xC00,
  CSR_TIME = 0xC01, CSR_INSTRET = 0xC02, CSR_HPMCOUNTER03 = 0xC03, CSR_HPMCOUNTER04 = 0xC04,
  CSR_HPMCOUNTER05 = 0xC05, CSR_HPMCOUNTER06 = 0xC06, CSR_HPMCOUNTER07 = 0xC07, CSR_HPMCOUNTER08 = 0xC08,
  CSR_HPMCOUNTER09 = 0xC09, CSR_HPMCOUNTER10 = 0xC0A, CSR_HPMCOUNTER11 = 0xC0B, CSR_HPMCOUNTER12 = 0xC0C,
  CSR_HPMCOUNTER13 = 0xC0D, CSR_HPMCOUNTER14 = 0xC0E, CSR_HPMCOUNTER15 = 0xC0F, CSR_HPMCOUNTER16 = 0xC10,
  CSR_HPMCOUNTER17 = 0xC11, CSR_HPMCOUNTER18 = 0xC12, CSR_HPMCOUNTER19 = 0xC13, CSR_HPMCOUNTER20 = 0xC14,
  CSR_HPMCOUNTER21 = 0xC15, CSR_HPMCOUNTER22 = 0xC16, CSR_HPMCOUNTER23 = 0xC17, CSR_HPMCOUNTER24 = 0xC18,
  CSR_HPMCOUNTER25 = 0xC19, CSR_HPMCOUNTER26 = 0xC1A, CSR_HPMCOUNTER27 = 0xC1B, CSR_HPMCOUNTER28 = 0xC1C,
  CSR_HPMCOUNTER29 = 0xC1D, CSR_HPMCOUNTER30 = 0xC1E, CSR_HPMCOUNTER31 = 0xC1F, CSR_SSTATUS = 0x100,
  CSR_SEDELEG = 0x102, CSR_SIDELEG = 0x103, CSR_SIE = 0x104, CSR_STVEC = 0x105,
  CSR_SCOUNTEREN = 0x106, CSR_SSCRATCH = 0x140, CSR_SEPC = 0x141, CSR_SCAUSE = 0x142,
  CSR_STVAL = 0x143, CSR_SIP = 0x144, CSR_SATP = 0x180, CSR_MVENDORID = 0xF11,
  CSR_MARCHID = 0xF12, CSR_MIMPID = 0xF13, CSR_MHARTID = 0xF14, CSR_MSTATUS = 0x300,
  CSR_MISA = 0x301, CSR_MEDELEG = 0x302, CSR_MIDELEG = 0x303, CSR_MIE = 0x304,
  CSR_MTVEC = 0x305, CSR_MCOUNTEREN = 0x306, CSR_MSCRATCH = 0x340, CSR_MEPC = 0x341,
  CSR_MCAUSE = 0x342, CSR_MTVAL = 0x343, CSR_MIP = 0x344, CSR_PMPCFG0 = 0x3A0,
  CSR_PMPCFG2 = 0x3A2, CSR_PMPADDR00 = 0x3B0, CSR_PMPADDR01 = 0x3B1, CSR_PMPADDR02 = 0x3B2,
  CSR_PMPADDR03 = 0x3B3, CSR_PMPADDR04 = 0x3B4, CSR_PMPADDR05 = 0x3B5, CSR_PMPADDR06 = 0x3B6,
  CSR_PMPADDR07 = 0x3B7, CSR_PMPADDR08 = 0x3B8, CSR_PMPADDR09 = 0x3B9, CSR_PMPADDR10 = 0x3BA,
  CSR_PMPADDR11 = 0x3BB, CSR_PMPADDR12 = 0x3BC, CSR_PMPADDR13 = 0x3BD, CSR_PMPADDR14 = 0x3BE,
  CSR_PMPADDR15 = 0x3BF, CSR_MCYCLE = 0xB00, CSR_MINSTRET = 0xB02, CSR_MHPMCOUNTER03 = 0xC03,
  CSR_MHPMCOUNTER04 = 0xC04, CSR_MHPMCOUNTER05 = 0xC05, CSR_MHPMCOUNTER06 = 0xC06, CSR_MHPMCOUNTER07 = 0xC07,
  CSR_MHPMCOUNTER08 = 0xC08, CSR_MHPMCOUNTER09 = 0xC09, CSR_MHPMCOUNTER10 = 0xC0A, CSR_MHPMCOUNTER11 = 0xC0B,
  CSR_MHPMCOUNTER12 = 0xC0C, CSR_MHPMCOUNTER13 = 0xC0D, CSR_MHPMCOUNTER14 = 0xC0E, CSR_MHPMCOUNTER15 = 0xC0F,
  CSR_MHPMCOUNTER16 = 0xC10, CSR_MHPMCOUNTER17 = 0xC11, CSR_MHPMCOUNTER18 = 0xC12, CSR_MHPMCOUNTER19 = 0xC13,
  CSR_MHPMCOUNTER20 = 0xC14, CSR_MHPMCOUNTER21 = 0xC15, CSR_MHPMCOUNTER22 = 0xC16, CSR_MHPMCOUNTER23 = 0xC17,
  CSR_MHPMCOUNTER24 = 0xC18, CSR_MHPMCOUNTER25 = 0xC19, CSR_MHPMCOUNTER26 = 0xC1A, CSR_MHPMCOUNTER27 = 0xC1B,
  CSR_MHPMCOUNTER28 = 0xC1C, CSR_MHPMCOUNTER29 = 0xC1D, CSR_MHPMCOUNTER30 = 0xC1E, CSR_MHPMCOUNTER31 = 0xC1F,
  CSR_MHPMEVENT03 = 0x323, CSR_MHPMEVENT04 = 0x324, CSR_MHPMEVENT05 = 0x325, CSR_MHPMEVENT06 = 0x326,
  CSR_MHPMEVENT07 = 0x327, CSR_MHPMEVENT08 = 0x328, CSR_MHPMEVENT09 = 0x329, CSR_MHPMEVENT10 = 0x32A,
  CSR_MHPMEVENT11 = 0x32B, CSR_MHPMEVENT12 = 0x32C, CSR_MHPMEVENT13 = 0x32D, CSR_MHPMEVENT14 = 0x32E,
  CSR_MHPMEVENT15 = 0x32F, CSR_MHPMEVENT16 = 0x330, CSR_MHPMEVENT17 = 0x331, CSR_MHPMEVENT18 = 0x332,
  CSR_MHPMEVENT19 = 0x333, CSR_MHPMEVENT20 = 0x334, CSR_MHPMEVENT21 = 0x335, CSR_MHPMEVENT22 = 0x336,
  CSR_MHPMEVENT23 = 0x337, CSR_MHPMEVENT24 = 0x338, CSR_MHPMEVENT25 = 0x339, CSR_MHPMEVENT26 = 0x33A,
  CSR_MHPMEVENT27 = 0x33B, CSR_MHPMEVENT28 = 0x33C, CSR_MHPMEVENT29 = 0x33D, CSR_MHPMEVENT30 = 0x33E,
  CSR_MHPMEVENT31 = 0x33F, CSR_TSELECT = 0x7A0, CSR_TDATA1 = 0x7A1, CSR_TDATA2 = 0x7A2,
  CSR_TDATA3 = 0x7A3, CSR_DCSR = 0x7B0, CSR_DPC = 0x7B1, CSR_DSCRATCH = 0x7B2
}
 

Functions

static SyscallReturn unameFunc64 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn unameFunc32 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
template<class XC >
void handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
template<class XC >
void handleLockedRead (XC *xc, const RequestPtr &req)
 
template<class XC >
void handleLockedSnoopHit (XC *xc)
 
template<class XC >
bool handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 
template<class XC >
void globalClearExclusive (XC *xc)
 
 BitUnion64 (SATP) Bitfield< 63
 
 EndBitUnion (SATP) enum AddrXlateMode
 
 BitUnion64 (PTESv39) Bitfield< 53
 
 EndBitUnion (PTESv39) struct TlbEntry
 
 BitUnion32 (IndexReg) Bitfield< 31 > p
 
 EndBitUnion (IndexReg) BitUnion32(RandomReg) Bitfield< 30
 
 EndBitUnion (RandomReg) BitUnion64(EntryLoReg) Bitfield< 63
 
 EndBitUnion (EntryLoReg) BitUnion64(ContextReg) Bitfield< 63
 
 EndBitUnion (ContextReg) BitUnion32(PageMaskReg) Bitfield< 28
 
 EndBitUnion (PageMaskReg) BitUnion32(PageGrainReg) Bitfield< 31
 
 EndBitUnion (PageGrainReg) BitUnion32(WiredReg) Bitfield< 30
 
 EndBitUnion (WiredReg) BitUnion32(HWREnaReg) Bitfield< 31
 
 EndBitUnion (HWREnaReg) BitUnion64(EntryHiReg) Bitfield< 63
 
 EndBitUnion (EntryHiReg) BitUnion32(StatusReg) SubBitUnion(cu
 
 EndSubBitUnion (cu) Bitfield< 27 > rp
 
 SubBitUnion (im, 15, 8) Bitfield< 15 > im7
 
 EndSubBitUnion (im) Bitfield< 7 > kx
 
 EndBitUnion (StatusReg) BitUnion32(IntCtlReg) Bitfield< 31
 
 EndBitUnion (IntCtlReg) BitUnion32(SRSCtlReg) Bitfield< 29
 
 EndBitUnion (SRSCtlReg) BitUnion32(SRSMapReg) Bitfield< 31
 
 EndBitUnion (SRSMapReg) BitUnion32(CauseReg) Bitfield< 31 > bd
 
 SubBitUnion (ip, 15, 8) Bitfield< 15 > ip7
 
 EndSubBitUnion (ip)
 
 EndBitUnion (CauseReg) BitUnion32(PRIdReg) Bitfield< 31
 
 EndBitUnion (PRIdReg) BitUnion32(EBaseReg) Bitfield< 29
 
 EndBitUnion (EBaseReg) BitUnion32(ConfigReg) Bitfield< 31 > m
 
 EndBitUnion (ConfigReg) BitUnion32(Config1Reg) Bitfield< 31 > m
 
 EndBitUnion (Config1Reg) BitUnion32(Config2Reg) Bitfield< 31 > m
 
 EndBitUnion (Config2Reg) BitUnion32(Config3Reg) Bitfield< 31 > m
 
 EndBitUnion (Config3Reg) BitUnion64(WatchLoReg) Bitfield< 63
 
 EndBitUnion (WatchLoReg) BitUnion32(WatchHiReg) Bitfield< 31 > m
 
 EndBitUnion (WatchHiReg) BitUnion32(PerfCntCtlReg) Bitfield< 31 > m
 
 EndBitUnion (PerfCntCtlReg) BitUnion32(CacheErrReg) Bitfield< 31 > er
 
 EndBitUnion (CacheErrReg) BitUnion32(TagLoReg) Bitfield< 31
 
static constexpr uint32_t unboxF32 (uint64_t v)
 
static constexpr uint64_t boxF32 (uint32_t v)
 
static constexpr float32_t f32 (uint32_t v)
 
static constexpr float64_t f64 (uint64_t v)
 
static constexpr float32_t f32 (freg_t r)
 
static constexpr float64_t f64 (freg_t r)
 
static constexpr freg_t freg (float32_t f)
 
static constexpr freg_t freg (float64_t f)
 
static constexpr freg_t freg (uint_fast16_t f)
 
 BitUnion64 (STATUS) Bitfield< 63 > sd
 These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org. More...
 
 EndBitUnion (STATUS) BitUnion64(INTERRUPT) Bitfield< 11 > mei
 These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org. More...
 
 EndBitUnion (INTERRUPT) const off_t MXL_OFFSET
 
template<typename T >
bool isquietnan (T val)
 
template<>
bool isquietnan< float > (float val)
 
template<>
bool isquietnan< double > (double val)
 
template<typename T >
bool issignalingnan (T val)
 
template<>
bool issignalingnan< float > (float val)
 
template<>
bool issignalingnan< double > (double val)
 
std::string registerName (RegId reg)
 

Variables

const GEM5_VAR_USED std::array< const char *, NUM_MISCREGSMiscRegNames
 
std::unordered_map< int, std::stack< Addr > > locked_addrs
 
const int WARN_FAILURE = 10000
 
const Addr PageShift = 12
 
const Addr PageBytes = 1ULL << PageShift
 
 mode
 
Bitfield< 59, 44 > asid
 
Bitfield< 43, 0 > ppn
 
const Addr VADDR_BITS = 39
 
const Addr LEVEL_BITS = 9
 
const Addr LEVEL_MASK = (1 << LEVEL_BITS) - 1
 
Bitfield< 53, 28 > ppn2
 
Bitfield< 27, 19 > ppn1
 
Bitfield< 18, 10 > ppn0
 
Bitfield< 7 > d
 
Bitfield< 6 > a
 
Bitfield< 5 > g
 
Bitfield< 4 > u
 
Bitfield< 3, 1 > perm
 
Bitfield< 3 > x
 
Bitfield< 2 > w
 
Bitfield< 1 > r
 
Bitfield< 0 > v
 
Bitfield< 30, 0 > index
 
 random
 
 fill
 
Bitfield< 29, 6 > pfn
 
Bitfield< 5, 3 > c
 
 pteBase
 
Bitfield< 22, 4 > badVPN2
 
 mask
 
Bitfield< 12, 11 > maskx
 
 aseUp
 
Bitfield< 29 > elpa
 
Bitfield< 28 > esp
 
Bitfield< 12, 8 > aseDn
 
 wired
 
 impl
 
Bitfield< 39, 13 > vpn2
 
Bitfield< 12, 11 > vpn2x
 
Bitfield< 31 > cu3
 
Bitfield< 30 > cu2
 
Bitfield< 29 > cu1
 
Bitfield< 28 > cu0
 
Bitfield< 26 > fr
 
Bitfield< 25 > re
 
Bitfield< 24 > mx
 
Bitfield< 23 > px
 
Bitfield< 22 > bev
 
Bitfield< 21 > ts
 
Bitfield< 20 > sr
 
Bitfield< 19 > nmi
 
Bitfield< 15, 10 > ipl
 
Bitfield< 14 > im6
 
Bitfield< 13 > im5
 
Bitfield< 12 > im4
 
Bitfield< 11 > im3
 
Bitfield< 10 > im2
 
Bitfield< 9 > im1
 
Bitfield< 8 > im0
 
Bitfield< 6 > sx
 
Bitfield< 5 > ux
 
Bitfield< 4, 3 > ksu
 
Bitfield< 4 > um
 
Bitfield< 3 > r0
 
Bitfield< 2 > erl
 
Bitfield< 1 > exl
 
Bitfield< 0 > ie
 
 ipti
 
Bitfield< 28, 26 > ippci
 
Bitfield< 9, 5 > vs
 
 hss
 
Bitfield< 21, 18 > eicss
 
Bitfield< 15, 12 > ess
 
Bitfield< 9, 6 > pss
 
Bitfield< 3, 0 > css
 
 ssv7
 
Bitfield< 27, 24 > ssv6
 
Bitfield< 23, 20 > ssv5
 
Bitfield< 19, 16 > ssv4
 
Bitfield< 15, 12 > ssv3
 
Bitfield< 11, 8 > ssv2
 
Bitfield< 7, 4 > ssv1
 
Bitfield< 3, 0 > ssv0
 
Bitfield< 30 > ti
 
Bitfield< 29, 28 > ce
 
Bitfield< 27 > dc
 
Bitfield< 26 > pci
 
Bitfield< 23 > iv
 
Bitfield< 22 > wp
 
Bitfield< 15, 10 > ripl
 
Bitfield< 14 > ip6
 
Bitfield< 13 > ip5
 
Bitfield< 12 > ip4
 
Bitfield< 11 > ip3
 
Bitfield< 10 > ip2
 
Bitfield< 9 > ip1
 
Bitfield< 8 > ip0
 
Bitfield< 6, 2 > excCode
 
 coOp
 
Bitfield< 23, 16 > coId
 
Bitfield< 15, 8 > procId
 
Bitfield< 7, 0 > rev
 
 exceptionBase
 
Bitfield< 9, 9 > cpuNum
 
Bitfield< 30, 28 > k23
 
Bitfield< 27, 25 > ku
 
Bitfield< 15 > be
 
Bitfield< 14, 13 > at
 
Bitfield< 12, 10 > ar
 
Bitfield< 9, 7 > mt
 
Bitfield< 3 > vi
 
Bitfield< 2, 0 > k0
 
Bitfield< 30, 25 > mmuSize
 
Bitfield< 24, 22 > is
 
Bitfield< 21, 19 > il
 
Bitfield< 18, 16 > ia
 
Bitfield< 15, 13 > ds
 
Bitfield< 12, 10 > dl
 
Bitfield< 9, 7 > da
 
Bitfield< 6 > c2
 
Bitfield< 5 > md
 
Bitfield< 4 > pc
 
Bitfield< 3 > wr
 
Bitfield< 2 > ca
 
Bitfield< 1 > ep
 
Bitfield< 0 > fp
 
Bitfield< 30, 28 > tu
 
Bitfield< 23, 20 > tl
 
Bitfield< 19, 16 > ta
 
Bitfield< 15, 12 > su
 
Bitfield< 11, 8 > ss
 
Bitfield< 7, 4 > sl
 
Bitfield< 3, 0 > sa
 
Bitfield< 10 > dspp
 
Bitfield< 7 > lpa
 
Bitfield< 6 > veic
 
Bitfield< 5 > vint
 
Bitfield< 4 > sp
 
Bitfield< 1 > sm
 
 vaddr
 
Bitfield< 2 > i
 
Bitfield< 10, 5 > event
 
Bitfield< 2 > s
 
Bitfield< 1 > k
 
Bitfield< 30 > ec
 
Bitfield< 29 > ed
 
Bitfield< 28 > et
 
Bitfield< 27 > es
 
Bitfield< 26 > ee
 
Bitfield< 25 > eb
 
 pTagLo
 
Bitfield< 7, 6 > pState
 
Bitfield< 5 > l
 
Bitfield< 0 > p
 
const int NumFloatRegs = 32
 
const std::vector< std::string > FloatRegNames
 
const int NumIntArchRegs = 32
 
const int NumMicroIntRegs = 1
 
const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs
 
const int ReturnAddrReg = 1
 
const int StackPointerReg = 2
 
const int ThreadPointerReg = 4
 
const int ReturnValueReg = 10
 
const std::vector< int > ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}
 
const int AMOTempReg = 32
 
const int SyscallNumReg = 17
 
const std::vector< std::string > IntRegNames
 
const std::map< int, CSRMetadataCSRData
 
Bitfield< 35, 34 > sxl
 
Bitfield< 33, 32 > uxl
 
Bitfield< 22 > tsr
 
Bitfield< 21 > tw
 
Bitfield< 20 > tvm
 
Bitfield< 19 > mxr
 
Bitfield< 18 > sum
 
Bitfield< 17 > mprv
 
Bitfield< 16, 15 > xs
 
Bitfield< 14, 13 > fs
 
Bitfield< 12, 11 > mpp
 
Bitfield< 8 > spp
 
Bitfield< 7 > mpie
 
Bitfield< 5 > spie
 
Bitfield< 4 > upie
 
Bitfield< 3 > mie
 
Bitfield< 1 > sie
 
Bitfield< 0 > uie
 
Bitfield< 9 > sei
 
Bitfield< 8 > uei
 
Bitfield< 7 > mti
 
Bitfield< 5 > sti
 
Bitfield< 4 > uti
 
Bitfield< 3 > msi
 
Bitfield< 1 > ssi
 
Bitfield< 0 > usi
 
const off_t SXL_OFFSET = 34
 
const off_t UXL_OFFSET = 32
 
const off_t FS_OFFSET = 13
 
const off_t FRM_OFFSET = 5
 
const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET
 
const RegVal ISA_EXT_MASK = mask(26)
 
const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a')
 
const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK
 
const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1)
 
const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET
 
const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET
 
const RegVal STATUS_TSR_MASK = 1ULL << 22
 
const RegVal STATUS_TW_MASK = 1ULL << 21
 
const RegVal STATUS_TVM_MASK = 1ULL << 20
 
const RegVal STATUS_MXR_MASK = 1ULL << 19
 
const RegVal STATUS_SUM_MASK = 1ULL << 18
 
const RegVal STATUS_MPRV_MASK = 1ULL << 17
 
const RegVal STATUS_XS_MASK = 3ULL << 15
 
const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET
 
const RegVal STATUS_MPP_MASK = 3ULL << 11
 
const RegVal STATUS_SPP_MASK = 1ULL << 8
 
const RegVal STATUS_MPIE_MASK = 1ULL << 7
 
const RegVal STATUS_SPIE_MASK = 1ULL << 5
 
const RegVal STATUS_UPIE_MASK = 1ULL << 4
 
const RegVal STATUS_MIE_MASK = 1ULL << 3
 
const RegVal STATUS_SIE_MASK = 1ULL << 1
 
const RegVal STATUS_UIE_MASK = 1ULL << 0
 
const RegVal MSTATUS_MASK
 
const RegVal SSTATUS_MASK
 
const RegVal USTATUS_MASK
 
const RegVal MEI_MASK = 1ULL << 11
 
const RegVal SEI_MASK = 1ULL << 9
 
const RegVal UEI_MASK = 1ULL << 8
 
const RegVal MTI_MASK = 1ULL << 7
 
const RegVal STI_MASK = 1ULL << 5
 
const RegVal UTI_MASK = 1ULL << 4
 
const RegVal MSI_MASK = 1ULL << 3
 
const RegVal SSI_MASK = 1ULL << 1
 
const RegVal USI_MASK = 1ULL << 0
 
const RegVal MI_MASK
 
const RegVal SI_MASK
 
const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK
 
const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1
 
const RegVal FRM_MASK = 0x7
 
const std::map< int, RegValCSRMasks
 
constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
 

Typedef Documentation

◆ ExtMachInst

typedef uint64_t gem5::RiscvISA::ExtMachInst

Definition at line 54 of file types.hh.

◆ freg_t

using gem5::RiscvISA::freg_t = typedef float64_t

Definition at line 67 of file float.hh.

◆ MachInst

typedef uint32_t gem5::RiscvISA::MachInst

Definition at line 53 of file types.hh.

◆ TlbEntryTrie

Definition at line 80 of file pagetable.hh.

◆ VecElem

Definition at line 61 of file vecregs.hh.

◆ VecPredRegContainer

Definition at line 66 of file vecregs.hh.

◆ VecRegContainer

Definition at line 62 of file vecregs.hh.

Enumeration Type Documentation

◆ CSRIndex

Enumerator
CSR_USTATUS 
CSR_UIE 
CSR_UTVEC 
CSR_USCRATCH 
CSR_UEPC 
CSR_UCAUSE 
CSR_UTVAL 
CSR_UIP 
CSR_FFLAGS 
CSR_FRM 
CSR_FCSR 
CSR_CYCLE 
CSR_TIME 
CSR_INSTRET 
CSR_HPMCOUNTER03 
CSR_HPMCOUNTER04 
CSR_HPMCOUNTER05 
CSR_HPMCOUNTER06 
CSR_HPMCOUNTER07 
CSR_HPMCOUNTER08 
CSR_HPMCOUNTER09 
CSR_HPMCOUNTER10 
CSR_HPMCOUNTER11 
CSR_HPMCOUNTER12 
CSR_HPMCOUNTER13 
CSR_HPMCOUNTER14 
CSR_HPMCOUNTER15 
CSR_HPMCOUNTER16 
CSR_HPMCOUNTER17 
CSR_HPMCOUNTER18 
CSR_HPMCOUNTER19 
CSR_HPMCOUNTER20 
CSR_HPMCOUNTER21 
CSR_HPMCOUNTER22 
CSR_HPMCOUNTER23 
CSR_HPMCOUNTER24 
CSR_HPMCOUNTER25 
CSR_HPMCOUNTER26 
CSR_HPMCOUNTER27 
CSR_HPMCOUNTER28 
CSR_HPMCOUNTER29 
CSR_HPMCOUNTER30 
CSR_HPMCOUNTER31 
CSR_SSTATUS 
CSR_SEDELEG 
CSR_SIDELEG 
CSR_SIE 
CSR_STVEC 
CSR_SCOUNTEREN 
CSR_SSCRATCH 
CSR_SEPC 
CSR_SCAUSE 
CSR_STVAL 
CSR_SIP 
CSR_SATP 
CSR_MVENDORID 
CSR_MARCHID 
CSR_MIMPID 
CSR_MHARTID 
CSR_MSTATUS 
CSR_MISA 
CSR_MEDELEG 
CSR_MIDELEG 
CSR_MIE 
CSR_MTVEC 
CSR_MCOUNTEREN 
CSR_MSCRATCH 
CSR_MEPC 
CSR_MCAUSE 
CSR_MTVAL 
CSR_MIP 
CSR_PMPCFG0 
CSR_PMPCFG2 
CSR_PMPADDR00 
CSR_PMPADDR01 
CSR_PMPADDR02 
CSR_PMPADDR03 
CSR_PMPADDR04 
CSR_PMPADDR05 
CSR_PMPADDR06 
CSR_PMPADDR07 
CSR_PMPADDR08 
CSR_PMPADDR09 
CSR_PMPADDR10 
CSR_PMPADDR11 
CSR_PMPADDR12 
CSR_PMPADDR13 
CSR_PMPADDR14 
CSR_PMPADDR15 
CSR_MCYCLE 
CSR_MINSTRET 
CSR_MHPMCOUNTER03 
CSR_MHPMCOUNTER04 
CSR_MHPMCOUNTER05 
CSR_MHPMCOUNTER06 
CSR_MHPMCOUNTER07 
CSR_MHPMCOUNTER08 
CSR_MHPMCOUNTER09 
CSR_MHPMCOUNTER10 
CSR_MHPMCOUNTER11 
CSR_MHPMCOUNTER12 
CSR_MHPMCOUNTER13 
CSR_MHPMCOUNTER14 
CSR_MHPMCOUNTER15 
CSR_MHPMCOUNTER16 
CSR_MHPMCOUNTER17 
CSR_MHPMCOUNTER18 
CSR_MHPMCOUNTER19 
CSR_MHPMCOUNTER20 
CSR_MHPMCOUNTER21 
CSR_MHPMCOUNTER22 
CSR_MHPMCOUNTER23 
CSR_MHPMCOUNTER24 
CSR_MHPMCOUNTER25 
CSR_MHPMCOUNTER26 
CSR_MHPMCOUNTER27 
CSR_MHPMCOUNTER28 
CSR_MHPMCOUNTER29 
CSR_MHPMCOUNTER30 
CSR_MHPMCOUNTER31 
CSR_MHPMEVENT03 
CSR_MHPMEVENT04 
CSR_MHPMEVENT05 
CSR_MHPMEVENT06 
CSR_MHPMEVENT07 
CSR_MHPMEVENT08 
CSR_MHPMEVENT09 
CSR_MHPMEVENT10 
CSR_MHPMEVENT11 
CSR_MHPMEVENT12 
CSR_MHPMEVENT13 
CSR_MHPMEVENT14 
CSR_MHPMEVENT15 
CSR_MHPMEVENT16 
CSR_MHPMEVENT17 
CSR_MHPMEVENT18 
CSR_MHPMEVENT19 
CSR_MHPMEVENT20 
CSR_MHPMEVENT21 
CSR_MHPMEVENT22 
CSR_MHPMEVENT23 
CSR_MHPMEVENT24 
CSR_MHPMEVENT25 
CSR_MHPMEVENT26 
CSR_MHPMEVENT27 
CSR_MHPMEVENT28 
CSR_MHPMEVENT29 
CSR_MHPMEVENT30 
CSR_MHPMEVENT31 
CSR_TSELECT 
CSR_TDATA1 
CSR_TDATA2 
CSR_TDATA3 
CSR_DCSR 
CSR_DPC 
CSR_DSCRATCH 

Definition at line 193 of file misc.hh.

◆ ExceptionCode

Enumerator
INST_ADDR_MISALIGNED 
INST_ACCESS 
INST_ILLEGAL 
BREAKPOINT 
LOAD_ADDR_MISALIGNED 
LOAD_ACCESS 
STORE_ADDR_MISALIGNED 
AMO_ADDR_MISALIGNED 
STORE_ACCESS 
AMO_ACCESS 
ECALL_USER 
ECALL_SUPER 
ECALL_MACHINE 
INST_PAGE 
LOAD_PAGE 
STORE_PAGE 
AMO_PAGE 
INT_SOFTWARE_USER 
INT_SOFTWARE_SUPER 
INT_SOFTWARE_MACHINE 
INT_TIMER_USER 
INT_TIMER_SUPER 
INT_TIMER_MACHINE 
INT_EXT_USER 
INT_EXT_SUPER 
INT_EXT_MACHINE 
NumInterruptTypes 

Definition at line 67 of file faults.hh.

◆ FloatException

Enumerator
FloatInexact 
FloatUnderflow 
FloatOverflow 
FloatDivZero 
FloatInvalid 

Definition at line 49 of file faults.hh.

◆ FPUStatus

Enumerator
OFF 
INITIAL 
CLEAN 
DIRTY 

Definition at line 59 of file isa.hh.

◆ MiscRegIndex

Enumerator
MISCREG_PRV 
MISCREG_ISA 
MISCREG_VENDORID 
MISCREG_ARCHID 
MISCREG_IMPID 
MISCREG_HARTID 
MISCREG_STATUS 
MISCREG_IP 
MISCREG_IE 
MISCREG_CYCLE 
MISCREG_TIME 
MISCREG_INSTRET 
MISCREG_HPMCOUNTER03 
MISCREG_HPMCOUNTER04 
MISCREG_HPMCOUNTER05 
MISCREG_HPMCOUNTER06 
MISCREG_HPMCOUNTER07 
MISCREG_HPMCOUNTER08 
MISCREG_HPMCOUNTER09 
MISCREG_HPMCOUNTER10 
MISCREG_HPMCOUNTER11 
MISCREG_HPMCOUNTER12 
MISCREG_HPMCOUNTER13 
MISCREG_HPMCOUNTER14 
MISCREG_HPMCOUNTER15 
MISCREG_HPMCOUNTER16 
MISCREG_HPMCOUNTER17 
MISCREG_HPMCOUNTER18 
MISCREG_HPMCOUNTER19 
MISCREG_HPMCOUNTER20 
MISCREG_HPMCOUNTER21 
MISCREG_HPMCOUNTER22 
MISCREG_HPMCOUNTER23 
MISCREG_HPMCOUNTER24 
MISCREG_HPMCOUNTER25 
MISCREG_HPMCOUNTER26 
MISCREG_HPMCOUNTER27 
MISCREG_HPMCOUNTER28 
MISCREG_HPMCOUNTER29 
MISCREG_HPMCOUNTER30 
MISCREG_HPMCOUNTER31 
MISCREG_HPMEVENT03 
MISCREG_HPMEVENT04 
MISCREG_HPMEVENT05 
MISCREG_HPMEVENT06 
MISCREG_HPMEVENT07 
MISCREG_HPMEVENT08 
MISCREG_HPMEVENT09 
MISCREG_HPMEVENT10 
MISCREG_HPMEVENT11 
MISCREG_HPMEVENT12 
MISCREG_HPMEVENT13 
MISCREG_HPMEVENT14 
MISCREG_HPMEVENT15 
MISCREG_HPMEVENT16 
MISCREG_HPMEVENT17 
MISCREG_HPMEVENT18 
MISCREG_HPMEVENT19 
MISCREG_HPMEVENT20 
MISCREG_HPMEVENT21 
MISCREG_HPMEVENT22 
MISCREG_HPMEVENT23 
MISCREG_HPMEVENT24 
MISCREG_HPMEVENT25 
MISCREG_HPMEVENT26 
MISCREG_HPMEVENT27 
MISCREG_HPMEVENT28 
MISCREG_HPMEVENT29 
MISCREG_HPMEVENT30 
MISCREG_HPMEVENT31 
MISCREG_TSELECT 
MISCREG_TDATA1 
MISCREG_TDATA2 
MISCREG_TDATA3 
MISCREG_DCSR 
MISCREG_DPC 
MISCREG_DSCRATCH 
MISCREG_MEDELEG 
MISCREG_MIDELEG 
MISCREG_MTVEC 
MISCREG_MCOUNTEREN 
MISCREG_MSCRATCH 
MISCREG_MEPC 
MISCREG_MCAUSE 
MISCREG_MTVAL 
MISCREG_PMPCFG0 
MISCREG_PMPCFG2 
MISCREG_PMPADDR00 
MISCREG_PMPADDR01 
MISCREG_PMPADDR02 
MISCREG_PMPADDR03 
MISCREG_PMPADDR04 
MISCREG_PMPADDR05 
MISCREG_PMPADDR06 
MISCREG_PMPADDR07 
MISCREG_PMPADDR08 
MISCREG_PMPADDR09 
MISCREG_PMPADDR10 
MISCREG_PMPADDR11 
MISCREG_PMPADDR12 
MISCREG_PMPADDR13 
MISCREG_PMPADDR14 
MISCREG_PMPADDR15 
MISCREG_SEDELEG 
MISCREG_SIDELEG 
MISCREG_STVEC 
MISCREG_SCOUNTEREN 
MISCREG_SSCRATCH 
MISCREG_SEPC 
MISCREG_SCAUSE 
MISCREG_STVAL 
MISCREG_SATP 
MISCREG_UTVEC 
MISCREG_USCRATCH 
MISCREG_UEPC 
MISCREG_UCAUSE 
MISCREG_UTVAL 
MISCREG_FFLAGS 
MISCREG_FRM 
NUM_MISCREGS 

Definition at line 63 of file misc.hh.

◆ PrivilegeMode

Enumerator
PRV_U 
PRV_S 
PRV_M 

Definition at line 52 of file isa.hh.

Function Documentation

◆ BitUnion32()

gem5::RiscvISA::BitUnion32 ( IndexReg  )

◆ BitUnion64() [1/3]

gem5::RiscvISA::BitUnion64 ( PTESv39  )

◆ BitUnion64() [2/3]

gem5::RiscvISA::BitUnion64 ( SATP  )

◆ BitUnion64() [3/3]

gem5::RiscvISA::BitUnion64 ( STATUS  )

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10, accessible at www.riscv.org.

in Figure 3.7. The main register that uses these fields is the MSTATUS register, which is shadowed by two others accessible at lower privilege levels (SSTATUS and USTATUS) that can't see the fields for higher privileges.

◆ boxF32()

static constexpr uint64_t gem5::RiscvISA::boxF32 ( uint32_t  v)
staticconstexpr

Definition at line 80 of file float.hh.

References mask, and v.

Referenced by freg().

◆ EndBitUnion() [1/28]

gem5::RiscvISA::EndBitUnion ( CacheErrReg  )

◆ EndBitUnion() [2/28]

gem5::RiscvISA::EndBitUnion ( CauseReg  )

◆ EndBitUnion() [3/28]

gem5::RiscvISA::EndBitUnion ( Config1Reg  )

◆ EndBitUnion() [4/28]

gem5::RiscvISA::EndBitUnion ( Config2Reg  )

◆ EndBitUnion() [5/28]

gem5::RiscvISA::EndBitUnion ( Config3Reg  )

◆ EndBitUnion() [6/28]

gem5::RiscvISA::EndBitUnion ( ConfigReg  )

◆ EndBitUnion() [7/28]

gem5::RiscvISA::EndBitUnion ( ContextReg  )

◆ EndBitUnion() [8/28]

gem5::RiscvISA::EndBitUnion ( EBaseReg  )

◆ EndBitUnion() [9/28]

gem5::RiscvISA::EndBitUnion ( EntryHiReg  )

◆ EndBitUnion() [10/28]

gem5::RiscvISA::EndBitUnion ( EntryLoReg  )

◆ EndBitUnion() [11/28]

gem5::RiscvISA::EndBitUnion ( HWREnaReg  )

◆ EndBitUnion() [12/28]

gem5::RiscvISA::EndBitUnion ( IndexReg  )

◆ EndBitUnion() [13/28]

gem5::RiscvISA::EndBitUnion ( IntCtlReg  )

◆ EndBitUnion() [14/28]

gem5::RiscvISA::EndBitUnion ( INTERRUPT  ) const

◆ EndBitUnion() [15/28]

gem5::RiscvISA::EndBitUnion ( PageGrainReg  )

◆ EndBitUnion() [16/28]

gem5::RiscvISA::EndBitUnion ( PageMaskReg  )

◆ EndBitUnion() [17/28]

gem5::RiscvISA::EndBitUnion ( PerfCntCtlReg  )

◆ EndBitUnion() [18/28]

gem5::RiscvISA::EndBitUnion ( PRIdReg  )

◆ EndBitUnion() [19/28]

gem5::RiscvISA::EndBitUnion ( PTESv39  )

◆ EndBitUnion() [20/28]

gem5::RiscvISA::EndBitUnion ( RandomReg  )

◆ EndBitUnion() [21/28]

gem5::RiscvISA::EndBitUnion ( SATP  )

Definition at line 49 of file pagetable.hh.

◆ EndBitUnion() [22/28]

gem5::RiscvISA::EndBitUnion ( SRSCtlReg  )

◆ EndBitUnion() [23/28]

gem5::RiscvISA::EndBitUnion ( SRSMapReg  )

◆ EndBitUnion() [24/28]

gem5::RiscvISA::EndBitUnion ( STATUS  )

These fields are specified in the RISC-V Instruction Set Manual, Volume II, v1.10 in Figures 3.11 and 3.12, accessible at www.riscv.org.

Both the MIP and MIE registers have the same fields, so accesses to either should use this bit union.

◆ EndBitUnion() [25/28]

gem5::RiscvISA::EndBitUnion ( StatusReg  )

◆ EndBitUnion() [26/28]

gem5::RiscvISA::EndBitUnion ( WatchHiReg  )

◆ EndBitUnion() [27/28]

gem5::RiscvISA::EndBitUnion ( WatchLoReg  )

◆ EndBitUnion() [28/28]

gem5::RiscvISA::EndBitUnion ( WiredReg  )

◆ EndSubBitUnion() [1/3]

gem5::RiscvISA::EndSubBitUnion ( cu  )

◆ EndSubBitUnion() [2/3]

gem5::RiscvISA::EndSubBitUnion ( im  )

◆ EndSubBitUnion() [3/3]

gem5::RiscvISA::EndSubBitUnion ( ip  )

◆ f32() [1/2]

static constexpr float32_t gem5::RiscvISA::f32 ( freg_t  r)
staticconstexpr

Definition at line 85 of file float.hh.

References r, and unboxF32().

◆ f32() [2/2]

static constexpr float32_t gem5::RiscvISA::f32 ( uint32_t  v)
staticconstexpr

Definition at line 83 of file float.hh.

References v.

◆ f64() [1/2]

static constexpr float64_t gem5::RiscvISA::f64 ( freg_t  r)
staticconstexpr

Definition at line 86 of file float.hh.

References r.

◆ f64() [2/2]

static constexpr float64_t gem5::RiscvISA::f64 ( uint64_t  v)
staticconstexpr

Definition at line 84 of file float.hh.

References v.

◆ freg() [1/3]

static constexpr freg_t gem5::RiscvISA::freg ( float32_t  f)
staticconstexpr

Definition at line 89 of file float.hh.

References boxF32(), and gem5::ArmISA::f.

◆ freg() [2/3]

static constexpr freg_t gem5::RiscvISA::freg ( float64_t  f)
staticconstexpr

Definition at line 90 of file float.hh.

References gem5::ArmISA::f.

◆ freg() [3/3]

static constexpr freg_t gem5::RiscvISA::freg ( uint_fast16_t  f)
staticconstexpr

Definition at line 91 of file float.hh.

References gem5::ArmISA::f.

◆ globalClearExclusive()

template<class XC >
void gem5::RiscvISA::globalClearExclusive ( XC *  xc)
inline

Definition at line 139 of file locked_mem.hh.

◆ handleLockedRead()

template<class XC >
void gem5::RiscvISA::handleLockedRead ( XC *  xc,
const RequestPtr req 
)
inline

Definition at line 89 of file locked_mem.hh.

References DPRINTF, and locked_addrs.

◆ handleLockedSnoop()

template<class XC >
void gem5::RiscvISA::handleLockedSnoop ( XC *  xc,
PacketPtr  pkt,
Addr  cacheBlockMask 
)
inline

Definition at line 75 of file locked_mem.hh.

References DPRINTF, gem5::Packet::getAddr(), and locked_addrs.

◆ handleLockedSnoopHit()

template<class XC >
void gem5::RiscvISA::handleLockedSnoopHit ( XC *  xc)
inline

Definition at line 99 of file locked_mem.hh.

◆ handleLockedWrite()

template<class XC >
bool gem5::RiscvISA::handleLockedWrite ( XC *  xc,
const RequestPtr req,
Addr  cacheBlockMask 
)
inline

Definition at line 103 of file locked_mem.hh.

References gem5::curTick(), DPRINTF, locked_addrs, warn, and WARN_FAILURE.

◆ isquietnan()

template<typename T >
bool gem5::RiscvISA::isquietnan ( val)
inline

Definition at line 66 of file utility.hh.

◆ isquietnan< double >()

template<>
bool gem5::RiscvISA::isquietnan< double > ( double  val)
inline

Definition at line 79 of file utility.hh.

References gem5::X86ISA::val.

◆ isquietnan< float >()

template<>
bool gem5::RiscvISA::isquietnan< float > ( float  val)
inline

Definition at line 72 of file utility.hh.

References gem5::X86ISA::val.

◆ issignalingnan()

template<typename T >
bool gem5::RiscvISA::issignalingnan ( val)
inline

Definition at line 86 of file utility.hh.

◆ issignalingnan< double >()

template<>
bool gem5::RiscvISA::issignalingnan< double > ( double  val)
inline

Definition at line 99 of file utility.hh.

References gem5::X86ISA::val.

◆ issignalingnan< float >()

template<>
bool gem5::RiscvISA::issignalingnan< float > ( float  val)
inline

Definition at line 92 of file utility.hh.

References gem5::X86ISA::val.

◆ registerName()

std::string gem5::RiscvISA::registerName ( RegId  reg)
inline

◆ SubBitUnion() [1/2]

gem5::RiscvISA::SubBitUnion ( im  ,
15  ,
 
)

◆ SubBitUnion() [2/2]

gem5::RiscvISA::SubBitUnion ( ip  ,
15  ,
 
)

◆ unameFunc32()

static SyscallReturn gem5::RiscvISA::unameFunc32 ( SyscallDesc desc,
ThreadContext tc,
VPtr< Linux::utsname name 
)
static

Target uname() handler.

Definition at line 113 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

◆ unameFunc64()

static SyscallReturn gem5::RiscvISA::unameFunc64 ( SyscallDesc desc,
ThreadContext tc,
VPtr< Linux::utsname name 
)
static

Target uname() handler.

Definition at line 98 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

◆ unboxF32()

static constexpr uint32_t gem5::RiscvISA::unboxF32 ( uint64_t  v)
staticconstexpr

Definition at line 71 of file float.hh.

References gem5::bits(), mask, and v.

Referenced by f32().

Variable Documentation

◆ a

Bitfield<6> gem5::RiscvISA::a

Definition at line 69 of file pagetable.hh.

◆ AMOTempReg

const int gem5::RiscvISA::AMOTempReg = 32

Definition at line 68 of file int.hh.

◆ ar

Bitfield<12, 10> gem5::RiscvISA::ar

Definition at line 225 of file pra_constants.hh.

◆ ArgumentRegs

const std::vector<int> gem5::RiscvISA::ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}

◆ aseDn

Bitfield<12, 8> gem5::RiscvISA::aseDn

Definition at line 83 of file pra_constants.hh.

◆ aseUp

gem5::RiscvISA::aseUp

Definition at line 79 of file pra_constants.hh.

◆ asid

Bitfield< 23, 16 > gem5::RiscvISA::asid

Definition at line 47 of file pagetable.hh.

Referenced by gem5::buildKey().

◆ at

Bitfield<14, 13> gem5::RiscvISA::at

Definition at line 224 of file pra_constants.hh.

◆ badVPN2

Bitfield<22, 4> gem5::RiscvISA::badVPN2

Definition at line 67 of file pra_constants.hh.

◆ be

Bitfield<15> gem5::RiscvISA::be

Definition at line 223 of file pra_constants.hh.

◆ bev

Bitfield<22> gem5::RiscvISA::bev

Definition at line 117 of file pra_constants.hh.

◆ c

Bitfield<5, 3> gem5::RiscvISA::c

Definition at line 59 of file pra_constants.hh.

Referenced by gem5::RiscvISA::PCState::compressed().

◆ c2

Bitfield<6> gem5::RiscvISA::c2

Definition at line 241 of file pra_constants.hh.

◆ ca

Bitfield<2> gem5::RiscvISA::ca

Definition at line 245 of file pra_constants.hh.

◆ ce

Bitfield<29, 28> gem5::RiscvISA::ce

Definition at line 180 of file pra_constants.hh.

◆ coId

Bitfield<23, 16> gem5::RiscvISA::coId

Definition at line 205 of file pra_constants.hh.

◆ coOp

gem5::RiscvISA::coOp

Definition at line 204 of file pra_constants.hh.

◆ cpuNum

Bitfield<9, 9> gem5::RiscvISA::cpuNum

Definition at line 215 of file pra_constants.hh.

◆ CSRData

const std::map<int, CSRMetadata> gem5::RiscvISA::CSRData

◆ CSRMasks

const std::map<int, RegVal> gem5::RiscvISA::CSRMasks

◆ css

Bitfield<3, 0> gem5::RiscvISA::css

Definition at line 163 of file pra_constants.hh.

◆ cu0

Bitfield<28> gem5::RiscvISA::cu0

Definition at line 110 of file pra_constants.hh.

◆ cu1

Bitfield<29> gem5::RiscvISA::cu1

Definition at line 109 of file pra_constants.hh.

◆ cu2

Bitfield<30> gem5::RiscvISA::cu2

Definition at line 108 of file pra_constants.hh.

◆ cu3

Bitfield<31> gem5::RiscvISA::cu3

Definition at line 106 of file pra_constants.hh.

◆ d

Bitfield< 2 > gem5::RiscvISA::d

Definition at line 68 of file pagetable.hh.

◆ da

Bitfield<9, 7> gem5::RiscvISA::da

Definition at line 240 of file pra_constants.hh.

◆ dc

Bitfield<27> gem5::RiscvISA::dc

Definition at line 181 of file pra_constants.hh.

◆ dl

Bitfield<12, 10> gem5::RiscvISA::dl

Definition at line 239 of file pra_constants.hh.

◆ ds

Bitfield<15, 13> gem5::RiscvISA::ds

Definition at line 238 of file pra_constants.hh.

◆ dspp

Bitfield<10> gem5::RiscvISA::dspp

Definition at line 265 of file pra_constants.hh.

◆ eb

Bitfield<25> gem5::RiscvISA::eb

Definition at line 315 of file pra_constants.hh.

◆ ec

Bitfield<30> gem5::RiscvISA::ec

Definition at line 310 of file pra_constants.hh.

◆ ed

Bitfield<29> gem5::RiscvISA::ed

Definition at line 311 of file pra_constants.hh.

◆ ee

Bitfield<26> gem5::RiscvISA::ee

Definition at line 314 of file pra_constants.hh.

◆ eicss

Bitfield<21, 18> gem5::RiscvISA::eicss

Definition at line 157 of file pra_constants.hh.

◆ elpa

Bitfield<29> gem5::RiscvISA::elpa

Definition at line 80 of file pra_constants.hh.

◆ ep

Bitfield<1> gem5::RiscvISA::ep

Definition at line 246 of file pra_constants.hh.

◆ erl

Bitfield<2> gem5::RiscvISA::erl

Definition at line 140 of file pra_constants.hh.

◆ es

Bitfield<27> gem5::RiscvISA::es

Definition at line 313 of file pra_constants.hh.

◆ esp

Bitfield<28> gem5::RiscvISA::esp

Definition at line 81 of file pra_constants.hh.

◆ ess

Bitfield<15, 12> gem5::RiscvISA::ess

Definition at line 159 of file pra_constants.hh.

◆ et

Bitfield<28> gem5::RiscvISA::et

Definition at line 312 of file pra_constants.hh.

◆ event

Bitfield<10, 5> gem5::RiscvISA::event

Definition at line 300 of file pra_constants.hh.

◆ excCode

Bitfield<6, 2> gem5::RiscvISA::excCode

Definition at line 199 of file pra_constants.hh.

◆ exceptionBase

gem5::RiscvISA::exceptionBase

Definition at line 213 of file pra_constants.hh.

◆ exl

Bitfield< 0 > gem5::RiscvISA::exl

Definition at line 141 of file pra_constants.hh.

◆ FFLAGS_MASK

const RegVal gem5::RiscvISA::FFLAGS_MASK = (1 << FRM_OFFSET) - 1

Definition at line 644 of file misc.hh.

◆ fill

Bitfield< 61, 40 > gem5::RiscvISA::fill

Definition at line 57 of file pra_constants.hh.

◆ FloatRegNames

const std::vector<std::string> gem5::RiscvISA::FloatRegNames
Initial value:
= {
"ft0", "ft1", "ft2", "ft3",
"ft4", "ft5", "ft6", "ft7",
"fs0", "fs1", "fa0", "fa1",
"fa2", "fa3", "fa4", "fa5",
"fa6", "fa7", "fs2", "fs3",
"fs4", "fs5", "fs6", "fs7",
"fs8", "fs9", "fs10", "fs11",
"ft8", "ft9", "ft10", "ft11"
}

Definition at line 95 of file float.hh.

Referenced by registerName().

◆ fp

Bitfield<0> gem5::RiscvISA::fp

Definition at line 247 of file pra_constants.hh.

◆ fr

Bitfield<26> gem5::RiscvISA::fr

Definition at line 113 of file pra_constants.hh.

◆ FRM_MASK

const RegVal gem5::RiscvISA::FRM_MASK = 0x7

Definition at line 645 of file misc.hh.

◆ FRM_OFFSET

const off_t gem5::RiscvISA::FRM_OFFSET = 5

Definition at line 581 of file misc.hh.

◆ fs

Bitfield<14, 13> gem5::RiscvISA::fs

Definition at line 548 of file misc.hh.

◆ FS_OFFSET

const off_t gem5::RiscvISA::FS_OFFSET = 13

Definition at line 580 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::clear().

◆ g

Bitfield< 30 > gem5::RiscvISA::g

Definition at line 70 of file pagetable.hh.

◆ hss

gem5::RiscvISA::hss

Definition at line 155 of file pra_constants.hh.

◆ i

Bitfield< 2 > gem5::RiscvISA::i

◆ ia

Bitfield<18, 16> gem5::RiscvISA::ia

Definition at line 237 of file pra_constants.hh.

◆ ie

Bitfield< 4 > gem5::RiscvISA::ie

Definition at line 142 of file pra_constants.hh.

◆ il

Bitfield<21, 19> gem5::RiscvISA::il

Definition at line 236 of file pra_constants.hh.

◆ im0

Bitfield<8> gem5::RiscvISA::im0

Definition at line 132 of file pra_constants.hh.

◆ im1

Bitfield<9> gem5::RiscvISA::im1

Definition at line 131 of file pra_constants.hh.

◆ im2

Bitfield<10> gem5::RiscvISA::im2

Definition at line 130 of file pra_constants.hh.

◆ im3

Bitfield<11> gem5::RiscvISA::im3

Definition at line 129 of file pra_constants.hh.

◆ im4

Bitfield<12> gem5::RiscvISA::im4

Definition at line 128 of file pra_constants.hh.

◆ im5

Bitfield<13> gem5::RiscvISA::im5

Definition at line 127 of file pra_constants.hh.

◆ im6

Bitfield<14> gem5::RiscvISA::im6

Definition at line 126 of file pra_constants.hh.

◆ impl

Bitfield< 4, 3 > gem5::RiscvISA::impl

Definition at line 93 of file pra_constants.hh.

◆ index

Bitfield< 22, 0 > gem5::RiscvISA::index

◆ IntRegNames

const std::vector<std::string> gem5::RiscvISA::IntRegNames
Initial value:
= {
"zero", "ra", "sp", "gp",
"tp", "t0", "t1", "t2",
"s0", "s1", "a0", "a1",
"a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3",
"s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11",
"t3", "t4", "t5", "t6"
}

Definition at line 72 of file int.hh.

Referenced by registerName().

◆ ip0

Bitfield<8> gem5::RiscvISA::ip0

Definition at line 196 of file pra_constants.hh.

◆ ip1

Bitfield<9> gem5::RiscvISA::ip1

Definition at line 195 of file pra_constants.hh.

◆ ip2

Bitfield<10> gem5::RiscvISA::ip2

Definition at line 194 of file pra_constants.hh.

◆ ip3

Bitfield<11> gem5::RiscvISA::ip3

Definition at line 193 of file pra_constants.hh.

◆ ip4

Bitfield<12> gem5::RiscvISA::ip4

Definition at line 192 of file pra_constants.hh.

◆ ip5

Bitfield<13> gem5::RiscvISA::ip5

Definition at line 191 of file pra_constants.hh.

◆ ip6

Bitfield<14> gem5::RiscvISA::ip6

Definition at line 190 of file pra_constants.hh.

◆ ipl

Bitfield<15, 10> gem5::RiscvISA::ipl

Definition at line 123 of file pra_constants.hh.

◆ ippci

Bitfield<28, 26> gem5::RiscvISA::ippci

Definition at line 147 of file pra_constants.hh.

◆ ipti

gem5::RiscvISA::ipti

Definition at line 146 of file pra_constants.hh.

◆ is

Bitfield<24, 22> gem5::RiscvISA::is

Definition at line 235 of file pra_constants.hh.

◆ ISA_EXT_C_MASK

const RegVal gem5::RiscvISA::ISA_EXT_C_MASK = 1UL << ('c' - 'a')

Definition at line 585 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::readMiscReg(), and gem5::RiscvISA::ISA::setMiscReg().

◆ ISA_EXT_MASK

const RegVal gem5::RiscvISA::ISA_EXT_MASK = mask(26)

Definition at line 584 of file misc.hh.

◆ ISA_MXL_MASK

const RegVal gem5::RiscvISA::ISA_MXL_MASK = 3ULL << MXL_OFFSET

Definition at line 583 of file misc.hh.

◆ iv

Bitfield<23> gem5::RiscvISA::iv

Definition at line 184 of file pra_constants.hh.

◆ k

Bitfield<1> gem5::RiscvISA::k

Definition at line 304 of file pra_constants.hh.

◆ k0

Bitfield<2, 0> gem5::RiscvISA::k0

Definition at line 229 of file pra_constants.hh.

◆ k23

Bitfield<30, 28> gem5::RiscvISA::k23

Definition at line 220 of file pra_constants.hh.

◆ ksu

Bitfield<4, 3> gem5::RiscvISA::ksu

Definition at line 137 of file pra_constants.hh.

◆ ku

Bitfield<27, 25> gem5::RiscvISA::ku

Definition at line 221 of file pra_constants.hh.

◆ l

Bitfield<5> gem5::RiscvISA::l

Definition at line 323 of file pra_constants.hh.

◆ LEVEL_BITS

const Addr gem5::RiscvISA::LEVEL_BITS = 9

◆ LEVEL_MASK

const Addr gem5::RiscvISA::LEVEL_MASK = (1 << LEVEL_BITS) - 1

◆ locked_addrs

std::unordered_map< int, std::stack< Addr > > gem5::RiscvISA::locked_addrs

◆ lpa

Bitfield<7> gem5::RiscvISA::lpa

Definition at line 267 of file pra_constants.hh.

◆ mask

Bitfield< 11, 3 > gem5::RiscvISA::mask

◆ maskx

Bitfield<12, 11> gem5::RiscvISA::maskx

Definition at line 74 of file pra_constants.hh.

◆ md

Bitfield<5> gem5::RiscvISA::md

Definition at line 242 of file pra_constants.hh.

◆ MEI_MASK

const RegVal gem5::RiscvISA::MEI_MASK = 1ULL << 11

Definition at line 628 of file misc.hh.

◆ MI_MASK

const RegVal gem5::RiscvISA::MI_MASK
Initial value:

Definition at line 637 of file misc.hh.

◆ mie

Bitfield<3> gem5::RiscvISA::mie

Definition at line 554 of file misc.hh.

◆ MISA_MASK

const RegVal gem5::RiscvISA::MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK

Definition at line 586 of file misc.hh.

◆ MiscRegNames

const GEM5_VAR_USED std::array<const char *, NUM_MISCREGS> gem5::RiscvISA::MiscRegNames

◆ mmuSize

Bitfield<30, 25> gem5::RiscvISA::mmuSize

Definition at line 234 of file pra_constants.hh.

◆ mode

gem5::RiscvISA::mode

◆ mpie

Bitfield<7> gem5::RiscvISA::mpie

Definition at line 551 of file misc.hh.

◆ mpp

Bitfield<12, 11> gem5::RiscvISA::mpp

Definition at line 549 of file misc.hh.

◆ mprv

Bitfield<17> gem5::RiscvISA::mprv

Definition at line 546 of file misc.hh.

◆ msi

Bitfield<3> gem5::RiscvISA::msi

Definition at line 572 of file misc.hh.

◆ MSI_MASK

const RegVal gem5::RiscvISA::MSI_MASK = 1ULL << 3

Definition at line 634 of file misc.hh.

◆ MSTATUS_MASK

const RegVal gem5::RiscvISA::MSTATUS_MASK

◆ mt

Bitfield< 2 > gem5::RiscvISA::mt

Definition at line 226 of file pra_constants.hh.

◆ mti

Bitfield<7> gem5::RiscvISA::mti

Definition at line 569 of file misc.hh.

◆ MTI_MASK

const RegVal gem5::RiscvISA::MTI_MASK = 1ULL << 7

Definition at line 631 of file misc.hh.

◆ mx

Bitfield<24> gem5::RiscvISA::mx

Definition at line 115 of file pra_constants.hh.

◆ mxr

Bitfield<19> gem5::RiscvISA::mxr

Definition at line 544 of file misc.hh.

◆ nmi

Bitfield<19> gem5::RiscvISA::nmi

Definition at line 120 of file pra_constants.hh.

◆ NumFloatRegs

const int gem5::RiscvISA::NumFloatRegs = 32

◆ NumIntArchRegs

const int gem5::RiscvISA::NumIntArchRegs = 32

Definition at line 58 of file int.hh.

Referenced by registerName().

◆ NumIntRegs

const int gem5::RiscvISA::NumIntRegs = NumIntArchRegs + NumMicroIntRegs

Definition at line 60 of file int.hh.

Referenced by gem5::RiscvISA::ISA::copyRegsFrom(), and gem5::RiscvISA::ISA::ISA().

◆ NumMicroIntRegs

const int gem5::RiscvISA::NumMicroIntRegs = 1

Definition at line 59 of file int.hh.

◆ NumVecElemPerVecReg

constexpr unsigned gem5::RiscvISA::NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
constexpr

Definition at line 63 of file vecregs.hh.

◆ p

Bitfield<0> gem5::RiscvISA::p

Definition at line 326 of file pra_constants.hh.

Referenced by gem5::RiscvISA::BareMetal::BareMetal().

◆ PageBytes

const Addr gem5::RiscvISA::PageBytes = 1ULL << PageShift

Definition at line 54 of file page_size.hh.

◆ PageShift

const Addr gem5::RiscvISA::PageShift = 12

◆ pc

Bitfield<4> gem5::RiscvISA::pc

◆ pci

Bitfield<26> gem5::RiscvISA::pci

Definition at line 182 of file pra_constants.hh.

◆ perm

Bitfield<3, 1> gem5::RiscvISA::perm

◆ pfn

Bitfield<29, 6> gem5::RiscvISA::pfn

Definition at line 58 of file pra_constants.hh.

◆ ppn

gem5::RiscvISA::ppn

◆ ppn0

Bitfield<18, 10> gem5::RiscvISA::ppn0

Definition at line 67 of file pagetable.hh.

◆ ppn1

Bitfield<27, 19> gem5::RiscvISA::ppn1

Definition at line 66 of file pagetable.hh.

◆ ppn2

Bitfield<53, 28> gem5::RiscvISA::ppn2

Definition at line 65 of file pagetable.hh.

◆ procId

Bitfield<15, 8> gem5::RiscvISA::procId

Definition at line 206 of file pra_constants.hh.

◆ pss

Bitfield<9, 6> gem5::RiscvISA::pss

Definition at line 161 of file pra_constants.hh.

◆ pState

Bitfield<7, 6> gem5::RiscvISA::pState

Definition at line 322 of file pra_constants.hh.

◆ pTagLo

gem5::RiscvISA::pTagLo

Definition at line 321 of file pra_constants.hh.

◆ pteBase

gem5::RiscvISA::pteBase

Definition at line 66 of file pra_constants.hh.

◆ px

Bitfield<23> gem5::RiscvISA::px

Definition at line 116 of file pra_constants.hh.

◆ r

Bitfield< 1 > gem5::RiscvISA::r

◆ r0

Bitfield<3> gem5::RiscvISA::r0

Definition at line 139 of file pra_constants.hh.

◆ random

gem5::RiscvISA::random

Definition at line 53 of file pra_constants.hh.

◆ re

Bitfield<25> gem5::RiscvISA::re

Definition at line 114 of file pra_constants.hh.

◆ ReturnAddrReg

const int gem5::RiscvISA::ReturnAddrReg = 1

Definition at line 63 of file int.hh.

◆ ReturnValueReg

const int gem5::RiscvISA::ReturnValueReg = 10

◆ rev

Bitfield<7, 0> gem5::RiscvISA::rev

Definition at line 207 of file pra_constants.hh.

◆ ripl

Bitfield<15, 10> gem5::RiscvISA::ripl

Definition at line 187 of file pra_constants.hh.

◆ s

Bitfield<2> gem5::RiscvISA::s

Definition at line 303 of file pra_constants.hh.

◆ sa

Bitfield<3, 0> gem5::RiscvISA::sa

Definition at line 259 of file pra_constants.hh.

◆ sei

Bitfield<9> gem5::RiscvISA::sei

Definition at line 567 of file misc.hh.

◆ SEI_MASK

const RegVal gem5::RiscvISA::SEI_MASK = 1ULL << 9

Definition at line 629 of file misc.hh.

◆ SI_MASK

const RegVal gem5::RiscvISA::SI_MASK
Initial value:

Definition at line 640 of file misc.hh.

◆ sie

Bitfield<1> gem5::RiscvISA::sie

Definition at line 555 of file misc.hh.

◆ sl

Bitfield<7, 4> gem5::RiscvISA::sl

Definition at line 258 of file pra_constants.hh.

◆ sm

Bitfield<1> gem5::RiscvISA::sm

Definition at line 273 of file pra_constants.hh.

◆ sp

Bitfield<4> gem5::RiscvISA::sp

Definition at line 270 of file pra_constants.hh.

◆ spie

Bitfield<5> gem5::RiscvISA::spie

Definition at line 552 of file misc.hh.

◆ spp

Bitfield<8> gem5::RiscvISA::spp

Definition at line 550 of file misc.hh.

◆ sr

Bitfield<20> gem5::RiscvISA::sr

Definition at line 119 of file pra_constants.hh.

◆ ss

Bitfield<11, 8> gem5::RiscvISA::ss

◆ ssi

Bitfield<1> gem5::RiscvISA::ssi

Definition at line 573 of file misc.hh.

◆ SSI_MASK

const RegVal gem5::RiscvISA::SSI_MASK = 1ULL << 1

Definition at line 635 of file misc.hh.

◆ SSTATUS_MASK

const RegVal gem5::RiscvISA::SSTATUS_MASK

◆ ssv0

Bitfield<3, 0> gem5::RiscvISA::ssv0

Definition at line 174 of file pra_constants.hh.

◆ ssv1

Bitfield<7, 4> gem5::RiscvISA::ssv1

Definition at line 173 of file pra_constants.hh.

◆ ssv2

Bitfield<11, 8> gem5::RiscvISA::ssv2

Definition at line 172 of file pra_constants.hh.

◆ ssv3

Bitfield<15, 12> gem5::RiscvISA::ssv3

Definition at line 171 of file pra_constants.hh.

◆ ssv4

Bitfield<19, 16> gem5::RiscvISA::ssv4

Definition at line 170 of file pra_constants.hh.

◆ ssv5

Bitfield<23, 20> gem5::RiscvISA::ssv5

Definition at line 169 of file pra_constants.hh.

◆ ssv6

Bitfield<27, 24> gem5::RiscvISA::ssv6

Definition at line 168 of file pra_constants.hh.

◆ ssv7

gem5::RiscvISA::ssv7

Definition at line 167 of file pra_constants.hh.

◆ StackPointerReg

const int gem5::RiscvISA::StackPointerReg = 2

Definition at line 64 of file int.hh.

Referenced by gem5::RiscvLinux64::archClone(), and gem5::RiscvLinux32::archClone().

◆ STATUS_FS_MASK

const RegVal gem5::RiscvISA::STATUS_FS_MASK = 3ULL << FS_OFFSET

Definition at line 598 of file misc.hh.

◆ STATUS_MIE_MASK

const RegVal gem5::RiscvISA::STATUS_MIE_MASK = 1ULL << 3

Definition at line 604 of file misc.hh.

◆ STATUS_MPIE_MASK

const RegVal gem5::RiscvISA::STATUS_MPIE_MASK = 1ULL << 7

Definition at line 601 of file misc.hh.

◆ STATUS_MPP_MASK

const RegVal gem5::RiscvISA::STATUS_MPP_MASK = 3ULL << 11

Definition at line 599 of file misc.hh.

◆ STATUS_MPRV_MASK

const RegVal gem5::RiscvISA::STATUS_MPRV_MASK = 1ULL << 17

Definition at line 596 of file misc.hh.

◆ STATUS_MXR_MASK

const RegVal gem5::RiscvISA::STATUS_MXR_MASK = 1ULL << 19

Definition at line 594 of file misc.hh.

◆ STATUS_SD_MASK

const RegVal gem5::RiscvISA::STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1)

Definition at line 588 of file misc.hh.

◆ STATUS_SIE_MASK

const RegVal gem5::RiscvISA::STATUS_SIE_MASK = 1ULL << 1

Definition at line 605 of file misc.hh.

◆ STATUS_SPIE_MASK

const RegVal gem5::RiscvISA::STATUS_SPIE_MASK = 1ULL << 5

Definition at line 602 of file misc.hh.

◆ STATUS_SPP_MASK

const RegVal gem5::RiscvISA::STATUS_SPP_MASK = 1ULL << 8

Definition at line 600 of file misc.hh.

◆ STATUS_SUM_MASK

const RegVal gem5::RiscvISA::STATUS_SUM_MASK = 1ULL << 18

Definition at line 595 of file misc.hh.

◆ STATUS_SXL_MASK

const RegVal gem5::RiscvISA::STATUS_SXL_MASK = 3ULL << SXL_OFFSET

Definition at line 589 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

◆ STATUS_TSR_MASK

const RegVal gem5::RiscvISA::STATUS_TSR_MASK = 1ULL << 22

Definition at line 591 of file misc.hh.

◆ STATUS_TVM_MASK

const RegVal gem5::RiscvISA::STATUS_TVM_MASK = 1ULL << 20

Definition at line 593 of file misc.hh.

◆ STATUS_TW_MASK

const RegVal gem5::RiscvISA::STATUS_TW_MASK = 1ULL << 21

Definition at line 592 of file misc.hh.

◆ STATUS_UIE_MASK

const RegVal gem5::RiscvISA::STATUS_UIE_MASK = 1ULL << 0

Definition at line 606 of file misc.hh.

◆ STATUS_UPIE_MASK

const RegVal gem5::RiscvISA::STATUS_UPIE_MASK = 1ULL << 4

Definition at line 603 of file misc.hh.

◆ STATUS_UXL_MASK

const RegVal gem5::RiscvISA::STATUS_UXL_MASK = 3ULL << UXL_OFFSET

Definition at line 590 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::setMiscReg().

◆ STATUS_XS_MASK

const RegVal gem5::RiscvISA::STATUS_XS_MASK = 3ULL << 15

Definition at line 597 of file misc.hh.

◆ sti

Bitfield<5> gem5::RiscvISA::sti

Definition at line 570 of file misc.hh.

◆ STI_MASK

const RegVal gem5::RiscvISA::STI_MASK = 1ULL << 5

Definition at line 632 of file misc.hh.

◆ su

Bitfield<15, 12> gem5::RiscvISA::su

Definition at line 256 of file pra_constants.hh.

◆ sum

Bitfield<18> gem5::RiscvISA::sum

◆ sx

Bitfield<6> gem5::RiscvISA::sx

Definition at line 135 of file pra_constants.hh.

◆ sxl

Bitfield<35, 34> gem5::RiscvISA::sxl

Definition at line 539 of file misc.hh.

◆ SXL_OFFSET

const off_t gem5::RiscvISA::SXL_OFFSET = 34

Definition at line 578 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::clear().

◆ SyscallNumReg

const int gem5::RiscvISA::SyscallNumReg = 17

Definition at line 70 of file int.hh.

Referenced by gem5::RiscvISA::EmuLinux::syscall().

◆ ta

Bitfield<19, 16> gem5::RiscvISA::ta

Definition at line 255 of file pra_constants.hh.

◆ ThreadPointerReg

const int gem5::RiscvISA::ThreadPointerReg = 4

Definition at line 65 of file int.hh.

Referenced by gem5::RiscvLinux64::archClone().

◆ ti

Bitfield<30> gem5::RiscvISA::ti

Definition at line 179 of file pra_constants.hh.

◆ tl

Bitfield< 0 > gem5::RiscvISA::tl

Definition at line 254 of file pra_constants.hh.

◆ ts

Bitfield< 27, 24 > gem5::RiscvISA::ts

Definition at line 118 of file pra_constants.hh.

◆ tsr

Bitfield<22> gem5::RiscvISA::tsr

Definition at line 541 of file misc.hh.

◆ tu

Bitfield<30, 28> gem5::RiscvISA::tu

Definition at line 252 of file pra_constants.hh.

◆ tvm

Bitfield<20> gem5::RiscvISA::tvm

Definition at line 543 of file misc.hh.

◆ tw

Bitfield<21> gem5::RiscvISA::tw

Definition at line 542 of file misc.hh.

◆ u

Bitfield< 3 > gem5::RiscvISA::u

Definition at line 71 of file pagetable.hh.

◆ uei

Bitfield<8> gem5::RiscvISA::uei

Definition at line 568 of file misc.hh.

◆ UEI_MASK

const RegVal gem5::RiscvISA::UEI_MASK = 1ULL << 8

Definition at line 630 of file misc.hh.

◆ UI_MASK

const RegVal gem5::RiscvISA::UI_MASK = UEI_MASK | UTI_MASK | USI_MASK

Definition at line 643 of file misc.hh.

◆ uie

Bitfield<0> gem5::RiscvISA::uie

Definition at line 556 of file misc.hh.

◆ um

Bitfield<4> gem5::RiscvISA::um

Definition at line 138 of file pra_constants.hh.

◆ upie

Bitfield<4> gem5::RiscvISA::upie

Definition at line 553 of file misc.hh.

◆ usi

Bitfield<0> gem5::RiscvISA::usi

Definition at line 574 of file misc.hh.

◆ USI_MASK

const RegVal gem5::RiscvISA::USI_MASK = 1ULL << 0

Definition at line 636 of file misc.hh.

◆ USTATUS_MASK

const RegVal gem5::RiscvISA::USTATUS_MASK

◆ uti

Bitfield<4> gem5::RiscvISA::uti

Definition at line 571 of file misc.hh.

◆ UTI_MASK

const RegVal gem5::RiscvISA::UTI_MASK = 1ULL << 4

Definition at line 633 of file misc.hh.

◆ ux

Bitfield<5> gem5::RiscvISA::ux

Definition at line 136 of file pra_constants.hh.

◆ uxl

Bitfield<33, 32> gem5::RiscvISA::uxl

Definition at line 540 of file misc.hh.

◆ UXL_OFFSET

const off_t gem5::RiscvISA::UXL_OFFSET = 32

Definition at line 579 of file misc.hh.

Referenced by gem5::RiscvISA::ISA::clear().

◆ v

Bitfield< 1 > gem5::RiscvISA::v

Definition at line 76 of file pagetable.hh.

Referenced by boxF32(), f32(), f64(), and unboxF32().

◆ vaddr

gem5::RiscvISA::vaddr

◆ VADDR_BITS

const Addr gem5::RiscvISA::VADDR_BITS = 39

Definition at line 59 of file pagetable.hh.

◆ veic

Bitfield<6> gem5::RiscvISA::veic

Definition at line 268 of file pra_constants.hh.

◆ vi

Bitfield<3> gem5::RiscvISA::vi

Definition at line 228 of file pra_constants.hh.

◆ vint

Bitfield<5> gem5::RiscvISA::vint

Definition at line 269 of file pra_constants.hh.

◆ vpn2

Bitfield<39, 13> gem5::RiscvISA::vpn2

Definition at line 100 of file pra_constants.hh.

◆ vpn2x

Bitfield<12, 11> gem5::RiscvISA::vpn2x

Definition at line 101 of file pra_constants.hh.

◆ vs

Bitfield<9, 5> gem5::RiscvISA::vs

Definition at line 149 of file pra_constants.hh.

◆ w

Bitfield< 30 > gem5::RiscvISA::w

Definition at line 74 of file pagetable.hh.

◆ WARN_FAILURE

const int gem5::RiscvISA::WARN_FAILURE = 10000

Definition at line 68 of file locked_mem.hh.

Referenced by handleLockedWrite().

◆ wired

gem5::RiscvISA::wired

Definition at line 89 of file pra_constants.hh.

◆ wp

Bitfield<22> gem5::RiscvISA::wp

Definition at line 185 of file pra_constants.hh.

◆ wr

Bitfield<3> gem5::RiscvISA::wr

Definition at line 244 of file pra_constants.hh.

◆ x

Bitfield<3> gem5::RiscvISA::x

Definition at line 73 of file pagetable.hh.

Referenced by sc_dt::and_on_help(), sc_dt::sc_proxy< sc_bv_base >::assign_(), sc_dt::assign_v_(), sc_dt::b_and_assign_(), sc_dt::b_or_assign_(), sc_dt::b_xor_assign_(), gem5::prefetch::BOP::bestOffsetLearning(), sc_dt::sc_proxy< sc_bv_base >::check_bounds(), gem5::o3::LSQUnit::checkSnoop(), sc_dt::sc_lv_base::clean_tail(), sc_dt::scfx_rep::clear(), gem5::o3::LSQUnit::commitStores(), gem5::CopyEngine::CopyEngine(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::SparcISA::TLB::demapAll(), gem5::SparcISA::TLB::demapContext(), gem5::SparcISA::TLB::dumpAll(), sc_dt::extend_sign_w_(), gem5::IGbE::DescCache< igbreg::RxDesc >::fetchComplete(), gem5::Float16::Float16(), gem5::floorLog2(), gem5::ArmISA::TLB::flush(), gem5::SparcISA::TLB::flushAll(), gem5::ArmISA::TLB::flushAll(), gem5::ArmISA::fp16_add(), gem5::ArmISA::fp16_div(), gem5::ArmISA::fp16_mul(), gem5::ArmISA::fp16_muladd(), gem5::ArmISA::fp16_sqrt(), gem5::ArmISA::fp16_unpack(), gem5::ArmISA::fp32_add(), gem5::ArmISA::fp32_div(), gem5::ArmISA::fp32_mul(), gem5::ArmISA::fp32_muladd(), gem5::ArmISA::fp32_sqrt(), gem5::ArmISA::fp32_unpack(), gem5::ArmISA::fp64_add(), gem5::ArmISA::fp64_div(), gem5::ArmISA::fp64_mul(), gem5::ArmISA::fp64_muladd(), gem5::ArmISA::fp64_sqrt(), gem5::ArmISA::fp64_unpack(), gem5::ArmISA::fplibCompareEQ(), gem5::ArmISA::fplibCompareGE(), gem5::ArmISA::fplibCompareGT(), gem5::ArmISA::fplibCompareUN(), gem5::ArmISA::fplibMax(), gem5::ArmISA::fplibMin(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::FpOp::fpSqrt(), gem5::ArmISA::FPToFixed_16(), gem5::ArmISA::FPToFixed_32(), gem5::ArmISA::FPToFixed_64(), sc_dt::scfx_rep::get_bit(), gem5::getFpRound(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::LOCAL::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::Gicv2m::Gicv2m(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hashPC(), QTIsaac< ALPHA >::ind(), gem5::SparcISA::TLB::insert(), gem5::branch_prediction::MultiperspectivePerceptron::insert(), gem5::prefetch::BOP::insertIntoDelayQueue(), gem5::Iob::Iob(), QTIsaac< ALPHA >::isaac(), gem5::ArmISA::TLB::lookup(), sc_dt::sc_proxy< sc_bv_base >::lrotate(), sc_dt::lrotate(), gem5::ArmISA::lsl16(), gem5::ArmISA::lsl32(), gem5::ArmISA::lsl64(), gem5::ArmISA::modeConv(), gem5::ps2::TouchKit::mouseAt(), sc_dt::scfx_rep::o_extend(), sc_dt::scfx_rep::o_set_high(), sc_dt::scfx_rep::o_zero_left(), sc_dt::scfx_rep::o_zero_right(), sc_dt::operator!=(), sc_dt::sc_proxy< sc_bv_base >::operator>>(), gem5::FrameBuffer::pixel(), gem5::SparcISA::SparcStaticInst::printRegArray(), gem5::ArmISA::TLB::printTlb(), sc_dt::scfx_rep::q_clear(), sc_dt::scfx_rep::q_incr(), gem5::RangeAddrMapper::RangeAddrMapper(), gem5::GicV2::readCpu(), gem5::SparcISA::ISA::readFSReg(), gem5::IGbE::DescCache< igbreg::RxDesc >::reset(), gem5::ArmISA::HTMCheckpoint::restore(), QTIsaac< ALPHA >::rngstep(), gem5::ArmISA::Crypto::ror(), sc_dt::scfx_rep::round(), sc_dt::sc_proxy< sc_bv_base >::rrotate(), gem5::ArmISA::HTMCheckpoint::save(), SC_MODULE(), sc_dt::scfx_rep::scfx_rep(), gem5::Shader::ScheduleAdd(), gem5::VncServer::sendFrameBufferUpdate(), gem5::Iob::serialize(), gem5::CopyEngine::serialize(), gem5::SparcISA::TLB::serialize(), gem5::IGbE::DescCache< igbreg::RxDesc >::serialize(), gem5::Pl111::serialize(), sc_dt::scfx_rep::set(), gem5::VncServer::setEncodings(), gem5::GicV2::softInt(), gem5::swap_byte(), gem5::swap_byte16(), gem5::swap_byte32(), gem5::swap_byte64(), gem5::System::System(), TEST(), gem5::SparcISA::TLB::TLB(), sc_dt::scfx_rep::to_string(), gem5::SparcISA::TLB::translateFunctional(), gem5::Iob::unserialize(), gem5::CopyEngine::unserialize(), gem5::SparcISA::TLB::unserialize(), gem5::IGbE::DescCache< igbreg::RxDesc >::unserialize(), gem5::Pl111::unserialize(), gem5::memory::PhysicalMemory::unserializeStore(), gem5::GicV2::updateIntState(), sc_dt::vec_mul_small_on(), gem5::VGic::VGic(), gem5::IGbE::DescCache< igbreg::RxDesc >::wbComplete(), gem5::BmpWriter::write(), gem5::PngWriter::write(), gem5::IGbE::DescCache< igbreg::RxDesc >::writeback1(), sc_dt::sc_proxy< sc_bv_base >::xor_reduce(), gem5::CopyEngine::~CopyEngine(), gem5::GicV2::~GicV2(), mm::~mm(), and gem5::VGic::~VGic().

◆ xs

Bitfield<16, 15> gem5::RiscvISA::xs

Definition at line 547 of file misc.hh.

Referenced by gem5::dumpFpuSpec().

gem5::RiscvISA::MI_MASK
const RegVal MI_MASK
Definition: misc.hh:637
gem5::RiscvISA::FRM_MASK
const RegVal FRM_MASK
Definition: misc.hh:645
gem5::RiscvISA::CSR_UIP
@ CSR_UIP
Definition: misc.hh:202
gem5::RiscvISA::CSR_SIP
@ CSR_SIP
Definition: misc.hh:250
gem5::RiscvISA::MISA_MASK
const RegVal MISA_MASK
Definition: misc.hh:586
gem5::RiscvISA::STATUS_UPIE_MASK
const RegVal STATUS_UPIE_MASK
Definition: misc.hh:603
gem5::RiscvISA::MSI_MASK
const RegVal MSI_MASK
Definition: misc.hh:634
gem5::RiscvISA::STATUS_TW_MASK
const RegVal STATUS_TW_MASK
Definition: misc.hh:592
gem5::RiscvISA::STATUS_TSR_MASK
const RegVal STATUS_TSR_MASK
Definition: misc.hh:591
gem5::RiscvISA::STATUS_SPP_MASK
const RegVal STATUS_SPP_MASK
Definition: misc.hh:600
gem5::RiscvISA::STATUS_XS_MASK
const RegVal STATUS_XS_MASK
Definition: misc.hh:597
gem5::RiscvISA::STATUS_SPIE_MASK
const RegVal STATUS_SPIE_MASK
Definition: misc.hh:602
gem5::RiscvISA::CSR_FFLAGS
@ CSR_FFLAGS
Definition: misc.hh:203
gem5::RiscvISA::STATUS_UXL_MASK
const RegVal STATUS_UXL_MASK
Definition: misc.hh:590
gem5::RiscvISA::FFLAGS_MASK
const RegVal FFLAGS_MASK
Definition: misc.hh:644
gem5::RiscvISA::STATUS_UIE_MASK
const RegVal STATUS_UIE_MASK
Definition: misc.hh:606
gem5::RiscvISA::STATUS_TVM_MASK
const RegVal STATUS_TVM_MASK
Definition: misc.hh:593
gem5::RiscvISA::CSR_FCSR
@ CSR_FCSR
Definition: misc.hh:205
gem5::RiscvISA::SSTATUS_MASK
const RegVal SSTATUS_MASK
Definition: misc.hh:617
gem5::RiscvISA::CSR_USTATUS
@ CSR_USTATUS
Definition: misc.hh:195
gem5::RiscvISA::SEI_MASK
const RegVal SEI_MASK
Definition: misc.hh:629
gem5::RiscvISA::CSR_MIE
@ CSR_MIE
Definition: misc.hh:261
gem5::RiscvISA::CSR_MSTATUS
@ CSR_MSTATUS
Definition: misc.hh:257
gem5::RiscvISA::STATUS_SXL_MASK
const RegVal STATUS_SXL_MASK
Definition: misc.hh:589
gem5::RiscvISA::CSR_FRM
@ CSR_FRM
Definition: misc.hh:204
gem5::RiscvISA::STATUS_FS_MASK
const RegVal STATUS_FS_MASK
Definition: misc.hh:598
gem5::RiscvISA::USTATUS_MASK
const RegVal USTATUS_MASK
Definition: misc.hh:623
gem5::RiscvISA::STATUS_MPIE_MASK
const RegVal STATUS_MPIE_MASK
Definition: misc.hh:601
gem5::RiscvISA::CSR_SIE
@ CSR_SIE
Definition: misc.hh:243
gem5::RiscvISA::CSR_UIE
@ CSR_UIE
Definition: misc.hh:196
gem5::RiscvISA::STATUS_SD_MASK
const RegVal STATUS_SD_MASK
Definition: misc.hh:588
gem5::RiscvISA::STATUS_MPP_MASK
const RegVal STATUS_MPP_MASK
Definition: misc.hh:599
gem5::RiscvISA::FRM_OFFSET
const off_t FRM_OFFSET
Definition: misc.hh:581
gem5::RiscvISA::UI_MASK
const RegVal UI_MASK
Definition: misc.hh:643
gem5::RiscvISA::USI_MASK
const RegVal USI_MASK
Definition: misc.hh:636
gem5::RiscvISA::STATUS_MIE_MASK
const RegVal STATUS_MIE_MASK
Definition: misc.hh:604
gem5::RiscvISA::CSR_SSTATUS
@ CSR_SSTATUS
Definition: misc.hh:240
gem5::RiscvISA::STATUS_MXR_MASK
const RegVal STATUS_MXR_MASK
Definition: misc.hh:594
gem5::RiscvISA::UTI_MASK
const RegVal UTI_MASK
Definition: misc.hh:633
gem5::RiscvISA::CSR_MISA
@ CSR_MISA
Definition: misc.hh:258
gem5::RiscvISA::STATUS_MPRV_MASK
const RegVal STATUS_MPRV_MASK
Definition: misc.hh:596
gem5::RiscvISA::MEI_MASK
const RegVal MEI_MASK
Definition: misc.hh:628
gem5::RiscvISA::STATUS_SUM_MASK
const RegVal STATUS_SUM_MASK
Definition: misc.hh:595
gem5::RiscvISA::SI_MASK
const RegVal SI_MASK
Definition: misc.hh:640
gem5::RiscvISA::MTI_MASK
const RegVal MTI_MASK
Definition: misc.hh:631
gem5::RiscvISA::MSTATUS_MASK
const RegVal MSTATUS_MASK
Definition: misc.hh:607
gem5::RiscvISA::STATUS_SIE_MASK
const RegVal STATUS_SIE_MASK
Definition: misc.hh:605
gem5::RiscvISA::SSI_MASK
const RegVal SSI_MASK
Definition: misc.hh:635
gem5::RiscvISA::UEI_MASK
const RegVal UEI_MASK
Definition: misc.hh:630
gem5::RiscvISA::STI_MASK
const RegVal STI_MASK
Definition: misc.hh:632
gem5::RiscvISA::CSR_MIP
@ CSR_MIP
Definition: misc.hh:268

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