gem5  v22.0.0.2
gem5::fastmodel::CortexR52TC Member List

This is the complete list of members for gem5::fastmodel::CortexR52TC, including all inherited members.

_contextIdgem5::Iris::ThreadContextprotected
_cpugem5::Iris::ThreadContextprotected
_instIdgem5::Iris::ThreadContextprotected
_irisPathgem5::Iris::ThreadContextprotected
_isagem5::Iris::ThreadContextprotected
_mmugem5::Iris::ThreadContextprotected
_statusgem5::Iris::ThreadContextprotected
_systemgem5::Iris::ThreadContextprotected
_threadIdgem5::Iris::ThreadContextprotected
activate() overridegem5::Iris::ThreadContextinlinevirtual
Active enum valuegem5::ThreadContext
BpId typedefgem5::Iris::ThreadContextprotected
BpInfoIt typedefgem5::Iris::ThreadContextprotected
BpInfoMap typedefgem5::Iris::ThreadContextprotected
BpInfoPtr typedefgem5::Iris::ThreadContextprotected
bpsgem5::Iris::ThreadContextprotected
bpSpaceIdsgem5::fastmodel::CortexR52TCprotectedstatic
breakpointEventStreamIdgem5::Iris::ThreadContextprotected
breakpointHit(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)gem5::Iris::ThreadContextprotected
call() constgem5::Iris::ThreadContextinlineprotected
ccRegIdsgem5::Iris::ThreadContextprotected
ccRegIdxNameMapgem5::fastmodel::CortexR52TCprotectedstatic
clearArchRegs() overridegem5::Iris::ThreadContextinlinevirtual
clientgem5::Iris::ThreadContextmutableprotected
comInstEventQueuegem5::Iris::ThreadContextprotected
compare(ThreadContext *one, ThreadContext *two)gem5::ThreadContextstatic
contextId() const overridegem5::Iris::ThreadContextinlinevirtual
copyArchRegs(gem5::ThreadContext *tc) overridegem5::Iris::ThreadContextinlinevirtual
CortexR52TC(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)gem5::fastmodel::CortexR52TC
cpuId() const overridegem5::Iris::ThreadContextinlinevirtual
DefaultFloatResultgem5::ThreadContextstatic
DefaultIntResultgem5::ThreadContextstatic
delBp(BpInfoIt it)gem5::Iris::ThreadContextprotected
descheduleInstCountEvent(Event *event) overridegem5::Iris::ThreadContextvirtual
enableAfterPseudoEventgem5::Iris::ThreadContextprotected
exit()gem5::ThreadContextinlinevirtual
extractResourceId(const ResourceMap &resources, const std::string &name)gem5::Iris::ThreadContextprotected
extractResourceMap(ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)gem5::Iris::ThreadContextprotected
flattenedIntIdsgem5::Iris::ThreadContextprotected
flattenRegId(const RegId &regId) const overridegem5::Iris::ThreadContextinlinevirtual
floatResultgem5::ThreadContext
floatsgem5::ThreadContextstatic
getBpSpaceIds() const overridegem5::fastmodel::CortexR52TCvirtual
getCheckerCpuPtr() overridegem5::Iris::ThreadContextinlinevirtual
getCpuPtr() overridegem5::Iris::ThreadContextinlinevirtual
getCurrentInstCount() overridegem5::Iris::ThreadContextvirtual
getDecoderPtr() overridegem5::Iris::ThreadContextinlinevirtual
getHtmCheckpointPtr() overridegem5::Iris::ThreadContextinlinevirtual
getIsaPtr() const overridegem5::Iris::ThreadContextinlinevirtual
getMemorySpaceId(const Iris::CanonicalMsn &msn) constgem5::Iris::ThreadContextprotected
getMMUPtr() overridegem5::Iris::ThreadContextinlinevirtual
getOrAllocBp(Addr pc)gem5::Iris::ThreadContextprotected
getProcessPtr() overridegem5::Iris::ThreadContextinlinevirtual
getReg(const RegId &reg) const overridegem5::Iris::ThreadContextvirtual
getReg(const RegId &reg, void *val) const overridegem5::Iris::ThreadContextvirtual
getRegFlat(const RegId &reg) const overridegem5::Iris::ThreadContextvirtual
getRegFlat(const RegId &reg, void *val) const overridegem5::Iris::ThreadContextvirtual
getSystemPtr() overridegem5::Iris::ThreadContextinlinevirtual
getUseForClone()gem5::ThreadContextinline
getWritableReg(const RegId &reg) overridegem5::Iris::ThreadContextvirtual
getWritableRegFlat(const RegId &reg) overridegem5::Iris::ThreadContextvirtual
getWritableVecPredReg(const RegId &reg)gem5::Iris::ThreadContextinlinevirtual
getWritableVecPredRegFlat(RegIndex idx)gem5::Iris::ThreadContextinlinevirtual
getWritableVecReg(const RegId &reg)gem5::Iris::ThreadContextinlinevirtual
getWritableVecRegFlat(RegIndex idx)gem5::Iris::ThreadContextinlinevirtual
halt() overridegem5::Iris::ThreadContextinlinevirtual
Halted enum valuegem5::ThreadContext
Halting enum valuegem5::ThreadContext
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) overridegem5::Iris::ThreadContextinlinevirtual
icountRscIdgem5::Iris::ThreadContextprotected
IdxNameMap typedefgem5::Iris::ThreadContext
initEventStreamIdgem5::Iris::ThreadContextprotected
initFromIrisInstance(const ResourceMap &resources) overridegem5::fastmodel::CortexR52TCvirtual
installBp(BpInfoIt it)gem5::Iris::ThreadContextprotected
instanceRegistryChanged(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)gem5::Iris::ThreadContextprotected
intOffsetgem5::ThreadContext
intReg32Idsgem5::Iris::ThreadContextprotected
intReg32IdxNameMapgem5::fastmodel::CortexR52TCprotectedstatic
intReg64Idsgem5::Iris::ThreadContextprotected
intResultgem5::ThreadContext
intsgem5::ThreadContextstatic
maintainStepping()gem5::Iris::ThreadContextprotected
memorySpaceIdsgem5::Iris::ThreadContextprotected
MemorySpaceMap typedefgem5::Iris::ThreadContext
memorySpacesgem5::Iris::ThreadContextprotected
miscRegIdsgem5::Iris::ThreadContextprotected
miscRegIdxNameMapgem5::fastmodel::CortexR52TCprotectedstatic
noThrow() constgem5::Iris::ThreadContextinlineprotected
pcgem5::Iris::ThreadContextmutableprotected
pcRscIdgem5::Iris::ThreadContextprotected
pcState() const overridegem5::Iris::ThreadContextvirtual
pcState(const PCStateBase &val) overridegem5::Iris::ThreadContextvirtual
gem5::ThreadContext::pcState(Addr addr)gem5::ThreadContextinline
pcStateNoRecord(const PCStateBase &val) overridegem5::Iris::ThreadContextinlinevirtual
phaseInitLeave(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)gem5::Iris::ThreadContextprotected
quiesce()gem5::ThreadContext
quiesceTick(Tick resume)gem5::ThreadContext
readCCReg(RegIndex reg_idx) constgem5::Iris::ThreadContextinlinevirtual
readCCRegFlat(RegIndex idx) const overridegem5::fastmodel::CortexR52TCvirtual
readFloatReg(RegIndex reg_idx) constgem5::ThreadContextinline
readFloatRegFlat(RegIndex idx) constgem5::ThreadContextinline
readIntReg(RegIndex reg_idx) const overridegem5::fastmodel::CortexR52TCvirtual
readIntRegFlat(RegIndex idx) const overridegem5::fastmodel::CortexR52TCinlinevirtual
readLastActivate() overridegem5::Iris::ThreadContextinlinevirtual
readLastSuspend() overridegem5::Iris::ThreadContextinlinevirtual
readMem(iris::MemorySpaceId space, Addr addr, void *p, size_t size)gem5::Iris::ThreadContextprotected
readMiscReg(RegIndex misc_reg) overridegem5::Iris::ThreadContextinlinevirtual
readMiscRegNoEffect(RegIndex idx) const overridegem5::fastmodel::CortexR52TCinlinevirtual
readStCondFailures() const overridegem5::Iris::ThreadContextinlinevirtual
readVecElem(const RegId &reg) constgem5::Iris::ThreadContextinlinevirtual
readVecElemFlat(RegIndex idx) constgem5::Iris::ThreadContextinlinevirtual
readVecPredReg(const RegId &reg) constgem5::Iris::ThreadContextvirtual
readVecPredRegFlat(RegIndex idx) constgem5::Iris::ThreadContextvirtual
readVecReg(const RegId &) const overridegem5::fastmodel::CortexR52TCinlinevirtual
readVecRegFlat(RegIndex idx) constgem5::Iris::ThreadContextvirtual
regEventStreamIdgem5::Iris::ThreadContextprotected
regStats(const std::string &name) overridegem5::Iris::ThreadContextinlinevirtual
remove(PCEvent *e) overridegem5::Iris::ThreadContextvirtual
ResourceIds typedefgem5::Iris::ThreadContext
ResourceMap typedefgem5::Iris::ThreadContext
schedule(PCEvent *e) overridegem5::Iris::ThreadContextvirtual
scheduleInstCountEvent(Event *event, Tick count) overridegem5::Iris::ThreadContextvirtual
semihostingEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)gem5::Iris::ThreadContextprotected
semihostingEventStreamIdgem5::Iris::ThreadContextprotected
sendFunctional(PacketPtr pkt) overridegem5::fastmodel::CortexR52TCvirtual
setCCReg(RegIndex reg_idx, RegVal val)gem5::Iris::ThreadContextinlinevirtual
setCCRegFlat(RegIndex idx, RegVal val) overridegem5::fastmodel::CortexR52TCvirtual
setContextId(int id) overridegem5::Iris::ThreadContextinlinevirtual
setFloatReg(RegIndex reg_idx, RegVal val)gem5::ThreadContextinline
setFloatRegFlat(RegIndex idx, RegVal val)gem5::ThreadContextinline
setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) overridegem5::Iris::ThreadContextinlinevirtual
setIntReg(RegIndex reg_idx, RegVal val) overridegem5::fastmodel::CortexR52TCvirtual
setIntRegFlat(RegIndex idx, RegVal val) overridegem5::fastmodel::CortexR52TCinlinevirtual
setMiscReg(RegIndex misc_reg, const RegVal val) overridegem5::Iris::ThreadContextinlinevirtual
setMiscRegNoEffect(RegIndex idx, const RegVal val) overridegem5::fastmodel::CortexR52TCinlinevirtual
setProcessPtr(Process *p) overridegem5::Iris::ThreadContextinlinevirtual
setReg(const RegId &reg, RegVal val) overridegem5::Iris::ThreadContextvirtual
setReg(const RegId &reg, const void *val) overridegem5::Iris::ThreadContextvirtual
setRegFlat(const RegId &reg, RegVal val) overridegem5::Iris::ThreadContextvirtual
setRegFlat(const RegId &reg, const void *val) overridegem5::Iris::ThreadContextvirtual
setStatus(Status new_status) overridegem5::Iris::ThreadContextvirtual
setStCondFailures(unsigned sc_failures) overridegem5::Iris::ThreadContextinlinevirtual
setThreadId(int id) overridegem5::Iris::ThreadContextinlinevirtual
setUseForClone(bool new_val)gem5::ThreadContextinline
setVecElem(const RegId &reg, RegVal val)gem5::Iris::ThreadContextinlinevirtual
setVecElemFlat(RegIndex idx, RegVal val)gem5::Iris::ThreadContextinlinevirtual
setVecPredReg(const RegId &reg, const ArmISA::VecPredRegContainer &val)gem5::Iris::ThreadContextinlinevirtual
setVecPredRegFlat(RegIndex idx, const ArmISA::VecPredRegContainer &val)gem5::Iris::ThreadContextinlinevirtual
setVecReg(const RegId &reg, const ArmISA::VecRegContainer &val)gem5::Iris::ThreadContextinlinevirtual
setVecRegFlat(RegIndex idx, const ArmISA::VecRegContainer &val)gem5::Iris::ThreadContextinlinevirtual
simulationTimeEvent(uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)gem5::Iris::ThreadContextprotected
socketId() const overridegem5::Iris::ThreadContextinlinevirtual
Status enum namegem5::ThreadContext
status() const overridegem5::Iris::ThreadContextvirtual
suspend() overridegem5::Iris::ThreadContextinlinevirtual
Suspended enum valuegem5::ThreadContext
takeOverFrom(gem5::ThreadContext *old_context) overridegem5::Iris::ThreadContextinlinevirtual
ThreadContext(gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)gem5::Iris::ThreadContext
threadId() const overridegem5::Iris::ThreadContextinlinevirtual
timeEventStreamIdgem5::Iris::ThreadContextprotected
translateAddress(Addr &paddr, Addr vaddr) overridegem5::fastmodel::CortexR52TCvirtual
gem5::Iris::ThreadContext::translateAddress(Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)gem5::Iris::ThreadContextprotected
translationsgem5::Iris::ThreadContextprotected
uninstallBp(BpInfoIt it)gem5::Iris::ThreadContextprotected
useForClonegem5::ThreadContextprotected
vecPredRegIdsgem5::Iris::ThreadContextprotected
vecPredRegsgem5::Iris::ThreadContextmutableprotected
vecRegIdsgem5::Iris::ThreadContextprotected
vecRegsgem5::Iris::ThreadContextmutableprotected
writeMem(iris::MemorySpaceId space, Addr addr, const void *p, size_t size)gem5::Iris::ThreadContextprotected
~ThreadContext()gem5::Iris::ThreadContextvirtual

Generated on Thu Jul 28 2022 13:33:29 for gem5 by doxygen 1.8.17