gem5  v21.1.0.2
Public Member Functions | Static Protected Attributes | List of all members
gem5::fastmodel::CortexR52TC Class Reference

#include <thread_context.hh>

Inheritance diagram for gem5::fastmodel::CortexR52TC:
gem5::Iris::ThreadContext gem5::ThreadContext gem5::PCEventScope

Public Member Functions

 CortexR52TC (gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
 
bool translateAddress (Addr &paddr, Addr vaddr) override
 
void initFromIrisInstance (const ResourceMap &resources) override
 
RegVal readIntReg (RegIndex reg_idx) const override
 
void setIntReg (RegIndex reg_idx, RegVal val) override
 
RegVal readCCRegFlat (RegIndex idx) const override
 
void setCCRegFlat (RegIndex idx, RegVal val) override
 
const std::vector< iris::MemorySpaceId > & getBpSpaceIds () const override
 
RegVal readMiscRegNoEffect (RegIndex) const override
 
void setMiscRegNoEffect (RegIndex, const RegVal) override
 
RegVal readIntRegFlat (RegIndex idx) const override
 Flat register interfaces. More...
 
void setIntRegFlat (RegIndex idx, RegVal val) override
 
const ArmISA::VecRegContainerreadVecReg (const RegId &) const override
 
- Public Member Functions inherited from gem5::Iris::ThreadContext
 ThreadContext (gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)
 
virtual ~ThreadContext ()
 
bool schedule (PCEvent *e) override
 
bool remove (PCEvent *e) override
 
void scheduleInstCountEvent (Event *event, Tick count) override
 
void descheduleInstCountEvent (Event *event) override
 
Tick getCurrentInstCount () override
 
gem5::BaseCPUgetCpuPtr () override
 
int cpuId () const override
 
uint32_t socketId () const override
 
int threadId () const override
 
void setThreadId (int id) override
 
int contextId () const override
 
void setContextId (int id) override
 
BaseMMUgetMMUPtr () override
 
CheckerCPUgetCheckerCpuPtr () override
 
ArmISA::DecodergetDecoderPtr () override
 
SystemgetSystemPtr () override
 
BaseISAgetIsaPtr () override
 
PortProxygetVirtProxy () override
 
void initMemProxies (gem5::ThreadContext *tc) override
 Initialise the physical and virtual port proxies and tie them to the data port of the CPU. More...
 
void sendFunctional (PacketPtr pkt) override
 
ProcessgetProcessPtr () override
 
void setProcessPtr (Process *p) override
 
Status status () const override
 
void setStatus (Status new_status) override
 
void activate () override
 Set the status to Active. More...
 
void suspend () override
 Set the status to Suspended. More...
 
void halt () override
 Set the status to Halted. More...
 
void takeOverFrom (gem5::ThreadContext *old_context) override
 
void regStats (const std::string &name) override
 
Tick readLastActivate () override
 
Tick readLastSuspend () override
 
void copyArchRegs (gem5::ThreadContext *tc) override
 
void clearArchRegs () override
 
RegVal readIntReg (RegIndex reg_idx) const override
 
RegVal readFloatReg (RegIndex reg_idx) const override
 
const ArmISA::VecRegContainerreadVecReg (const RegId &reg) const override
 
ArmISA::VecRegContainergetWritableVecReg (const RegId &reg) override
 
const ArmISA::VecElemreadVecElem (const RegId &reg) const override
 
const ArmISA::VecPredRegContainerreadVecPredReg (const RegId &reg) const override
 
ArmISA::VecPredRegContainergetWritableVecPredReg (const RegId &reg) override
 
RegVal readCCReg (RegIndex reg_idx) const override
 
void setIntReg (RegIndex reg_idx, RegVal val) override
 
void setFloatReg (RegIndex reg_idx, RegVal val) override
 
void setVecReg (const RegId &reg, const ArmISA::VecRegContainer &val) override
 
void setVecElem (const RegId &reg, const ArmISA::VecElem &val) override
 
void setVecPredReg (const RegId &reg, const ArmISA::VecPredRegContainer &val) override
 
void setCCReg (RegIndex reg_idx, RegVal val) override
 
void pcStateNoRecord (const ArmISA::PCState &val) override
 
MicroPC microPC () const override
 
ArmISA::PCState pcState () const override
 
void pcState (const ArmISA::PCState &val) override
 
Addr instAddr () const override
 
Addr nextInstAddr () const override
 
RegVal readMiscRegNoEffect (RegIndex misc_reg) const override
 
RegVal readMiscReg (RegIndex misc_reg) override
 
void setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override
 
void setMiscReg (RegIndex misc_reg, const RegVal val) override
 
RegId flattenRegId (const RegId &regId) const override
 
unsigned readStCondFailures () const override
 
void setStCondFailures (unsigned sc_failures) override
 
void htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override
 
BaseHTMCheckpointPtrgetHtmCheckpointPtr () override
 
void setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt) override
 
RegVal readIntRegFlat (RegIndex idx) const override
 Flat register interfaces. More...
 
void setIntRegFlat (RegIndex idx, uint64_t val) override
 
RegVal readFloatRegFlat (RegIndex idx) const override
 
void setFloatRegFlat (RegIndex idx, RegVal val) override
 
const ArmISA::VecRegContainerreadVecRegFlat (RegIndex idx) const override
 
ArmISA::VecRegContainergetWritableVecRegFlat (RegIndex idx) override
 
void setVecRegFlat (RegIndex idx, const ArmISA::VecRegContainer &val) override
 
const ArmISA::VecElemreadVecElemFlat (RegIndex idx, const ElemIndex &elemIdx) const override
 
void setVecElemFlat (RegIndex idx, const ElemIndex &elemIdx, const ArmISA::VecElem &val) override
 
const ArmISA::VecPredRegContainerreadVecPredRegFlat (RegIndex idx) const override
 
ArmISA::VecPredRegContainergetWritableVecPredRegFlat (RegIndex idx) override
 
void setVecPredRegFlat (RegIndex idx, const ArmISA::VecPredRegContainer &val) override
 
RegVal readCCRegFlat (RegIndex idx) const override
 
void setCCRegFlat (RegIndex idx, RegVal val) override
 
- Public Member Functions inherited from gem5::ThreadContext
bool getUseForClone ()
 
void setUseForClone (bool new_val)
 
void quiesce ()
 Quiesce thread context. More...
 
void quiesceTick (Tick resume)
 Quiesce, suspend, and schedule activate at resume. More...
 
virtual void setVecPredReg (const RegId &reg, const TheISA::VecPredRegContainer &val)=0
 
void setNPC (Addr val)
 
virtual int exit ()
 
virtual void setVecPredRegFlat (RegIndex idx, const TheISA::VecPredRegContainer &val)=0
 

Static Protected Attributes

static IdxNameMap intReg32IdxNameMap
 
static IdxNameMap ccRegIdxNameMap
 
static std::vector< iris::MemorySpaceId > bpSpaceIds
 

Additional Inherited Members

- Public Types inherited from gem5::Iris::ThreadContext
typedef std::map< std::string, iris::ResourceInfo > ResourceMap
 
typedef std::vector< iris::ResourceId > ResourceIds
 
typedef std::map< int, std::string > IdxNameMap
 
- Public Types inherited from gem5::ThreadContext
enum  Status { Active, Suspended, Halting, Halted }
 
- Static Public Member Functions inherited from gem5::ThreadContext
static void compare (ThreadContext *one, ThreadContext *two)
 function to compare two thread contexts (for debugging) More...
 
- Public Attributes inherited from gem5::ThreadContext
int intResult = DefaultIntResult
 
double floatResult = DefaultFloatResult
 
int intOffset = 0
 
- Static Public Attributes inherited from gem5::ThreadContext
static const int ints []
 
static const double floats []
 
static const int DefaultIntResult = 0
 
static const double DefaultFloatResult = 0.0
 
- Protected Types inherited from gem5::Iris::ThreadContext
using BpId = uint64_t
 
using BpInfoPtr = std::unique_ptr< BpInfo >
 
using BpInfoMap = std::map< Addr, BpInfoPtr >
 
using BpInfoIt = BpInfoMap::iterator
 
- Protected Member Functions inherited from gem5::Iris::ThreadContext
iris::ResourceId extractResourceId (const ResourceMap &resources, const std::string &name)
 
void extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)
 
void maintainStepping ()
 
BpInfoIt getOrAllocBp (Addr pc)
 
void installBp (BpInfoIt it)
 
void uninstallBp (BpInfoIt it)
 
void delBp (BpInfoIt it)
 
iris::IrisErrorCode instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisErrorCode semihostingEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)
 
iris::IrisCppAdapter & call () const
 
iris::IrisCppAdapter & noThrow () const
 
bool translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)
 
- Protected Attributes inherited from gem5::Iris::ThreadContext
gem5::BaseCPU_cpu
 
int _threadId
 
ContextID _contextId
 
System_system
 
gem5::BaseMMU_mmu
 
gem5::BaseISA_isa
 
std::string _irisPath
 
iris::InstanceId _instId = iris::IRIS_UINT64_MAX
 
std::vector< ArmISA::VecRegContainervecRegs
 
std::vector< ArmISA::VecPredRegContainervecPredRegs
 
Status _status = Active
 
EventenableAfterPseudoEvent
 
ResourceIds miscRegIds
 
ResourceIds intReg32Ids
 
ResourceIds intReg64Ids
 
ResourceIds flattenedIntIds
 
ResourceIds ccRegIds
 
iris::ResourceId pcRscId = iris::IRIS_UINT64_MAX
 
iris::ResourceId icountRscId
 
ResourceIds vecRegIds
 
ResourceIds vecPredRegIds
 
std::vector< iris::MemorySpaceInfo > memorySpaces
 
std::vector< iris::MemorySupportedAddressTranslationResult > translations
 
std::unique_ptr< PortProxyvirtProxy = nullptr
 
EventQueue comInstEventQueue
 
BpInfoMap bps
 
iris::EventStreamId regEventStreamId
 
iris::EventStreamId initEventStreamId
 
iris::EventStreamId timeEventStreamId
 
iris::EventStreamId breakpointEventStreamId
 
iris::EventStreamId semihostingEventStreamId
 
iris::IrisInstance client
 
- Protected Attributes inherited from gem5::ThreadContext
bool useForClone = false
 

Detailed Description

Definition at line 42 of file thread_context.hh.

Constructor & Destructor Documentation

◆ CortexR52TC()

gem5::fastmodel::CortexR52TC::CortexR52TC ( gem5::BaseCPU cpu,
int  id,
System system,
gem5::BaseMMU mmu,
gem5::BaseISA isa,
iris::IrisConnectionInterface *  iris_if,
const std::string &  iris_path 
)

Definition at line 42 of file thread_context.cc.

Member Function Documentation

◆ getBpSpaceIds()

const std::vector< iris::MemorySpaceId > & gem5::fastmodel::CortexR52TC::getBpSpaceIds ( ) const
overridevirtual

◆ initFromIrisInstance()

void gem5::fastmodel::CortexR52TC::initFromIrisInstance ( const ResourceMap resources)
overridevirtual

◆ readCCRegFlat()

RegVal gem5::fastmodel::CortexR52TC::readCCRegFlat ( RegIndex  idx) const
overridevirtual

◆ readIntReg()

RegVal gem5::fastmodel::CortexR52TC::readIntReg ( RegIndex  reg_idx) const
overridevirtual

◆ readIntRegFlat()

RegVal gem5::fastmodel::CortexR52TC::readIntRegFlat ( RegIndex  idx) const
inlineoverridevirtual

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Implements gem5::ThreadContext.

Definition at line 90 of file thread_context.hh.

References panic.

◆ readMiscRegNoEffect()

RegVal gem5::fastmodel::CortexR52TC::readMiscRegNoEffect ( RegIndex  ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 77 of file thread_context.hh.

References panic.

Referenced by setCCRegFlat().

◆ readVecReg()

const ArmISA::VecRegContainer& gem5::fastmodel::CortexR52TC::readVecReg ( const RegId ) const
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 105 of file thread_context.hh.

References panic.

◆ setCCRegFlat()

void gem5::fastmodel::CortexR52TC::setCCRegFlat ( RegIndex  idx,
RegVal  val 
)
overridevirtual

◆ setIntReg()

void gem5::fastmodel::CortexR52TC::setIntReg ( RegIndex  reg_idx,
RegVal  val 
)
overridevirtual

◆ setIntRegFlat()

void gem5::fastmodel::CortexR52TC::setIntRegFlat ( RegIndex  idx,
RegVal  val 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 96 of file thread_context.hh.

References panic.

◆ setMiscRegNoEffect()

void gem5::fastmodel::CortexR52TC::setMiscRegNoEffect ( RegIndex  ,
const  RegVal 
)
inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 83 of file thread_context.hh.

References panic.

◆ translateAddress()

bool gem5::fastmodel::CortexR52TC::translateAddress ( Addr paddr,
Addr  vaddr 
)
overridevirtual

Member Data Documentation

◆ bpSpaceIds

std::vector< iris::MemorySpaceId > gem5::fastmodel::CortexR52TC::bpSpaceIds
staticprotected

Definition at line 47 of file thread_context.hh.

Referenced by getBpSpaceIds().

◆ ccRegIdxNameMap

Iris::ThreadContext::IdxNameMap gem5::fastmodel::CortexR52TC::ccRegIdxNameMap
staticprotected

Definition at line 46 of file thread_context.hh.

Referenced by initFromIrisInstance().

◆ intReg32IdxNameMap

Iris::ThreadContext::IdxNameMap gem5::fastmodel::CortexR52TC::intReg32IdxNameMap
staticprotected

Definition at line 45 of file thread_context.hh.

Referenced by initFromIrisInstance().


The documentation for this class was generated from the following files:

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