#include <thread_context.hh>

Inheritance diagram for gem5::Iris::ThreadContext:

Classes
struct	BpInfo

Public Types
typedef std::map< std::string, iris::ResourceInfo >	ResourceMap

typedef std::vector< iris::ResourceId >	ResourceIds

typedef std::map< int, std::string >	IdxNameMap

typedef std::unordered_map< Iris::CanonicalMsn, iris::MemorySpaceId >	MemorySpaceMap

Public Types inherited from gem5::ThreadContext
enum	Status { Active , Suspended , Halting , Halted }

Public Member Functions
	ThreadContext (gem5::BaseCPU cpu, int id, System system, gem5::BaseMMU mmu, gem5::BaseISA isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path)

virtual	~ThreadContext ()

virtual bool	translateAddress (Addr &paddr, Addr vaddr)=0

bool	schedule (PCEvent *e) override

bool	remove (PCEvent *e) override

void	scheduleInstCountEvent (Event *event, Tick count) override

void	descheduleInstCountEvent (Event *event) override

Tick	getCurrentInstCount () override

gem5::BaseCPU *	getCpuPtr () override

int	cpuId () const override

uint32_t	socketId () const override

int	threadId () const override

void	setThreadId (int id) override

int	contextId () const override

void	setContextId (int id) override

BaseMMU *	getMMUPtr () override

CheckerCPU *	getCheckerCpuPtr () override

InstDecoder *	getDecoderPtr () override

System *	getSystemPtr () override

BaseISA *	getIsaPtr () const override

void	sendFunctional (PacketPtr pkt) override

Process *	getProcessPtr () override

void	setProcessPtr (Process *p) override

Status	status () const override

void	setStatus (Status new_status) override

void	activate () override
	Set the status to Active. More...

void	suspend () override
	Set the status to Suspended. More...

void	halt () override
	Set the status to Halted. More...

void	takeOverFrom (gem5::ThreadContext *old_context) override

void	regStats (const std::string &name) override

Tick	readLastActivate () override

Tick	readLastSuspend () override

void	copyArchRegs (gem5::ThreadContext *tc) override

void	clearArchRegs () override

RegVal	getReg (const RegId &reg) const override

void	getReg (const RegId &reg, void *val) const override

void *	getWritableReg (const RegId &reg) override

void	setReg (const RegId &reg, RegVal val) override

void	setReg (const RegId &reg, const void *val) override

iris::ResourceId	getIntRegRscId (RegIndex int_reg) const

virtual RegVal	readIntReg (RegIndex reg_idx) const

iris::ResourceId	getVecRegRscId (RegIndex vec_reg) const

virtual const ArmISA::VecRegContainer &	readVecReg (const RegId &reg) const

virtual ArmISA::VecRegContainer &	getWritableVecReg (const RegId &reg)

virtual RegVal	readVecElem (const RegId &reg) const

iris::ResourceId	getVecPredRegRscId (RegIndex vec_reg) const

virtual const ArmISA::VecPredRegContainer &	readVecPredReg (const RegId &reg) const

virtual ArmISA::VecPredRegContainer &	getWritableVecPredReg (const RegId &reg)

virtual RegVal	readCCReg (RegIndex reg_idx) const

virtual void	setIntReg (RegIndex reg_idx, RegVal val)

virtual void	setVecReg (const RegId &reg, const ArmISA::VecRegContainer &val)

virtual void	setVecElem (const RegId &reg, RegVal val)

virtual void	setVecPredReg (const RegId &reg, const ArmISA::VecPredRegContainer &val)

virtual void	setCCReg (RegIndex reg_idx, RegVal val)

void	pcStateNoRecord (const PCStateBase &val) override

const PCStateBase &	pcState () const override

void	pcState (const PCStateBase &val) override

iris::ResourceId	getMiscRegRscId (RegIndex misc_reg) const

RegVal	readMiscRegNoEffect (RegIndex misc_reg) const override

RegVal	readMiscReg (RegIndex misc_reg) override

void	setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override

void	setMiscReg (RegIndex misc_reg, const RegVal val) override

unsigned	readStCondFailures () const override

void	setStCondFailures (unsigned sc_failures) override

void	htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override

BaseHTMCheckpointPtr &	getHtmCheckpointPtr () override

void	setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt) override

void	readMemWithCurrentMsn (Addr vaddr, size_t size, char *data)

void	writeMemWithCurrentMsn (Addr vaddr, size_t size, const char *data)


iris::ResourceId	getIntRegFlatRscId (RegIndex int_reg) const
	Flat register interfaces. More...

virtual RegVal	readIntRegFlat (RegIndex idx) const

virtual void	setIntRegFlat (RegIndex idx, uint64_t val)

virtual const ArmISA::VecRegContainer &	readVecRegFlat (RegIndex idx) const

virtual ArmISA::VecRegContainer &	getWritableVecRegFlat (RegIndex idx)

virtual void	setVecRegFlat (RegIndex idx, const ArmISA::VecRegContainer &val)

virtual RegVal	readVecElemFlat (RegIndex idx) const

virtual void	setVecElemFlat (RegIndex idx, RegVal val)

virtual ArmISA::VecPredRegContainer	readVecPredRegFlat (RegIndex idx) const

virtual ArmISA::VecPredRegContainer &	getWritableVecPredRegFlat (RegIndex idx)

virtual void	setVecPredRegFlat (RegIndex idx, const ArmISA::VecPredRegContainer &val)

iris::ResourceId	getCCRegFlatRscId (RegIndex cc_reg) const

virtual RegVal	readCCRegFlat (RegIndex idx) const

virtual void	setCCRegFlat (RegIndex idx, RegVal val)

Public Member Functions inherited from gem5::ThreadContext
bool	getUseForClone ()

void	setUseForClone (bool new_val)

void	quiesce ()
	Quiesce thread context. More...

void	quiesceTick (Tick resume)
	Quiesce, suspend, and schedule activate at resume. More...

void	pcState (Addr addr)

virtual int	exit ()

Protected Types
using	BpId = uint64_t

using	BpInfoPtr = std::unique_ptr< BpInfo >

using	BpInfoMap = std::map< Addr, BpInfoPtr >

using	BpInfoIt = BpInfoMap::iterator

Protected Member Functions
virtual void	initFromIrisInstance (const ResourceMap &resources)

iris::ResourceId	extractResourceId (const ResourceMap &resources, const std::string &name)

void	extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names)

iris::MemorySpaceId	getMemorySpaceId (const Iris::CanonicalMsn &msn) const

void	maintainStepping ()

BpInfoIt	getOrAllocBp (Addr pc)

void	installBp (BpInfoIt it)

void	uninstallBp (BpInfoIt it)

void	delBp (BpInfoIt it)

virtual const std::vector< iris::MemorySpaceId > &	getBpSpaceIds () const =0

iris::IrisErrorCode	instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisErrorCode	semihostingEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out)

iris::IrisCppAdapter &	call () const

iris::IrisCppAdapter &	noThrow () const

void	readMem (iris::MemorySpaceId space, Addr addr, void *p, size_t size)

void	writeMem (iris::MemorySpaceId space, Addr addr, const void *p, size_t size)

bool	translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space)

Protected Attributes
gem5::BaseCPU *	_cpu

int	_threadId

ContextID	_contextId

System *	_system

gem5::BaseMMU *	_mmu

gem5::BaseISA *	_isa

std::string	_irisPath

iris::InstanceId	_instId = iris::IRIS_UINT64_MAX

std::vector< ArmISA::VecRegContainer >	vecRegs

std::vector< ArmISA::VecPredRegContainer >	vecPredRegs

Status	_status = Active

Event *	enableAfterPseudoEvent

ResourceIds	miscRegIds

ResourceIds	intReg32Ids

ResourceIds	intReg64Ids

ResourceIds	flattenedIntIds

ResourceIds	ccRegIds

iris::ResourceId	pcRscId = iris::IRIS_UINT64_MAX

iris::ResourceId	icountRscId

ResourceIds	vecRegIds

ResourceIds	vecPredRegIds

std::vector< iris::MemorySpaceInfo >	memorySpaces

std::vector< iris::MemorySupportedAddressTranslationResult >	translations

MemorySpaceMap	memorySpaceIds

EventQueue	comInstEventQueue

BpInfoMap	bps

iris::EventStreamId	regEventStreamId

iris::EventStreamId	initEventStreamId

iris::EventStreamId	timeEventStreamId

iris::EventStreamId	breakpointEventStreamId

iris::EventStreamId	semihostingEventStreamId

iris::IrisInstance	client

ArmISA::PCState	pc

Protected Attributes inherited from gem5::ThreadContext
bool	useForClone = false

Additional Inherited Members
Static Public Member Functions inherited from gem5::ThreadContext
static void	compare (ThreadContext one, ThreadContext two)
	function to compare two thread contexts (for debugging) More...

Public Attributes inherited from gem5::ThreadContext
int	intResult = DefaultIntResult

double	floatResult = DefaultFloatResult

int	intOffset = 0

Static Public Attributes inherited from gem5::ThreadContext
static const int	ints []

static const double	floats []

static const int	DefaultIntResult = 0

static const double	DefaultFloatResult = 0.0

Detailed Description

Definition at line 53 of file thread_context.hh.

Member Typedef Documentation

◆ BpId

using gem5::Iris::ThreadContext::BpId = uint64_t

protected

Definition at line 116 of file thread_context.hh.

◆ BpInfoIt

using gem5::Iris::ThreadContext::BpInfoIt = BpInfoMap::iterator

protected

Definition at line 133 of file thread_context.hh.

◆ BpInfoMap

using gem5::Iris::ThreadContext::BpInfoMap = std::map<Addr, BpInfoPtr>

protected

Definition at line 132 of file thread_context.hh.

◆ BpInfoPtr

using gem5::Iris::ThreadContext::BpInfoPtr = std::unique_ptr<BpInfo>

protected

Definition at line 131 of file thread_context.hh.

◆ IdxNameMap

typedef std::map<int, std::string> gem5::Iris::ThreadContext::IdxNameMap

Definition at line 59 of file thread_context.hh.

◆ MemorySpaceMap

typedef std::unordered_map<Iris::CanonicalMsn, iris::MemorySpaceId> gem5::Iris::ThreadContext::MemorySpaceMap

Definition at line 62 of file thread_context.hh.

◆ ResourceIds

typedef std::vector<iris::ResourceId> gem5::Iris::ThreadContext::ResourceIds

Definition at line 58 of file thread_context.hh.

◆ ResourceMap

typedef std::map<std::string, iris::ResourceInfo> gem5::Iris::ThreadContext::ResourceMap

Definition at line 56 of file thread_context.hh.

Constructor & Destructor Documentation

◆ ThreadContext()

gem5::Iris::ThreadContext::ThreadContext	(	gem5::BaseCPU *	cpu,
		int	id,
		System *	system,
		gem5::BaseMMU *	mmu,
		gem5::BaseISA *	isa,
		iris::IrisConnectionInterface *	iris_if,
		const std::string &	iris_path
	)

Definition at line 327 of file thread_context.cc.

References _instId, breakpointEventStreamId, call(), client, enableAfterPseudoEvent, initEventStreamId, noThrow(), regEventStreamId, semihostingEventStreamId, gem5::EventBase::Sim_Exit_Pri, and timeEventStreamId.

◆ ~ThreadContext()

gem5::Iris::ThreadContext::~ThreadContext ( )

virtual

Reimplemented from gem5::ThreadContext.

Definition at line 394 of file thread_context.cc.

References call(), client, gem5::EventManager::deschedule(), enableAfterPseudoEvent, getCpuPtr(), initEventStreamId, regEventStreamId, gem5::Event::scheduled(), and timeEventStreamId.

Member Function Documentation

◆ activate()

void gem5::Iris::ThreadContext::activate ( )

inlineoverridevirtual

Set the status to Active.

Implements gem5::ThreadContext.

Definition at line 243 of file thread_context.hh.

References gem5::ThreadContext::Active, and setStatus().

◆ breakpointHit()

iris::IrisErrorCode gem5::Iris::ThreadContext::breakpointHit	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 285 of file thread_context.cc.

References gem5::ArmISA::e, getOrAllocBp(), and pc.

◆ call()

iris::IrisCppAdapter& gem5::Iris::ThreadContext::call ( ) const

inlineprotected

◆ clearArchRegs()

void gem5::Iris::ThreadContext::clearArchRegs ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 274 of file thread_context.hh.

References warn.

◆ contextId()

int gem5::Iris::ThreadContext::contextId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 204 of file thread_context.hh.

References _contextId.

◆ copyArchRegs()

void gem5::Iris::ThreadContext::copyArchRegs ( gem5::ThreadContext * tc )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 268 of file thread_context.hh.

References panic.

◆ cpuId()

int gem5::Iris::ThreadContext::cpuId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 198 of file thread_context.hh.

References _cpu, and gem5::BaseCPU::cpuId().

◆ delBp()

void gem5::Iris::ThreadContext::delBp ( BpInfoIt it )

protected

Definition at line 199 of file thread_context.cc.

References bps, panic_if, and uninstallBp().

Referenced by remove().

◆ descheduleInstCountEvent()

void gem5::Iris::ThreadContext::descheduleInstCountEvent ( Event * event )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 503 of file thread_context.cc.

References comInstEventQueue, gem5::EventQueue::deschedule(), gem5::MipsISA::event, and maintainStepping().

◆ extractResourceId()

iris::ResourceId gem5::Iris::ThreadContext::extractResourceId	(	const ResourceMap &	resources,
		const std::string &	name
	)

protected

Definition at line 107 of file thread_context.cc.

References name().

Referenced by extractResourceMap(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and gem5::fastmodel::CortexR52TC::initFromIrisInstance().

◆ extractResourceMap()

void gem5::Iris::ThreadContext::extractResourceMap	(	ResourceIds &	ids,
		const ResourceMap &	resources,
		const IdxNameMap &	idx_names
	)

protected

Definition at line 114 of file thread_context.cc.

References extractResourceId(), gem5::ArmISA::ids, and name().

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and gem5::fastmodel::CortexR52TC::initFromIrisInstance().

◆ getBpSpaceIds()

virtual const std::vector<iris::MemorySpaceId>& gem5::Iris::ThreadContext::getBpSpaceIds ( ) const

protectedpure virtual

Implemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

Referenced by installBp().

◆ getCCRegFlatRscId()

iris::ResourceId gem5::Iris::ThreadContext::getCCRegFlatRscId ( RegIndex cc_reg ) const

Definition at line 848 of file thread_context.cc.

References ccRegIds.

Referenced by readCCRegFlat(), and setCCRegFlat().

◆ getCheckerCpuPtr()

CheckerCPU* gem5::Iris::ThreadContext::getCheckerCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 213 of file thread_context.hh.

◆ getCpuPtr()

gem5::BaseCPU* gem5::Iris::ThreadContext::getCpuPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 197 of file thread_context.hh.

References _cpu.

Referenced by semihostingEvent(), setStatus(), and ~ThreadContext().

◆ getCurrentInstCount()

Tick gem5::Iris::ThreadContext::getCurrentInstCount ( )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 510 of file thread_context.cc.

References _instId, call(), gem5::X86ISA::count, and panic_if.

Referenced by maintainStepping(), and scheduleInstCountEvent().

◆ getDecoderPtr()

InstDecoder* gem5::Iris::ThreadContext::getDecoderPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 215 of file thread_context.hh.

References panic.

◆ getHtmCheckpointPtr()

BaseHTMCheckpointPtr& gem5::Iris::ThreadContext::getHtmCheckpointPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 447 of file thread_context.hh.

References panic.

◆ getIntRegFlatRscId()

iris::ResourceId gem5::Iris::ThreadContext::getIntRegFlatRscId ( RegIndex int_reg ) const

Flat register interfaces.

Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.

Definition at line 813 of file thread_context.cc.

References flattenedIntIds.

Referenced by readIntRegFlat(), and setIntRegFlat().

◆ getIntRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getIntRegRscId ( RegIndex int_reg ) const

Definition at line 783 of file thread_context.cc.

References intReg32Ids, intReg64Ids, gem5::ArmISA::intRegClass, gem5::ArmISA::MISCREG_CPSR, panic_if, and readMiscRegNoEffect().

Referenced by readIntReg(), and setIntReg().

◆ getIsaPtr()

BaseISA* gem5::Iris::ThreadContext::getIsaPtr ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 223 of file thread_context.hh.

References _isa.

◆ getMemorySpaceId()

iris::MemorySpaceId gem5::Iris::ThreadContext::getMemorySpaceId ( const Iris::CanonicalMsn & msn ) const

protected

Definition at line 130 of file thread_context.cc.

References memorySpaceIds.

Referenced by gem5::fastmodel::CortexA76TC::getBpSpaceIds(), gem5::fastmodel::CortexR52TC::getBpSpaceIds(), readMemWithCurrentMsn(), gem5::fastmodel::CortexR52TC::sendFunctional(), sendFunctional(), gem5::fastmodel::CortexA76TC::translateAddress(), and writeMemWithCurrentMsn().

◆ getMiscRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getMiscRegRscId ( RegIndex misc_reg ) const

Definition at line 608 of file thread_context.cc.

References gem5::ArmISA::miscRegClass, miscRegIds, and panic_if.

Referenced by readMiscRegNoEffect(), and setMiscRegNoEffect().

◆ getMMUPtr()

BaseMMU* gem5::Iris::ThreadContext::getMMUPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 208 of file thread_context.hh.

References _mmu.

◆ getOrAllocBp()

ThreadContext::BpInfoIt gem5::Iris::ThreadContext::getOrAllocBp ( Addr pc )

protected

Definition at line 166 of file thread_context.cc.

References bps, panic_if, and pc.

Referenced by breakpointHit(), remove(), and schedule().

◆ getProcessPtr()

Process* gem5::Iris::ThreadContext::getProcessPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 231 of file thread_context.hh.

References panic.

◆ getReg() [1/2]

RegVal gem5::Iris::ThreadContext::getReg ( const RegId & reg ) const

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 636 of file thread_context.cc.

References gem5::X86ISA::reg, and gem5::X86ISA::val.

◆ getReg() [2/2]

void gem5::Iris::ThreadContext::getReg	(	const RegId &	reg,
		void *	val
	)		const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 650 of file thread_context.cc.

References gem5::CCRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, readCCReg(), readCCRegFlat(), readIntReg(), readIntRegFlat(), readVecElem(), readVecElemFlat(), readVecPredReg(), readVecPredRegFlat(), readVecReg(), readVecRegFlat(), gem5::X86ISA::reg, gem5::X86ISA::type, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ getSystemPtr()

System* gem5::Iris::ThreadContext::getSystemPtr ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 220 of file thread_context.hh.

References _cpu, and gem5::BaseCPU::system.

◆ getVecPredRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getVecPredRegRscId ( RegIndex vec_reg ) const

Definition at line 917 of file thread_context.cc.

References vecPredRegIds.

Referenced by readVecPredReg().

◆ getVecRegRscId()

iris::ResourceId gem5::Iris::ThreadContext::getVecRegRscId ( RegIndex vec_reg ) const

Definition at line 879 of file thread_context.cc.

References vecRegIds.

Referenced by readVecReg().

◆ getWritableReg()

void * gem5::Iris::ThreadContext::getWritableReg ( const RegId & reg )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 756 of file thread_context.cc.

References getWritableVecPredReg(), getWritableVecPredRegFlat(), getWritableVecReg(), getWritableVecRegFlat(), panic, gem5::X86ISA::reg, gem5::X86ISA::type, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ getWritableVecPredReg()

virtual ArmISA::VecPredRegContainer& gem5::Iris::ThreadContext::getWritableVecPredReg ( const RegId & reg )

inlinevirtual

Definition at line 310 of file thread_context.hh.

References panic.

Referenced by getWritableReg().

◆ getWritableVecPredRegFlat()

virtual ArmISA::VecPredRegContainer& gem5::Iris::ThreadContext::getWritableVecPredRegFlat ( RegIndex idx )

inlinevirtual

Definition at line 423 of file thread_context.hh.

References panic.

Referenced by getWritableReg().

◆ getWritableVecReg()

virtual ArmISA::VecRegContainer& gem5::Iris::ThreadContext::getWritableVecReg ( const RegId & reg )

inlinevirtual

Definition at line 295 of file thread_context.hh.

References panic.

Referenced by getWritableReg().

◆ getWritableVecRegFlat()

virtual ArmISA::VecRegContainer& gem5::Iris::ThreadContext::getWritableVecRegFlat ( RegIndex idx )

inlinevirtual

Definition at line 400 of file thread_context.hh.

References panic.

Referenced by getWritableReg().

◆ halt()

void gem5::Iris::ThreadContext::halt ( )

inlineoverridevirtual

Set the status to Halted.

Implements gem5::ThreadContext.

Definition at line 245 of file thread_context.hh.

References gem5::ThreadContext::Halted, and setStatus().

◆ htmAbortTransaction()

void gem5::Iris::ThreadContext::htmAbortTransaction	(	uint64_t	htm_uid,
		HtmFailureFaultCause	cause
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 441 of file thread_context.hh.

References panic.

◆ initFromIrisInstance()

void gem5::Iris::ThreadContext::initFromIrisInstance ( const ResourceMap & resources )

protectedvirtual

Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

Definition at line 66 of file thread_context.cc.

References _instId, _status, gem5::ThreadContext::Active, bps, breakpointEventStreamId, call(), client, gem5::statistics::enabled(), installBp(), memorySpaceIds, memorySpaces, semihostingEventStreamId, suspend(), gem5::ThreadContext::Suspended, and translations.

Referenced by phaseInitLeave().

◆ installBp()

void gem5::Iris::ThreadContext::installBp ( BpInfoIt it )

protected

Definition at line 179 of file thread_context.cc.

References _instId, call(), getBpSpaceIds(), gem5::ArmISA::id, and pc.

Referenced by initFromIrisInstance(), and schedule().

◆ instanceRegistryChanged()

iris::IrisErrorCode gem5::Iris::ThreadContext::instanceRegistryChanged	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 211 of file thread_context.cc.

References _instId, _irisPath, gem5::MipsISA::event, gem5::ArmISA::id, name(), and panic.

◆ maintainStepping()

void gem5::Iris::ThreadContext::maintainStepping ( )

protected

Definition at line 137 of file thread_context.cc.

References _instId, call(), comInstEventQueue, gem5::EventQueue::empty(), getCurrentInstCount(), gem5::EventQueue::nextTick(), and gem5::EventQueue::serviceEvents().

Referenced by descheduleInstCountEvent(), scheduleInstCountEvent(), and simulationTimeEvent().

◆ noThrow()

iris::IrisCppAdapter& gem5::Iris::ThreadContext::noThrow ( ) const

inlineprotected

Definition at line 170 of file thread_context.hh.

References client.

Referenced by ThreadContext(), and translateAddress().

◆ pcState() [1/2]

const PCStateBase & gem5::Iris::ThreadContext::pcState ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 571 of file thread_context.cc.

References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::itState(), gem5::ArmISA::MISCREG_CPSR, pc, pcRscId, and readMiscRegNoEffect().

Referenced by pcStateNoRecord().

◆ pcState() [2/2]

void gem5::Iris::ThreadContext::pcState ( const PCStateBase & val )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 595 of file thread_context.cc.

References _instId, call(), gem5::ArmISA::MISCREG_CPSR, pc, pcRscId, readMiscRegNoEffect(), and gem5::X86ISA::val.

◆ pcStateNoRecord()

void gem5::Iris::ThreadContext::pcStateNoRecord ( const PCStateBase & val )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 348 of file thread_context.hh.

References pcState(), and gem5::X86ISA::val.

◆ phaseInitLeave()

iris::IrisErrorCode gem5::Iris::ThreadContext::phaseInitLeave	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 233 of file thread_context.cc.

References _instId, call(), initFromIrisInstance(), and name().

◆ readCCReg()

virtual RegVal gem5::Iris::ThreadContext::readCCReg ( RegIndex reg_idx ) const

inlinevirtual

Definition at line 316 of file thread_context.hh.

References readCCRegFlat().

Referenced by getReg().

◆ readCCRegFlat()

RegVal gem5::Iris::ThreadContext::readCCRegFlat ( RegIndex idx ) const

virtual

Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

Definition at line 857 of file thread_context.cc.

References _instId, call(), and getCCRegFlatRscId().

Referenced by getReg(), readCCReg(), gem5::fastmodel::CortexA76TC::readCCRegFlat(), and gem5::fastmodel::CortexR52TC::readCCRegFlat().

◆ readIntReg()

RegVal gem5::Iris::ThreadContext::readIntReg ( RegIndex reg_idx ) const

virtual

Reimplemented in gem5::fastmodel::CortexR52TC.

Definition at line 798 of file thread_context.cc.

References _instId, call(), and getIntRegRscId().

Referenced by getReg(), and semihostingEvent().

◆ readIntRegFlat()

RegVal gem5::Iris::ThreadContext::readIntRegFlat ( RegIndex idx ) const

virtual

Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

Definition at line 826 of file thread_context.cc.

References _instId, call(), and getIntRegFlatRscId().

Referenced by getReg().

◆ readLastActivate()

Tick gem5::Iris::ThreadContext::readLastActivate ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 258 of file thread_context.hh.

References panic.

◆ readLastSuspend()

Tick gem5::Iris::ThreadContext::readLastSuspend ( )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 262 of file thread_context.hh.

References panic.

◆ readMem()

void gem5::Iris::ThreadContext::readMem	(	iris::MemorySpaceId	space,
		Addr	addr,
		void *	p,
		size_t	size
	)

protected

Definition at line 441 of file thread_context.cc.

References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::err, gem5::VegaISA::p, panic_if, and gem5::VegaISA::r.

Referenced by readMemWithCurrentMsn(), gem5::fastmodel::CortexR52TC::sendFunctional(), and sendFunctional().

◆ readMemWithCurrentMsn()

void gem5::Iris::ThreadContext::readMemWithCurrentMsn	(	Addr	vaddr,
		size_t	size,
		char *	data
	)

Definition at line 537 of file thread_context.cc.

References gem5::Iris::CurrentMsn, data, getMemorySpaceId(), readMem(), and gem5::MipsISA::vaddr.

◆ readMiscReg()

RegVal gem5::Iris::ThreadContext::readMiscReg ( RegIndex misc_reg )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 356 of file thread_context.hh.

References readMiscRegNoEffect().

◆ readMiscRegNoEffect()

RegVal gem5::Iris::ThreadContext::readMiscRegNoEffect ( RegIndex misc_reg ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 621 of file thread_context.cc.

References _instId, call(), and getMiscRegRscId().

Referenced by getIntRegRscId(), pcState(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), readMiscReg(), gem5::fastmodel::CortexR52TC::readMiscRegNoEffect(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), and gem5::fastmodel::CortexA76TC::setIntRegFlat().

◆ readStCondFailures()

unsigned gem5::Iris::ThreadContext::readStCondFailures ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 371 of file thread_context.hh.

References panic.

◆ readVecElem()

virtual RegVal gem5::Iris::ThreadContext::readVecElem ( const RegId & reg ) const

inlinevirtual

Definition at line 301 of file thread_context.hh.

References panic.

Referenced by getReg().

◆ readVecElemFlat()

virtual RegVal gem5::Iris::ThreadContext::readVecElemFlat ( RegIndex idx ) const

inlinevirtual

Definition at line 411 of file thread_context.hh.

References panic.

Referenced by getReg().

◆ readVecPredReg()

const ArmISA::VecPredRegContainer & gem5::Iris::ThreadContext::readVecPredReg ( const RegId & reg ) const

virtual

Definition at line 926 of file thread_context.cc.

References _instId, call(), getVecPredRegRscId(), gem5::RegId::index(), gem5::ArmISA::offset, gem5::X86ISA::reg, and vecPredRegs.

Referenced by getReg(), and readVecPredRegFlat().

◆ readVecPredRegFlat()

ArmISA::VecPredRegContainer gem5::Iris::ThreadContext::readVecPredRegFlat ( RegIndex idx ) const

virtual

Definition at line 956 of file thread_context.cc.

References readVecPredReg(), and gem5::ArmISA::vecPredRegClass.

Referenced by getReg().

◆ readVecReg()

const ArmISA::VecRegContainer & gem5::Iris::ThreadContext::readVecReg ( const RegId & reg ) const

virtual

Reimplemented in gem5::fastmodel::CortexR52TC.

Definition at line 888 of file thread_context.cc.

References _instId, call(), getVecRegRscId(), gem5::RegId::index(), gem5::X86ISA::reg, and vecRegs.

Referenced by getReg(), and readVecRegFlat().

◆ readVecRegFlat()

const ArmISA::VecRegContainer & gem5::Iris::ThreadContext::readVecRegFlat ( RegIndex idx ) const

virtual

Definition at line 911 of file thread_context.cc.

References readVecReg(), and gem5::ArmISA::vecRegClass.

Referenced by getReg().

◆ regStats()

void gem5::Iris::ThreadContext::regStats ( const std::string & name )

inlineoverridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 253 of file thread_context.hh.

◆ remove()

bool gem5::Iris::ThreadContext::remove ( PCEvent * e )

overridevirtual

Implements gem5::PCEventScope.

Definition at line 429 of file thread_context.cc.

References delBp(), gem5::ArmISA::e, and getOrAllocBp().

◆ schedule()

bool gem5::Iris::ThreadContext::schedule ( PCEvent * e )

overridevirtual

Implements gem5::PCEventScope.

Definition at line 417 of file thread_context.cc.

References _instId, gem5::ArmISA::e, getOrAllocBp(), and installBp().

◆ scheduleInstCountEvent()

void gem5::Iris::ThreadContext::scheduleInstCountEvent	(	Event *	event,
		Tick	count
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 492 of file thread_context.cc.

References call(), comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, getCurrentInstCount(), maintainStepping(), and gem5::EventQueue::schedule().

◆ semihostingEvent()

iris::IrisErrorCode gem5::Iris::ThreadContext::semihostingEvent	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 306 of file thread_context.cc.

References _instId, call(), gem5::ArmSystem::callSemihosting(), gem5::curTick(), enableAfterPseudoEvent, getCpuPtr(), readIntReg(), gem5::EventManager::schedule(), and gem5::Event::scheduled().

◆ sendFunctional()

void gem5::Iris::ThreadContext::sendFunctional ( PacketPtr pkt )

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 519 of file thread_context.cc.

References gem5::X86ISA::addr, data, gem5::Packet::getAddr(), getMemorySpaceId(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::Packet::isRead(), gem5::ArmISA::isSecure(), gem5::Packet::makeResponse(), gem5::Iris::PhysicalMemoryNonSecureMsn, gem5::Iris::PhysicalMemorySecureMsn, readMem(), and writeMem().

◆ setCCReg()

virtual void gem5::Iris::ThreadContext::setCCReg	(	RegIndex	reg_idx,
		RegVal	val
	)

inlinevirtual

Definition at line 343 of file thread_context.hh.

References setCCRegFlat(), and gem5::X86ISA::val.

Referenced by setReg().

◆ setCCRegFlat()

void gem5::Iris::ThreadContext::setCCRegFlat	(	RegIndex	idx,
		RegVal	val
	)

virtual

Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

Definition at line 868 of file thread_context.cc.

References _instId, call(), gem5::ArmISA::ccRegClass(), getCCRegFlatRscId(), panic_if, and gem5::X86ISA::val.

Referenced by setCCReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), and setReg().

◆ setContextId()

void gem5::Iris::ThreadContext::setContextId ( int id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 205 of file thread_context.hh.

References _contextId, and gem5::ArmISA::id.

◆ setHtmCheckpointPtr()

void gem5::Iris::ThreadContext::setHtmCheckpointPtr ( BaseHTMCheckpointPtr cpt )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 453 of file thread_context.hh.

References panic.

◆ setIntReg()

void gem5::Iris::ThreadContext::setIntReg	(	RegIndex	reg_idx,
		RegVal	val
	)

virtual

Reimplemented in gem5::fastmodel::CortexR52TC.

Definition at line 806 of file thread_context.cc.

References _instId, call(), getIntRegRscId(), and gem5::X86ISA::val.

Referenced by setReg().

◆ setIntRegFlat()

void gem5::Iris::ThreadContext::setIntRegFlat	(	RegIndex	idx,
		uint64_t	val
	)

virtual

Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

Definition at line 837 of file thread_context.cc.

References _instId, call(), getIntRegFlatRscId(), gem5::ArmISA::intRegClass, panic_if, and gem5::X86ISA::val.

Referenced by setReg().

◆ setMiscReg()

void gem5::Iris::ThreadContext::setMiscReg	(	RegIndex	misc_reg,
		const RegVal	val
	)

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 363 of file thread_context.hh.

References setMiscRegNoEffect(), and gem5::X86ISA::val.

Referenced by gem5::fastmodel::CortexA76TC::setIntRegFlat().

◆ setMiscRegNoEffect()

void gem5::Iris::ThreadContext::setMiscRegNoEffect	(	RegIndex	misc_reg,
		const RegVal	val
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 629 of file thread_context.cc.

References _instId, call(), getMiscRegRscId(), and gem5::X86ISA::val.

Referenced by setMiscReg(), and gem5::fastmodel::CortexR52TC::setMiscRegNoEffect().

◆ setProcessPtr()

void gem5::Iris::ThreadContext::setProcessPtr ( Process * p )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 236 of file thread_context.hh.

References panic.

◆ setReg() [1/2]

void gem5::Iris::ThreadContext::setReg	(	const RegId &	reg,
		const void *	val
	)

overridevirtual

Implements gem5::ThreadContext.

Definition at line 703 of file thread_context.cc.

References gem5::CCRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, gem5::X86ISA::reg, setCCReg(), setCCRegFlat(), setIntReg(), setIntRegFlat(), setVecElem(), setVecElemFlat(), setVecPredReg(), setVecPredRegFlat(), setVecReg(), setVecRegFlat(), gem5::X86ISA::type, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.

◆ setReg() [2/2]

void gem5::Iris::ThreadContext::setReg	(	const RegId &	reg,
		RegVal	val
	)

overridevirtual

Reimplemented from gem5::ThreadContext.

Definition at line 644 of file thread_context.cc.

References gem5::X86ISA::reg, and gem5::X86ISA::val.

◆ setStatus()

void gem5::Iris::ThreadContext::setStatus ( Status new_status )

overridevirtual

Implements gem5::ThreadContext.

Definition at line 556 of file thread_context.cc.

References _instId, _status, gem5::ThreadContext::Active, call(), gem5::EventManager::deschedule(), enableAfterPseudoEvent, getCpuPtr(), and gem5::Event::scheduled().

Referenced by activate(), halt(), and suspend().

◆ setStCondFailures()

void gem5::Iris::ThreadContext::setStCondFailures ( unsigned sc_failures )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 377 of file thread_context.hh.

References panic.

◆ setThreadId()

void gem5::Iris::ThreadContext::setThreadId ( int id )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 202 of file thread_context.hh.

References _threadId, and gem5::ArmISA::id.

◆ setVecElem()

virtual void gem5::Iris::ThreadContext::setVecElem	(	const RegId &	reg,
		RegVal	val
	)

inlinevirtual

Definition at line 330 of file thread_context.hh.

References panic.

Referenced by setReg().

◆ setVecElemFlat()

virtual void gem5::Iris::ThreadContext::setVecElemFlat	(	RegIndex	idx,
		RegVal	val
	)

inlinevirtual

Definition at line 416 of file thread_context.hh.

References panic.

Referenced by setReg().

◆ setVecPredReg()

virtual void gem5::Iris::ThreadContext::setVecPredReg	(	const RegId &	reg,
		const ArmISA::VecPredRegContainer &	val
	)

inlinevirtual

Definition at line 336 of file thread_context.hh.

References panic.

Referenced by setReg().

◆ setVecPredRegFlat()

virtual void gem5::Iris::ThreadContext::setVecPredRegFlat	(	RegIndex	idx,
		const ArmISA::VecPredRegContainer &	val
	)

inlinevirtual

Definition at line 428 of file thread_context.hh.

References panic.

Referenced by setReg().

◆ setVecReg()

virtual void gem5::Iris::ThreadContext::setVecReg	(	const RegId &	reg,
		const ArmISA::VecRegContainer &	val
	)

inlinevirtual

Definition at line 324 of file thread_context.hh.

References panic.

Referenced by setReg().

◆ setVecRegFlat()

virtual void gem5::Iris::ThreadContext::setVecRegFlat	(	RegIndex	idx,
		const ArmISA::VecRegContainer &	val
	)

inlinevirtual

Definition at line 405 of file thread_context.hh.

References panic.

Referenced by setReg().

◆ simulationTimeEvent()

iris::IrisErrorCode gem5::Iris::ThreadContext::simulationTimeEvent	(	uint64_t	esId,
		const iris::IrisValueMap &	fields,
		uint64_t	time,
		uint64_t	sInstId,
		bool	syncEc,
		std::string &	error_message_out
	)

protected

Definition at line 263 of file thread_context.cc.

References call(), and maintainStepping().

◆ socketId()

uint32_t gem5::Iris::ThreadContext::socketId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 199 of file thread_context.hh.

References _cpu, and gem5::BaseCPU::socketId().

◆ status()

ThreadContext::Status gem5::Iris::ThreadContext::status ( ) const

overridevirtual

Implements gem5::ThreadContext.

Definition at line 550 of file thread_context.cc.

References _status.

◆ suspend()

void gem5::Iris::ThreadContext::suspend ( )

inlineoverridevirtual

Set the status to Suspended.

Implements gem5::ThreadContext.

Definition at line 244 of file thread_context.hh.

References setStatus(), and gem5::ThreadContext::Suspended.

Referenced by initFromIrisInstance().

◆ takeOverFrom()

void gem5::Iris::ThreadContext::takeOverFrom ( gem5::ThreadContext * old_context )

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 248 of file thread_context.hh.

References panic.

◆ threadId()

int gem5::Iris::ThreadContext::threadId ( ) const

inlineoverridevirtual

Implements gem5::ThreadContext.

Definition at line 201 of file thread_context.hh.

References _threadId.

◆ translateAddress() [1/2]

virtual bool gem5::Iris::ThreadContext::translateAddress	(	Addr &	paddr,
		Addr	vaddr
	)

pure virtual

Implemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.

◆ translateAddress() [2/2]

bool gem5::Iris::ThreadContext::translateAddress	(	Addr &	paddr,
		iris::MemorySpaceId	p_space,
		Addr	vaddr,
		iris::MemorySpaceId	v_space
	)

protected

Definition at line 462 of file thread_context.cc.

References _instId, noThrow(), panic, translations, gem5::MipsISA::vaddr, and warn.

◆ uninstallBp()

void gem5::Iris::ThreadContext::uninstallBp ( BpInfoIt it )

protected

Definition at line 191 of file thread_context.cc.

References _instId, and call().

Referenced by delBp().

◆ writeMem()

void gem5::Iris::ThreadContext::writeMem	(	iris::MemorySpaceId	space,
		Addr	addr,
		const void *	p,
		size_t	size
	)

protected

Definition at line 451 of file thread_context.cc.

References _instId, gem5::X86ISA::addr, call(), data, gem5::ArmISA::err, gem5::VegaISA::p, panic_if, and gem5::VegaISA::r.

Referenced by gem5::fastmodel::CortexR52TC::sendFunctional(), sendFunctional(), and writeMemWithCurrentMsn().

◆ writeMemWithCurrentMsn()

void gem5::Iris::ThreadContext::writeMemWithCurrentMsn	(	Addr	vaddr,
		size_t	size,
		const char *	data
	)

Definition at line 543 of file thread_context.cc.

References gem5::Iris::CurrentMsn, data, getMemorySpaceId(), gem5::MipsISA::vaddr, and writeMem().

Member Data Documentation

◆ _contextId

ContextID gem5::Iris::ThreadContext::_contextId

protected

Definition at line 67 of file thread_context.hh.

Referenced by contextId(), and setContextId().

◆ _cpu

gem5::BaseCPU* gem5::Iris::ThreadContext::_cpu

protected

Definition at line 65 of file thread_context.hh.

Referenced by cpuId(), getCpuPtr(), getSystemPtr(), and socketId().

◆ _instId

iris::InstanceId gem5::Iris::ThreadContext::_instId = iris::IRIS_UINT64_MAX

protected

◆ _irisPath

std::string gem5::Iris::ThreadContext::_irisPath

protected

Definition at line 72 of file thread_context.hh.

Referenced by instanceRegistryChanged().

◆ _isa

gem5::BaseISA* gem5::Iris::ThreadContext::_isa

protected

Definition at line 70 of file thread_context.hh.

Referenced by getIsaPtr().

◆ _mmu

gem5::BaseMMU* gem5::Iris::ThreadContext::_mmu

protected

Definition at line 69 of file thread_context.hh.

Referenced by getMMUPtr().

◆ _status

Status gem5::Iris::ThreadContext::_status = Active

protected

Definition at line 80 of file thread_context.hh.

Referenced by initFromIrisInstance(), setStatus(), and status().

◆ _system

System* gem5::Iris::ThreadContext::_system

protected

Definition at line 68 of file thread_context.hh.

◆ _threadId

int gem5::Iris::ThreadContext::_threadId

protected

Definition at line 66 of file thread_context.hh.

Referenced by setThreadId(), and threadId().

◆ bps

BpInfoMap gem5::Iris::ThreadContext::bps

protected

Definition at line 135 of file thread_context.hh.

Referenced by delBp(), getOrAllocBp(), and initFromIrisInstance().

◆ breakpointEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::breakpointEventStreamId

protected

Definition at line 165 of file thread_context.hh.

Referenced by initFromIrisInstance(), and ThreadContext().

◆ ccRegIds

ResourceIds gem5::Iris::ThreadContext::ccRegIds

protected

Definition at line 96 of file thread_context.hh.

Referenced by getCCRegFlatRscId(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and gem5::fastmodel::CortexR52TC::initFromIrisInstance().

◆ client

iris::IrisInstance gem5::Iris::ThreadContext::client

mutableprotected

Definition at line 168 of file thread_context.hh.

Referenced by call(), initFromIrisInstance(), noThrow(), ThreadContext(), and ~ThreadContext().

◆ comInstEventQueue

EventQueue gem5::Iris::ThreadContext::comInstEventQueue

protected

Definition at line 109 of file thread_context.hh.

Referenced by descheduleInstCountEvent(), maintainStepping(), and scheduleInstCountEvent().

◆ enableAfterPseudoEvent

Event* gem5::Iris::ThreadContext::enableAfterPseudoEvent

protected

Definition at line 81 of file thread_context.hh.

Referenced by semihostingEvent(), setStatus(), ThreadContext(), and ~ThreadContext().

◆ flattenedIntIds

ResourceIds gem5::Iris::ThreadContext::flattenedIntIds

protected

Definition at line 95 of file thread_context.hh.

Referenced by getIntRegFlatRscId(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().

◆ icountRscId

iris::ResourceId gem5::Iris::ThreadContext::icountRscId

protected

Definition at line 99 of file thread_context.hh.

◆ initEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::initEventStreamId

protected

Definition at line 163 of file thread_context.hh.

Referenced by ThreadContext(), and ~ThreadContext().

◆ intReg32Ids

ResourceIds gem5::Iris::ThreadContext::intReg32Ids

protected

Definition at line 93 of file thread_context.hh.

Referenced by getIntRegRscId(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexR52TC::readIntReg(), and gem5::fastmodel::CortexR52TC::setIntReg().

◆ intReg64Ids

ResourceIds gem5::Iris::ThreadContext::intReg64Ids

protected

Definition at line 94 of file thread_context.hh.

Referenced by getIntRegRscId(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().

◆ memorySpaceIds

MemorySpaceMap gem5::Iris::ThreadContext::memorySpaceIds

protected

Definition at line 106 of file thread_context.hh.

Referenced by getMemorySpaceId(), and initFromIrisInstance().

◆ memorySpaces

std::vector<iris::MemorySpaceInfo> gem5::Iris::ThreadContext::memorySpaces

protected

Definition at line 104 of file thread_context.hh.

Referenced by initFromIrisInstance().

◆ miscRegIds

ResourceIds gem5::Iris::ThreadContext::miscRegIds

protected

Definition at line 92 of file thread_context.hh.

Referenced by getMiscRegRscId(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and gem5::fastmodel::CortexR52TC::initFromIrisInstance().

◆ pc

ArmISA::PCState gem5::Iris::ThreadContext::pc

mutableprotected

Definition at line 172 of file thread_context.hh.

Referenced by breakpointHit(), getOrAllocBp(), installBp(), and pcState().

◆ pcRscId

iris::ResourceId gem5::Iris::ThreadContext::pcRscId = iris::IRIS_UINT64_MAX

protected

Definition at line 98 of file thread_context.hh.

Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), gem5::fastmodel::CortexR52TC::initFromIrisInstance(), and pcState().

◆ regEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::regEventStreamId

protected

Definition at line 162 of file thread_context.hh.

Referenced by ThreadContext(), and ~ThreadContext().

◆ semihostingEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::semihostingEventStreamId

protected

Definition at line 166 of file thread_context.hh.

Referenced by initFromIrisInstance(), and ThreadContext().

◆ timeEventStreamId

iris::EventStreamId gem5::Iris::ThreadContext::timeEventStreamId

protected

Definition at line 164 of file thread_context.hh.

Referenced by ThreadContext(), and ~ThreadContext().

◆ translations

std::vector<iris::MemorySupportedAddressTranslationResult> gem5::Iris::ThreadContext::translations

protected

Definition at line 105 of file thread_context.hh.

Referenced by initFromIrisInstance(), and translateAddress().

◆ vecPredRegIds

ResourceIds gem5::Iris::ThreadContext::vecPredRegIds

protected

Definition at line 102 of file thread_context.hh.

Referenced by getVecPredRegRscId().

◆ vecPredRegs

std::vector<ArmISA::VecPredRegContainer> gem5::Iris::ThreadContext::vecPredRegs

mutableprotected

Definition at line 78 of file thread_context.hh.

Referenced by readVecPredReg().

◆ vecRegIds

ResourceIds gem5::Iris::ThreadContext::vecRegIds

protected

Definition at line 101 of file thread_context.hh.

Referenced by getVecRegRscId(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().

◆ vecRegs

std::vector<ArmISA::VecRegContainer> gem5::Iris::ThreadContext::vecRegs

mutableprotected

Definition at line 77 of file thread_context.hh.

Referenced by readVecReg().

The documentation for this class was generated from the following files:

arch/arm/fastmodel/iris/thread_context.hh
arch/arm/fastmodel/iris/thread_context.cc

Classes

Public Types

Public Member Functions

Protected Types

Protected Member Functions

Protected Attributes

Additional Inherited Members

Detailed Description

Member Typedef Documentation

◆ BpId

◆ BpInfoIt

◆ BpInfoMap

◆ BpInfoPtr

◆ IdxNameMap

◆ MemorySpaceMap

◆ ResourceIds

◆ ResourceMap

Constructor & Destructor Documentation

◆ ThreadContext()

◆ ~ThreadContext()

Member Function Documentation

◆ activate()

◆ breakpointHit()

◆ call()

◆ clearArchRegs()

◆ contextId()

◆ copyArchRegs()

◆ cpuId()

◆ delBp()

◆ descheduleInstCountEvent()

◆ extractResourceId()

◆ extractResourceMap()

◆ getBpSpaceIds()

◆ getCCRegFlatRscId()

◆ getCheckerCpuPtr()

◆ getCpuPtr()

◆ getCurrentInstCount()

◆ getDecoderPtr()

◆ getHtmCheckpointPtr()

◆ getIntRegFlatRscId()

◆ getIntRegRscId()

◆ getIsaPtr()

◆ getMemorySpaceId()

◆ getMiscRegRscId()

◆ getMMUPtr()

◆ getOrAllocBp()

◆ getProcessPtr()

◆ getReg() [1/2]

◆ getReg() [2/2]

◆ getSystemPtr()

◆ getVecPredRegRscId()

◆ getVecRegRscId()

◆ getWritableReg()

◆ getWritableVecPredReg()

◆ getWritableVecPredRegFlat()

◆ getWritableVecReg()

◆ getWritableVecRegFlat()

◆ halt()

◆ htmAbortTransaction()

◆ initFromIrisInstance()

◆ installBp()

◆ instanceRegistryChanged()

◆ maintainStepping()

◆ noThrow()

◆ pcState() [1/2]

◆ pcState() [2/2]

◆ pcStateNoRecord()

◆ phaseInitLeave()

◆ readCCReg()

◆ readCCRegFlat()

◆ readIntReg()

◆ readIntRegFlat()

◆ readLastActivate()

◆ readLastSuspend()

◆ readMem()

◆ readMemWithCurrentMsn()

◆ readMiscReg()

◆ readMiscRegNoEffect()

◆ readStCondFailures()

◆ readVecElem()