gem5
v22.0.0.1
|
#include <thread_context.hh>
Classes | |
struct | BpInfo |
Public Types | |
typedef std::map< std::string, iris::ResourceInfo > | ResourceMap |
typedef std::vector< iris::ResourceId > | ResourceIds |
typedef std::map< int, std::string > | IdxNameMap |
typedef std::unordered_map< Iris::CanonicalMsn, iris::MemorySpaceId > | MemorySpaceMap |
![]() | |
enum | Status { Active, Suspended, Halting, Halted } |
Public Member Functions | |
ThreadContext (gem5::BaseCPU *cpu, int id, System *system, gem5::BaseMMU *mmu, gem5::BaseISA *isa, iris::IrisConnectionInterface *iris_if, const std::string &iris_path) | |
virtual | ~ThreadContext () |
virtual bool | translateAddress (Addr &paddr, Addr vaddr)=0 |
bool | schedule (PCEvent *e) override |
bool | remove (PCEvent *e) override |
void | scheduleInstCountEvent (Event *event, Tick count) override |
void | descheduleInstCountEvent (Event *event) override |
Tick | getCurrentInstCount () override |
gem5::BaseCPU * | getCpuPtr () override |
int | cpuId () const override |
uint32_t | socketId () const override |
int | threadId () const override |
void | setThreadId (int id) override |
int | contextId () const override |
void | setContextId (int id) override |
BaseMMU * | getMMUPtr () override |
CheckerCPU * | getCheckerCpuPtr () override |
InstDecoder * | getDecoderPtr () override |
System * | getSystemPtr () override |
BaseISA * | getIsaPtr () const override |
void | sendFunctional (PacketPtr pkt) override |
Process * | getProcessPtr () override |
void | setProcessPtr (Process *p) override |
Status | status () const override |
void | setStatus (Status new_status) override |
void | activate () override |
Set the status to Active. More... | |
void | suspend () override |
Set the status to Suspended. More... | |
void | halt () override |
Set the status to Halted. More... | |
void | takeOverFrom (gem5::ThreadContext *old_context) override |
void | regStats (const std::string &name) override |
Tick | readLastActivate () override |
Tick | readLastSuspend () override |
void | copyArchRegs (gem5::ThreadContext *tc) override |
void | clearArchRegs () override |
RegVal | getReg (const RegId ®) const override |
void | getReg (const RegId ®, void *val) const override |
void * | getWritableReg (const RegId ®) override |
void | setReg (const RegId ®, RegVal val) override |
void | setReg (const RegId ®, const void *val) override |
virtual RegVal | readIntReg (RegIndex reg_idx) const |
virtual const ArmISA::VecRegContainer & | readVecReg (const RegId ®) const |
virtual ArmISA::VecRegContainer & | getWritableVecReg (const RegId ®) |
virtual RegVal | readVecElem (const RegId ®) const |
virtual const ArmISA::VecPredRegContainer & | readVecPredReg (const RegId ®) const |
virtual ArmISA::VecPredRegContainer & | getWritableVecPredReg (const RegId ®) |
virtual RegVal | readCCReg (RegIndex reg_idx) const |
virtual void | setIntReg (RegIndex reg_idx, RegVal val) |
virtual void | setVecReg (const RegId ®, const ArmISA::VecRegContainer &val) |
virtual void | setVecElem (const RegId ®, RegVal val) |
virtual void | setVecPredReg (const RegId ®, const ArmISA::VecPredRegContainer &val) |
virtual void | setCCReg (RegIndex reg_idx, RegVal val) |
void | pcStateNoRecord (const PCStateBase &val) override |
const PCStateBase & | pcState () const override |
void | pcState (const PCStateBase &val) override |
RegVal | readMiscRegNoEffect (RegIndex misc_reg) const override |
RegVal | readMiscReg (RegIndex misc_reg) override |
void | setMiscRegNoEffect (RegIndex misc_reg, const RegVal val) override |
void | setMiscReg (RegIndex misc_reg, const RegVal val) override |
RegId | flattenRegId (const RegId ®Id) const override |
unsigned | readStCondFailures () const override |
void | setStCondFailures (unsigned sc_failures) override |
void | htmAbortTransaction (uint64_t htm_uid, HtmFailureFaultCause cause) override |
BaseHTMCheckpointPtr & | getHtmCheckpointPtr () override |
void | setHtmCheckpointPtr (BaseHTMCheckpointPtr cpt) override |
RegVal | getRegFlat (const RegId ®) const override |
Flat register interfaces. More... | |
void | getRegFlat (const RegId ®, void *val) const override |
void * | getWritableRegFlat (const RegId ®) override |
void | setRegFlat (const RegId ®, RegVal val) override |
void | setRegFlat (const RegId ®, const void *val) override |
virtual RegVal | readIntRegFlat (RegIndex idx) const |
virtual void | setIntRegFlat (RegIndex idx, uint64_t val) |
virtual const ArmISA::VecRegContainer & | readVecRegFlat (RegIndex idx) const |
virtual ArmISA::VecRegContainer & | getWritableVecRegFlat (RegIndex idx) |
virtual void | setVecRegFlat (RegIndex idx, const ArmISA::VecRegContainer &val) |
virtual RegVal | readVecElemFlat (RegIndex idx) const |
virtual void | setVecElemFlat (RegIndex idx, RegVal val) |
virtual ArmISA::VecPredRegContainer | readVecPredRegFlat (RegIndex idx) const |
virtual ArmISA::VecPredRegContainer & | getWritableVecPredRegFlat (RegIndex idx) |
virtual void | setVecPredRegFlat (RegIndex idx, const ArmISA::VecPredRegContainer &val) |
virtual RegVal | readCCRegFlat (RegIndex idx) const |
virtual void | setCCRegFlat (RegIndex idx, RegVal val) |
![]() | |
bool | getUseForClone () |
void | setUseForClone (bool new_val) |
void | quiesce () |
Quiesce thread context. More... | |
void | quiesceTick (Tick resume) |
Quiesce, suspend, and schedule activate at resume. More... | |
RegVal | readIntReg (RegIndex reg_idx) const |
RegVal | readFloatReg (RegIndex reg_idx) const |
TheISA::VecRegContainer | readVecReg (const RegId ®) const |
TheISA::VecRegContainer & | getWritableVecReg (const RegId ®) |
RegVal | readVecElem (const RegId ®) const |
RegVal | readCCReg (RegIndex reg_idx) const |
void | setIntReg (RegIndex reg_idx, RegVal val) |
void | setFloatReg (RegIndex reg_idx, RegVal val) |
void | setVecReg (const RegId ®, const TheISA::VecRegContainer &val) |
void | setVecElem (const RegId ®, RegVal val) |
void | setCCReg (RegIndex reg_idx, RegVal val) |
void | pcState (Addr addr) |
virtual int | exit () |
RegVal | readIntRegFlat (RegIndex idx) const |
void | setIntRegFlat (RegIndex idx, RegVal val) |
RegVal | readFloatRegFlat (RegIndex idx) const |
void | setFloatRegFlat (RegIndex idx, RegVal val) |
TheISA::VecRegContainer | readVecRegFlat (RegIndex idx) const |
TheISA::VecRegContainer & | getWritableVecRegFlat (RegIndex idx) |
void | setVecRegFlat (RegIndex idx, const TheISA::VecRegContainer &val) |
RegVal | readVecElemFlat (RegIndex idx) const |
void | setVecElemFlat (RegIndex idx, RegVal val) |
RegVal | readCCRegFlat (RegIndex idx) const |
void | setCCRegFlat (RegIndex idx, RegVal val) |
Protected Types | |
using | BpId = uint64_t |
using | BpInfoPtr = std::unique_ptr< BpInfo > |
using | BpInfoMap = std::map< Addr, BpInfoPtr > |
using | BpInfoIt = BpInfoMap::iterator |
Protected Member Functions | |
virtual void | initFromIrisInstance (const ResourceMap &resources) |
iris::ResourceId | extractResourceId (const ResourceMap &resources, const std::string &name) |
void | extractResourceMap (ResourceIds &ids, const ResourceMap &resources, const IdxNameMap &idx_names) |
iris::MemorySpaceId | getMemorySpaceId (const Iris::CanonicalMsn &msn) const |
void | maintainStepping () |
BpInfoIt | getOrAllocBp (Addr pc) |
void | installBp (BpInfoIt it) |
void | uninstallBp (BpInfoIt it) |
void | delBp (BpInfoIt it) |
virtual const std::vector< iris::MemorySpaceId > & | getBpSpaceIds () const =0 |
iris::IrisErrorCode | instanceRegistryChanged (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out) |
iris::IrisErrorCode | phaseInitLeave (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out) |
iris::IrisErrorCode | simulationTimeEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out) |
iris::IrisErrorCode | breakpointHit (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out) |
iris::IrisErrorCode | semihostingEvent (uint64_t esId, const iris::IrisValueMap &fields, uint64_t time, uint64_t sInstId, bool syncEc, std::string &error_message_out) |
iris::IrisCppAdapter & | call () const |
iris::IrisCppAdapter & | noThrow () const |
void | readMem (iris::MemorySpaceId space, Addr addr, void *p, size_t size) |
void | writeMem (iris::MemorySpaceId space, Addr addr, const void *p, size_t size) |
bool | translateAddress (Addr &paddr, iris::MemorySpaceId p_space, Addr vaddr, iris::MemorySpaceId v_space) |
Additional Inherited Members | |
![]() | |
static void | compare (ThreadContext *one, ThreadContext *two) |
function to compare two thread contexts (for debugging) More... | |
![]() | |
int | intResult = DefaultIntResult |
double | floatResult = DefaultFloatResult |
int | intOffset = 0 |
![]() | |
static const int | ints [] |
static const double | floats [] |
static const int | DefaultIntResult = 0 |
static const double | DefaultFloatResult = 0.0 |
Definition at line 53 of file thread_context.hh.
|
protected |
Definition at line 116 of file thread_context.hh.
|
protected |
Definition at line 133 of file thread_context.hh.
|
protected |
Definition at line 132 of file thread_context.hh.
|
protected |
Definition at line 131 of file thread_context.hh.
typedef std::map<int, std::string> gem5::Iris::ThreadContext::IdxNameMap |
Definition at line 59 of file thread_context.hh.
typedef std::unordered_map<Iris::CanonicalMsn, iris::MemorySpaceId> gem5::Iris::ThreadContext::MemorySpaceMap |
Definition at line 62 of file thread_context.hh.
typedef std::vector<iris::ResourceId> gem5::Iris::ThreadContext::ResourceIds |
Definition at line 58 of file thread_context.hh.
typedef std::map<std::string, iris::ResourceInfo> gem5::Iris::ThreadContext::ResourceMap |
Definition at line 56 of file thread_context.hh.
gem5::Iris::ThreadContext::ThreadContext | ( | gem5::BaseCPU * | cpu, |
int | id, | ||
System * | system, | ||
gem5::BaseMMU * | mmu, | ||
gem5::BaseISA * | isa, | ||
iris::IrisConnectionInterface * | iris_if, | ||
const std::string & | iris_path | ||
) |
Definition at line 326 of file thread_context.cc.
References _instId, breakpointEventStreamId, call(), client, enableAfterPseudoEvent, initEventStreamId, noThrow(), regEventStreamId, semihostingEventStreamId, gem5::EventBase::Sim_Exit_Pri, and timeEventStreamId.
|
virtual |
Reimplemented from gem5::ThreadContext.
Definition at line 393 of file thread_context.cc.
References call(), client, enableAfterPseudoEvent, getCpuPtr(), initEventStreamId, regEventStreamId, gem5::Event::scheduled(), and timeEventStreamId.
|
inlineoverridevirtual |
Set the status to Active.
Implements gem5::ThreadContext.
Definition at line 243 of file thread_context.hh.
References gem5::ThreadContext::Active, and setStatus().
|
protected |
Definition at line 284 of file thread_context.cc.
References gem5::ArmISA::e, getOrAllocBp(), and pc.
|
inlineprotected |
Definition at line 169 of file thread_context.hh.
References client.
Referenced by getCurrentInstCount(), initFromIrisInstance(), installBp(), maintainStepping(), pcState(), phaseInitLeave(), readCCRegFlat(), gem5::fastmodel::CortexR52TC::readIntReg(), readIntReg(), readIntRegFlat(), readMem(), readMiscRegNoEffect(), readVecPredReg(), readVecReg(), scheduleInstCountEvent(), semihostingEvent(), setCCRegFlat(), gem5::fastmodel::CortexR52TC::setIntReg(), setIntReg(), setIntRegFlat(), setMiscRegNoEffect(), setStatus(), simulationTimeEvent(), ThreadContext(), uninstallBp(), writeMem(), and ~ThreadContext().
|
inlineoverridevirtual |
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 204 of file thread_context.hh.
References _contextId.
|
inlineoverridevirtual |
|
inlineoverridevirtual |
|
protected |
Definition at line 198 of file thread_context.cc.
References bps, panic_if, and uninstallBp().
Referenced by remove().
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 502 of file thread_context.cc.
References comInstEventQueue, gem5::EventQueue::deschedule(), gem5::MipsISA::event, and maintainStepping().
|
protected |
Definition at line 106 of file thread_context.cc.
References name().
Referenced by extractResourceMap(), gem5::fastmodel::CortexR52TC::initFromIrisInstance(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().
|
protected |
Definition at line 113 of file thread_context.cc.
References extractResourceId(), gem5::ArmISA::ids, and name().
Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), and gem5::fastmodel::CortexA76TC::initFromIrisInstance().
|
protectedpure virtual |
Implemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.
Referenced by installBp().
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 213 of file thread_context.hh.
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 197 of file thread_context.hh.
References _cpu.
Referenced by semihostingEvent(), setStatus(), and ~ThreadContext().
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 509 of file thread_context.cc.
References _instId, call(), gem5::X86ISA::count, and panic_if.
Referenced by maintainStepping(), and scheduleInstCountEvent().
|
inlineoverridevirtual |
|
inlineoverridevirtual |
|
inlineoverridevirtual |
|
protected |
Definition at line 129 of file thread_context.cc.
References memorySpaceIds.
Referenced by gem5::fastmodel::CortexA76TC::getBpSpaceIds(), gem5::fastmodel::CortexR52TC::getBpSpaceIds(), gem5::fastmodel::CortexR52TC::sendFunctional(), sendFunctional(), and gem5::fastmodel::CortexA76TC::translateAddress().
|
inlineoverridevirtual |
|
protected |
Definition at line 165 of file thread_context.cc.
References bps, panic_if, and pc.
Referenced by breakpointHit(), remove(), and schedule().
|
inlineoverridevirtual |
Reimplemented from gem5::ThreadContext.
Definition at line 609 of file thread_context.cc.
References gem5::X86ISA::reg, and gem5::X86ISA::val.
|
overridevirtual |
Reimplemented from gem5::ThreadContext.
Definition at line 623 of file thread_context.cc.
References gem5::CCRegClass, gem5::FloatRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, readCCReg(), gem5::ThreadContext::readFloatReg(), readIntReg(), readVecElem(), readVecPredReg(), readVecReg(), gem5::X86ISA::reg, gem5::X86ISA::type, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.
Flat register interfaces.
Some architectures have different registers visible in different modes. Such architectures "flatten" a register (see flattenRegId()) to map it into the gem5 register file. This interface provides a flat interface to the underlying register file, which allows for example serialization code to access all registers.
Reimplemented from gem5::ThreadContext.
Definition at line 699 of file thread_context.cc.
References gem5::X86ISA::reg, and gem5::X86ISA::val.
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 713 of file thread_context.cc.
References gem5::CCRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, readCCRegFlat(), readIntRegFlat(), readVecElemFlat(), readVecPredRegFlat(), readVecRegFlat(), gem5::X86ISA::reg, gem5::X86ISA::type, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.
|
inlineoverridevirtual |
|
overridevirtual |
Reimplemented from gem5::ThreadContext.
Definition at line 685 of file thread_context.cc.
References getWritableVecPredReg(), getWritableVecReg(), panic, gem5::X86ISA::reg, gem5::X86ISA::type, gem5::VecPredRegClass, and gem5::VecRegClass.
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 769 of file thread_context.cc.
References getWritableVecPredRegFlat(), getWritableVecRegFlat(), panic, gem5::X86ISA::reg, gem5::X86ISA::type, gem5::VecPredRegClass, and gem5::VecRegClass.
|
inlinevirtual |
|
inlinevirtual |
Definition at line 431 of file thread_context.hh.
References panic.
Referenced by getWritableRegFlat().
|
inlinevirtual |
|
inlinevirtual |
Definition at line 408 of file thread_context.hh.
References panic.
Referenced by getWritableRegFlat().
|
inlineoverridevirtual |
Set the status to Halted.
Implements gem5::ThreadContext.
Definition at line 245 of file thread_context.hh.
References gem5::ThreadContext::Halted, and setStatus().
|
inlineoverridevirtual |
|
protectedvirtual |
Reimplemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.
Definition at line 65 of file thread_context.cc.
References _instId, _status, gem5::ThreadContext::Active, bps, breakpointEventStreamId, call(), client, gem5::statistics::enabled(), installBp(), memorySpaceIds, memorySpaces, semihostingEventStreamId, suspend(), gem5::ThreadContext::Suspended, and translations.
Referenced by phaseInitLeave().
|
protected |
Definition at line 178 of file thread_context.cc.
References _instId, call(), getBpSpaceIds(), gem5::ArmISA::id, and pc.
Referenced by initFromIrisInstance(), and schedule().
|
protected |
Definition at line 210 of file thread_context.cc.
References _instId, _irisPath, gem5::MipsISA::event, gem5::ArmISA::id, name(), and panic.
|
protected |
Definition at line 136 of file thread_context.cc.
References _instId, call(), comInstEventQueue, gem5::EventQueue::empty(), getCurrentInstCount(), gem5::EventQueue::nextTick(), and gem5::EventQueue::serviceEvents().
Referenced by descheduleInstCountEvent(), scheduleInstCountEvent(), and simulationTimeEvent().
|
inlineprotected |
Definition at line 170 of file thread_context.hh.
References client.
Referenced by ThreadContext(), and translateAddress().
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 557 of file thread_context.cc.
References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::itState(), gem5::ArmISA::MISCREG_CPSR, pc, pcRscId, and readMiscRegNoEffect().
Referenced by pcStateNoRecord().
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 581 of file thread_context.cc.
References _instId, call(), gem5::ArmISA::MISCREG_CPSR, pc, pcRscId, readMiscRegNoEffect(), and gem5::X86ISA::val.
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 345 of file thread_context.hh.
References pcState(), and gem5::X86ISA::val.
|
protected |
Definition at line 232 of file thread_context.cc.
References _instId, call(), initFromIrisInstance(), and name().
Definition at line 313 of file thread_context.hh.
References readCCRegFlat().
Referenced by getReg().
Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.
Definition at line 838 of file thread_context.cc.
References _instId, call(), and ccRegIds.
Referenced by getRegFlat(), readCCReg(), gem5::fastmodel::CortexA76TC::readCCRegFlat(), and gem5::fastmodel::CortexR52TC::readCCRegFlat().
Reimplemented in gem5::fastmodel::CortexR52TC.
Definition at line 784 of file thread_context.cc.
References _instId, call(), intReg32Ids, intReg64Ids, gem5::ArmISA::MISCREG_CPSR, and readMiscRegNoEffect().
Referenced by getReg(), and semihostingEvent().
Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.
Definition at line 813 of file thread_context.cc.
References _instId, call(), and flattenedIntIds.
Referenced by getRegFlat().
|
inlineoverridevirtual |
|
inlineoverridevirtual |
|
protected |
Definition at line 440 of file thread_context.cc.
References _instId, gem5::X86ISA::addr, call(), gem5::ArmISA::err, gem5::VegaISA::p, panic_if, and gem5::VegaISA::r.
Referenced by gem5::fastmodel::CortexR52TC::sendFunctional(), and sendFunctional().
Implements gem5::ThreadContext.
Definition at line 352 of file thread_context.hh.
References readMiscRegNoEffect().
Implements gem5::ThreadContext.
Definition at line 594 of file thread_context.cc.
References _instId, call(), and miscRegIds.
Referenced by pcState(), readIntReg(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), readMiscReg(), gem5::fastmodel::CortexR52TC::readMiscRegNoEffect(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), setIntReg(), and gem5::fastmodel::CortexA76TC::setIntRegFlat().
|
inlineoverridevirtual |
|
virtual |
Definition at line 885 of file thread_context.cc.
References _instId, call(), gem5::RegId::index(), gem5::ArmISA::offset, gem5::X86ISA::reg, vecPredRegIds, and vecPredRegs.
Referenced by getReg(), and readVecPredRegFlat().
|
virtual |
Definition at line 914 of file thread_context.cc.
References readVecPredReg(), and gem5::VecPredRegClass.
Referenced by getRegFlat().
|
virtual |
Reimplemented in gem5::fastmodel::CortexR52TC.
Definition at line 857 of file thread_context.cc.
References _instId, call(), gem5::RegId::index(), gem5::X86ISA::reg, vecRegIds, and vecRegs.
Referenced by getReg(), and readVecRegFlat().
|
virtual |
Definition at line 879 of file thread_context.cc.
References readVecReg(), and gem5::VecRegClass.
Referenced by getRegFlat().
|
inlineoverridevirtual |
Reimplemented from gem5::ThreadContext.
Definition at line 253 of file thread_context.hh.
|
overridevirtual |
Implements gem5::PCEventScope.
Definition at line 428 of file thread_context.cc.
References delBp(), gem5::ArmISA::e, and getOrAllocBp().
|
overridevirtual |
Implements gem5::PCEventScope.
Definition at line 416 of file thread_context.cc.
References _instId, gem5::ArmISA::e, getOrAllocBp(), and installBp().
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 491 of file thread_context.cc.
References call(), comInstEventQueue, gem5::X86ISA::count, gem5::MipsISA::event, getCurrentInstCount(), maintainStepping(), and gem5::EventQueue::schedule().
|
protected |
Definition at line 305 of file thread_context.cc.
References _instId, call(), gem5::ArmSystem::callSemihosting(), gem5::curTick(), enableAfterPseudoEvent, getCpuPtr(), readIntReg(), and gem5::Event::scheduled().
|
overridevirtual |
Reimplemented from gem5::ThreadContext.
Definition at line 518 of file thread_context.cc.
References gem5::X86ISA::addr, data, gem5::Packet::getAddr(), getMemorySpaceId(), gem5::Packet::getPtr(), gem5::Packet::getSize(), gem5::Packet::isRead(), gem5::ArmISA::isSecure(), gem5::Packet::makeResponse(), gem5::Iris::PhysicalMemoryNonSecureMsn, gem5::Iris::PhysicalMemorySecureMsn, readMem(), and writeMem().
Definition at line 340 of file thread_context.hh.
References setCCRegFlat(), and gem5::X86ISA::val.
Referenced by setReg().
Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.
Definition at line 848 of file thread_context.cc.
References _instId, call(), ccRegIds, panic_if, and gem5::X86ISA::val.
Referenced by setCCReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), and setRegFlat().
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 205 of file thread_context.hh.
References _contextId, and gem5::ArmISA::id.
|
inlineoverridevirtual |
Reimplemented in gem5::fastmodel::CortexR52TC.
Definition at line 797 of file thread_context.cc.
References _instId, call(), intReg32Ids, intReg64Ids, gem5::ArmISA::MISCREG_CPSR, readMiscRegNoEffect(), and gem5::X86ISA::val.
Referenced by setReg().
|
virtual |
Reimplemented in gem5::fastmodel::CortexR52TC, and gem5::fastmodel::CortexA76TC.
Definition at line 826 of file thread_context.cc.
References _instId, call(), flattenedIntIds, panic_if, and gem5::X86ISA::val.
Referenced by setRegFlat().
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 359 of file thread_context.hh.
References setMiscRegNoEffect(), and gem5::X86ISA::val.
Referenced by gem5::fastmodel::CortexA76TC::setIntRegFlat().
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 602 of file thread_context.cc.
References _instId, call(), miscRegIds, and gem5::X86ISA::val.
Referenced by setMiscReg(), and gem5::fastmodel::CortexR52TC::setMiscRegNoEffect().
|
inlineoverridevirtual |
|
overridevirtual |
Reimplemented from gem5::ThreadContext.
Definition at line 654 of file thread_context.cc.
References gem5::CCRegClass, gem5::FloatRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, gem5::X86ISA::reg, setCCReg(), gem5::ThreadContext::setFloatReg(), setIntReg(), setVecElem(), setVecPredReg(), setVecReg(), gem5::X86ISA::type, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.
Reimplemented from gem5::ThreadContext.
Definition at line 617 of file thread_context.cc.
References gem5::X86ISA::reg, and gem5::X86ISA::val.
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 741 of file thread_context.cc.
References gem5::CCRegClass, gem5::IntRegClass, gem5::MiscRegClass, panic, gem5::X86ISA::reg, setCCRegFlat(), setIntRegFlat(), setVecElemFlat(), setVecPredRegFlat(), setVecRegFlat(), gem5::X86ISA::type, gem5::X86ISA::val, gem5::VecElemClass, gem5::VecPredRegClass, and gem5::VecRegClass.
Reimplemented from gem5::ThreadContext.
Definition at line 707 of file thread_context.cc.
References gem5::X86ISA::reg, and gem5::X86ISA::val.
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 542 of file thread_context.cc.
References _instId, _status, gem5::ThreadContext::Active, call(), enableAfterPseudoEvent, getCpuPtr(), and gem5::Event::scheduled().
Referenced by activate(), halt(), and suspend().
|
inlineoverridevirtual |
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 202 of file thread_context.hh.
References _threadId, and gem5::ArmISA::id.
|
inlinevirtual |
|
inlinevirtual |
|
inlinevirtual |
|
inlinevirtual |
|
protected |
Definition at line 262 of file thread_context.cc.
References call(), and maintainStepping().
|
inlineoverridevirtual |
|
overridevirtual |
Implements gem5::ThreadContext.
Definition at line 536 of file thread_context.cc.
References _status.
|
inlineoverridevirtual |
Set the status to Suspended.
Implements gem5::ThreadContext.
Definition at line 244 of file thread_context.hh.
References setStatus(), and gem5::ThreadContext::Suspended.
Referenced by initFromIrisInstance().
|
inlineoverridevirtual |
|
inlineoverridevirtual |
Implements gem5::ThreadContext.
Definition at line 201 of file thread_context.hh.
References _threadId.
Implemented in gem5::fastmodel::CortexA76TC, and gem5::fastmodel::CortexR52TC.
|
protected |
Definition at line 461 of file thread_context.cc.
References _instId, noThrow(), panic, translations, gem5::MipsISA::vaddr, and warn.
|
protected |
Definition at line 190 of file thread_context.cc.
References _instId, and call().
Referenced by delBp().
|
protected |
Definition at line 450 of file thread_context.cc.
References _instId, gem5::X86ISA::addr, call(), data, gem5::ArmISA::err, gem5::VegaISA::p, panic_if, and gem5::VegaISA::r.
Referenced by gem5::fastmodel::CortexR52TC::sendFunctional(), and sendFunctional().
|
protected |
Definition at line 67 of file thread_context.hh.
Referenced by contextId(), and setContextId().
|
protected |
Definition at line 65 of file thread_context.hh.
Referenced by cpuId(), getCpuPtr(), getSystemPtr(), and socketId().
|
protected |
Definition at line 73 of file thread_context.hh.
Referenced by getCurrentInstCount(), initFromIrisInstance(), installBp(), instanceRegistryChanged(), maintainStepping(), pcState(), phaseInitLeave(), readCCRegFlat(), gem5::fastmodel::CortexR52TC::readIntReg(), readIntReg(), readIntRegFlat(), readMem(), readMiscRegNoEffect(), readVecPredReg(), readVecReg(), schedule(), semihostingEvent(), setCCRegFlat(), gem5::fastmodel::CortexR52TC::setIntReg(), setIntReg(), setIntRegFlat(), setMiscRegNoEffect(), setStatus(), ThreadContext(), translateAddress(), uninstallBp(), and writeMem().
|
protected |
Definition at line 72 of file thread_context.hh.
Referenced by instanceRegistryChanged().
|
protected |
Definition at line 70 of file thread_context.hh.
Referenced by getIsaPtr().
|
protected |
Definition at line 69 of file thread_context.hh.
Referenced by getMMUPtr().
Definition at line 80 of file thread_context.hh.
Referenced by initFromIrisInstance(), setStatus(), and status().
|
protected |
Definition at line 68 of file thread_context.hh.
|
protected |
Definition at line 66 of file thread_context.hh.
Referenced by setThreadId(), and threadId().
|
protected |
Definition at line 135 of file thread_context.hh.
Referenced by delBp(), getOrAllocBp(), and initFromIrisInstance().
|
protected |
Definition at line 165 of file thread_context.hh.
Referenced by initFromIrisInstance(), and ThreadContext().
|
protected |
Definition at line 96 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readCCRegFlat(), and setCCRegFlat().
|
mutableprotected |
Definition at line 168 of file thread_context.hh.
Referenced by call(), initFromIrisInstance(), noThrow(), ThreadContext(), and ~ThreadContext().
|
protected |
Definition at line 109 of file thread_context.hh.
Referenced by descheduleInstCountEvent(), maintainStepping(), and scheduleInstCountEvent().
|
protected |
Definition at line 81 of file thread_context.hh.
Referenced by semihostingEvent(), setStatus(), ThreadContext(), and ~ThreadContext().
|
protected |
Definition at line 95 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readIntRegFlat(), and setIntRegFlat().
|
protected |
Definition at line 99 of file thread_context.hh.
|
protected |
Definition at line 163 of file thread_context.hh.
Referenced by ThreadContext(), and ~ThreadContext().
|
protected |
Definition at line 93 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), gem5::fastmodel::CortexR52TC::readIntReg(), readIntReg(), gem5::fastmodel::CortexR52TC::setIntReg(), and setIntReg().
|
protected |
Definition at line 94 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readIntReg(), and setIntReg().
|
protected |
Definition at line 106 of file thread_context.hh.
Referenced by getMemorySpaceId(), and initFromIrisInstance().
|
protected |
Definition at line 104 of file thread_context.hh.
Referenced by initFromIrisInstance().
|
protected |
Definition at line 92 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), readMiscRegNoEffect(), and setMiscRegNoEffect().
|
mutableprotected |
Definition at line 172 of file thread_context.hh.
Referenced by breakpointHit(), getOrAllocBp(), installBp(), and pcState().
|
protected |
Definition at line 98 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexR52TC::initFromIrisInstance(), gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and pcState().
|
protected |
Definition at line 162 of file thread_context.hh.
Referenced by ThreadContext(), and ~ThreadContext().
|
protected |
Definition at line 166 of file thread_context.hh.
Referenced by initFromIrisInstance(), and ThreadContext().
|
protected |
Definition at line 164 of file thread_context.hh.
Referenced by ThreadContext(), and ~ThreadContext().
|
protected |
Definition at line 105 of file thread_context.hh.
Referenced by initFromIrisInstance(), and translateAddress().
|
protected |
Definition at line 102 of file thread_context.hh.
Referenced by readVecPredReg().
|
mutableprotected |
Definition at line 78 of file thread_context.hh.
Referenced by readVecPredReg().
|
protected |
Definition at line 101 of file thread_context.hh.
Referenced by gem5::fastmodel::CortexA76TC::initFromIrisInstance(), and readVecReg().
|
mutableprotected |
Definition at line 77 of file thread_context.hh.
Referenced by readVecReg().