gem5  v22.0.0.1
generic_timer_miscregs_types.hh
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37 
38 #ifndef __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
39 #define __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
40 
41 #include "base/bitunion.hh"
42 
43 namespace gem5
44 {
45 
46 namespace ArmISA
47 {
48  BitUnion64(CNTKCTL)
49  // IF Armv8.6-ECV
50  Bitfield<17> evntis;
51  // ENDIF Armv8.6-ECV
52  Bitfield<9> el0pten;
53  Bitfield<8> el0vten;
54  Bitfield<7,4> evnti;
55  Bitfield<3> evntdir;
56  Bitfield<2> evnten;
57  Bitfield<1> el0vcten;
58  Bitfield<0> el0pcten;
59  EndBitUnion(CNTKCTL)
60 
61  BitUnion64(CNTHCTL)
62  // IF Armv8.6-ECV
63  Bitfield<17> evntis;
64  Bitfield<16> el1nvvct;
65  Bitfield<15> el1nvpct;
66  Bitfield<14> el1tvct;
67  Bitfield<13> el1tvt;
68  Bitfield<12> ecv;
69  // ENDIF Armv8.6-ECV
70  Bitfield<7,4> evnti;
71  Bitfield<3> evntdir;
72  Bitfield<2> evnten;
73  Bitfield<1> el1pcen;
74  Bitfield<0> el1pcten;
75  EndBitUnion(CNTHCTL)
76  // IF Armv8.1-VHE && HCR_EL2.E2H == 1
77  BitUnion64(CNTHCTL_E2H)
78  // IF Armv8.6-ECV
79  Bitfield<17> evntis;
80  Bitfield<16> el1nvvct;
81  Bitfield<15> el1nvpct;
82  Bitfield<14> el1tvct;
83  Bitfield<13> el1tvt;
84  Bitfield<12> ecv;
85  // ENDIF Armv8.6-ECV
86  Bitfield<11> el1pten;
87  Bitfield<10> el1pcten;
88  Bitfield<9> el0pten;
89  Bitfield<8> el0vten;
90  Bitfield<7,4> evnti;
91  Bitfield<3> evntdir;
92  Bitfield<2> evnten;
93  Bitfield<1> el0vcten;
94  Bitfield<0> el0pcten;
95  EndBitUnion(CNTHCTL_E2H)
96  // ENDIF Armv8.1-VHE && HCR_EL2.E2H == 1
97 }
98 
99 } // namespace gem5
100 
101 #endif // __DEV_ARM_GENERIC_TIMER_MISCREGS_TYPES_HH__
gem5::ArmISA::el1tvct
Bitfield< 14 > el1tvct
Definition: generic_timer_miscregs_types.hh:66
gem5::ArmISA::BitUnion64
BitUnion64(ExtMachInst) Bitfield< 63
gem5::ArmISA::el1nvpct
Bitfield< 15 > el1nvpct
Definition: generic_timer_miscregs_types.hh:65
gem5::ArmISA::el1pcen
Bitfield< 1 > el1pcen
Definition: generic_timer_miscregs_types.hh:73
gem5::ArmISA::el1tvt
Bitfield< 13 > el1tvt
Definition: generic_timer_miscregs_types.hh:67
gem5::ArmISA::el0vcten
Bitfield< 1 > el0vcten
Definition: generic_timer_miscregs_types.hh:57
gem5::ArmISA::ecv
ecv
Definition: misc_types.hh:122
gem5::ArmISA::el0pten
Bitfield< 9 > el0pten
Definition: generic_timer_miscregs_types.hh:52
bitunion.hh
gem5::ArmISA::el1nvvct
Bitfield< 16 > el1nvvct
Definition: generic_timer_miscregs_types.hh:64
gem5::ArmISA::el0pcten
Bitfield< 0 > el0pcten
Definition: generic_timer_miscregs_types.hh:58
gem5::ArmISA::evnten
Bitfield< 2 > evnten
Definition: generic_timer_miscregs_types.hh:56
gem5::ArmISA::el1pcten
Bitfield< 0 > el1pcten
Definition: generic_timer_miscregs_types.hh:74
gem5::ArmISA::evntdir
Bitfield< 3 > evntdir
Definition: generic_timer_miscregs_types.hh:55
gem5::ArmISA::el0vten
Bitfield< 8 > el0vten
Definition: generic_timer_miscregs_types.hh:53
gem5::ArmISA::el1pten
Bitfield< 11 > el1pten
Definition: generic_timer_miscregs_types.hh:86
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ArmISA::EndBitUnion
EndBitUnion(PackedIntReg) namespace int_reg
Definition: int.hh:64
gem5::ArmISA::evnti
Bitfield< 7, 4 > evnti
Definition: generic_timer_miscregs_types.hh:54

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