gem5::ArmISA Namespace Reference

Namespaces
namespace	cc_reg
namespace	int_reg
namespace	misc_regs
namespace	mpam
namespace	vector_element_traits

Classes
class	AbortFault
class	ArmFault
class	ArmFaultVals
class	ArmSev
class	ArmStaticInst
class	BaseISADevice
	Base class for devices that use the MiscReg interfaces. More...
class	BigFpMemImmOp
class	BigFpMemLitOp
class	BigFpMemPostOp
class	BigFpMemPreOp
class	BigFpMemRegOp
class	BranchEret64
class	BranchEretA64
class	BranchImm
class	BranchImm64
class	BranchImmCond
class	BranchImmCond64
class	BranchImmImmReg64
class	BranchImmReg
class	BranchImmReg64
class	BranchReg
class	BranchReg64
class	BranchRegCond
class	BranchRegReg
class	BranchRegReg64
class	BranchRet64
class	BranchRetA64
class	BrkPoint
class	CCRegClassOps
class	Crypto
class	DataAbort
class	DataImmOp
class	DataRegOp
class	DataRegRegOp
class	DataX1Reg2ImmOp
class	DataX1RegImmOp
class	DataX1RegOp
class	DataX2RegImmOp
class	DataX2RegOp
class	DataX3RegOp
class	DataXCondCompImmOp
class	DataXCondCompRegOp
class	DataXCondSelOp
class	DataXERegOp
class	DataXImmOnlyOp
class	DataXImmOp
class	DataXSRegOp
class	Decoder
class	DTLBIALL
	Data TLB Invalidate All. More...
class	DTLBIASID
	Data TLB Invalidate by ASID match. More...
class	DTLBIMVA
	Data TLB Invalidate by VA. More...
class	DummyISADevice
	Dummy device that prints a warning when it is accessed. More...
class	DumpStats
class	DumpStats64
class	EmuFreebsd
class	EmuLinux
class	FastInterrupt
class	FpCondCompRegOp
class	FpCondSelOp
class	FpOp
class	FpRegImmOp
class	FpRegRegImmOp
class	FpRegRegOp
class	FpRegRegRegCondOp
class	FpRegRegRegImmOp
class	FpRegRegRegOp
class	FpRegRegRegRegOp
class	FsFreebsd
class	FsLinux
class	FsWorkload
class	HardwareBreakpoint
class	HTMCheckpoint
class	HypervisorCall
class	HypervisorTrap
class	IllegalInstSetStateFault
	Illegal Instruction Set State fault (AArch64 only) More...
class	Interrupt
class	Interrupts
class	IntRegClassOps
class	ISA
class	ITLBIALL
	Instruction TLB Invalidate All. More...
class	ITLBIASID
	Instruction TLB Invalidate by ASID match. More...
class	ITLBIMVA
	Instruction TLB Invalidate by VA. More...
class	MacroMemOp
	Base class for microcoded integer memory instructions. More...
class	MacroVFPMemOp
	Base class for microcoded floating point memory instructions. More...
class	Memory
class	Memory64
class	MemoryAtomicPair64
class	MemoryDImm
class	MemoryDImm64
class	MemoryDImmEx64
class	MemoryDReg
class	MemoryEx64
class	MemoryExDImm
class	MemoryExImm
class	MemoryImm
class	MemoryImm64
class	MemoryLiteral64
class	MemoryOffset
class	MemoryPostIndex
class	MemoryPostIndex64
class	MemoryPreIndex
class	MemoryPreIndex64
class	MemoryRaw64
class	MemoryReg
class	MemoryReg64
class	MicroIntImmOp
	Microops of the form IntRegA = IntRegB op Imm. More...
class	MicroIntImmXOp
class	MicroIntMov
	Microops of the form IntRegA = IntRegB. More...
class	MicroIntOp
	Microops of the form IntRegA = IntRegB op IntRegC. More...
class	MicroIntRegOp
	Microops of the form IntRegA = IntRegB op shifted IntRegC. More...
class	MicroIntRegXOp
class	MicroMemOp
	Memory microops which use IntReg + Imm addressing. More...
class	MicroMemPairOp
class	MicroNeonMemOp
	Microops for Neon loads/stores. More...
class	MicroNeonMixLaneOp
class	MicroNeonMixLaneOp64
class	MicroNeonMixOp
	Microops for Neon load/store (de)interleaving. More...
class	MicroNeonMixOp64
	Microops for AArch64 NEON load/store (de)interleaving. More...
class	MicroOp
	Base class for Memory microops. More...
class	MicroOpX
class	MicroSetPCCPSR
	Microops of the form PC = IntRegA CPSR = IntRegB. More...
class	MightBeMicro
class	MightBeMicro64
class	MiscRegClassOps
struct	MiscRegLUTEntry
	MiscReg metadata. More...
class	MiscRegLUTEntryInitializer
	Metadata table accessible via the value of the register. More...
struct	MiscRegNum32
struct	MiscRegNum64
class	MMU
class	Mult3
	Base class for multipy instructions using three registers. More...
class	Mult4
	Base class for multipy instructions using four registers. More...
struct	PageTableOps
class	PairMemOp
	Base class for pair load/store instructions. More...
class	PCAlignmentFault
	PC alignment fault (AArch64 only) More...
class	PMU
	Model of an ARM PMU version 3. More...
class	PredImmOp
	Base class for predicated immediate operations. More...
class	PredIntOp
	Base class for predicated integer operations. More...
class	PredMacroOp
	Base class for predicated macro-operations. More...
class	PredMicroop
	Base class for predicated micro-operations. More...
class	PredOp
	Base class for predicated integer operations. More...
class	PrefetchAbort
struct	PTE
struct	RegABI32
struct	RegABI64
class	RemoteGDB
class	Reset
class	RfeOp
class	SecureMonitorCall
class	SecureMonitorTrap
class	SelfDebug
class	SEWorkload
class	SkipFunc
class	SkipFuncLinux32
class	SkipFuncLinux64
class	SmeAddOp
class	SmeAddVlOp
class	SmeLd1xSt1xOp
class	SmeLdrStrOp
class	SmeMovExtractOp
class	SmeMovInsertOp
class	SmeOPOp
class	SmeRdsvlOp
class	SmeZeroOp
class	SoftwareBreakpoint
	Software Breakpoint (AArch64 only) More...
class	SoftwareStep
class	SoftwareStepFault
class	SPAlignmentFault
	Stack pointer alignment fault (AArch64 only) More...
class	SrsOp
class	StackTrace
class	Stage2LookUp
class	SupervisorCall
class	SupervisorTrap
class	SveAdrOp
	ADR. More...
class	SveBinConstrPredOp
	Binary, constructive, predicated SVE instruction. More...
class	SveBinDestrPredOp
	Binary, destructive, predicated (merging) SVE instruction. More...
class	SveBinIdxUnpredOp
	Binary, unpredicated SVE instruction. More...
class	SveBinImmIdxUnpredOp
	Binary with immediate index, destructive, unpredicated SVE instruction. More...
class	SveBinImmPredOp
	Binary with immediate, destructive, predicated (merging) SVE instruction. More...
class	SveBinImmUnpredConstrOp
	Binary with immediate, destructive, unpredicated SVE instruction. More...
class	SveBinImmUnpredDestrOp
	SVE vector - immediate binary operation. More...
class	SveBinUnpredOp
	Binary, unpredicated SVE instruction with indexed operand. More...
class	SveBinWideImmUnpredOp
	Binary with wide immediate, destructive, unpredicated SVE instruction. More...
class	SveClampOp
class	SveCmpImmOp
	SVE compare-with-immediate instructions, predicated (zeroing). More...
class	SveCmpOp
	SVE compare instructions, predicated (zeroing). More...
class	SveComplexIdxOp
	SVE Complex Instructions (indexed) More...
class	SveComplexOp
	SVE Complex Instructions (vectors) More...
class	SveCompTermOp
	Compare and terminate loop SVE instruction. More...
class	SveContigMemSI
class	SveContigMemSS
class	SveDotProdIdxOp
	SVE dot product instruction (indexed) More...
class	SveDotProdOp
	SVE dot product instruction (vectors) More...
class	SveElemCountOp
	Element count SVE instruction. More...
class	SveIndexedMemSV
class	SveIndexedMemVI
class	SveIndexIIOp
	Index generation instruction, immediate operands. More...
class	SveIndexIROp
class	SveIndexRIOp
class	SveIndexRROp
class	SveIntCmpImmOp
	Integer compare with immediate SVE instruction. More...
class	SveIntCmpOp
	Integer compare SVE instruction. More...
class	SveLdStructSI
class	SveLdStructSS
class	SveMemPredFillSpill
class	SveMemVecFillSpill
class	SveOrdReducOp
	SVE ordered reductions. More...
class	SvePartBrkOp
	Partition break SVE instruction. More...
class	SvePartBrkPropOp
	Partition break with propagation SVE instruction. More...
class	SvePredBinPermOp
	Predicate binary permute instruction. More...
class	SvePredCountOp
class	SvePredCountPredOp
class	SvePredLogicalOp
	Predicate logical instruction. More...
class	SvePredTestOp
	SVE predicate test. More...
class	SvePredUnaryWImplicitDstOp
	SVE unary predicate instructions with implicit destination operand. More...
class	SvePredUnaryWImplicitSrcOp
	SVE unary predicate instructions with implicit source operand. More...
class	SvePredUnaryWImplicitSrcPredOp
	SVE unary predicate instructions, predicated, with implicit source operand. More...
class	SvePselOp
	Psel predicate selection SVE instruction. More...
class	SvePtrueOp
	PTRUE, PTRUES. More...
class	SveReducOp
	SVE reductions. More...
class	SveSelectOp
	Scalar element select SVE instruction. More...
class	SveStStructSI
class	SveStStructSS
class	SveTblOp
	SVE table lookup/permute using vector of element indices (TBL) More...
class	SveTerImmUnpredOp
	Ternary with immediate, destructive, unpredicated SVE instruction. More...
class	SveTerPredOp
	Ternary, destructive, predicated (merging) SVE instruction. More...
class	SveTerUnpredOp
	Ternary, destructive, unpredicated SVE instruction. More...
class	SveUnaryPredOp
	Unary, constructive, predicated (merging) SVE instruction. More...
class	SveUnaryPredPredOp
	SVE unary operation on predicate (predicated) More...
class	SveUnarySca2VecUnpredOp
	Unary unpredicated scalar to vector instruction. More...
class	SveUnaryUnpredOp
	Unary, constructive, unpredicated SVE instruction. More...
class	SveUnaryWideImmPredOp
	Unary with wide immediate, constructive, predicated SVE instruction. More...
class	SveUnaryWideImmUnpredOp
	Unary with wide immediate, constructive, unpredicated SVE instruction. More...
class	SveUnpackOp
	SVE unpack and widen predicate. More...
class	SveWhileOp
	While predicate generation SVE instruction. More...
class	SveWImplicitSrcDstOp
	SVE unary predicate instructions with implicit destination operand. More...
class	SyscallTable32
class	SyscallTable64
class	SysDC64
class	SystemError
	System error (AArch64 only) More...
class	TableWalker
class	TLB
struct	TlbEntry
class	TLBIALL
	TLB Invalidate All. More...
class	TLBIALLEL
	Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions. More...
class	TLBIALLN
	TLB Invalidate All, Non-Secure. More...
class	TLBIASID
	TLB Invalidate by ASID match. More...
class	TLBIIPA
	TLB Invalidate by Intermediate Physical Address. More...
class	TLBIMVA
	TLB Invalidate by VA. More...
class	TLBIMVAA
	TLB Invalidate by VA, All ASID. More...
class	TLBIOp
class	TLBIRange
class	TLBIRIPA
	TLB Range Invalidate by VA, All ASIDs. More...
class	TLBIRMVA
	TLB Range Invalidate by VA. More...
class	TLBIRMVAA
	TLB Range Invalidate by VA, All ASIDs. More...
class	TLBIVMALL
	Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions. More...
class	TlbTestInterface
class	UndefinedInstruction
struct	V7LPageTableOps
struct	V8PageTableOps16k
struct	V8PageTableOps4k
struct	V8PageTableOps64k
class	VfpMacroOp
class	VirtualDataAbort
class	VirtualFastInterrupt
class	VirtualInterrupt
class	VldMultOp
	Base classes for microcoded integer memory instructions. More...
class	VldMultOp64
	Base classes for microcoded AArch64 NEON memory instructions. More...
class	VldSingleOp
class	VldSingleOp64
struct	VReg
	128-bit NEON vector register. More...
class	VstMultOp
	Base class for microcoded integer memory instructions. More...
class	VstMultOp64
class	VstSingleOp
class	VstSingleOp64
class	WatchPoint
class	Watchpoint

Typedefs
typedef Addr	FaultOffset
typedef uint64_t	XReg
typedef int	VfpSavedState
using	MatRegContainer
template<typename ElemType >
using	MatTile
template<typename ElemType >
using	MatTileRow
template<typename ElemType >
using	MatTileCol
template<typename ElemType >
using	MatRow
template<typename ElemType >
using	MatCol
using	VecElem = uint32_t
using	VecRegContainer
using	VecPredReg
using	ConstVecPredReg
using	VecPredRegContainer = VecPredReg::Container
typedef uint32_t	MachInst
typedef uint16_t	vmid_t
typedef int	RegContextParam
typedef int	RegContextVal

Enumerations
enum	FPRounding {   FPRounding_TIEEVEN = 0 , FPRounding_POSINF = 1 , FPRounding_NEGINF = 2 , FPRounding_ZERO = 3 ,   FPRounding_TIEAWAY = 4 , FPRounding_ODD = 5 }
enum class	FpDataType { Fp16 , Fp32 , Fp64 }
	Floating point data types. More...
enum class	SvePredType { NONE , MERGE , ZERO , SELECT }
enum	VfpMicroMode { VfpNotAMicroop , VfpMicroop , VfpFirstMicroop , VfpLastMicroop }
enum	FeExceptionBit {   FeDivByZero = FE_DIVBYZERO , FeInexact = FE_INEXACT , FeInvalid = FE_INVALID , FeOverflow = FE_OVERFLOW ,   FeUnderflow = FE_UNDERFLOW , FeAllExceptions = FE_ALL_EXCEPT }
enum	FeRoundingMode { FeRoundDown = FE_DOWNWARD , FeRoundNearest = FE_TONEAREST , FeRoundZero = FE_TOWARDZERO , FeRoundUpward = FE_UPWARD }
enum	VfpRoundingMode {   VfpRoundNearest = 0 , VfpRoundUpward = 1 , VfpRoundDown = 2 , VfpRoundZero = 3 ,   VfpRoundAway = 4 }
enum	InterruptTypes {   INT_RST , INT_ABT , INT_IRQ , INT_FIQ ,   INT_SEV , INT_VIRT_IRQ , INT_VIRT_FIQ , NumInterruptTypes ,   INT_VIRT_ABT }
enum	GrainSize { Grain4KB = 12 , Grain16KB = 14 , Grain64KB = 16 , ReservedGrain = 0 }
enum	ConditionCode {   COND_EQ = 0 , COND_NE , COND_CS , COND_CC ,   COND_MI , COND_PL , COND_VS , COND_VC ,   COND_HI , COND_LS , COND_GE , COND_LT ,   COND_GT , COND_LE , COND_AL , COND_UC }
enum	MiscRegIndex {   MISCREG_CPSR = 0 , MISCREG_SPSR , MISCREG_SPSR_FIQ , MISCREG_SPSR_IRQ ,   MISCREG_SPSR_SVC , MISCREG_SPSR_MON , MISCREG_SPSR_ABT , MISCREG_SPSR_HYP ,   MISCREG_SPSR_UND , MISCREG_ELR_HYP , MISCREG_FPSID , MISCREG_FPSCR ,   MISCREG_MVFR1 , MISCREG_MVFR0 , MISCREG_FPEXC , MISCREG_CPSR_MODE ,   MISCREG_CPSR_Q , MISCREG_FPSCR_EXC , MISCREG_FPSCR_QC , MISCREG_LOCKADDR ,   MISCREG_LOCKFLAG , MISCREG_PRRR_MAIR0 , MISCREG_PRRR_MAIR0_NS , MISCREG_PRRR_MAIR0_S ,   MISCREG_NMRR_MAIR1 , MISCREG_NMRR_MAIR1_NS , MISCREG_NMRR_MAIR1_S , MISCREG_PMXEVTYPER_PMCCFILTR ,   MISCREG_SEV_MAILBOX , MISCREG_TLBINEEDSYNC , MISCREG_DBGDIDR , MISCREG_DBGDSCRint ,   MISCREG_DBGDCCINT , MISCREG_DBGDTRTXint , MISCREG_DBGDTRRXint , MISCREG_DBGWFAR ,   MISCREG_DBGVCR , MISCREG_DBGDTRRXext , MISCREG_DBGDSCRext , MISCREG_DBGDTRTXext ,   MISCREG_DBGOSECCR , MISCREG_DBGBVR0 , MISCREG_DBGBVR1 , MISCREG_DBGBVR2 ,   MISCREG_DBGBVR3 , MISCREG_DBGBVR4 , MISCREG_DBGBVR5 , MISCREG_DBGBVR6 ,   MISCREG_DBGBVR7 , MISCREG_DBGBVR8 , MISCREG_DBGBVR9 , MISCREG_DBGBVR10 ,   MISCREG_DBGBVR11 , MISCREG_DBGBVR12 , MISCREG_DBGBVR13 , MISCREG_DBGBVR14 ,   MISCREG_DBGBVR15 , MISCREG_DBGBCR0 , MISCREG_DBGBCR1 , MISCREG_DBGBCR2 ,   MISCREG_DBGBCR3 , MISCREG_DBGBCR4 , MISCREG_DBGBCR5 , MISCREG_DBGBCR6 ,   MISCREG_DBGBCR7 , MISCREG_DBGBCR8 , MISCREG_DBGBCR9 , MISCREG_DBGBCR10 ,   MISCREG_DBGBCR11 , MISCREG_DBGBCR12 , MISCREG_DBGBCR13 , MISCREG_DBGBCR14 ,   MISCREG_DBGBCR15 , MISCREG_DBGWVR0 , MISCREG_DBGWVR1 , MISCREG_DBGWVR2 ,   MISCREG_DBGWVR3 , MISCREG_DBGWVR4 , MISCREG_DBGWVR5 , MISCREG_DBGWVR6 ,   MISCREG_DBGWVR7 , MISCREG_DBGWVR8 , MISCREG_DBGWVR9 , MISCREG_DBGWVR10 ,   MISCREG_DBGWVR11 , MISCREG_DBGWVR12 , MISCREG_DBGWVR13 , MISCREG_DBGWVR14 ,   MISCREG_DBGWVR15 , MISCREG_DBGWCR0 , MISCREG_DBGWCR1 , MISCREG_DBGWCR2 ,   MISCREG_DBGWCR3 , MISCREG_DBGWCR4 , MISCREG_DBGWCR5 , MISCREG_DBGWCR6 ,   MISCREG_DBGWCR7 , MISCREG_DBGWCR8 , MISCREG_DBGWCR9 , MISCREG_DBGWCR10 ,   MISCREG_DBGWCR11 , MISCREG_DBGWCR12 , MISCREG_DBGWCR13 , MISCREG_DBGWCR14 ,   MISCREG_DBGWCR15 , MISCREG_DBGDRAR , MISCREG_DBGBXVR0 , MISCREG_DBGBXVR1 ,   MISCREG_DBGBXVR2 , MISCREG_DBGBXVR3 , MISCREG_DBGBXVR4 , MISCREG_DBGBXVR5 ,   MISCREG_DBGBXVR6 , MISCREG_DBGBXVR7 , MISCREG_DBGBXVR8 , MISCREG_DBGBXVR9 ,   MISCREG_DBGBXVR10 , MISCREG_DBGBXVR11 , MISCREG_DBGBXVR12 , MISCREG_DBGBXVR13 ,   MISCREG_DBGBXVR14 , MISCREG_DBGBXVR15 , MISCREG_DBGOSLAR , MISCREG_DBGOSLSR ,   MISCREG_DBGOSDLR , MISCREG_DBGPRCR , MISCREG_DBGDSAR , MISCREG_DBGCLAIMSET ,   MISCREG_DBGCLAIMCLR , MISCREG_DBGAUTHSTATUS , MISCREG_DBGDEVID2 , MISCREG_DBGDEVID1 ,   MISCREG_DBGDEVID0 , MISCREG_TEECR , MISCREG_JIDR , MISCREG_TEEHBR ,   MISCREG_JOSCR , MISCREG_JMCR , MISCREG_MIDR , MISCREG_CTR ,   MISCREG_TCMTR , MISCREG_TLBTR , MISCREG_MPIDR , MISCREG_REVIDR ,   MISCREG_ID_PFR0 , MISCREG_ID_PFR1 , MISCREG_ID_DFR0 , MISCREG_ID_AFR0 ,   MISCREG_ID_MMFR0 , MISCREG_ID_MMFR1 , MISCREG_ID_MMFR2 , MISCREG_ID_MMFR3 ,   MISCREG_ID_MMFR4 , MISCREG_ID_ISAR0 , MISCREG_ID_ISAR1 , MISCREG_ID_ISAR2 ,   MISCREG_ID_ISAR3 , MISCREG_ID_ISAR4 , MISCREG_ID_ISAR5 , MISCREG_ID_ISAR6 ,   MISCREG_CCSIDR , MISCREG_CLIDR , MISCREG_AIDR , MISCREG_CSSELR ,   MISCREG_CSSELR_NS , MISCREG_CSSELR_S , MISCREG_VPIDR , MISCREG_VMPIDR ,   MISCREG_SCTLR , MISCREG_SCTLR_NS , MISCREG_SCTLR_S , MISCREG_ACTLR ,   MISCREG_ACTLR_NS , MISCREG_ACTLR_S , MISCREG_CPACR , MISCREG_SDCR ,   MISCREG_SCR , MISCREG_SDER , MISCREG_NSACR , MISCREG_HSCTLR ,   MISCREG_HACTLR , MISCREG_HCR , MISCREG_HCR2 , MISCREG_HDCR ,   MISCREG_HCPTR , MISCREG_HSTR , MISCREG_HACR , MISCREG_TTBR0 ,   MISCREG_TTBR0_NS , MISCREG_TTBR0_S , MISCREG_TTBR1 , MISCREG_TTBR1_NS ,   MISCREG_TTBR1_S , MISCREG_TTBCR , MISCREG_TTBCR_NS , MISCREG_TTBCR_S ,   MISCREG_HTCR , MISCREG_VTCR , MISCREG_DACR , MISCREG_DACR_NS ,   MISCREG_DACR_S , MISCREG_DFSR , MISCREG_DFSR_NS , MISCREG_DFSR_S ,   MISCREG_IFSR , MISCREG_IFSR_NS , MISCREG_IFSR_S , MISCREG_ADFSR ,   MISCREG_ADFSR_NS , MISCREG_ADFSR_S , MISCREG_AIFSR , MISCREG_AIFSR_NS ,   MISCREG_AIFSR_S , MISCREG_HADFSR , MISCREG_HAIFSR , MISCREG_HSR ,   MISCREG_DFAR , MISCREG_DFAR_NS , MISCREG_DFAR_S , MISCREG_IFAR ,   MISCREG_IFAR_NS , MISCREG_IFAR_S , MISCREG_HDFAR , MISCREG_HIFAR ,   MISCREG_HPFAR , MISCREG_ICIALLUIS , MISCREG_BPIALLIS , MISCREG_PAR ,   MISCREG_PAR_NS , MISCREG_PAR_S , MISCREG_ICIALLU , MISCREG_ICIMVAU ,   MISCREG_CP15ISB , MISCREG_BPIALL , MISCREG_BPIMVA , MISCREG_DCIMVAC ,   MISCREG_DCISW , MISCREG_ATS1CPR , MISCREG_ATS1CPW , MISCREG_ATS1CUR ,   MISCREG_ATS1CUW , MISCREG_ATS12NSOPR , MISCREG_ATS12NSOPW , MISCREG_ATS12NSOUR ,   MISCREG_ATS12NSOUW , MISCREG_DCCMVAC , MISCREG_DCCSW , MISCREG_CP15DSB ,   MISCREG_CP15DMB , MISCREG_DCCMVAU , MISCREG_DCCIMVAC , MISCREG_DCCISW ,   MISCREG_ATS1HR , MISCREG_ATS1HW , MISCREG_TLBIALLIS , MISCREG_TLBIMVAIS ,   MISCREG_TLBIASIDIS , MISCREG_TLBIMVAAIS , MISCREG_TLBIMVALIS , MISCREG_TLBIMVAALIS ,   MISCREG_ITLBIALL , MISCREG_ITLBIMVA , MISCREG_ITLBIASID , MISCREG_DTLBIALL ,   MISCREG_DTLBIMVA , MISCREG_DTLBIASID , MISCREG_TLBIALL , MISCREG_TLBIMVA ,   MISCREG_TLBIASID , MISCREG_TLBIMVAA , MISCREG_TLBIMVAL , MISCREG_TLBIMVAAL ,   MISCREG_TLBIIPAS2IS , MISCREG_TLBIIPAS2LIS , MISCREG_TLBIALLHIS , MISCREG_TLBIMVAHIS ,   MISCREG_TLBIALLNSNHIS , MISCREG_TLBIMVALHIS , MISCREG_TLBIIPAS2 , MISCREG_TLBIIPAS2L ,   MISCREG_TLBIALLH , MISCREG_TLBIMVAH , MISCREG_TLBIALLNSNH , MISCREG_TLBIMVALH ,   MISCREG_PMCR , MISCREG_PMCNTENSET , MISCREG_PMCNTENCLR , MISCREG_PMOVSR ,   MISCREG_PMSWINC , MISCREG_PMSELR , MISCREG_PMCEID0 , MISCREG_PMCEID1 ,   MISCREG_PMCCNTR , MISCREG_PMXEVTYPER , MISCREG_PMCCFILTR , MISCREG_PMXEVCNTR ,   MISCREG_PMUSERENR , MISCREG_PMINTENSET , MISCREG_PMINTENCLR , MISCREG_PMOVSSET ,   MISCREG_L2CTLR , MISCREG_L2ECTLR , MISCREG_PRRR , MISCREG_PRRR_NS ,   MISCREG_PRRR_S , MISCREG_MAIR0 , MISCREG_MAIR0_NS , MISCREG_MAIR0_S ,   MISCREG_NMRR , MISCREG_NMRR_NS , MISCREG_NMRR_S , MISCREG_MAIR1 ,   MISCREG_MAIR1_NS , MISCREG_MAIR1_S , MISCREG_AMAIR0 , MISCREG_AMAIR0_NS ,   MISCREG_AMAIR0_S , MISCREG_AMAIR1 , MISCREG_AMAIR1_NS , MISCREG_AMAIR1_S ,   MISCREG_HMAIR0 , MISCREG_HMAIR1 , MISCREG_HAMAIR0 , MISCREG_HAMAIR1 ,   MISCREG_VBAR , MISCREG_VBAR_NS , MISCREG_VBAR_S , MISCREG_MVBAR ,   MISCREG_RMR , MISCREG_ISR , MISCREG_HVBAR , MISCREG_FCSEIDR ,   MISCREG_CONTEXTIDR , MISCREG_CONTEXTIDR_NS , MISCREG_CONTEXTIDR_S , MISCREG_TPIDRURW ,   MISCREG_TPIDRURW_NS , MISCREG_TPIDRURW_S , MISCREG_TPIDRURO , MISCREG_TPIDRURO_NS ,   MISCREG_TPIDRURO_S , MISCREG_TPIDRPRW , MISCREG_TPIDRPRW_NS , MISCREG_TPIDRPRW_S ,   MISCREG_HTPIDR , MISCREG_CNTFRQ , MISCREG_CNTPCT , MISCREG_CNTVCT ,   MISCREG_CNTP_CTL , MISCREG_CNTP_CTL_NS , MISCREG_CNTP_CTL_S , MISCREG_CNTP_CVAL ,   MISCREG_CNTP_CVAL_NS , MISCREG_CNTP_CVAL_S , MISCREG_CNTP_TVAL , MISCREG_CNTP_TVAL_NS ,   MISCREG_CNTP_TVAL_S , MISCREG_CNTV_CTL , MISCREG_CNTV_CVAL , MISCREG_CNTV_TVAL ,   MISCREG_CNTKCTL , MISCREG_CNTHCTL , MISCREG_CNTHP_CTL , MISCREG_CNTHP_CVAL ,   MISCREG_CNTHP_TVAL , MISCREG_CNTVOFF , MISCREG_IL1DATA0 , MISCREG_IL1DATA1 ,   MISCREG_IL1DATA2 , MISCREG_IL1DATA3 , MISCREG_DL1DATA0 , MISCREG_DL1DATA1 ,   MISCREG_DL1DATA2 , MISCREG_DL1DATA3 , MISCREG_DL1DATA4 , MISCREG_RAMINDEX ,   MISCREG_L2ACTLR , MISCREG_CBAR , MISCREG_HTTBR , MISCREG_VTTBR ,   MISCREG_CPUMERRSR , MISCREG_L2MERRSR , MISCREG_MDCCINT_EL1 , MISCREG_OSDTRRX_EL1 ,   MISCREG_MDSCR_EL1 , MISCREG_OSDTRTX_EL1 , MISCREG_OSECCR_EL1 , MISCREG_DBGBVR0_EL1 ,   MISCREG_DBGBVR1_EL1 , MISCREG_DBGBVR2_EL1 , MISCREG_DBGBVR3_EL1 , MISCREG_DBGBVR4_EL1 ,   MISCREG_DBGBVR5_EL1 , MISCREG_DBGBVR6_EL1 , MISCREG_DBGBVR7_EL1 , MISCREG_DBGBVR8_EL1 ,   MISCREG_DBGBVR9_EL1 , MISCREG_DBGBVR10_EL1 , MISCREG_DBGBVR11_EL1 , MISCREG_DBGBVR12_EL1 ,   MISCREG_DBGBVR13_EL1 , MISCREG_DBGBVR14_EL1 , MISCREG_DBGBVR15_EL1 , MISCREG_DBGBCR0_EL1 ,   MISCREG_DBGBCR1_EL1 , MISCREG_DBGBCR2_EL1 , MISCREG_DBGBCR3_EL1 , MISCREG_DBGBCR4_EL1 ,   MISCREG_DBGBCR5_EL1 , MISCREG_DBGBCR6_EL1 , MISCREG_DBGBCR7_EL1 , MISCREG_DBGBCR8_EL1 ,   MISCREG_DBGBCR9_EL1 , MISCREG_DBGBCR10_EL1 , MISCREG_DBGBCR11_EL1 , MISCREG_DBGBCR12_EL1 ,   MISCREG_DBGBCR13_EL1 , MISCREG_DBGBCR14_EL1 , MISCREG_DBGBCR15_EL1 , MISCREG_DBGWVR0_EL1 ,   MISCREG_DBGWVR1_EL1 , MISCREG_DBGWVR2_EL1 , MISCREG_DBGWVR3_EL1 , MISCREG_DBGWVR4_EL1 ,   MISCREG_DBGWVR5_EL1 , MISCREG_DBGWVR6_EL1 , MISCREG_DBGWVR7_EL1 , MISCREG_DBGWVR8_EL1 ,   MISCREG_DBGWVR9_EL1 , MISCREG_DBGWVR10_EL1 , MISCREG_DBGWVR11_EL1 , MISCREG_DBGWVR12_EL1 ,   MISCREG_DBGWVR13_EL1 , MISCREG_DBGWVR14_EL1 , MISCREG_DBGWVR15_EL1 , MISCREG_DBGWCR0_EL1 ,   MISCREG_DBGWCR1_EL1 , MISCREG_DBGWCR2_EL1 , MISCREG_DBGWCR3_EL1 , MISCREG_DBGWCR4_EL1 ,   MISCREG_DBGWCR5_EL1 , MISCREG_DBGWCR6_EL1 , MISCREG_DBGWCR7_EL1 , MISCREG_DBGWCR8_EL1 ,   MISCREG_DBGWCR9_EL1 , MISCREG_DBGWCR10_EL1 , MISCREG_DBGWCR11_EL1 , MISCREG_DBGWCR12_EL1 ,   MISCREG_DBGWCR13_EL1 , MISCREG_DBGWCR14_EL1 , MISCREG_DBGWCR15_EL1 , MISCREG_MDCCSR_EL0 ,   MISCREG_MDDTR_EL0 , MISCREG_MDDTRTX_EL0 , MISCREG_MDDTRRX_EL0 , MISCREG_DBGVCR32_EL2 ,   MISCREG_MDRAR_EL1 , MISCREG_OSLAR_EL1 , MISCREG_OSLSR_EL1 , MISCREG_OSDLR_EL1 ,   MISCREG_DBGPRCR_EL1 , MISCREG_DBGCLAIMSET_EL1 , MISCREG_DBGCLAIMCLR_EL1 , MISCREG_DBGAUTHSTATUS_EL1 ,   MISCREG_TEECR32_EL1 , MISCREG_TEEHBR32_EL1 , MISCREG_MIDR_EL1 , MISCREG_MPIDR_EL1 ,   MISCREG_REVIDR_EL1 , MISCREG_ID_PFR0_EL1 , MISCREG_ID_PFR1_EL1 , MISCREG_ID_DFR0_EL1 ,   MISCREG_ID_AFR0_EL1 , MISCREG_ID_MMFR0_EL1 , MISCREG_ID_MMFR1_EL1 , MISCREG_ID_MMFR2_EL1 ,   MISCREG_ID_MMFR3_EL1 , MISCREG_ID_MMFR4_EL1 , MISCREG_ID_ISAR0_EL1 , MISCREG_ID_ISAR1_EL1 ,   MISCREG_ID_ISAR2_EL1 , MISCREG_ID_ISAR3_EL1 , MISCREG_ID_ISAR4_EL1 , MISCREG_ID_ISAR5_EL1 ,   MISCREG_ID_ISAR6_EL1 , MISCREG_MVFR0_EL1 , MISCREG_MVFR1_EL1 , MISCREG_MVFR2_EL1 ,   MISCREG_ID_AA64PFR0_EL1 , MISCREG_ID_AA64PFR1_EL1 , MISCREG_ID_AA64DFR0_EL1 , MISCREG_ID_AA64DFR1_EL1 ,   MISCREG_ID_AA64AFR0_EL1 , MISCREG_ID_AA64AFR1_EL1 , MISCREG_ID_AA64ISAR0_EL1 , MISCREG_ID_AA64ISAR1_EL1 ,   MISCREG_ID_AA64MMFR0_EL1 , MISCREG_ID_AA64MMFR1_EL1 , MISCREG_CCSIDR_EL1 , MISCREG_CLIDR_EL1 ,   MISCREG_AIDR_EL1 , MISCREG_CSSELR_EL1 , MISCREG_CTR_EL0 , MISCREG_DCZID_EL0 ,   MISCREG_VPIDR_EL2 , MISCREG_VMPIDR_EL2 , MISCREG_SCTLR_EL1 , MISCREG_SCTLR_EL12 ,   MISCREG_SCTLR2_EL1 , MISCREG_SCTLR2_EL12 , MISCREG_ACTLR_EL1 , MISCREG_CPACR_EL1 ,   MISCREG_CPACR_EL12 , MISCREG_SCTLR_EL2 , MISCREG_SCTLR2_EL2 , MISCREG_ACTLR_EL2 ,   MISCREG_HCR_EL2 , MISCREG_HCRX_EL2 , MISCREG_MDCR_EL2 , MISCREG_CPTR_EL2 ,   MISCREG_HSTR_EL2 , MISCREG_HACR_EL2 , MISCREG_SCTLR_EL3 , MISCREG_SCTLR2_EL3 ,   MISCREG_ACTLR_EL3 , MISCREG_SCR_EL3 , MISCREG_SDER32_EL3 , MISCREG_CPTR_EL3 ,   MISCREG_MDCR_EL3 , MISCREG_TTBR0_EL1 , MISCREG_TTBR0_EL12 , MISCREG_TTBR1_EL1 ,   MISCREG_TTBR1_EL12 , MISCREG_TCR_EL1 , MISCREG_TCR_EL12 , MISCREG_TCR2_EL1 ,   MISCREG_TCR2_EL12 , MISCREG_TTBR0_EL2 , MISCREG_TCR_EL2 , MISCREG_TCR2_EL2 ,   MISCREG_VTTBR_EL2 , MISCREG_VTCR_EL2 , MISCREG_VSTTBR_EL2 , MISCREG_VSTCR_EL2 ,   MISCREG_TTBR0_EL3 , MISCREG_TCR_EL3 , MISCREG_DACR32_EL2 , MISCREG_SPSR_EL1 ,   MISCREG_SPSR_EL12 , MISCREG_ELR_EL1 , MISCREG_ELR_EL12 , MISCREG_SP_EL0 ,   MISCREG_SPSEL , MISCREG_CURRENTEL , MISCREG_NZCV , MISCREG_DAIF ,   MISCREG_FPCR , MISCREG_FPSR , MISCREG_DSPSR_EL0 , MISCREG_DLR_EL0 ,   MISCREG_SPSR_EL2 , MISCREG_ELR_EL2 , MISCREG_SP_EL1 , MISCREG_SPSR_IRQ_AA64 ,   MISCREG_SPSR_ABT_AA64 , MISCREG_SPSR_UND_AA64 , MISCREG_SPSR_FIQ_AA64 , MISCREG_SPSR_EL3 ,   MISCREG_ELR_EL3 , MISCREG_SP_EL2 , MISCREG_AFSR0_EL1 , MISCREG_AFSR0_EL12 ,   MISCREG_AFSR1_EL1 , MISCREG_AFSR1_EL12 , MISCREG_ESR_EL1 , MISCREG_ESR_EL12 ,   MISCREG_IFSR32_EL2 , MISCREG_AFSR0_EL2 , MISCREG_AFSR1_EL2 , MISCREG_ESR_EL2 ,   MISCREG_FPEXC32_EL2 , MISCREG_AFSR0_EL3 , MISCREG_AFSR1_EL3 , MISCREG_ESR_EL3 ,   MISCREG_FAR_EL1 , MISCREG_FAR_EL12 , MISCREG_FAR_EL2 , MISCREG_HPFAR_EL2 ,   MISCREG_FAR_EL3 , MISCREG_IC_IALLUIS , MISCREG_PAR_EL1 , MISCREG_IC_IALLU ,   MISCREG_DC_IVAC_Xt , MISCREG_DC_ISW_Xt , MISCREG_AT_S1E1R_Xt , MISCREG_AT_S1E1W_Xt ,   MISCREG_AT_S1E0R_Xt , MISCREG_AT_S1E0W_Xt , MISCREG_DC_CSW_Xt , MISCREG_DC_CISW_Xt ,   MISCREG_DC_ZVA_Xt , MISCREG_IC_IVAU_Xt , MISCREG_DC_CVAC_Xt , MISCREG_DC_CVAU_Xt ,   MISCREG_DC_CIVAC_Xt , MISCREG_AT_S1E2R_Xt , MISCREG_AT_S1E2W_Xt , MISCREG_AT_S12E1R_Xt ,   MISCREG_AT_S12E1W_Xt , MISCREG_AT_S12E0R_Xt , MISCREG_AT_S12E0W_Xt , MISCREG_AT_S1E3R_Xt ,   MISCREG_AT_S1E3W_Xt , MISCREG_TLBI_VMALLE1IS , MISCREG_TLBI_VMALLE1OS , MISCREG_TLBI_VAE1IS ,   MISCREG_TLBI_VAE1OS , MISCREG_TLBI_ASIDE1IS , MISCREG_TLBI_ASIDE1OS , MISCREG_TLBI_VAAE1IS ,   MISCREG_TLBI_VAAE1OS , MISCREG_TLBI_VALE1IS , MISCREG_TLBI_VALE1OS , MISCREG_TLBI_VAALE1IS ,   MISCREG_TLBI_VAALE1OS , MISCREG_TLBI_VMALLE1 , MISCREG_TLBI_VAE1 , MISCREG_TLBI_ASIDE1 ,   MISCREG_TLBI_VAAE1 , MISCREG_TLBI_VALE1 , MISCREG_TLBI_VAALE1 , MISCREG_TLBI_IPAS2E1IS ,   MISCREG_TLBI_IPAS2E1OS , MISCREG_TLBI_IPAS2LE1IS , MISCREG_TLBI_IPAS2LE1OS , MISCREG_TLBI_ALLE2IS ,   MISCREG_TLBI_ALLE2OS , MISCREG_TLBI_VAE2IS , MISCREG_TLBI_VAE2OS , MISCREG_TLBI_ALLE1IS ,   MISCREG_TLBI_ALLE1OS , MISCREG_TLBI_VALE2IS , MISCREG_TLBI_VALE2OS , MISCREG_TLBI_VMALLS12E1IS ,   MISCREG_TLBI_VMALLS12E1OS , MISCREG_TLBI_IPAS2E1 , MISCREG_TLBI_IPAS2LE1 , MISCREG_TLBI_ALLE2 ,   MISCREG_TLBI_VAE2 , MISCREG_TLBI_ALLE1 , MISCREG_TLBI_VALE2 , MISCREG_TLBI_VMALLS12E1 ,   MISCREG_TLBI_ALLE3IS , MISCREG_TLBI_ALLE3OS , MISCREG_TLBI_VAE3IS , MISCREG_TLBI_VAE3OS ,   MISCREG_TLBI_VALE3IS , MISCREG_TLBI_VALE3OS , MISCREG_TLBI_ALLE3 , MISCREG_TLBI_VAE3 ,   MISCREG_TLBI_VALE3 , MISCREG_TLBI_RVAE1 , MISCREG_TLBI_RVAAE1 , MISCREG_TLBI_RVALE1 ,   MISCREG_TLBI_RVAALE1 , MISCREG_TLBI_RIPAS2E1 , MISCREG_TLBI_RIPAS2LE1 , MISCREG_TLBI_RVAE2 ,   MISCREG_TLBI_RVALE2 , MISCREG_TLBI_RVAE3 , MISCREG_TLBI_RVALE3 , MISCREG_TLBI_RVAE1IS ,   MISCREG_TLBI_RVAAE1IS , MISCREG_TLBI_RVALE1IS , MISCREG_TLBI_RVAALE1IS , MISCREG_TLBI_RIPAS2E1IS ,   MISCREG_TLBI_RIPAS2LE1IS , MISCREG_TLBI_RVAE2IS , MISCREG_TLBI_RVALE2IS , MISCREG_TLBI_RVAE3IS ,   MISCREG_TLBI_RVALE3IS , MISCREG_TLBI_RVAE1OS , MISCREG_TLBI_RVAAE1OS , MISCREG_TLBI_RVALE1OS ,   MISCREG_TLBI_RVAALE1OS , MISCREG_TLBI_RIPAS2E1OS , MISCREG_TLBI_RIPAS2LE1OS , MISCREG_TLBI_RVAE2OS ,   MISCREG_TLBI_RVALE2OS , MISCREG_TLBI_RVAE3OS , MISCREG_TLBI_RVALE3OS , MISCREG_PMINTENSET_EL1 ,   MISCREG_PMINTENCLR_EL1 , MISCREG_PMCR_EL0 , MISCREG_PMCNTENSET_EL0 , MISCREG_PMCNTENCLR_EL0 ,   MISCREG_PMOVSCLR_EL0 , MISCREG_PMSWINC_EL0 , MISCREG_PMSELR_EL0 , MISCREG_PMCEID0_EL0 ,   MISCREG_PMCEID1_EL0 , MISCREG_PMCCNTR_EL0 , MISCREG_PMXEVTYPER_EL0 , MISCREG_PMCCFILTR_EL0 ,   MISCREG_PMXEVCNTR_EL0 , MISCREG_PMUSERENR_EL0 , MISCREG_PMOVSSET_EL0 , MISCREG_MAIR_EL1 ,   MISCREG_MAIR_EL12 , MISCREG_AMAIR_EL1 , MISCREG_AMAIR_EL12 , MISCREG_MAIR_EL2 ,   MISCREG_AMAIR_EL2 , MISCREG_MAIR_EL3 , MISCREG_AMAIR_EL3 , MISCREG_L2CTLR_EL1 ,   MISCREG_L2ECTLR_EL1 , MISCREG_VBAR_EL1 , MISCREG_VBAR_EL12 , MISCREG_RVBAR_EL1 ,   MISCREG_ISR_EL1 , MISCREG_VBAR_EL2 , MISCREG_RVBAR_EL2 , MISCREG_VBAR_EL3 ,   MISCREG_RVBAR_EL3 , MISCREG_RMR_EL3 , MISCREG_CONTEXTIDR_EL1 , MISCREG_CONTEXTIDR_EL12 ,   MISCREG_TPIDR_EL1 , MISCREG_TPIDR_EL0 , MISCREG_TPIDRRO_EL0 , MISCREG_TPIDR_EL2 ,   MISCREG_TPIDR_EL3 , MISCREG_CNTFRQ_EL0 , MISCREG_CNTPCT_EL0 , MISCREG_CNTVCT_EL0 ,   MISCREG_CNTP_CTL_EL0 , MISCREG_CNTP_CVAL_EL0 , MISCREG_CNTP_TVAL_EL0 , MISCREG_CNTV_CTL_EL0 ,   MISCREG_CNTV_CVAL_EL0 , MISCREG_CNTV_TVAL_EL0 , MISCREG_CNTP_CTL_EL02 , MISCREG_CNTP_CVAL_EL02 ,   MISCREG_CNTP_TVAL_EL02 , MISCREG_CNTV_CTL_EL02 , MISCREG_CNTV_CVAL_EL02 , MISCREG_CNTV_TVAL_EL02 ,   MISCREG_CNTKCTL_EL1 , MISCREG_CNTKCTL_EL12 , MISCREG_CNTPS_CTL_EL1 , MISCREG_CNTPS_CVAL_EL1 ,   MISCREG_CNTPS_TVAL_EL1 , MISCREG_CNTHCTL_EL2 , MISCREG_CNTHP_CTL_EL2 , MISCREG_CNTHP_CVAL_EL2 ,   MISCREG_CNTHP_TVAL_EL2 , MISCREG_CNTHPS_CTL_EL2 , MISCREG_CNTHPS_CVAL_EL2 , MISCREG_CNTHPS_TVAL_EL2 ,   MISCREG_CNTHV_CTL_EL2 , MISCREG_CNTHV_CVAL_EL2 , MISCREG_CNTHV_TVAL_EL2 , MISCREG_CNTHVS_CTL_EL2 ,   MISCREG_CNTHVS_CVAL_EL2 , MISCREG_CNTHVS_TVAL_EL2 , MISCREG_CNTVOFF_EL2 , MISCREG_PMEVCNTR0_EL0 ,   MISCREG_PMEVCNTR1_EL0 , MISCREG_PMEVCNTR2_EL0 , MISCREG_PMEVCNTR3_EL0 , MISCREG_PMEVCNTR4_EL0 ,   MISCREG_PMEVCNTR5_EL0 , MISCREG_PMEVTYPER0_EL0 , MISCREG_PMEVTYPER1_EL0 , MISCREG_PMEVTYPER2_EL0 ,   MISCREG_PMEVTYPER3_EL0 , MISCREG_PMEVTYPER4_EL0 , MISCREG_PMEVTYPER5_EL0 , MISCREG_IL1DATA0_EL1 ,   MISCREG_IL1DATA1_EL1 , MISCREG_IL1DATA2_EL1 , MISCREG_IL1DATA3_EL1 , MISCREG_DL1DATA0_EL1 ,   MISCREG_DL1DATA1_EL1 , MISCREG_DL1DATA2_EL1 , MISCREG_DL1DATA3_EL1 , MISCREG_DL1DATA4_EL1 ,   MISCREG_L2ACTLR_EL1 , MISCREG_CPUACTLR_EL1 , MISCREG_CPUECTLR_EL1 , MISCREG_CPUMERRSR_EL1 ,   MISCREG_L2MERRSR_EL1 , MISCREG_CBAR_EL1 , MISCREG_CONTEXTIDR_EL2 , MISCREG_TTBR1_EL2 ,   MISCREG_ID_AA64MMFR2_EL1 , MISCREG_ID_AA64MMFR3_EL1 , MISCREG_APDAKeyHi_EL1 , MISCREG_APDAKeyLo_EL1 ,   MISCREG_APDBKeyHi_EL1 , MISCREG_APDBKeyLo_EL1 , MISCREG_APGAKeyHi_EL1 , MISCREG_APGAKeyLo_EL1 ,   MISCREG_APIAKeyHi_EL1 , MISCREG_APIAKeyLo_EL1 , MISCREG_APIBKeyHi_EL1 , MISCREG_APIBKeyLo_EL1 ,   MISCREG_ICC_PMR_EL1 , MISCREG_ICC_IAR0_EL1 , MISCREG_ICC_EOIR0_EL1 , MISCREG_ICC_HPPIR0_EL1 ,   MISCREG_ICC_BPR0_EL1 , MISCREG_ICC_AP0R0_EL1 , MISCREG_ICC_AP0R1_EL1 , MISCREG_ICC_AP0R2_EL1 ,   MISCREG_ICC_AP0R3_EL1 , MISCREG_ICC_AP1R0_EL1 , MISCREG_ICC_AP1R0_EL1_NS , MISCREG_ICC_AP1R0_EL1_S ,   MISCREG_ICC_AP1R1_EL1 , MISCREG_ICC_AP1R1_EL1_NS , MISCREG_ICC_AP1R1_EL1_S , MISCREG_ICC_AP1R2_EL1 ,   MISCREG_ICC_AP1R2_EL1_NS , MISCREG_ICC_AP1R2_EL1_S , MISCREG_ICC_AP1R3_EL1 , MISCREG_ICC_AP1R3_EL1_NS ,   MISCREG_ICC_AP1R3_EL1_S , MISCREG_ICC_DIR_EL1 , MISCREG_ICC_RPR_EL1 , MISCREG_ICC_SGI1R_EL1 ,   MISCREG_ICC_ASGI1R_EL1 , MISCREG_ICC_SGI0R_EL1 , MISCREG_ICC_IAR1_EL1 , MISCREG_ICC_EOIR1_EL1 ,   MISCREG_ICC_HPPIR1_EL1 , MISCREG_ICC_BPR1_EL1 , MISCREG_ICC_BPR1_EL1_NS , MISCREG_ICC_BPR1_EL1_S ,   MISCREG_ICC_CTLR_EL1 , MISCREG_ICC_CTLR_EL1_NS , MISCREG_ICC_CTLR_EL1_S , MISCREG_ICC_SRE_EL1 ,   MISCREG_ICC_SRE_EL1_NS , MISCREG_ICC_SRE_EL1_S , MISCREG_ICC_IGRPEN0_EL1 , MISCREG_ICC_IGRPEN1_EL1 ,   MISCREG_ICC_IGRPEN1_EL1_NS , MISCREG_ICC_IGRPEN1_EL1_S , MISCREG_ICC_SRE_EL2 , MISCREG_ICC_CTLR_EL3 ,   MISCREG_ICC_SRE_EL3 , MISCREG_ICC_IGRPEN1_EL3 , MISCREG_ICH_AP0R0_EL2 , MISCREG_ICH_AP0R1_EL2 ,   MISCREG_ICH_AP0R2_EL2 , MISCREG_ICH_AP0R3_EL2 , MISCREG_ICH_AP1R0_EL2 , MISCREG_ICH_AP1R1_EL2 ,   MISCREG_ICH_AP1R2_EL2 , MISCREG_ICH_AP1R3_EL2 , MISCREG_ICH_HCR_EL2 , MISCREG_ICH_VTR_EL2 ,   MISCREG_ICH_MISR_EL2 , MISCREG_ICH_EISR_EL2 , MISCREG_ICH_ELRSR_EL2 , MISCREG_ICH_VMCR_EL2 ,   MISCREG_ICH_LR0_EL2 , MISCREG_ICH_LR1_EL2 , MISCREG_ICH_LR2_EL2 , MISCREG_ICH_LR3_EL2 ,   MISCREG_ICH_LR4_EL2 , MISCREG_ICH_LR5_EL2 , MISCREG_ICH_LR6_EL2 , MISCREG_ICH_LR7_EL2 ,   MISCREG_ICH_LR8_EL2 , MISCREG_ICH_LR9_EL2 , MISCREG_ICH_LR10_EL2 , MISCREG_ICH_LR11_EL2 ,   MISCREG_ICH_LR12_EL2 , MISCREG_ICH_LR13_EL2 , MISCREG_ICH_LR14_EL2 , MISCREG_ICH_LR15_EL2 ,   MISCREG_ICV_PMR_EL1 , MISCREG_ICV_IAR0_EL1 , MISCREG_ICV_EOIR0_EL1 , MISCREG_ICV_HPPIR0_EL1 ,   MISCREG_ICV_BPR0_EL1 , MISCREG_ICV_AP0R0_EL1 , MISCREG_ICV_AP0R1_EL1 , MISCREG_ICV_AP0R2_EL1 ,   MISCREG_ICV_AP0R3_EL1 , MISCREG_ICV_AP1R0_EL1 , MISCREG_ICV_AP1R0_EL1_NS , MISCREG_ICV_AP1R0_EL1_S ,   MISCREG_ICV_AP1R1_EL1 , MISCREG_ICV_AP1R1_EL1_NS , MISCREG_ICV_AP1R1_EL1_S , MISCREG_ICV_AP1R2_EL1 ,   MISCREG_ICV_AP1R2_EL1_NS , MISCREG_ICV_AP1R2_EL1_S , MISCREG_ICV_AP1R3_EL1 , MISCREG_ICV_AP1R3_EL1_NS ,   MISCREG_ICV_AP1R3_EL1_S , MISCREG_ICV_DIR_EL1 , MISCREG_ICV_RPR_EL1 , MISCREG_ICV_SGI1R_EL1 ,   MISCREG_ICV_ASGI1R_EL1 , MISCREG_ICV_SGI0R_EL1 , MISCREG_ICV_IAR1_EL1 , MISCREG_ICV_EOIR1_EL1 ,   MISCREG_ICV_HPPIR1_EL1 , MISCREG_ICV_BPR1_EL1 , MISCREG_ICV_BPR1_EL1_NS , MISCREG_ICV_BPR1_EL1_S ,   MISCREG_ICV_CTLR_EL1 , MISCREG_ICV_CTLR_EL1_NS , MISCREG_ICV_CTLR_EL1_S , MISCREG_ICV_SRE_EL1 ,   MISCREG_ICV_SRE_EL1_NS , MISCREG_ICV_SRE_EL1_S , MISCREG_ICV_IGRPEN0_EL1 , MISCREG_ICV_IGRPEN1_EL1 ,   MISCREG_ICV_IGRPEN1_EL1_NS , MISCREG_ICV_IGRPEN1_EL1_S , MISCREG_ICC_AP0R0 , MISCREG_ICC_AP0R1 ,   MISCREG_ICC_AP0R2 , MISCREG_ICC_AP0R3 , MISCREG_ICC_AP1R0 , MISCREG_ICC_AP1R0_NS ,   MISCREG_ICC_AP1R0_S , MISCREG_ICC_AP1R1 , MISCREG_ICC_AP1R1_NS , MISCREG_ICC_AP1R1_S ,   MISCREG_ICC_AP1R2 , MISCREG_ICC_AP1R2_NS , MISCREG_ICC_AP1R2_S , MISCREG_ICC_AP1R3 ,   MISCREG_ICC_AP1R3_NS , MISCREG_ICC_AP1R3_S , MISCREG_ICC_ASGI1R , MISCREG_ICC_BPR0 ,   MISCREG_ICC_BPR1 , MISCREG_ICC_BPR1_NS , MISCREG_ICC_BPR1_S , MISCREG_ICC_CTLR ,   MISCREG_ICC_CTLR_NS , MISCREG_ICC_CTLR_S , MISCREG_ICC_DIR , MISCREG_ICC_EOIR0 ,   MISCREG_ICC_EOIR1 , MISCREG_ICC_HPPIR0 , MISCREG_ICC_HPPIR1 , MISCREG_ICC_HSRE ,   MISCREG_ICC_IAR0 , MISCREG_ICC_IAR1 , MISCREG_ICC_IGRPEN0 , MISCREG_ICC_IGRPEN1 ,   MISCREG_ICC_IGRPEN1_NS , MISCREG_ICC_IGRPEN1_S , MISCREG_ICC_MCTLR , MISCREG_ICC_MGRPEN1 ,   MISCREG_ICC_MSRE , MISCREG_ICC_PMR , MISCREG_ICC_RPR , MISCREG_ICC_SGI0R ,   MISCREG_ICC_SGI1R , MISCREG_ICC_SRE , MISCREG_ICC_SRE_NS , MISCREG_ICC_SRE_S ,   MISCREG_ICH_AP0R0 , MISCREG_ICH_AP0R1 , MISCREG_ICH_AP0R2 , MISCREG_ICH_AP0R3 ,   MISCREG_ICH_AP1R0 , MISCREG_ICH_AP1R1 , MISCREG_ICH_AP1R2 , MISCREG_ICH_AP1R3 ,   MISCREG_ICH_HCR , MISCREG_ICH_VTR , MISCREG_ICH_MISR , MISCREG_ICH_EISR ,   MISCREG_ICH_ELRSR , MISCREG_ICH_VMCR , MISCREG_ICH_LR0 , MISCREG_ICH_LR1 ,   MISCREG_ICH_LR2 , MISCREG_ICH_LR3 , MISCREG_ICH_LR4 , MISCREG_ICH_LR5 ,   MISCREG_ICH_LR6 , MISCREG_ICH_LR7 , MISCREG_ICH_LR8 , MISCREG_ICH_LR9 ,   MISCREG_ICH_LR10 , MISCREG_ICH_LR11 , MISCREG_ICH_LR12 , MISCREG_ICH_LR13 ,   MISCREG_ICH_LR14 , MISCREG_ICH_LR15 , MISCREG_ICH_LRC0 , MISCREG_ICH_LRC1 ,   MISCREG_ICH_LRC2 , MISCREG_ICH_LRC3 , MISCREG_ICH_LRC4 , MISCREG_ICH_LRC5 ,   MISCREG_ICH_LRC6 , MISCREG_ICH_LRC7 , MISCREG_ICH_LRC8 , MISCREG_ICH_LRC9 ,   MISCREG_ICH_LRC10 , MISCREG_ICH_LRC11 , MISCREG_ICH_LRC12 , MISCREG_ICH_LRC13 ,   MISCREG_ICH_LRC14 , MISCREG_ICH_LRC15 , MISCREG_ID_AA64ZFR0_EL1 , MISCREG_ZCR_EL3 ,   MISCREG_ZCR_EL2 , MISCREG_ZCR_EL12 , MISCREG_ZCR_EL1 , MISCREG_ID_AA64SMFR0_EL1 ,   MISCREG_SVCR , MISCREG_SMIDR_EL1 , MISCREG_SMPRI_EL1 , MISCREG_SMPRIMAP_EL2 ,   MISCREG_SMCR_EL3 , MISCREG_SMCR_EL2 , MISCREG_SMCR_EL12 , MISCREG_SMCR_EL1 ,   MISCREG_TPIDR2_EL0 , MISCREG_MPAMSM_EL1 , MISCREG_RNDR , MISCREG_RNDRRS ,   MISCREG_HFGITR_EL2 , MISCREG_HFGRTR_EL2 , MISCREG_HFGWTR_EL2 , MISCREG_HDFGRTR_EL2 ,   MISCREG_HDFGWTR_EL2 , MISCREG_MPAMIDR_EL1 , MISCREG_MPAM0_EL1 , MISCREG_MPAM1_EL1 ,   MISCREG_MPAM2_EL2 , MISCREG_MPAM3_EL3 , MISCREG_MPAM1_EL12 , MISCREG_MPAMHCR_EL2 ,   MISCREG_MPAMVPMV_EL2 , MISCREG_MPAMVPM0_EL2 , MISCREG_MPAMVPM1_EL2 , MISCREG_MPAMVPM2_EL2 ,   MISCREG_MPAMVPM3_EL2 , MISCREG_MPAMVPM4_EL2 , MISCREG_MPAMVPM5_EL2 , MISCREG_MPAMVPM6_EL2 ,   MISCREG_MPAMVPM7_EL2 , NUM_PHYS_MISCREGS , MISCREG_NOP , MISCREG_RAZ ,   MISCREG_UNKNOWN , MISCREG_IMPDEF_UNIMPL , MISCREG_ERRIDR_EL1 , MISCREG_ERRSELR_EL1 ,   MISCREG_ERXFR_EL1 , MISCREG_ERXCTLR_EL1 , MISCREG_ERXSTATUS_EL1 , MISCREG_ERXADDR_EL1 ,   MISCREG_ERXMISC0_EL1 , MISCREG_ERXMISC1_EL1 , MISCREG_DISR_EL1 , MISCREG_VSESR_EL2 ,   MISCREG_VDISR_EL2 , MISCREG_PAN , MISCREG_UAO , NUM_MISCREGS }
enum	MiscRegInfo {   MISCREG_IMPLEMENTED , MISCREG_UNVERIFIABLE , MISCREG_UNSERIALIZE , MISCREG_WARN_NOT_FAIL ,   MISCREG_MUTEX , MISCREG_BANKED , MISCREG_BANKED64 , MISCREG_BANKED_CHILD ,   MISCREG_USR_NS_RD , MISCREG_USR_NS_WR , MISCREG_USR_S_RD , MISCREG_USR_S_WR ,   MISCREG_PRI_NS_RD , MISCREG_PRI_NS_WR , MISCREG_PRI_S_RD , MISCREG_PRI_S_WR ,   MISCREG_HYP_NS_RD , MISCREG_HYP_NS_WR , MISCREG_HYP_S_RD , MISCREG_HYP_S_WR ,   MISCREG_MON_NS0_RD , MISCREG_MON_NS0_WR , MISCREG_MON_NS1_RD , MISCREG_MON_NS1_WR ,   NUM_MISCREG_INFOS }
enum	ArmExtendType {   UXTB = 0 , UXTH = 1 , UXTW = 2 , UXTX = 3 ,   SXTB = 4 , SXTH = 5 , SXTW = 6 , SXTX = 7 }
enum	ConvertType {   SINGLE_TO_DOUBLE , SINGLE_TO_WORD , SINGLE_TO_LONG , DOUBLE_TO_SINGLE ,   DOUBLE_TO_WORD , DOUBLE_TO_LONG , LONG_TO_SINGLE , LONG_TO_DOUBLE ,   LONG_TO_WORD , LONG_TO_PS , WORD_TO_SINGLE , WORD_TO_DOUBLE ,   WORD_TO_LONG , WORD_TO_PS , PL_TO_SINGLE , PU_TO_SINGLE }
enum	RoundMode { RND_ZERO , RND_DOWN , RND_UP , RND_NEAREST }
enum	ExceptionLevel { EL0 = 0 , EL1 , EL2 , EL3 }
enum class	TranslationRegime { EL10 , EL20 , EL2 , EL3 }
enum	OperatingMode {   MODE_EL0T = 0x0 , MODE_EL1T = 0x4 , MODE_EL1H = 0x5 , MODE_EL2T = 0x8 ,   MODE_EL2H = 0x9 , MODE_EL3T = 0xC , MODE_EL3H = 0xD , MODE_USER = 16 ,   MODE_FIQ = 17 , MODE_IRQ = 18 , MODE_SVC = 19 , MODE_MON = 22 ,   MODE_ABORT = 23 , MODE_HYP = 26 , MODE_UNDEFINED = 27 , MODE_SYSTEM = 31 ,   MODE_MAXMODE = MODE_SYSTEM }
enum class	ExceptionClass {   INVALID = -1 , UNKNOWN = 0x0 , TRAPPED_WFI_WFE = 0x1 , TRAPPED_CP15_MCR_MRC = 0x3 ,   TRAPPED_CP15_MCRR_MRRC = 0x4 , TRAPPED_CP14_MCR_MRC = 0x5 , TRAPPED_CP14_LDC_STC = 0x6 , TRAPPED_HCPTR = 0x7 ,   TRAPPED_SIMD_FP = 0x7 , TRAPPED_CP10_MRC_VMRS = 0x8 , TRAPPED_PAC = 0x9 , TRAPPED_BXJ = 0xA ,   TRAPPED_CP14_MCRR_MRRC = 0xC , ILLEGAL_INST = 0xE , SVC_TO_HYP = 0x11 , SVC = 0x11 ,   HVC = 0x12 , SMC_TO_HYP = 0x13 , SMC = 0x13 , SVC_64 = 0x15 ,   HVC_64 = 0x16 , SMC_64 = 0x17 , TRAPPED_MSR_MRS_64 = 0x18 , TRAPPED_SVE = 0x19 ,   TRAPPED_ERET = 0x1A , TRAPPED_SME = 0x1D , PREFETCH_ABORT_TO_HYP = 0x20 , PREFETCH_ABORT_LOWER_EL = 0x20 ,   PREFETCH_ABORT_FROM_HYP = 0x21 , PREFETCH_ABORT_CURR_EL = 0x21 , PC_ALIGNMENT = 0x22 , DATA_ABORT_TO_HYP = 0x24 ,   DATA_ABORT_LOWER_EL = 0x24 , DATA_ABORT_FROM_HYP = 0x25 , DATA_ABORT_CURR_EL = 0x25 , STACK_PTR_ALIGNMENT = 0x26 ,   FP_EXCEPTION = 0x28 , FP_EXCEPTION_64 = 0x2C , SERROR = 0x2F , HW_BREAKPOINT = 0x30 ,   HW_BREAKPOINT_LOWER_EL = 0x30 , HW_BREAKPOINT_CURR_EL = 0x31 , SOFTWARE_STEP = 0x32 , SOFTWARE_STEP_LOWER_EL = 0x32 ,   SOFTWARE_STEP_CURR_EL = 0x33 , WATCHPOINT = 0x34 , WATCHPOINT_LOWER_EL = 0x34 , WATCHPOINT_CURR_EL = 0x35 ,   SOFTWARE_BREAKPOINT = 0x38 , VECTOR_CATCH = 0x3A , SOFTWARE_BREAKPOINT_64 = 0x3C }
enum	DecoderFault : std::uint8_t { OK = 0x0 , UNALIGNED = 0x1 , PANIC = 0x3 }
	Instruction decoder fault codes in ExtMachInst. More...

Functions
bool	getFaultVAddr (Fault fault, Addr &va)
	Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.
static SyscallReturn	issetugidFunc (SyscallDesc *desc, ThreadContext *tc)
static SyscallReturn	sysctlFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> namep, size_t nameLen, VPtr<> oldp, VPtr<> oldlenp, VPtr<> newp, size_t newlen)
static uint16_t	lsl16 (uint16_t x, uint32_t shift)
static uint16_t	lsr16 (uint16_t x, uint32_t shift)
static uint32_t	lsl32 (uint32_t x, uint32_t shift)
static uint32_t	lsr32 (uint32_t x, uint32_t shift)
static uint64_t	lsl64 (uint64_t x, uint32_t shift)
static uint64_t	lsr64 (uint64_t x, uint32_t shift)
static void	lsl128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
static void	lsr128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
static void	mul62x62 (uint64_t *x0, uint64_t *x1, uint64_t a, uint64_t b)
static void	mul64x32 (uint64_t *x0, uint64_t *x1, uint64_t a, uint32_t b)
static void	add128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
static void	sub128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
static int	cmp128 (uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
static uint16_t	fp16_normalise (uint16_t mnt, int *exp)
static uint32_t	fp32_normalise (uint32_t mnt, int *exp)
static uint64_t	fp64_normalise (uint64_t mnt, int *exp)
static void	fp128_normalise (uint64_t *mnt0, uint64_t *mnt1, int *exp)
static uint16_t	fp16_pack (uint16_t sgn, uint16_t exp, uint16_t mnt)
static uint32_t	fp32_pack (uint32_t sgn, uint32_t exp, uint32_t mnt)
static uint64_t	fp64_pack (uint64_t sgn, uint64_t exp, uint64_t mnt)
static uint16_t	fp16_zero (int sgn)
static uint32_t	fp32_zero (int sgn)
static uint64_t	fp64_zero (int sgn)
static uint16_t	fp16_max_normal (int sgn)
static uint32_t	fp32_max_normal (int sgn)
static uint64_t	fp64_max_normal (int sgn)
static uint16_t	fp16_infinity (int sgn)
static uint32_t	fp32_infinity (int sgn)
static uint64_t	fp64_infinity (int sgn)
static uint16_t	fp16_defaultNaN ()
static uint32_t	fp32_defaultNaN ()
static uint64_t	fp64_defaultNaN ()
static void	fp16_unpack (int *sgn, int *exp, uint16_t *mnt, uint16_t x, int mode, int *flags)
static void	fp32_unpack (int *sgn, int *exp, uint32_t *mnt, uint32_t x, int mode, int *flags)
static void	fp64_unpack (int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode, int *flags)
static int	fp16_is_NaN (int exp, uint16_t mnt)
static int	fp32_is_NaN (int exp, uint32_t mnt)
static int	fp64_is_NaN (int exp, uint64_t mnt)
static int	fp16_is_signalling_NaN (int exp, uint16_t mnt)
static int	fp32_is_signalling_NaN (int exp, uint32_t mnt)
static int	fp64_is_signalling_NaN (int exp, uint64_t mnt)
static int	fp16_is_quiet_NaN (int exp, uint16_t mnt)
static int	fp32_is_quiet_NaN (int exp, uint32_t mnt)
static int	fp64_is_quiet_NaN (int exp, uint64_t mnt)
static int	fp16_is_infinity (int exp, uint16_t mnt)
static int	fp32_is_infinity (int exp, uint32_t mnt)
static int	fp64_is_infinity (int exp, uint64_t mnt)
static uint16_t	fp16_process_NaN (uint16_t a, int mode, int *flags)
static uint32_t	fp32_process_NaN (uint32_t a, int mode, int *flags)
static uint64_t	fp64_process_NaN (uint64_t a, int mode, int *flags)
static uint16_t	fp16_process_NaNs (uint16_t a, uint16_t b, int mode, int *flags)
static uint32_t	fp32_process_NaNs (uint32_t a, uint32_t b, int mode, int *flags)
static uint64_t	fp64_process_NaNs (uint64_t a, uint64_t b, int mode, int *flags)
static uint16_t	fp16_process_NaNs3 (uint16_t a, uint16_t b, uint16_t c, int mode, int *flags)
static uint32_t	fp32_process_NaNs3 (uint32_t a, uint32_t b, uint32_t c, int mode, int *flags)
static uint64_t	fp64_process_NaNs3 (uint64_t a, uint64_t b, uint64_t c, int mode, int *flags)
static uint16_t	fp16_round_ (int sgn, int exp, uint16_t mnt, int rm, int mode, int *flags)
static uint16_t	fp16_round (int sgn, int exp, uint16_t mnt, int mode, int *flags)
static uint32_t	fp32_round_ (int sgn, int exp, uint32_t mnt, int rm, int mode, int *flags)
static uint32_t	fp32_round (int sgn, int exp, uint32_t mnt, int mode, int *flags)
static uint64_t	fp64_round_ (int sgn, int exp, uint64_t mnt, int rm, int mode, int *flags)
static uint64_t	fp64_round (int sgn, int exp, uint64_t mnt, int mode, int *flags)
static int	fp16_compare_eq (uint16_t a, uint16_t b, int mode, int *flags)
static int	fp16_compare_ge (uint16_t a, uint16_t b, int mode, int *flags)
static int	fp16_compare_gt (uint16_t a, uint16_t b, int mode, int *flags)
static int	fp16_compare_un (uint16_t a, uint16_t b, int mode, int *flags)
static int	fp32_compare_eq (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp32_compare_ge (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp32_compare_gt (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp32_compare_un (uint32_t a, uint32_t b, int mode, int *flags)
static int	fp64_compare_eq (uint64_t a, uint64_t b, int mode, int *flags)
static int	fp64_compare_ge (uint64_t a, uint64_t b, int mode, int *flags)
static int	fp64_compare_gt (uint64_t a, uint64_t b, int mode, int *flags)
static int	fp64_compare_un (uint64_t a, uint64_t b, int mode, int *flags)
static uint16_t	fp16_add (uint16_t a, uint16_t b, int neg, int mode, int *flags)
static uint32_t	fp32_add (uint32_t a, uint32_t b, int neg, int mode, int *flags)
static uint64_t	fp64_add (uint64_t a, uint64_t b, int neg, int mode, int *flags)
static uint16_t	fp16_mul (uint16_t a, uint16_t b, int mode, int *flags)
static uint32_t	fp32_mul (uint32_t a, uint32_t b, int mode, int *flags)
static uint64_t	fp64_mul (uint64_t a, uint64_t b, int mode, int *flags)
static uint16_t	fp16_muladd (uint16_t a, uint16_t b, uint16_t c, int scale, int mode, int *flags)
static uint32_t	fp32_muladd (uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int *flags)
static uint64_t	fp64_muladd (uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int *flags)
static uint16_t	fp16_div (uint16_t a, uint16_t b, int mode, int *flags)
static uint32_t	fp32_div (uint32_t a, uint32_t b, int mode, int *flags)
static uint64_t	fp64_div (uint64_t a, uint64_t b, int mode, int *flags)
static void	set_fpscr0 (FPSCR &fpscr, int flags)
static uint16_t	fp16_scale (uint16_t a, int16_t b, int mode, int *flags)
static uint32_t	fp32_scale (uint32_t a, int32_t b, int mode, int *flags)
static uint64_t	fp64_scale (uint64_t a, int64_t b, int mode, int *flags)
static uint16_t	fp16_sqrt (uint16_t a, int mode, int *flags)
static uint32_t	fp32_sqrt (uint32_t a, int mode, int *flags)
static uint64_t	fp64_sqrt (uint64_t a, int mode, int *flags)
static int	modeConv (FPSCR fpscr)
static void	set_fpscr (FPSCR &fpscr, int flags)
template<>
bool	fplibCompareEQ (uint16_t a, uint16_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint16_t a, uint16_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint16_t a, uint16_t b, FPSCR &fpscr)
template<>
bool	fplibCompareUN (uint16_t a, uint16_t b, FPSCR &fpscr)
template<>
bool	fplibCompareEQ (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareUN (uint32_t a, uint32_t b, FPSCR &fpscr)
template<>
bool	fplibCompareEQ (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
bool	fplibCompareUN (uint64_t a, uint64_t b, FPSCR &fpscr)
template<>
uint16_t	fplibAbs (uint16_t op)
template<>
uint32_t	fplibAbs (uint32_t op)
template<>
uint64_t	fplibAbs (uint64_t op)
template<>
uint16_t	fplibAdd (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibAdd (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibAdd (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
int	fplibCompare (uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr)
template<>
int	fplibCompare (uint32_t op1, uint32_t op2, bool signal_nans, FPSCR &fpscr)
template<>
int	fplibCompare (uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr)
static uint16_t	fp16_FPConvertNaN_32 (uint32_t op)
static uint16_t	fp16_FPConvertNaN_64 (uint64_t op)
static uint32_t	fp32_FPConvertNaN_16 (uint16_t op)
static uint32_t	fp32_FPConvertNaN_64 (uint64_t op)
static uint64_t	fp64_FPConvertNaN_16 (uint16_t op)
static uint64_t	fp64_FPConvertNaN_32 (uint32_t op)
static uint16_t	fp16_FPOnePointFive (int sgn)
static uint32_t	fp32_FPOnePointFive (int sgn)
static uint64_t	fp64_FPOnePointFive (int sgn)
static uint16_t	fp16_FPThree (int sgn)
static uint32_t	fp32_FPThree (int sgn)
static uint64_t	fp64_FPThree (int sgn)
static uint16_t	fp16_FPTwo (int sgn)
static uint32_t	fp32_FPTwo (int sgn)
static uint64_t	fp64_FPTwo (int sgn)
template<>
uint16_t	fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibMulAdd (uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMulAdd (uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMulAdd (uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibDiv (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibDiv (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibDiv (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibExpA (uint16_t op)
template<>
uint32_t	fplibExpA (uint32_t op)
template<>
uint64_t	fplibExpA (uint64_t op)
static uint16_t	fp16_repack (int sgn, int exp, uint16_t mnt)
static uint32_t	fp32_repack (int sgn, int exp, uint32_t mnt)
static uint64_t	fp64_repack (int sgn, int exp, uint64_t mnt)
static void	fp16_minmaxnum (uint16_t *op1, uint16_t *op2, int sgn)
static void	fp32_minmaxnum (uint32_t *op1, uint32_t *op2, int sgn)
static void	fp64_minmaxnum (uint64_t *op1, uint64_t *op2, int sgn)
template<>
uint16_t	fplibMax (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMax (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMax (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMaxNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMaxNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMaxNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMin (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMin (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMin (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMinNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMinNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMinNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMulX (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMulX (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMulX (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibNeg (uint16_t op)
template<>
uint32_t	fplibNeg (uint32_t op)
template<>
uint64_t	fplibNeg (uint64_t op)
template<>
uint16_t	fplibRSqrtEstimate (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRSqrtEstimate (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRSqrtEstimate (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibRSqrtStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRSqrtStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibRSqrtStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibRecipEstimate (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRecipEstimate (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecipEstimate (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibRecipStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRecipStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibRecipStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibRecpX (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRecpX (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecpX (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibRoundInt (uint16_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint32_t	fplibRoundInt (uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint64_t	fplibRoundInt (uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint16_t	fplibScale (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibScale (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibScale (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibSqrt (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibSqrt (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibSqrt (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibSub (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibSub (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibSub (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibTrigMulAdd (uint8_t coeff_index, uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibTrigMulAdd (uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibTrigMulAdd (uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibTrigSMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibTrigSMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibTrigSMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibTrigSSel (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibTrigSSel (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibTrigSSel (uint64_t op1, uint64_t op2, FPSCR &fpscr)
static uint64_t	FPToFixed_64 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
static uint32_t	FPToFixed_32 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
static uint16_t	FPToFixed_16 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
template<>
uint16_t	fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
uint32_t	fplibFPToFixedJS (uint64_t op, FPSCR &fpscr, bool Is64, uint8_t &nz)
	Floating-point JS convert to a signed integer, with rounding to zero.
template<>
uint64_t	fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
static uint16_t	fp16_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
static uint32_t	fp32_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
static uint64_t	fp64_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
template<>
uint16_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibInfinity (int sgn)
template<>
uint32_t	fplibInfinity (int sgn)
template<>
uint64_t	fplibInfinity (int sgn)
template<>
uint16_t	fplibDefaultNaN ()
template<>
uint32_t	fplibDefaultNaN ()
template<>
uint64_t	fplibDefaultNaN ()
static FPRounding	FPCRRounding (FPSCR &fpscr)
template<class T >
T	fplibAbs (T op)
	Floating-point absolute value.
template<class T >
T	fplibAdd (T op1, T op2, FPSCR &fpscr)
	Floating-point add.
template<class T >
int	fplibCompare (T op1, T op2, bool signal_nans, FPSCR &fpscr)
	Floating-point compare (quiet and signaling).
template<class T >
bool	fplibCompareEQ (T op1, T op2, FPSCR &fpscr)
	Floating-point compare equal.
template<class T >
bool	fplibCompareGE (T op1, T op2, FPSCR &fpscr)
	Floating-point compare greater than or equal.
template<class T >
bool	fplibCompareGT (T op1, T op2, FPSCR &fpscr)
	Floating-point compare greater than.
template<class T >
bool	fplibCompareUN (T op1, T op2, FPSCR &fpscr)
	Floating-point compare unordered.
template<class T1 , class T2 >
T2	fplibConvert (T1 op, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert precision.
template<class T >
T	fplibDiv (T op1, T op2, FPSCR &fpscr)
	Floating-point division.
template<class T >
T	fplibExpA (T op)
	Floating-point exponential accelerator.
template<class T >
T	fplibMax (T op1, T op2, FPSCR &fpscr)
	Floating-point maximum.
template<class T >
T	fplibMaxNum (T op1, T op2, FPSCR &fpscr)
	Floating-point maximum number.
template<class T >
T	fplibMin (T op1, T op2, FPSCR &fpscr)
	Floating-point minimum.
template<class T >
T	fplibMinNum (T op1, T op2, FPSCR &fpscr)
	Floating-point minimum number.
template<class T >
T	fplibMul (T op1, T op2, FPSCR &fpscr)
	Floating-point multiply.
template<class T >
T	fplibMulAdd (T addend, T op1, T op2, FPSCR &fpscr)
	Floating-point multiply-add.
template<class T >
T	fplibMulX (T op1, T op2, FPSCR &fpscr)
	Floating-point multiply extended.
template<class T >
T	fplibNeg (T op)
	Floating-point negate.
template<class T >
T	fplibRSqrtEstimate (T op, FPSCR &fpscr)
	Floating-point reciprocal square root estimate.
template<class T >
T	fplibRSqrtStepFused (T op1, T op2, FPSCR &fpscr)
	Floating-point reciprocal square root step.
template<class T >
T	fplibRecipEstimate (T op, FPSCR &fpscr)
	Floating-point reciprocal estimate.
template<class T >
T	fplibRecipStepFused (T op1, T op2, FPSCR &fpscr)
	Floating-point reciprocal step.
template<class T >
T	fplibRecpX (T op, FPSCR &fpscr)
	Floating-point reciprocal exponent.
template<class T >
T	fplibRoundInt (T op, FPRounding rounding, bool exact, FPSCR &fpscr)
	Floating-point convert to integer.
template<class T >
T	fplibScale (T op1, T op2, FPSCR &fpscr)
	Floating-point adjust exponent.
template<class T >
T	fplibSqrt (T op, FPSCR &fpscr)
	Floating-point square root.
template<class T >
T	fplibSub (T op1, T op2, FPSCR &fpscr)
	Floating-point subtract.
template<class T >
T	fplibTrigMulAdd (uint8_t coeff_index, T op1, T op2, FPSCR &fpscr)
	Floating-point trigonometric multiply-add coefficient.
template<class T >
T	fplibTrigSMul (T op1, T op2, FPSCR &fpscr)
	Floating-point trigonometric starting value.
template<class T >
T	fplibTrigSSel (T op1, T op2, FPSCR &fpscr)
	Floating-point trigonometric select coefficient.
template<class T1 , class T2 >
T2	fplibFPToFixed (T1 op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert to fixed-point.
template<class T >
T	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
	Floating-point convert from fixed-point.
template<class T >
T	fplibInfinity (int sgn)
	Floating-point value for +/- infinity.
template<class T >
T	fplibDefaultNaN ()
	Foating-point value for default NaN.
template<>
uint16_t	fplibAbs (uint16_t op)
template<>
uint32_t	fplibAbs (uint32_t op)
template<>
uint64_t	fplibAbs (uint64_t op)
template<>
uint16_t	fplibAdd (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibAdd (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibAdd (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
int	fplibCompare (uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr)
template<>
int	fplibCompare (uint32_t op1, uint32_t op2, bool signal_nans, FPSCR &fpscr)
template<>
int	fplibCompare (uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr)
template<>
bool	fplibCompareEQ (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareEQ (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareEQ (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareGE (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareGT (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareUN (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareUN (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
bool	fplibCompareUN (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibDiv (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibDiv (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibDiv (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibExpA (uint16_t op)
template<>
uint32_t	fplibExpA (uint32_t op)
template<>
uint64_t	fplibExpA (uint64_t op)
template<>
uint16_t	fplibMax (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMax (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMax (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMaxNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMaxNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMaxNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMin (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMin (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMin (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMinNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMinNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMinNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMulAdd (uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMulAdd (uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMulAdd (uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibMulX (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibMulX (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibMulX (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibNeg (uint16_t op)
template<>
uint32_t	fplibNeg (uint32_t op)
template<>
uint64_t	fplibNeg (uint64_t op)
template<>
uint16_t	fplibRSqrtEstimate (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRSqrtEstimate (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRSqrtEstimate (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibRSqrtStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRSqrtStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibRSqrtStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibRecipEstimate (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRecipEstimate (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecipEstimate (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibRecipStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibRecipStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibRecipStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibRecpX (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibRecpX (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibRecpX (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibRoundInt (uint16_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint32_t	fplibRoundInt (uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint64_t	fplibRoundInt (uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
template<>
uint16_t	fplibScale (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibScale (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibScale (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibSqrt (uint16_t op, FPSCR &fpscr)
template<>
uint32_t	fplibSqrt (uint32_t op, FPSCR &fpscr)
template<>
uint64_t	fplibSqrt (uint64_t op, FPSCR &fpscr)
template<>
uint16_t	fplibSub (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibSub (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibSub (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibTrigMulAdd (uint8_t coeff_index, uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibTrigMulAdd (uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibTrigMulAdd (uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibTrigSMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibTrigSMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibTrigSMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibTrigSSel (uint16_t op1, uint16_t op2, FPSCR &fpscr)
template<>
uint32_t	fplibTrigSSel (uint32_t op1, uint32_t op2, FPSCR &fpscr)
template<>
uint64_t	fplibTrigSSel (uint64_t op1, uint64_t op2, FPSCR &fpscr)
template<>
uint16_t	fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint32_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint64_t	fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
template<>
uint16_t	fplibInfinity (int sgn)
template<>
uint32_t	fplibInfinity (int sgn)
template<>
uint64_t	fplibInfinity (int sgn)
template<>
uint16_t	fplibDefaultNaN ()
template<>
uint32_t	fplibDefaultNaN ()
template<>
uint64_t	fplibDefaultNaN ()
static unsigned int	number_of_ones (int32_t val)
void	writeVecElem (VReg *dest, XReg src, int index, int eSize)
	Write a single NEON vector element leaving the others untouched.
XReg	readVecElem (VReg src, int index, int eSize)
	Read a single NEON vector element.
static uint32_t	rotate_imm (uint32_t immValue, uint32_t rotateValue)
static uint32_t	modified_imm (uint8_t ctrlImm, uint8_t dataImm)
static uint64_t	simd_modified_imm (bool op, uint8_t cmode, uint8_t data, bool &immValid, bool isAarch64=false)
static uint64_t	vfp_modified_imm (uint8_t data, FpDataType dtype)
static FpDataType	decode_fp_data_type (uint8_t encoding)
static uint8_t	getRestoredITBits (ThreadContext *tc, CPSR spsr)
static bool	illegalExceptionReturn (ThreadContext *tc, CPSR cpsr, CPSR spsr)
const char *	svePredTypeToStr (SvePredType pt)
	Returns the specifier for the predication type pt as a string.
std::string	sveDisasmPredCountImm (uint8_t imm)
	Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.
unsigned int	sveDecodePredCount (uint8_t imm, unsigned int num_elems)
	Returns the actual number of elements active for PTRUE(S) instructions.
uint64_t	sveExpandFpImmAddSub (uint8_t imm, uint8_t size)
	Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).
uint64_t	sveExpandFpImmMaxMin (uint8_t imm, uint8_t size)
	Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).
uint64_t	sveExpandFpImmMul (uint8_t imm, uint8_t size)
	Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).
VfpSavedState	prepFpState (uint32_t rMode)
void	finishVfp (FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
template<class fpType >
fpType	fixDest (bool flush, bool defaultNan, fpType val, fpType op1)
template float	fixDest< float > (bool flush, bool defaultNan, float val, float op1)
template double	fixDest< double > (bool flush, bool defaultNan, double val, double op1)
template<class fpType >
fpType	fixDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
template float	fixDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
template double	fixDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
template<class fpType >
fpType	fixDivDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
template float	fixDivDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
template double	fixDivDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
float	fixFpDFpSDest (FPSCR fpscr, double val)
double	fixFpSFpDDest (FPSCR fpscr, float val)
static uint16_t	vcvtFpFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble)
uint16_t	vcvtFpSFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
uint16_t	vcvtFpDFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
static uint64_t	vcvtFpHFp (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
double	vcvtFpHFpD (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
float	vcvtFpHFpS (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
float	vfpUFixedToFpS (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
float	vfpSFixedToFpS (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
double	vfpUFixedToFpD (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
double	vfpSFixedToFpD (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
static double	recipSqrtEstimate (double a)
float	fprSqrtEstimate (FPSCR &fpscr, float op)
uint32_t	unsignedRSqrtEstimate (uint32_t op)
static double	recipEstimate (double a)
float	fpRecipEstimate (FPSCR &fpscr, float op)
uint32_t	unsignedRecipEstimate (uint32_t op)
FPSCR	fpStandardFPSCRValue (const FPSCR &fpscr)
template<class T >
static void	setVfpMicroFlags (VfpMicroMode mode, T &flags)
static float	bitsToFp (uint64_t, float)
static double	bitsToFp (uint64_t, double)
static uint32_t	fpToBits (float)
static uint64_t	fpToBits (double)
template<class fpType >
static bool	flushToZero (fpType &op)
template<class fpType >
static bool	flushToZero (fpType &op1, fpType &op2)
template<class fpType >
static void	vfpFlushToZero (FPSCR &fpscr, fpType &op)
template<class fpType >
static void	vfpFlushToZero (FPSCR &fpscr, fpType &op1, fpType &op2)
template<class fpType >
static bool	isSnan (fpType val)
template<class fpType >
fpType	fixDest (FPSCR fpscr, fpType val, fpType op1)
template<class fpType >
fpType	fixDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
template<class fpType >
fpType	fixDivDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
static double	makeDouble (uint32_t low, uint32_t high)
static uint32_t	lowFromDouble (double val)
static uint32_t	highFromDouble (double val)
static void	setFPExceptions (int exceptions)
template<typename T >
uint64_t	vfpFpToFixed (T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
template<typename T >
static T	fpAdd (T a, T b)
template<typename T >
static T	fpSub (T a, T b)
static float	fpAddS (float a, float b)
static double	fpAddD (double a, double b)
static float	fpSubS (float a, float b)
static double	fpSubD (double a, double b)
static float	fpDivS (float a, float b)
static double	fpDivD (double a, double b)
template<typename T >
static T	fpDiv (T a, T b)
template<typename T >
static T	fpMulX (T a, T b)
template<typename T >
static T	fpMul (T a, T b)
static float	fpMulS (float a, float b)
static double	fpMulD (double a, double b)
template<typename T >
static T	fpMulAdd (T op1, T op2, T addend)
template<typename T >
static T	fpRIntX (T a, FPSCR &fpscr)
template<typename T >
static T	fpMaxNum (T a, T b)
template<typename T >
static T	fpMax (T a, T b)
template<typename T >
static T	fpMinNum (T a, T b)
template<typename T >
static T	fpMin (T a, T b)
template<typename T >
static T	fpRSqrts (T a, T b)
template<typename T >
static T	fpRecps (T a, T b)
static float	fpRSqrtsS (float a, float b)
static float	fpRecpsS (float a, float b)
template<typename T >
static T	roundNEven (T a)
template<class XC >
static void	lockedSnoopHandler (ThreadContext *tc, XC *xc, PacketPtr pkt, Addr cacheBlockMask)
template<class XC >
static bool	lockedWriteHandler (ThreadContext *tc, XC *xc, const RequestPtr &req, Addr cacheBlockMask)
static SyscallReturn	unameFunc32 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler.
static SyscallReturn	unameFunc64 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler.
static SyscallReturn	setTLSFunc32 (SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
	Target set_tls() handler.
static SyscallReturn	setTLSFunc64 (SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
template<typename T >
MMU *	getMMUPtr (T *tc)
const PageTableOps *	getPageTableOps (GrainSize trans_granule)
bool	upperAndLowerRange (ThreadContext *tc, ExceptionLevel el)
bool	calculateTBI (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, bool data)
int	calculateBottomPACBit (ThreadContext *tc, ExceptionLevel el, bool top_bit)
Fault	trapPACUse (ThreadContext *tc, ExceptionLevel el)
uint64_t	addPAC (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t k0, bool data)
uint64_t	auth (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t K0, bool data, uint8_t errorcode)
Fault	authDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	authDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	authIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	authIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	addPACDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	addPACDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	addPACGA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	addPACIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
Fault	addPACIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
void	stripPAC (ThreadContext *tc, uint64_t A, bool data, uint64_t *out)
	BitUnion8 (ITSTATE) Bitfield< 7
	BitUnion32 (PackedIntReg) Bitfield< 31
	EndBitUnion (PackedIntReg) namespace int_reg
static const RegId &	flattenIntRegModeIndex (int reg)
static RegIndex	makeSP (RegIndex reg)
static bool	couldBeSP (RegIndex reg)
static bool	isSP (RegIndex reg)
static bool	couldBeZero (RegIndex reg)
static bool	isZero (RegIndex reg)
static RegIndex	makeZero (RegIndex reg)
template<typename ElemType >
MatTile< ElemType >	getTile (MatRegContainer &reg, uint8_t tile_idx)
template<typename ElemType >
MatTileRow< ElemType >	getTileHSlice (MatRegContainer &reg, uint8_t tile_idx, uint8_t row_idx)
template<typename ElemType >
MatTileCol< ElemType >	getTileVSlice (MatRegContainer &reg, uint8_t tile_idx, uint8_t col_idx)
template<typename ElemType >
MatRow< ElemType >	getHSlice (MatRegContainer &reg, uint8_t row_idx)
template<typename ElemType >
MatCol< ElemType >	getVSlice (MatRegContainer &reg, uint8_t col_idx)
MiscRegIndex	decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
MiscRegIndex	decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
MiscRegIndex	decodeCP15Reg64 (unsigned crm, unsigned opc1)
std::tuple< bool, bool >	canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
	Check for permission to read coprocessor registers.
std::tuple< bool, bool >	canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
	Check for permission to write coprocessor registers.
bool	AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
int	snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
int	snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
int	snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
void	preUnflattenMiscReg ()
int	unflattenMiscReg (int reg)
Fault	checkFaultAccessAArch64SysReg (MiscRegIndex reg, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst)
MiscRegIndex	decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
MiscRegIndex	decodeAArch64SysReg (const MiscRegNum64 &sys_reg)
std::optional< MiscRegNum64 >	encodeAArch64SysReg (MiscRegIndex misc_reg)
static Fault	defaultFaultE2H_EL2 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
static Fault	defaultFaultE2H_EL3 (const MiscRegLUTEntry &entry, ThreadContext *tc, const MiscRegOp64 &inst)
static CPSR	resetCPSR (ArmSystem *system)
bool	aarch64SysRegReadOnly (MiscRegIndex miscReg)
	BitUnion32 (CPSR) Bitfield< 31
	EndBitUnion (CPSR) BitUnion32(ISR) Bitfield< 8 > a
	EndBitUnion (ISR) BitUnion32(ISAR5) Bitfield< 31
	EndBitUnion (ISAR5) BitUnion32(ISAR6) Bitfield< 31
	EndBitUnion (ISAR6) BitUnion64(AA64DFR0) Bitfield< 43
	EndBitUnion (AA64DFR0) BitUnion64(AA64ISAR0) Bitfield< 63
	EndBitUnion (AA64ISAR0) BitUnion64(AA64ISAR1) Bitfield< 55
	EndBitUnion (AA64ISAR1) BitUnion64(AA64MMFR0) Bitfield< 63
	EndBitUnion (AA64MMFR0) BitUnion64(AA64MMFR1) Bitfield< 43
	EndBitUnion (AA64MMFR1) BitUnion64(AA64MMFR2) Bitfield< 63
	EndBitUnion (AA64MMFR2) BitUnion64(AA64MMFR3) Bitfield< 47
	EndBitUnion (AA64MMFR3) BitUnion64(AA64PFR0) Bitfield< 63
	EndBitUnion (AA64PFR0) BitUnion64(AA64PFR1) Bitfield< 27
	EndBitUnion (AA64PFR1) BitUnion64(AA64ZFR0) Bitfield< 59
	EndBitUnion (AA64ZFR0) BitUnion64(AA64SMFR0) Bitfield< 63 > fa64
	EndBitUnion (AA64SMFR0) BitUnion32(HDCR) Bitfield< 27 > tdcc
	EndBitUnion (HDCR) BitUnion32(HCPTR) Bitfield< 31 > tcpac
	EndBitUnion (HCPTR) BitUnion32(HSTR) Bitfield< 17 > tjdbx
	EndBitUnion (HSTR) BitUnion64(HCR) Bitfield< 55 > ttlbos
	EndBitUnion (HCR) BitUnion32(NSACR) Bitfield< 20 > nstrcdis
	EndBitUnion (NSACR) BitUnion64(SCR) Bitfield< 44 > sctlr2En
	EndBitUnion (SCR) BitUnion64(SCTLR) Bitfield< 31 > enia
	EndBitUnion (SCTLR) BitUnion32(CPACR) Bitfield< 1
	EndBitUnion (CPACR) BitUnion32(FSR) Bitfield< 3
	EndBitUnion (FSR) BitUnion32(FPSCR) Bitfield< 0 > ioc
	EndBitUnion (FPSCR) BitUnion32(FPEXC) Bitfield< 31 > ex
	EndBitUnion (FPEXC) BitUnion32(MVFR0) Bitfield< 3
	EndBitUnion (MVFR0) BitUnion32(MVFR1) Bitfield< 3
	EndBitUnion (MVFR1) BitUnion64(TTBCR) Bitfield< 2
	EndBitUnion (TTBCR) BitUnion64(TCR) Bitfield< 5
	EndBitUnion (TCR) BitUnion32(HTCR) Bitfield< 2
	EndBitUnion (HTCR) BitUnion32(VTCR_t) Bitfield< 3
	EndBitUnion (VTCR_t) BitUnion32(PRRR) Bitfield< 1
	EndBitUnion (PRRR) BitUnion32(NMRR) Bitfield< 1
	EndBitUnion (NMRR) BitUnion32(CONTEXTIDR) Bitfield< 7
	EndBitUnion (CONTEXTIDR) BitUnion32(L2CTLR) Bitfield< 2
	EndBitUnion (L2CTLR) BitUnion32(CTR) Bitfield< 3
	EndBitUnion (CTR) BitUnion32(PMSELR) Bitfield< 4
	EndBitUnion (PMSELR) BitUnion64(PAR) Bitfield< 63
	EndBitUnion (PAR) BitUnion32(ESR) Bitfield< 31
	SubBitUnion (cond_iss, 24, 0) Bitfield< 24 > cv
	EndSubBitUnion (cond_iss) SubBitUnion(data_abort_iss
	EndSubBitUnion (data_abort_iss) SubBitUnion(instruction_abort_iss
	EndSubBitUnion (instruction_abort_iss) SubBitUnion(software_step_iss
	EndSubBitUnion (software_step_iss) SubBitUnion(watchpoint_iss
	EndSubBitUnion (watchpoint_iss) EndBitUnion(ESR) BitUnion32(CPTR) Bitfield< 31 > tcpac
	EndBitUnion (CPTR) BitUnion64(ZCR) Bitfield< 3
	EndBitUnion (ZCR) BitUnion64(SMCR) Bitfield< 63
	EndBitUnion (SMCR) BitUnion64(SVCR) Bitfield< 63
	EndBitUnion (SVCR) BitUnion64(SMIDR) Bitfield< 63
	EndBitUnion (SMIDR) BitUnion64(SMPRI) Bitfield< 63
	EndBitUnion (SMPRI) BitUnion32(OSL) Bitfield< 64
	EndBitUnion (OSL) BitUnion64(DBGBCR) Bitfield< 63
	EndBitUnion (DBGBCR) BitUnion64(DBGWCR) Bitfield< 63
	EndBitUnion (DBGWCR) BitUnion32(DBGDS32) Bitfield< 31 > tfo
	EndBitUnion (DBGDS32) BitUnion32(DBGVCR) Bitfield< 31 > nsf
	EndBitUnion (DBGVCR) BitUnion32(DEVID) Bitfield< 31
	EndBitUnion (DEVID) BitUnion64(HFGITR) Bitfield< 54 > dccvac
	EndBitUnion (HFGITR) BitUnion64(HFGTR) Bitfield< 50 > nAccdataEL1
	EndBitUnion (HFGTR) BitUnion64(HDFGTR) Bitfield< 11 > osdlrEL1
	EndBitUnion (HDFGTR) BitUnion64(HCRX) Bitfield< 15 > sctlr2En
	EndBitUnion (HCRX) BitUnion64(MPAMIDR) Bitfield< 61 > hasSdeflt
	EndBitUnion (MPAMIDR) BitUnion64(MPAM) Bitfield< 63 > mpamEn
	SubBitUnion (el1, 62, 48) Bitfield< 60 > forcedNs
	EndSubBitUnion (el1) SubBitUnion(el2
	EndSubBitUnion (el2) SubBitUnion(el3
	EndSubBitUnion (el3) Bitfield< 47
	EndBitUnion (MPAM) BitUnion64(MPAMHCR) Bitfield< 31 > trapMpamIdrEL1
	BitUnion64 (ExtMachInst) Bitfield< 63
	SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
	EndSubBitUnion (puswl) Bitfield< 24
	EndBitUnion (ExtMachInst) BitUnion32(Affinity) Bitfield< 31
	EndBitUnion (Affinity) enum ArmShiftType
	BitUnion8 (OperatingMode64) Bitfield< 0 > spX
	EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
static bool	opModeIsH (OperatingMode mode)
static bool	opModeIsT (OperatingMode mode)
static ExceptionLevel	opModeToEL (OperatingMode mode)
static bool	unknownMode (OperatingMode mode)
static bool	unknownMode32 (OperatingMode mode)
static const char *	regimeToStr (TranslationRegime regime)
void	sendEvent (ThreadContext *tc)
	Send an event (SEV) to a specific PE if there isn't already a pending event.
bool	isSecure (ThreadContext *tc)
bool	isSecureBelowEL3 (ThreadContext *tc)
bool	isSecureAtEL (ThreadContext *tc, ExceptionLevel el)
ExceptionLevel	debugTargetFrom (ThreadContext *tc, bool secure)
bool	inAArch64 (ThreadContext *tc)
ExceptionLevel	currEL (const ThreadContext *tc)
	Returns the current Exception Level (EL) of the provided ThreadContext.
bool	longDescFormatInUse (ThreadContext *tc)
RegVal	readMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
	This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems)
RegVal	getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
	This helper function is returning the value of MPIDR_EL1.
static RegVal	getAff2 (ArmSystem *arm_sys, ThreadContext *tc)
static RegVal	getAff1 (ArmSystem *arm_sys, ThreadContext *tc)
static RegVal	getAff0 (ArmSystem *arm_sys, ThreadContext *tc)
Affinity	getAffinity (ArmSystem *arm_sys, ThreadContext *tc)
	Retrieves MPIDR_EL1.
bool	HaveExt (ThreadContext *tc, ArmExtension ext)
	Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.
ExceptionLevel	s1TranslationRegime (ThreadContext *tc, ExceptionLevel el)
bool	IsSecureEL2Enabled (ThreadContext *tc)
bool	EL2Enabled (ThreadContext *tc)
bool	ELIs64 (ThreadContext *tc, ExceptionLevel el)
bool	ELIs32 (ThreadContext *tc, ExceptionLevel el)
bool	ELIsInHost (ThreadContext *tc, ExceptionLevel el)
	Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions).
std::pair< bool, bool >	ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el)
	This function checks whether selected EL provided as an argument is using the AArch32 ISA.
bool	haveAArch32EL (ThreadContext *tc, ExceptionLevel el)
std::pair< bool, bool >	ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure)
bool	ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure)
bool	isBigEndian64 (const ThreadContext *tc)
bool	badMode32 (ThreadContext *tc, OperatingMode mode)
	badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32
bool	badMode (ThreadContext *tc, OperatingMode mode)
	badMode is checking if the execution mode provided as an argument is valid and implemented.
int	computeAddrTop (ThreadContext *tc, bool selbit, bool is_instr, TCR tcr, ExceptionLevel el)
Addr	maskTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, int topbit)
Addr	purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
	Removes the tag from tagged addresses if that mode is enabled.
Addr	purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool is_instr)
Addr	truncPage (Addr addr)
Addr	roundPage (Addr addr)
Fault	mcrMrc15Trap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
bool	mcrMrc15TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
bool	mcrMrc14TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss)
Fault	mcrrMrrc15Trap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm)
bool	mcrrMrrc15TrapToHyp (const MiscRegIndex misc_reg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
Fault	AArch64AArch32SystemAccessTrap (const MiscRegIndex misc_reg, ExtMachInst mach_inst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
bool	isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
bool	isGenericTimerCommonEL0HypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
bool	isGenericTimerPhysHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc, ExceptionClass *ec)
bool	condGenericTimerPhysHypTrap (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex misc_reg, ThreadContext *tc)
bool	decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
bool	isUnpriviledgeAccess (ThreadContext *tc)
bool	SPAlignmentCheckEnabled (ThreadContext *tc)
int	decodePhysAddrRange64 (uint8_t pa_enc)
	Returns the n.
uint8_t	encodePhysAddrRange64 (int pa_size)
	Returns the encoding corresponding to the specified n.
void	syncVecRegsToElems (ThreadContext *tc)
void	syncVecElemsToRegs (ThreadContext *tc)
bool	fgtEnabled (ThreadContext *tc)
bool	isHcrxEL2Enabled (ThreadContext *tc)
TranslationRegime	translationRegime (ThreadContext *tc, ExceptionLevel el)
ExceptionLevel	translationEl (TranslationRegime regime)
bool	testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
static bool	inUserMode (CPSR cpsr)
static bool	inPrivilegedMode (CPSR cpsr)
ExceptionLevel	currEL (CPSR cpsr)
static uint8_t	itState (CPSR psr)
static uint32_t	mcrMrcIssBuild (bool isRead, uint32_t crm, RegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
static void	mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
static uint32_t	mcrrMrrcIssBuild (bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2, uint32_t opc1)
static int	decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
ByteOrder	byteOrder (const ThreadContext *tc)
static bool	useVMID (TranslationRegime regime)
	BitUnion64 (CNTKCTL) Bitfield< 17 > evntis
	EndBitUnion (CNTKCTL) BitUnion64(CNTHCTL) Bitfield< 17 > evntis
	EndBitUnion (CNTHCTL) BitUnion64(CNTHCTL_E2H) Bitfield< 17 > evntis

Variables
const uint32_t	HighVecs = 0xFFFF0000
static SyscallDescTable< EmuFreebsd::SyscallABI32 >	syscallDescs32 ({})
static SyscallDescTable< EmuFreebsd::SyscallABI64 >	syscallDescs64
static const uint8_t	recip_sqrt_estimate [256]
static SyscallTable32	syscallDescs32Low (0)
static SyscallTable32	syscallDescs32High (0x900000)
static SyscallTable64	syscallDescs64Low (0)
static SyscallTable64	syscallDescs64High (0x900000)
static SyscallDescTable< EmuLinux::SyscallABI32 >	privSyscallDescs32
static SyscallDescTable< EmuLinux::SyscallABI64 >	privSyscallDescs64
const Addr	PageShift = 12
const Addr	PageBytes = 1ULL << PageShift
const GrainSize	GrainMap_tg0 []
const GrainSize	GrainMap_tg1 []
const unsigned	MaxPhysAddrRange = 52
	cond
Bitfield< 3, 0 >	mask
Bitfield< 7, 2 >	top6
Bitfield< 1, 0 >	bottom2
static CCRegClassOps	ccRegClassOps
constexpr RegClass	ccRegClass
	uh1
Bitfield< 15, 0 >	uh0
SignedBitfield< 31, 16 >	sh1
SignedBitfield< 15, 0 >	sh0
Bitfield< 31, 0 >	uw
SignedBitfield< 31, 0 >	sw
constexpr IntRegClassOps	intRegClassOps
constexpr RegClass	intRegClass
constexpr RegClass	flatIntRegClass
constexpr size_t	NumArgumentRegs = 4
constexpr size_t	NumArgumentRegs64 = 8
constexpr auto &	ReturnValueReg = int_reg::X0
constexpr auto &	ReturnValueReg1 = int_reg::X1
constexpr auto &	ArgumentReg0 = int_reg::X0
constexpr auto &	ArgumentReg1 = int_reg::X1
constexpr auto &	ArgumentReg2 = int_reg::X2
constexpr auto &	FramePointerReg = int_reg::X11
constexpr auto &	StackPointerReg = int_reg::Sp
constexpr auto &	ReturnAddressReg = int_reg::Lr
constexpr auto &	SyscallNumReg = ReturnValueReg
constexpr auto &	SyscallPseudoReturnReg = ReturnValueReg
constexpr auto &	SyscallSuccessReg = ReturnValueReg
const int	NumMatrixRegs = 1
static TypedRegClassOps< ArmISA::MatRegContainer >	matRegClassOps
constexpr RegClass	matRegClass
int	unflattenResultMiscReg [NUM_MISCREGS]
	If the reg is a child reg of a banked set, then the parent is the last banked one in the list.
std::vector< struct MiscRegLUTEntry >	lookUpMiscReg (NUM_MISCREGS)
const char *const	miscRegName []
static MiscRegClassOps	miscRegClassOps
constexpr RegClass	miscRegClass
static const uint32_t	CondCodesMask = 0xF00F0000
static const uint32_t	CpsrMaskQ = 0x08000000
static const uint32_t	ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
static const uint32_t	CpsrMask = ApsrMask | 0x00F003DF
static const uint32_t	FpCondCodesMask = 0xF0000000
static const uint32_t	FpscrQcMask = 0x08000000
static const uint32_t	FpscrAhpMask = 0x04000000
static const uint32_t	FpscrExcMask = 0x0000009F
	nz
Bitfield< 29 >	c
Bitfield< 28 >	v
Bitfield< 27 >	q
Bitfield< 26, 25 >	it1
Bitfield< 24 >	dit
Bitfield< 23 >	uao
Bitfield< 22 >	pan
Bitfield< 21 >	ss
Bitfield< 20 >	il
Bitfield< 19, 16 >	ge
Bitfield< 15, 10 >	it2
Bitfield< 9 >	d
Bitfield< 9 >	e
Bitfield< 8 >	a
Bitfield< 7 >	i
Bitfield< 6 >	f
Bitfield< 8, 6 >	aif
Bitfield< 9, 6 >	daif
Bitfield< 5 >	t
Bitfield< 4 >	width
Bitfield< 3, 2 >	el
Bitfield< 4, 0 >	mode
Bitfield< 0 >	sp
	vcma
Bitfield< 27, 24 >	rdm
Bitfield< 19, 16 >	crc32
Bitfield< 15, 12 >	sha2
Bitfield< 11, 8 >	sha1
Bitfield< 7, 4 >	aes
Bitfield< 3, 0 >	sevl
	clrbhb
Bitfield< 27, 24 >	i8mm
Bitfield< 23, 20 >	bf16
Bitfield< 19, 16 >	specres
Bitfield< 15, 12 >	sb
Bitfield< 11, 8 >	fhm
Bitfield< 7, 4 >	dp
Bitfield< 3, 0 >	jscvt
	tracefilt
Bitfield< 39, 36 >	doublelock
Bitfield< 35, 32 >	pmsver
Bitfield< 31, 28 >	ctx_cmps
Bitfield< 23, 20 >	wrps
Bitfield< 15, 12 >	brps
Bitfield< 11, 8 >	pmuver
Bitfield< 7, 4 >	tracever
Bitfield< 3, 0 >	debugver
	rndr
Bitfield< 59, 56 >	tlb
Bitfield< 55, 52 >	ts
Bitfield< 43, 40 >	sm4
Bitfield< 39, 36 >	sm3
Bitfield< 35, 32 >	sha3
Bitfield< 27, 24 >	tme
Bitfield< 23, 20 >	atomic
Bitfield< 35, 32 >	frintts
Bitfield< 31, 28 >	gpi
Bitfield< 27, 24 >	gpa
Bitfield< 23, 20 >	lrcpc
Bitfield< 19, 16 >	fcma
Bitfield< 11, 8 >	api
Bitfield< 7, 4 >	apa
Bitfield< 3, 0 >	dpb
	ecv
Bitfield< 47, 44 >	exs
Bitfield< 43, 40 >	tgran4_2
Bitfield< 39, 36 >	tgran64_2
Bitfield< 35, 32 >	tgran16_2
Bitfield< 31, 28 >	tgran4
Bitfield< 27, 24 >	tgran64
Bitfield< 23, 20 >	tgran16
Bitfield< 19, 16 >	bigendEL0
Bitfield< 15, 12 >	snsmem
Bitfield< 11, 8 >	bigend
Bitfield< 7, 4 >	asidbits
Bitfield< 3, 0 >	parange
	hcx
Bitfield< 31, 28 >	xnx
Bitfield< 27, 24 >	specsei
Bitfield< 19, 16 >	lo
Bitfield< 15, 12 >	hpds
Bitfield< 11, 8 >	vh
Bitfield< 7, 4 >	vmidbits
Bitfield< 3, 0 >	hafdbs
	e0pd
Bitfield< 59, 56 >	evt
Bitfield< 55, 52 >	bbm
Bitfield< 51, 48 >	ttl
Bitfield< 43, 40 >	fwb
Bitfield< 39, 36 >	ids
Bitfield< 35, 32 >	at
Bitfield< 31, 28 >	st
Bitfield< 27, 24 >	nv
Bitfield< 23, 20 >	ccidx
Bitfield< 19, 16 >	varange
Bitfield< 15, 12 >	iesb
Bitfield< 11, 8 >	lsm
Bitfield< 3, 0 >	cnp
	anerr
Bitfield< 43, 40 >	snerr
Bitfield< 39, 36 >	d128_2
Bitfield< 35, 32 >	d128
Bitfield< 31, 28 >	mec
Bitfield< 27, 24 >	aie
Bitfield< 23, 20 >	s2poe
Bitfield< 19, 16 >	s1poe
Bitfield< 15, 12 >	s2pie
Bitfield< 11, 8 >	s1pie
Bitfield< 7, 4 >	sctlrx
Bitfield< 3, 0 >	tcrx
	csv3
Bitfield< 59, 56 >	csv2
Bitfield< 47, 44 >	amu
Bitfield< 43, 40 >	mpam
Bitfield< 39, 36 >	sel2
Bitfield< 35, 32 >	sve
Bitfield< 31, 28 >	ras
Bitfield< 27, 24 >	gic
Bitfield< 23, 20 >	advsimd
Bitfield< 19, 16 >	fp
Bitfield< 15, 12 >	el3
Bitfield< 11, 8 >	el2
Bitfield< 7, 4 >	el1
Bitfield< 3, 0 >	el0
	sme
Bitfield< 19, 16 >	mpamFrac
	f64mm
Bitfield< 55, 52 >	f32mm
Bitfield< 27, 24 >	b16b16
Bitfield< 19, 16 >	bitPerm
Bitfield< 3, 0 >	sveVer
Bitfield< 59, 56 >	smEver
Bitfield< 55, 52 >	i16i64
Bitfield< 48 >	f64f64
Bitfield< 39, 36 >	i8i32
Bitfield< 35 >	f16f32
Bitfield< 34 >	b16f32
Bitfield< 32 >	f32f32
Bitfield< 11 >	tdra
Bitfield< 10 >	tdosa
Bitfield< 9 >	tda
Bitfield< 8 >	tde
Bitfield< 7 >	hpme
Bitfield< 6 >	tpm
Bitfield< 5 >	tpmcr
Bitfield< 4, 0 >	hpmn
Bitfield< 20 >	tta
Bitfield< 15 >	tase
Bitfield< 13 >	tcp13
Bitfield< 12 >	tcp12
Bitfield< 11 >	tcp11
Bitfield< 10 >	tcp10
Bitfield< 10 >	tfp
Bitfield< 9 >	tcp9
Bitfield< 8 >	tcp8
Bitfield< 8 >	tz
Bitfield< 7 >	tcp7
Bitfield< 6 >	tcp6
Bitfield< 5 >	tcp5
Bitfield< 4 >	tcp4
Bitfield< 3 >	tcp3
Bitfield< 2 >	tcp2
Bitfield< 1 >	tcp1
Bitfield< 0 >	tcp0
Bitfield< 16 >	ttee
Bitfield< 15 >	t15
Bitfield< 13 >	t13
Bitfield< 12 >	t12
Bitfield< 11 >	t11
Bitfield< 10 >	t10
Bitfield< 9 >	t9
Bitfield< 8 >	t8
Bitfield< 7 >	t7
Bitfield< 6 >	t6
Bitfield< 5 >	t5
Bitfield< 4 >	t4
Bitfield< 3 >	t3
Bitfield< 2 >	t2
Bitfield< 1 >	t1
Bitfield< 0 >	t0
Bitfield< 54 >	ttlbis
Bitfield< 52 >	tocu
Bitfield< 50 >	ticab
Bitfield< 49 >	tid4
Bitfield< 47 >	fien
Bitfield< 45 >	nv2
Bitfield< 43 >	nv1
Bitfield< 40 >	apk
Bitfield< 38 >	miocnce
Bitfield< 37 >	tea
Bitfield< 36 >	terr
Bitfield< 35 >	tlor
Bitfield< 34 >	e2h
Bitfield< 33 >	id
Bitfield< 32 >	cd
Bitfield< 31 >	rw
Bitfield< 30 >	trvm
Bitfield< 29 >	hcd
Bitfield< 28 >	tdz
Bitfield< 27 >	tge
Bitfield< 26 >	tvm
Bitfield< 25 >	ttlb
Bitfield< 24 >	tpu
Bitfield< 23 >	tpc
Bitfield< 22 >	tsw
Bitfield< 21 >	tac
Bitfield< 21 >	tacr
Bitfield< 20 >	tidcp
Bitfield< 19 >	tsc
Bitfield< 18 >	tid3
Bitfield< 17 >	tid2
Bitfield< 16 >	tid1
Bitfield< 15 >	tid0
Bitfield< 14 >	twe
Bitfield< 13 >	twi
Bitfield< 12 >	dc
Bitfield< 11, 10 >	bsu
Bitfield< 9 >	fb
Bitfield< 8 >	va
Bitfield< 8 >	vse
Bitfield< 7 >	vi
Bitfield< 6 >	vf
Bitfield< 5 >	amo
Bitfield< 4 >	imo
Bitfield< 3 >	fmo
Bitfield< 2 >	ptw
Bitfield< 1 >	swio
Bitfield< 0 >	vm
Bitfield< 19 >	rfr
Bitfield< 15 >	nsasedis
Bitfield< 14 >	nsd32dis
Bitfield< 13 >	cp13
Bitfield< 12 >	cp12
Bitfield< 11 >	cp11
Bitfield< 10 >	cp10
Bitfield< 9 >	cp9
Bitfield< 8 >	cp8
Bitfield< 7 >	cp7
Bitfield< 6 >	cp6
Bitfield< 5 >	cp5
Bitfield< 4 >	cp4
Bitfield< 3 >	cp3
Bitfield< 2 >	cp2
Bitfield< 1 >	cp1
Bitfield< 0 >	cp0
Bitfield< 43 >	tcr2En
Bitfield< 40 >	trndr
Bitfield< 38 >	hxen
Bitfield< 27 >	fgten
Bitfield< 20 >	nmea
Bitfield< 19 >	ease
Bitfield< 18 >	eel2
Bitfield< 15 >	teer
Bitfield< 9 >	sif
Bitfield< 8 >	hce
Bitfield< 7 >	scd
Bitfield< 7 >	smd
Bitfield< 6 >	nEt
Bitfield< 5 >	aw
Bitfield< 4 >	fw
Bitfield< 3 >	ea
Bitfield< 2 >	fiq
Bitfield< 1 >	irq
Bitfield< 0 >	ns
Bitfield< 30 >	enib
Bitfield< 30 >	te
Bitfield< 29 >	afe
Bitfield< 28 >	tre
Bitfield< 27 >	nmfi
Bitfield< 27 >	enda
Bitfield< 26 >	uci
Bitfield< 25 >	ee
Bitfield< 24 >	e0e
Bitfield< 23 >	span
Bitfield< 23 >	xp
Bitfield< 22 >	u
Bitfield< 21 >	fi
Bitfield< 20 >	uwxn
Bitfield< 19 >	dz
Bitfield< 19 >	wxn
Bitfield< 18 >	ntwe
Bitfield< 18 >	rao2
Bitfield< 16 >	ntwi
Bitfield< 16 >	rao3
Bitfield< 15 >	uct
Bitfield< 14 >	rr
Bitfield< 14 >	dze
Bitfield< 13 >	endb
Bitfield< 11 >	z
Bitfield< 9, 8 >	rs
Bitfield< 9 >	uma
Bitfield< 8 >	sed
Bitfield< 7 >	b
Bitfield< 7 >	itd
Bitfield< 6, 3 >	rao4
Bitfield< 5 >	cp15ben
Bitfield< 4 >	sa0
Bitfield< 3 >	sa
Bitfield< 0 >	m
Bitfield< 17, 16 >	zen
Bitfield< 21, 20 >	fpen
Bitfield< 25, 24 >	smen
Bitfield< 29, 28 >	rsvd
Bitfield< 30 >	d32dis
Bitfield< 31 >	asedis
	fsLow
Bitfield< 5, 0 >	status
Bitfield< 7, 4 >	domain
Bitfield< 9 >	lpae
Bitfield< 10 >	fsHigh
Bitfield< 11 >	wnr
Bitfield< 12 >	ext
Bitfield< 13 >	cm
Bitfield< 1 >	dzc
Bitfield< 2 >	ofc
Bitfield< 3 >	ufc
Bitfield< 4 >	ixc
Bitfield< 7 >	idc
Bitfield< 8 >	ioe
Bitfield< 10 >	ofe
Bitfield< 11 >	ufe
Bitfield< 12 >	ixe
Bitfield< 15 >	ide
Bitfield< 18, 16 >	len
Bitfield< 19 >	fz16
Bitfield< 21, 20 >	stride
Bitfield< 23, 22 >	rMode
Bitfield< 24 >	fz
Bitfield< 25 >	dn
Bitfield< 26 >	ahp
Bitfield< 27 >	qc
Bitfield< 31 >	n
Bitfield< 30 >	en
Bitfield< 29, 0 >	subArchDefined
	advSimdRegisters
Bitfield< 7, 4 >	singlePrecision
Bitfield< 11, 8 >	doublePrecision
Bitfield< 15, 12 >	vfpExceptionTrapping
Bitfield< 19, 16 >	divide
Bitfield< 23, 20 >	squareRoot
Bitfield< 27, 24 >	shortVectors
Bitfield< 31, 28 >	roundingModes
	flushToZero
Bitfield< 7, 4 >	defaultNaN
Bitfield< 11, 8 >	advSimdLoadStore
Bitfield< 15, 12 >	advSimdInteger
Bitfield< 19, 16 >	advSimdSinglePrecision
Bitfield< 23, 20 >	advSimdHalfPrecision
Bitfield< 27, 24 >	vfpHalfPrecision
Bitfield< 31, 28 >	raz
Bitfield< 4 >	pd0
Bitfield< 5 >	pd1
Bitfield< 2, 0 >	t0sz
Bitfield< 6 >	t2e
Bitfield< 7 >	epd0
Bitfield< 9, 8 >	irgn0
Bitfield< 11, 10 >	orgn0
Bitfield< 14 >	tg0
Bitfield< 18, 16 >	t1sz
Bitfield< 22 >	a1
Bitfield< 23 >	epd1
Bitfield< 25, 24 >	irgn1
Bitfield< 27, 26 >	orgn1
Bitfield< 30 >	tg1
Bitfield< 34, 32 >	ips
Bitfield< 36 >	as
Bitfield< 37 >	tbi0
Bitfield< 38 >	tbi1
Bitfield< 31 >	eae
Bitfield< 18, 16 >	ps
Bitfield< 20 >	tbi
Bitfield< 41 >	hpd0
Bitfield< 42 >	hpd1
Bitfield< 24 >	hpd
Bitfield< 29 >	tbid
Bitfield< 39 >	ha
Bitfield< 40 >	hd
Bitfield< 51 >	tbid0
Bitfield< 52 >	tbid1
Bitfield< 4 >	s
Bitfield< 5, 0 >	t0sz64
Bitfield< 7, 6 >	sl0
Bitfield< 19 >	vs
	tr0
Bitfield< 3, 2 >	tr1
Bitfield< 5, 4 >	tr2
Bitfield< 7, 6 >	tr3
Bitfield< 9, 8 >	tr4
Bitfield< 11, 10 >	tr5
Bitfield< 13, 12 >	tr6
Bitfield< 15, 14 >	tr7
Bitfield< 16 >	ds0
Bitfield< 17 >	ds1
Bitfield< 18 >	ns0
Bitfield< 19 >	ns1
Bitfield< 24 >	nos0
Bitfield< 25 >	nos1
Bitfield< 26 >	nos2
Bitfield< 27 >	nos3
Bitfield< 28 >	nos4
Bitfield< 29 >	nos5
Bitfield< 30 >	nos6
Bitfield< 31 >	nos7
	ir0
Bitfield< 3, 2 >	ir1
Bitfield< 5, 4 >	ir2
Bitfield< 7, 6 >	ir3
Bitfield< 9, 8 >	ir4
Bitfield< 11, 10 >	ir5
Bitfield< 13, 12 >	ir6
Bitfield< 15, 14 >	ir7
Bitfield< 17, 16 >	or0
Bitfield< 19, 18 >	or1
Bitfield< 21, 20 >	or2
Bitfield< 23, 22 >	or3
Bitfield< 25, 24 >	or4
Bitfield< 27, 26 >	or5
Bitfield< 29, 28 >	or6
Bitfield< 31, 30 >	or7
	asid
Bitfield< 31, 8 >	procid
	sataRAMLatency
Bitfield< 4, 3 >	reserved_4_3
Bitfield< 5 >	dataRAMSetup
Bitfield< 8, 6 >	tagRAMLatency
Bitfield< 9 >	tagRAMSetup
Bitfield< 11, 10 >	dataRAMSlice
Bitfield< 12 >	tagRAMSlice
Bitfield< 20, 13 >	reserved_20_13
Bitfield< 21 >	eccandParityEnable
Bitfield< 22 >	reserved_22
Bitfield< 23 >	interptCtrlPresent
Bitfield< 25, 24 >	numCPUs
Bitfield< 30, 26 >	reserved_30_26
Bitfield< 31 >	l2rstDISABLE_monitor
	iCacheLineSize
Bitfield< 13, 4 >	raz_13_4
Bitfield< 15, 14 >	l1IndexPolicy
Bitfield< 19, 16 >	dCacheLineSize
Bitfield< 23, 20 >	erg
Bitfield< 27, 24 >	cwg
Bitfield< 28 >	raz_28
Bitfield< 31, 29 >	format
	sel
	attr
Bitfield< 39, 12 >	pa
Bitfield< 8, 7 >	sh
Bitfield< 6, 1 >	fst
Bitfield< 6 >	fs5
Bitfield< 5, 1 >	fs4_0
	ec
Bitfield< 24, 0 >	iss
Bitfield< 24 >	isv
Bitfield< 23, 22 >	sas
Bitfield< 21 >	sse
Bitfield< 20, 16 >	srt
Bitfield< 15 >	sf
Bitfield< 14 >	ar
Bitfield< 13 >	vncr
Bitfield< 10 >	fnv
Bitfield< 7 >	s1ptw
Bitfield< 5, 0 >	dfsc
Bitfield< 12, 11 >	set
Bitfield< 5, 0 >	ifsc
Bitfield< 6 >	ex
Bitfield< 30 >	tam
Bitfield< 28 >	tta_e2h
Bitfield< 13, 13 >	res1_13_el2
Bitfield< 12, 12 >	res1_12_el2
Bitfield< 12 >	esm
Bitfield< 12 >	tsm
Bitfield< 9 >	res1_9_el2
Bitfield< 8 >	res1_8_el2
Bitfield< 8 >	ez
Bitfield< 7, 0 >	res1_7_0_el2
	res0_63_32
Bitfield< 31, 31 >	fa64
Bitfield< 30, 9 >	res0_30_9
Bitfield< 8, 4 >	razwi_8_4
	res0_63_2
Bitfield< 1, 1 >	za
Bitfield< 0, 0 >	sm
Bitfield< 31, 24 >	implementer
Bitfield< 23, 16 >	revision
Bitfield< 15, 15 >	smps
Bitfield< 14, 12 >	res0_14_12
Bitfield< 11, 0 >	affinity
	res0_63_4
Bitfield< 3, 0 >	priority
	res0
Bitfield< 3 >	oslm_3
Bitfield< 2 >	nTT
Bitfield< 1 >	oslk
Bitfield< 0 >	oslm_0
	res0_2
Bitfield< 23, 20 >	bt
Bitfield< 19, 16 >	lbn
Bitfield< 15, 14 >	ssc
Bitfield< 13 >	hmc
Bitfield< 12, 9 >	res0_1
Bitfield< 8, 5 >	bas
Bitfield< 4, 3 >	res0_0
Bitfield< 2, 1 >	pmc
Bitfield< 20 >	wt
Bitfield< 4, 3 >	lsv
Bitfield< 2, 1 >	pac
Bitfield< 30 >	rxfull
Bitfield< 29 >	txfull
Bitfield< 28 >	res0_5
Bitfield< 27 >	rxo
Bitfield< 26 >	txu
Bitfield< 25, 24 >	res0_4
Bitfield< 23, 22 >	intdis
Bitfield< 20 >	res0_3
Bitfield< 19 >	sc2
Bitfield< 17 >	spniddis
Bitfield< 16 >	spiddis
Bitfield< 15 >	mdbgen
Bitfield< 14 >	hde
Bitfield< 13 >	res0_
Bitfield< 12 >	udccdis
Bitfield< 12 >	tdcc
Bitfield< 6 >	err
Bitfield< 5, 2 >	moe
Bitfield< 30 >	nsi
Bitfield< 28 >	nsd
Bitfield< 27 >	nsp
Bitfield< 26 >	nss
Bitfield< 25 >	nsu
Bitfield< 15 >	mf
Bitfield< 14 >	mi
Bitfield< 12 >	md
Bitfield< 11 >	mp
Bitfield< 10 >	ms
Bitfield< 6 >	si
Bitfield< 4 >	sd
Bitfield< 1 >	su
	cidmask
Bitfield< 27, 24 >	auxregs
Bitfield< 19, 16 >	virtextns
Bitfield< 15, 12 >	vectorcatch
Bitfield< 11, 8 >	bpaddremask
Bitfield< 7, 4 >	wpaddrmask
Bitfield< 3, 0 >	pcsample
Bitfield< 53 >	svcEL1
Bitfield< 52 >	svcEL0
Bitfield< 51 >	eret
Bitfield< 47 >	tlbivaale1
Bitfield< 46 >	tlbivale1
Bitfield< 45 >	tlbivaae1
Bitfield< 44 >	tlbiaside1
Bitfield< 43 >	tlbivae1
Bitfield< 42 >	tlbivmalle1
Bitfield< 41 >	tlbirvaale1
Bitfield< 40 >	tlbirvale1
Bitfield< 39 >	tlbirvaae1
Bitfield< 38 >	tlbirvae1
Bitfield< 37 >	tlbirvaale1is
Bitfield< 36 >	tlbirvale1is
Bitfield< 35 >	tlbirvaae1is
Bitfield< 34 >	tlbirvae1is
Bitfield< 33 >	tlbivaale1is
Bitfield< 32 >	tlbivale1is
Bitfield< 31 >	tlbivaae1is
Bitfield< 30 >	tlbiaside1is
Bitfield< 29 >	tlbivae1is
Bitfield< 28 >	tlbivmalle1is
Bitfield< 27 >	tlbirvaale1os
Bitfield< 26 >	tlbirvale1os
Bitfield< 25 >	tlbirvaae1os
Bitfield< 24 >	tlbirvae1os
Bitfield< 23 >	tlbivaale1os
Bitfield< 22 >	tlbivale1os
Bitfield< 21 >	tlbivaae1os
Bitfield< 20 >	tlbiaside1os
Bitfield< 19 >	tlbivae1os
Bitfield< 18 >	tlbivmalle1os
Bitfield< 17 >	ats1e1wp
Bitfield< 16 >	ats1e1rp
Bitfield< 15 >	ats1e0w
Bitfield< 14 >	ats1e0r
Bitfield< 13 >	ats1e1w
Bitfield< 12 >	ats1e1r
Bitfield< 11 >	dczva
Bitfield< 10 >	dccivac
Bitfield< 9 >	dccvapd
Bitfield< 8 >	dccvap
Bitfield< 7 >	dccvau
Bitfield< 6 >	dccisw
Bitfield< 5 >	dccsw
Bitfield< 4 >	dcisw
Bitfield< 3 >	dcivac
Bitfield< 2 >	icivau
Bitfield< 1 >	iciallu
Bitfield< 0 >	icialluis
Bitfield< 49 >	erxaddrEL1
Bitfield< 48 >	erxpfgcdnEL1
Bitfield< 47 >	erxpfgctlEL1
Bitfield< 46 >	erxpfgfEL1
Bitfield< 45 >	erxmiscNEL1
Bitfield< 44 >	erxstatusEL1
Bitfield< 43 >	erxctlrEL1
Bitfield< 42 >	erxfrEL1
Bitfield< 41 >	errselrEL1
Bitfield< 40 >	erridrEL1
Bitfield< 39 >	iccIgrpEnEL1
Bitfield< 38 >	vbarEL1
Bitfield< 37 >	ttbr1EL1
Bitfield< 36 >	ttbr0EL1
Bitfield< 35 >	tpidrEL0
Bitfield< 34 >	tpidrroEL0
Bitfield< 33 >	tpidrEL1
Bitfield< 32 >	tcrEL1
Bitfield< 31 >	scxtnumEL0
Bitfield< 30 >	scxtnumEL1
Bitfield< 29 >	sctlrEL1
Bitfield< 28 >	revidrEL1
Bitfield< 27 >	parEL1
Bitfield< 26 >	mpidrEL1
Bitfield< 25 >	midrEL1
Bitfield< 24 >	mairEL1
Bitfield< 23 >	lorsaEL1
Bitfield< 22 >	lornEL1
Bitfield< 21 >	loridEL1
Bitfield< 20 >	loreaEL1
Bitfield< 19 >	lorcEL1
Bitfield< 18 >	isrEL1
Bitfield< 17 >	farEL1
Bitfield< 16 >	esrEL1
Bitfield< 15 >	dczidEL0
Bitfield< 14 >	ctrEL0
Bitfield< 13 >	csselrEL1
Bitfield< 12 >	cpacrEL1
Bitfield< 11 >	contextidrEL1
Bitfield< 10 >	clidrEL1
Bitfield< 9 >	ccsidrEL1
Bitfield< 8 >	apibKey
Bitfield< 7 >	apiaKey
Bitfield< 6 >	apgaKey
Bitfield< 5 >	apdbKey
Bitfield< 4 >	apdaKey
Bitfield< 3 >	amairEL1
Bitfield< 2 >	aidrEL1
Bitfield< 1 >	afsr1EL1
Bitfield< 0 >	afsr0EL1
Bitfield< 10 >	oseccrEL1
Bitfield< 9 >	oslsrEL1
Bitfield< 8 >	oslarEL1
Bitfield< 7 >	dbgprcrEL1
Bitfield< 6 >	dbgauthstatusEL1
Bitfield< 5 >	dbgclaim
Bitfield< 4 >	mdscrEL1
Bitfield< 3 >	dbgwvrnEL1
Bitfield< 2 >	dbgwcrnEL1
Bitfield< 1 >	dbgbvrnEL1
Bitfield< 0 >	dbgbcrnEL1
Bitfield< 60 >	hasForceNs
Bitfield< 58 >	hasTidr
Bitfield< 39, 32 >	pmgMax
Bitfield< 20, 18 >	vpmrMax
Bitfield< 17 >	hasHcr
Bitfield< 15, 0 >	partidMax
Bitfield< 58 >	tidr
Bitfield< 50 >	enMpamSm
Bitfield< 49 >	trapMpam0EL1
Bitfield< 48 >	trapMpam1EL1
Bitfield< 62 >	trapLower
Bitfield< 61 >	sdeflt
Bitfield< 60 >	forceNs
	pmgD
Bitfield< 39, 32 >	pmgI
Bitfield< 31, 16 >	partidD
Bitfield< 15, 0 >	partidI
Bitfield< 8 >	gstappPlk
Bitfield< 1 >	el1Vpmen
Bitfield< 0 >	el0Vpmen
constexpr unsigned	NumVecElemPerNeonVecReg = 4
constexpr unsigned	NumVecElemPerVecReg = MaxSveVecLenInWords
const int	NumFloatV7ArchRegs = 64
const int	NumVecV7ArchRegs = 16
const int	NumVecV8ArchRegs = 32
const int	NumVecSpecialRegs = 8
const int	NumVecIntrlvRegs = 4
const int	NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs
const int	NumVecPredRegs = 18
const int	VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg
const int	INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs
const int	INTRLVREG1 = INTRLVREG0 + 1
const int	INTRLVREG2 = INTRLVREG0 + 2
const int	INTRLVREG3 = INTRLVREG0 + 3
const int	VECREG_UREG0 = 32
const int	PREDREG_FFR = 16
const int	PREDREG_UREG0 = 17
static VecElemRegClassOps< RegVal >	vecRegElemClassOps (NumVecElemPerVecReg)
static TypedRegClassOps< ArmISA::VecRegContainer >	vecRegClassOps
static TypedRegClassOps< ArmISA::VecPredRegContainer >	vecPredRegClassOps
constexpr RegClass	vecRegClass
constexpr RegClass	vecElemClass
constexpr RegClass	vecPredRegClass
	decoderFault
Bitfield< 61 >	illegalExecution
Bitfield< 60 >	debugStep
Bitfield< 59, 56 >	sveLen
Bitfield< 55, 48 >	itstate
Bitfield< 55, 52 >	itstateCond
Bitfield< 51, 48 >	itstateMask
Bitfield< 41, 40 >	fpscrStride
Bitfield< 39, 37 >	fpscrLen
Bitfield< 36 >	thumb
Bitfield< 35 >	bigThumb
Bitfield< 34 >	aarch64
Bitfield< 33 >	sevenAndFour
Bitfield< 32 >	isMisc
uint32_t	instBits
Bitfield< 27, 25 >	encoding
Bitfield< 25 >	useImm
Bitfield< 24, 21 >	opcode
Bitfield< 24, 20 >	mediaOpcode
Bitfield< 24 >	opcode24
Bitfield< 24, 23 >	opcode24_23
Bitfield< 23, 20 >	opcode23_20
Bitfield< 23, 21 >	opcode23_21
Bitfield< 20 >	opcode20
Bitfield< 22 >	opcode22
Bitfield< 19, 16 >	opcode19_16
Bitfield< 19 >	opcode19
Bitfield< 18 >	opcode18
Bitfield< 15, 12 >	opcode15_12
Bitfield< 15 >	opcode15
Bitfield< 7, 4 >	miscOpcode
Bitfield< 7, 5 >	opc2
Bitfield< 7 >	opcode7
Bitfield< 6 >	opcode6
Bitfield< 4 >	opcode4
Bitfield< 31, 28 >	condCode
Bitfield< 20 >	sField
Bitfield< 19, 16 >	rn
Bitfield< 15, 12 >	rd
Bitfield< 15, 12 >	rt
Bitfield< 11, 7 >	shiftSize
Bitfield< 6, 5 >	shift
Bitfield< 3, 0 >	rm
Bitfield< 23 >	up
Bitfield< 22 >	psruser
Bitfield< 21 >	writeback
Bitfield< 20 >	loadOp
	pubwl
Bitfield< 7, 0 >	imm
Bitfield< 11, 8 >	rotate
Bitfield< 11, 0 >	immed11_0
Bitfield< 7, 0 >	immed7_0
Bitfield< 11, 8 >	immedHi11_8
Bitfield< 3, 0 >	immedLo3_0
Bitfield< 15, 0 >	regList
Bitfield< 23, 0 >	offset
Bitfield< 23, 0 >	immed23_0
Bitfield< 11, 8 >	cpNum
Bitfield< 18, 16 >	fn
Bitfield< 14, 12 >	fd
Bitfield< 3 >	fpRegImm
Bitfield< 3, 0 >	fm
Bitfield< 2, 0 >	fpImm
Bitfield< 24, 20 >	punwl
Bitfield< 15, 8 >	m5Func
Bitfield< 15, 13 >	topcode15_13
Bitfield< 13, 11 >	topcode13_11
Bitfield< 12, 11 >	topcode12_11
Bitfield< 12, 10 >	topcode12_10
Bitfield< 11, 9 >	topcode11_9
Bitfield< 11, 8 >	topcode11_8
Bitfield< 10, 9 >	topcode10_9
Bitfield< 10, 8 >	topcode10_8
Bitfield< 9, 6 >	topcode9_6
Bitfield< 7 >	topcode7
Bitfield< 7, 6 >	topcode7_6
Bitfield< 7, 5 >	topcode7_5
Bitfield< 7, 4 >	topcode7_4
Bitfield< 3, 0 >	topcode3_0
Bitfield< 28, 27 >	htopcode12_11
Bitfield< 26, 25 >	htopcode10_9
Bitfield< 25 >	htopcode9
Bitfield< 25, 24 >	htopcode9_8
Bitfield< 25, 21 >	htopcode9_5
Bitfield< 25, 20 >	htopcode9_4
Bitfield< 24 >	htopcode8
Bitfield< 24, 23 >	htopcode8_7
Bitfield< 24, 22 >	htopcode8_6
Bitfield< 24, 21 >	htopcode8_5
Bitfield< 23 >	htopcode7
Bitfield< 23, 21 >	htopcode7_5
Bitfield< 22 >	htopcode6
Bitfield< 22, 21 >	htopcode6_5
Bitfield< 21, 20 >	htopcode5_4
Bitfield< 20 >	htopcode4
Bitfield< 19, 16 >	htrn
Bitfield< 20 >	hts
Bitfield< 15 >	ltopcode15
Bitfield< 11, 8 >	ltopcode11_8
Bitfield< 7, 6 >	ltopcode7_6
Bitfield< 7, 4 >	ltopcode7_4
Bitfield< 4 >	ltopcode4
Bitfield< 11, 8 >	ltrd
Bitfield< 11, 8 >	ltcoproc
	aff3
Bitfield< 23, 16 >	aff2
Bitfield< 15, 8 >	aff1
Bitfield< 7, 0 >	aff0
constexpr unsigned	MaxSveVecLenInBits = 2048
constexpr unsigned	MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
constexpr unsigned	MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
constexpr unsigned	MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
constexpr unsigned	VecRegSizeBytes = MaxSveVecLenInBytes
constexpr unsigned	VecPredRegSizeBits = MaxSveVecLenInBytes
constexpr unsigned	MaxSmeVecLenInBits = 2048
constexpr unsigned	MaxSmeVecLenInBytes = MaxSmeVecLenInBits >> 3
constexpr unsigned	MaxSmeVecLenInWords = MaxSmeVecLenInBits >> 5
constexpr unsigned	MaxSmeVecLenInDWords = MaxSmeVecLenInBits >> 6
Bitfield< 9 >	el0pten
Bitfield< 8 >	el0vten
Bitfield< 7, 4 >	evnti
Bitfield< 3 >	evntdir
Bitfield< 2 >	evnten
Bitfield< 1 >	el0vcten
Bitfield< 0 >	el0pcten
Bitfield< 16 >	el1nvvct
Bitfield< 15 >	el1nvpct
Bitfield< 14 >	el1tvct
Bitfield< 13 >	el1tvt
Bitfield< 1 >	el1pcen
Bitfield< 0 >	el1pcten
Bitfield< 11 >	el1pten

Typedef Documentation

ConstVecPredReg

using gem5::ArmISA::ConstVecPredReg

Initial value:

 
    gem5::VecPredRegT<VecElem, NumVecElemPerVecReg, false, true>

Definition at line 69 of file vec.hh.

FaultOffset

typedef Addr gem5::ArmISA::FaultOffset

Definition at line 60 of file faults.hh.

MachInst

typedef uint32_t gem5::ArmISA::MachInst

Definition at line 55 of file types.hh.

MatCol

template<typename ElemType >

using gem5::ArmISA::MatCol

Initial value:

 gem5::VerticalSlice<ElemType,
                                   MatRegContainer,
                                   false>

Definition at line 83 of file mat.hh.

MatRegContainer

using gem5::ArmISA::MatRegContainer

Initial value:

 gem5::MatStore<MaxSmeVecLenInBytes,
                                       MaxSmeVecLenInBytes>

Definition at line 60 of file mat.hh.

MatRow

template<typename ElemType >

using gem5::ArmISA::MatRow

Initial value:

 gem5::HorizontalSlice<ElemType,
                                     MatRegContainer,
                                     false>

Definition at line 78 of file mat.hh.

MatTile

template<typename ElemType >

using gem5::ArmISA::MatTile

Initial value:

 gem5::Tile<ElemType,
                           MatRegContainer>

Definition at line 64 of file mat.hh.

MatTileCol

template<typename ElemType >

using gem5::ArmISA::MatTileCol

Initial value:

 gem5::VerticalSlice<ElemType,
                                       MatRegContainer,
                                       true>

Definition at line 73 of file mat.hh.

MatTileRow

template<typename ElemType >

using gem5::ArmISA::MatTileRow

Initial value:

 gem5::HorizontalSlice<ElemType,
                                         MatRegContainer,
                                         true>

Definition at line 68 of file mat.hh.

RegContextParam

typedef int gem5::ArmISA::RegContextParam

Definition at line 234 of file types.hh.

RegContextVal

typedef int gem5::ArmISA::RegContextVal

Definition at line 235 of file types.hh.

VecElem

using gem5::ArmISA::VecElem = uint32_t

Definition at line 63 of file vec.hh.

VecPredReg

using gem5::ArmISA::VecPredReg

Initial value:

 
    gem5::VecPredRegT<VecElem, NumVecElemPerVecReg, false, false>

Definition at line 67 of file vec.hh.

VecPredRegContainer

using gem5::ArmISA::VecPredRegContainer = VecPredReg::Container

Definition at line 71 of file vec.hh.

VecRegContainer

using gem5::ArmISA::VecRegContainer

Initial value:

 
    gem5::VecRegContainer<NumVecElemPerVecReg * sizeof(VecElem)>

Definition at line 64 of file vec.hh.

VfpSavedState

typedef int gem5::ArmISA::VfpSavedState

Definition at line 217 of file vfp.hh.

vmid_t

typedef uint16_t gem5::ArmISA::vmid_t

Definition at line 57 of file types.hh.

XReg

typedef uint64_t gem5::ArmISA::XReg

Definition at line 53 of file neon64_mem.hh.

Enumeration Type Documentation

ArmExtendType

enum gem5::ArmISA::ArmExtendType

Enumerator
UXTB
UXTH
UXTW
UXTX
SXTB
SXTH
SXTW
SXTX

Definition at line 222 of file types.hh.

ConditionCode

enum gem5::ArmISA::ConditionCode

Enumerator
COND_EQ
COND_NE
COND_CS
COND_CC
COND_MI
COND_PL
COND_VS
COND_VC
COND_HI
COND_LS
COND_GE
COND_LT
COND_GT
COND_LE
COND_AL
COND_UC

Definition at line 103 of file cc.hh.

ConvertType

enum gem5::ArmISA::ConvertType

Enumerator
SINGLE_TO_DOUBLE
SINGLE_TO_WORD
SINGLE_TO_LONG
DOUBLE_TO_SINGLE
DOUBLE_TO_WORD
DOUBLE_TO_LONG
LONG_TO_SINGLE
LONG_TO_DOUBLE
LONG_TO_WORD
LONG_TO_PS
WORD_TO_SINGLE
WORD_TO_DOUBLE
WORD_TO_LONG
WORD_TO_PS
PL_TO_SINGLE
PU_TO_SINGLE

Definition at line 238 of file types.hh.

DecoderFault

enum gem5::ArmISA::DecoderFault : std::uint8_t

Instruction decoder fault codes in ExtMachInst.

Enumerator
OK	No fault.
UNALIGNED	Unaligned instruction fault.
PANIC	Internal gem5 error.

Definition at line 366 of file types.hh.

ExceptionClass

enum class gem5::ArmISA::ExceptionClass

strong

Enumerator
INVALID
UNKNOWN
TRAPPED_WFI_WFE
TRAPPED_CP15_MCR_MRC
TRAPPED_CP15_MCRR_MRRC
TRAPPED_CP14_MCR_MRC
TRAPPED_CP14_LDC_STC
TRAPPED_HCPTR
TRAPPED_SIMD_FP
TRAPPED_CP10_MRC_VMRS
TRAPPED_PAC
TRAPPED_BXJ
TRAPPED_CP14_MCRR_MRRC
ILLEGAL_INST
SVC_TO_HYP
SVC
HVC
SMC_TO_HYP
SMC
SVC_64
HVC_64
SMC_64
TRAPPED_MSR_MRS_64
TRAPPED_SVE
TRAPPED_ERET
TRAPPED_SME
PREFETCH_ABORT_TO_HYP
PREFETCH_ABORT_LOWER_EL
PREFETCH_ABORT_FROM_HYP
PREFETCH_ABORT_CURR_EL
PC_ALIGNMENT
DATA_ABORT_TO_HYP
DATA_ABORT_LOWER_EL
DATA_ABORT_FROM_HYP
DATA_ABORT_CURR_EL
STACK_PTR_ALIGNMENT
FP_EXCEPTION
FP_EXCEPTION_64
SERROR
HW_BREAKPOINT
HW_BREAKPOINT_LOWER_EL
HW_BREAKPOINT_CURR_EL
SOFTWARE_STEP
SOFTWARE_STEP_LOWER_EL
SOFTWARE_STEP_CURR_EL
WATCHPOINT
WATCHPOINT_LOWER_EL
WATCHPOINT_CURR_EL
SOFTWARE_BREAKPOINT
VECTOR_CATCH
SOFTWARE_BREAKPOINT_64

Definition at line 308 of file types.hh.

ExceptionLevel

enum gem5::ArmISA::ExceptionLevel

Enumerator
EL0
EL1
EL2
EL3

Definition at line 271 of file types.hh.

FeExceptionBit

enum gem5::ArmISA::FeExceptionBit

Enumerator
FeDivByZero
FeInexact
FeInvalid
FeOverflow
FeUnderflow
FeAllExceptions

Definition at line 88 of file vfp.hh.

FeRoundingMode

enum gem5::ArmISA::FeRoundingMode

Enumerator
FeRoundDown
FeRoundNearest
FeRoundZero
FeRoundUpward

Definition at line 98 of file vfp.hh.

FpDataType

enum class gem5::ArmISA::FpDataType

strong

Floating point data types.

Enumerator
Fp16
Fp32
Fp64

Definition at line 168 of file pred_inst.hh.

FPRounding

enum gem5::ArmISA::FPRounding

Enumerator
FPRounding_TIEEVEN
FPRounding_POSINF
FPRounding_NEGINF
FPRounding_ZERO
FPRounding_TIEAWAY
FPRounding_ODD

Definition at line 60 of file fplib.hh.

GrainSize

enum gem5::ArmISA::GrainSize

Enumerator
Grain4KB
Grain16KB
Grain64KB
ReservedGrain

Definition at line 61 of file pagetable.hh.

InterruptTypes

enum gem5::ArmISA::InterruptTypes

Enumerator
INT_RST
INT_ABT
INT_IRQ
INT_FIQ
INT_SEV
INT_VIRT_IRQ
INT_VIRT_FIQ
NumInterruptTypes
INT_VIRT_ABT

Definition at line 59 of file interrupts.hh.

MiscRegIndex

enum gem5::ArmISA::MiscRegIndex

Enumerator
MISCREG_CPSR
MISCREG_SPSR
MISCREG_SPSR_FIQ
MISCREG_SPSR_IRQ
MISCREG_SPSR_SVC
MISCREG_SPSR_MON
MISCREG_SPSR_ABT
MISCREG_SPSR_HYP
MISCREG_SPSR_UND
MISCREG_ELR_HYP
MISCREG_FPSID
MISCREG_FPSCR
MISCREG_MVFR1
MISCREG_MVFR0
MISCREG_FPEXC
MISCREG_CPSR_MODE
MISCREG_CPSR_Q
MISCREG_FPSCR_EXC
MISCREG_FPSCR_QC
MISCREG_LOCKADDR
MISCREG_LOCKFLAG
MISCREG_PRRR_MAIR0
MISCREG_PRRR_MAIR0_NS
MISCREG_PRRR_MAIR0_S
MISCREG_NMRR_MAIR1
MISCREG_NMRR_MAIR1_NS
MISCREG_NMRR_MAIR1_S
MISCREG_PMXEVTYPER_PMCCFILTR
MISCREG_SEV_MAILBOX
MISCREG_TLBINEEDSYNC
MISCREG_DBGDIDR
MISCREG_DBGDSCRint
MISCREG_DBGDCCINT
MISCREG_DBGDTRTXint
MISCREG_DBGDTRRXint
MISCREG_DBGWFAR
MISCREG_DBGVCR
MISCREG_DBGDTRRXext
MISCREG_DBGDSCRext
MISCREG_DBGDTRTXext
MISCREG_DBGOSECCR
MISCREG_DBGBVR0
MISCREG_DBGBVR1
MISCREG_DBGBVR2
MISCREG_DBGBVR3
MISCREG_DBGBVR4
MISCREG_DBGBVR5
MISCREG_DBGBVR6
MISCREG_DBGBVR7
MISCREG_DBGBVR8
MISCREG_DBGBVR9
MISCREG_DBGBVR10
MISCREG_DBGBVR11
MISCREG_DBGBVR12
MISCREG_DBGBVR13
MISCREG_DBGBVR14
MISCREG_DBGBVR15
MISCREG_DBGBCR0
MISCREG_DBGBCR1
MISCREG_DBGBCR2
MISCREG_DBGBCR3
MISCREG_DBGBCR4
MISCREG_DBGBCR5
MISCREG_DBGBCR6
MISCREG_DBGBCR7
MISCREG_DBGBCR8
MISCREG_DBGBCR9
MISCREG_DBGBCR10
MISCREG_DBGBCR11
MISCREG_DBGBCR12
MISCREG_DBGBCR13
MISCREG_DBGBCR14
MISCREG_DBGBCR15
MISCREG_DBGWVR0
MISCREG_DBGWVR1
MISCREG_DBGWVR2
MISCREG_DBGWVR3
MISCREG_DBGWVR4
MISCREG_DBGWVR5
MISCREG_DBGWVR6
MISCREG_DBGWVR7
MISCREG_DBGWVR8
MISCREG_DBGWVR9
MISCREG_DBGWVR10
MISCREG_DBGWVR11
MISCREG_DBGWVR12
MISCREG_DBGWVR13
MISCREG_DBGWVR14
MISCREG_DBGWVR15
MISCREG_DBGWCR0
MISCREG_DBGWCR1
MISCREG_DBGWCR2
MISCREG_DBGWCR3
MISCREG_DBGWCR4
MISCREG_DBGWCR5
MISCREG_DBGWCR6
MISCREG_DBGWCR7
MISCREG_DBGWCR8
MISCREG_DBGWCR9
MISCREG_DBGWCR10
MISCREG_DBGWCR11
MISCREG_DBGWCR12
MISCREG_DBGWCR13
MISCREG_DBGWCR14
MISCREG_DBGWCR15
MISCREG_DBGDRAR
MISCREG_DBGBXVR0
MISCREG_DBGBXVR1
MISCREG_DBGBXVR2
MISCREG_DBGBXVR3
MISCREG_DBGBXVR4
MISCREG_DBGBXVR5
MISCREG_DBGBXVR6
MISCREG_DBGBXVR7
MISCREG_DBGBXVR8
MISCREG_DBGBXVR9
MISCREG_DBGBXVR10
MISCREG_DBGBXVR11
MISCREG_DBGBXVR12
MISCREG_DBGBXVR13
MISCREG_DBGBXVR14
MISCREG_DBGBXVR15
MISCREG_DBGOSLAR
MISCREG_DBGOSLSR
MISCREG_DBGOSDLR
MISCREG_DBGPRCR
MISCREG_DBGDSAR
MISCREG_DBGCLAIMSET
MISCREG_DBGCLAIMCLR
MISCREG_DBGAUTHSTATUS
MISCREG_DBGDEVID2
MISCREG_DBGDEVID1
MISCREG_DBGDEVID0
MISCREG_TEECR
MISCREG_JIDR
MISCREG_TEEHBR
MISCREG_JOSCR
MISCREG_JMCR
MISCREG_MIDR
MISCREG_CTR
MISCREG_TCMTR
MISCREG_TLBTR
MISCREG_MPIDR
MISCREG_REVIDR
MISCREG_ID_PFR0
MISCREG_ID_PFR1
MISCREG_ID_DFR0
MISCREG_ID_AFR0
MISCREG_ID_MMFR0
MISCREG_ID_MMFR1
MISCREG_ID_MMFR2
MISCREG_ID_MMFR3
MISCREG_ID_MMFR4
MISCREG_ID_ISAR0
MISCREG_ID_ISAR1
MISCREG_ID_ISAR2
MISCREG_ID_ISAR3
MISCREG_ID_ISAR4
MISCREG_ID_ISAR5
MISCREG_ID_ISAR6
MISCREG_CCSIDR
MISCREG_CLIDR
MISCREG_AIDR
MISCREG_CSSELR
MISCREG_CSSELR_NS
MISCREG_CSSELR_S
MISCREG_VPIDR
MISCREG_VMPIDR
MISCREG_SCTLR
MISCREG_SCTLR_NS
MISCREG_SCTLR_S
MISCREG_ACTLR
MISCREG_ACTLR_NS
MISCREG_ACTLR_S
MISCREG_CPACR
MISCREG_SDCR
MISCREG_SCR
MISCREG_SDER
MISCREG_NSACR
MISCREG_HSCTLR
MISCREG_HACTLR
MISCREG_HCR
MISCREG_HCR2
MISCREG_HDCR
MISCREG_HCPTR
MISCREG_HSTR
MISCREG_HACR
MISCREG_TTBR0
MISCREG_TTBR0_NS
MISCREG_TTBR0_S
MISCREG_TTBR1
MISCREG_TTBR1_NS
MISCREG_TTBR1_S
MISCREG_TTBCR
MISCREG_TTBCR_NS
MISCREG_TTBCR_S
MISCREG_HTCR
MISCREG_VTCR
MISCREG_DACR
MISCREG_DACR_NS
MISCREG_DACR_S
MISCREG_DFSR
MISCREG_DFSR_NS
MISCREG_DFSR_S
MISCREG_IFSR
MISCREG_IFSR_NS
MISCREG_IFSR_S
MISCREG_ADFSR
MISCREG_ADFSR_NS
MISCREG_ADFSR_S
MISCREG_AIFSR
MISCREG_AIFSR_NS
MISCREG_AIFSR_S
MISCREG_HADFSR
MISCREG_HAIFSR
MISCREG_HSR
MISCREG_DFAR
MISCREG_DFAR_NS
MISCREG_DFAR_S
MISCREG_IFAR
MISCREG_IFAR_NS
MISCREG_IFAR_S
MISCREG_HDFAR
MISCREG_HIFAR
MISCREG_HPFAR
MISCREG_ICIALLUIS
MISCREG_BPIALLIS
MISCREG_PAR
MISCREG_PAR_NS
MISCREG_PAR_S
MISCREG_ICIALLU
MISCREG_ICIMVAU
MISCREG_CP15ISB
MISCREG_BPIALL
MISCREG_BPIMVA
MISCREG_DCIMVAC
MISCREG_DCISW
MISCREG_ATS1CPR
MISCREG_ATS1CPW
MISCREG_ATS1CUR
MISCREG_ATS1CUW
MISCREG_ATS12NSOPR
MISCREG_ATS12NSOPW
MISCREG_ATS12NSOUR
MISCREG_ATS12NSOUW
MISCREG_DCCMVAC
MISCREG_DCCSW
MISCREG_CP15DSB
MISCREG_CP15DMB
MISCREG_DCCMVAU
MISCREG_DCCIMVAC
MISCREG_DCCISW
MISCREG_ATS1HR
MISCREG_ATS1HW
MISCREG_TLBIALLIS
MISCREG_TLBIMVAIS
MISCREG_TLBIASIDIS
MISCREG_TLBIMVAAIS
MISCREG_TLBIMVALIS
MISCREG_TLBIMVAALIS
MISCREG_ITLBIALL
MISCREG_ITLBIMVA
MISCREG_ITLBIASID
MISCREG_DTLBIALL
MISCREG_DTLBIMVA
MISCREG_DTLBIASID
MISCREG_TLBIALL
MISCREG_TLBIMVA
MISCREG_TLBIASID
MISCREG_TLBIMVAA
MISCREG_TLBIMVAL
MISCREG_TLBIMVAAL
MISCREG_TLBIIPAS2IS
MISCREG_TLBIIPAS2LIS
MISCREG_TLBIALLHIS
MISCREG_TLBIMVAHIS
MISCREG_TLBIALLNSNHIS
MISCREG_TLBIMVALHIS
MISCREG_TLBIIPAS2
MISCREG_TLBIIPAS2L
MISCREG_TLBIALLH
MISCREG_TLBIMVAH
MISCREG_TLBIALLNSNH
MISCREG_TLBIMVALH
MISCREG_PMCR
MISCREG_PMCNTENSET
MISCREG_PMCNTENCLR
MISCREG_PMOVSR
MISCREG_PMSWINC
MISCREG_PMSELR
MISCREG_PMCEID0
MISCREG_PMCEID1
MISCREG_PMCCNTR
MISCREG_PMXEVTYPER
MISCREG_PMCCFILTR
MISCREG_PMXEVCNTR
MISCREG_PMUSERENR
MISCREG_PMINTENSET
MISCREG_PMINTENCLR
MISCREG_PMOVSSET
MISCREG_L2CTLR
MISCREG_L2ECTLR
MISCREG_PRRR
MISCREG_PRRR_NS
MISCREG_PRRR_S
MISCREG_MAIR0
MISCREG_MAIR0_NS
MISCREG_MAIR0_S
MISCREG_NMRR
MISCREG_NMRR_NS
MISCREG_NMRR_S
MISCREG_MAIR1
MISCREG_MAIR1_NS
MISCREG_MAIR1_S
MISCREG_AMAIR0
MISCREG_AMAIR0_NS
MISCREG_AMAIR0_S
MISCREG_AMAIR1
MISCREG_AMAIR1_NS
MISCREG_AMAIR1_S
MISCREG_HMAIR0
MISCREG_HMAIR1
MISCREG_HAMAIR0
MISCREG_HAMAIR1
MISCREG_VBAR
MISCREG_VBAR_NS
MISCREG_VBAR_S
MISCREG_MVBAR
MISCREG_RMR
MISCREG_ISR
MISCREG_HVBAR
MISCREG_FCSEIDR
MISCREG_CONTEXTIDR
MISCREG_CONTEXTIDR_NS
MISCREG_CONTEXTIDR_S
MISCREG_TPIDRURW
MISCREG_TPIDRURW_NS
MISCREG_TPIDRURW_S
MISCREG_TPIDRURO
MISCREG_TPIDRURO_NS
MISCREG_TPIDRURO_S
MISCREG_TPIDRPRW
MISCREG_TPIDRPRW_NS
MISCREG_TPIDRPRW_S
MISCREG_HTPIDR
MISCREG_CNTFRQ
MISCREG_CNTPCT
MISCREG_CNTVCT
MISCREG_CNTP_CTL
MISCREG_CNTP_CTL_NS
MISCREG_CNTP_CTL_S
MISCREG_CNTP_CVAL
MISCREG_CNTP_CVAL_NS
MISCREG_CNTP_CVAL_S
MISCREG_CNTP_TVAL
MISCREG_CNTP_TVAL_NS
MISCREG_CNTP_TVAL_S
MISCREG_CNTV_CTL
MISCREG_CNTV_CVAL
MISCREG_CNTV_TVAL
MISCREG_CNTKCTL
MISCREG_CNTHCTL
MISCREG_CNTHP_CTL
MISCREG_CNTHP_CVAL
MISCREG_CNTHP_TVAL
MISCREG_CNTVOFF
MISCREG_IL1DATA0
MISCREG_IL1DATA1
MISCREG_IL1DATA2
MISCREG_IL1DATA3
MISCREG_DL1DATA0
MISCREG_DL1DATA1
MISCREG_DL1DATA2
MISCREG_DL1DATA3
MISCREG_DL1DATA4
MISCREG_RAMINDEX
MISCREG_L2ACTLR
MISCREG_CBAR
MISCREG_HTTBR
MISCREG_VTTBR
MISCREG_CPUMERRSR
MISCREG_L2MERRSR
MISCREG_MDCCINT_EL1
MISCREG_OSDTRRX_EL1
MISCREG_MDSCR_EL1
MISCREG_OSDTRTX_EL1
MISCREG_OSECCR_EL1
MISCREG_DBGBVR0_EL1
MISCREG_DBGBVR1_EL1
MISCREG_DBGBVR2_EL1
MISCREG_DBGBVR3_EL1
MISCREG_DBGBVR4_EL1
MISCREG_DBGBVR5_EL1
MISCREG_DBGBVR6_EL1
MISCREG_DBGBVR7_EL1
MISCREG_DBGBVR8_EL1
MISCREG_DBGBVR9_EL1
MISCREG_DBGBVR10_EL1
MISCREG_DBGBVR11_EL1
MISCREG_DBGBVR12_EL1
MISCREG_DBGBVR13_EL1
MISCREG_DBGBVR14_EL1
MISCREG_DBGBVR15_EL1
MISCREG_DBGBCR0_EL1
MISCREG_DBGBCR1_EL1
MISCREG_DBGBCR2_EL1
MISCREG_DBGBCR3_EL1
MISCREG_DBGBCR4_EL1
MISCREG_DBGBCR5_EL1
MISCREG_DBGBCR6_EL1
MISCREG_DBGBCR7_EL1
MISCREG_DBGBCR8_EL1
MISCREG_DBGBCR9_EL1
MISCREG_DBGBCR10_EL1
MISCREG_DBGBCR11_EL1
MISCREG_DBGBCR12_EL1
MISCREG_DBGBCR13_EL1
MISCREG_DBGBCR14_EL1
MISCREG_DBGBCR15_EL1
MISCREG_DBGWVR0_EL1
MISCREG_DBGWVR1_EL1
MISCREG_DBGWVR2_EL1
MISCREG_DBGWVR3_EL1
MISCREG_DBGWVR4_EL1
MISCREG_DBGWVR5_EL1
MISCREG_DBGWVR6_EL1
MISCREG_DBGWVR7_EL1
MISCREG_DBGWVR8_EL1
MISCREG_DBGWVR9_EL1
MISCREG_DBGWVR10_EL1
MISCREG_DBGWVR11_EL1
MISCREG_DBGWVR12_EL1
MISCREG_DBGWVR13_EL1
MISCREG_DBGWVR14_EL1
MISCREG_DBGWVR15_EL1
MISCREG_DBGWCR0_EL1
MISCREG_DBGWCR1_EL1
MISCREG_DBGWCR2_EL1
MISCREG_DBGWCR3_EL1
MISCREG_DBGWCR4_EL1
MISCREG_DBGWCR5_EL1
MISCREG_DBGWCR6_EL1
MISCREG_DBGWCR7_EL1
MISCREG_DBGWCR8_EL1
MISCREG_DBGWCR9_EL1
MISCREG_DBGWCR10_EL1
MISCREG_DBGWCR11_EL1
MISCREG_DBGWCR12_EL1
MISCREG_DBGWCR13_EL1
MISCREG_DBGWCR14_EL1
MISCREG_DBGWCR15_EL1
MISCREG_MDCCSR_EL0
MISCREG_MDDTR_EL0
MISCREG_MDDTRTX_EL0
MISCREG_MDDTRRX_EL0
MISCREG_DBGVCR32_EL2
MISCREG_MDRAR_EL1
MISCREG_OSLAR_EL1
MISCREG_OSLSR_EL1
MISCREG_OSDLR_EL1
MISCREG_DBGPRCR_EL1
MISCREG_DBGCLAIMSET_EL1
MISCREG_DBGCLAIMCLR_EL1
MISCREG_DBGAUTHSTATUS_EL1
MISCREG_TEECR32_EL1
MISCREG_TEEHBR32_EL1
MISCREG_MIDR_EL1
MISCREG_MPIDR_EL1
MISCREG_REVIDR_EL1
MISCREG_ID_PFR0_EL1
MISCREG_ID_PFR1_EL1
MISCREG_ID_DFR0_EL1
MISCREG_ID_AFR0_EL1
MISCREG_ID_MMFR0_EL1
MISCREG_ID_MMFR1_EL1
MISCREG_ID_MMFR2_EL1
MISCREG_ID_MMFR3_EL1
MISCREG_ID_MMFR4_EL1
MISCREG_ID_ISAR0_EL1
MISCREG_ID_ISAR1_EL1
MISCREG_ID_ISAR2_EL1
MISCREG_ID_ISAR3_EL1
MISCREG_ID_ISAR4_EL1
MISCREG_ID_ISAR5_EL1
MISCREG_ID_ISAR6_EL1
MISCREG_MVFR0_EL1
MISCREG_MVFR1_EL1
MISCREG_MVFR2_EL1
MISCREG_ID_AA64PFR0_EL1
MISCREG_ID_AA64PFR1_EL1
MISCREG_ID_AA64DFR0_EL1
MISCREG_ID_AA64DFR1_EL1
MISCREG_ID_AA64AFR0_EL1
MISCREG_ID_AA64AFR1_EL1
MISCREG_ID_AA64ISAR0_EL1
MISCREG_ID_AA64ISAR1_EL1
MISCREG_ID_AA64MMFR0_EL1
MISCREG_ID_AA64MMFR1_EL1
MISCREG_CCSIDR_EL1
MISCREG_CLIDR_EL1
MISCREG_AIDR_EL1
MISCREG_CSSELR_EL1
MISCREG_CTR_EL0
MISCREG_DCZID_EL0
MISCREG_VPIDR_EL2
MISCREG_VMPIDR_EL2
MISCREG_SCTLR_EL1
MISCREG_SCTLR_EL12
MISCREG_SCTLR2_EL1
MISCREG_SCTLR2_EL12
MISCREG_ACTLR_EL1
MISCREG_CPACR_EL1
MISCREG_CPACR_EL12
MISCREG_SCTLR_EL2
MISCREG_SCTLR2_EL2
MISCREG_ACTLR_EL2
MISCREG_HCR_EL2
MISCREG_HCRX_EL2
MISCREG_MDCR_EL2
MISCREG_CPTR_EL2
MISCREG_HSTR_EL2
MISCREG_HACR_EL2
MISCREG_SCTLR_EL3
MISCREG_SCTLR2_EL3
MISCREG_ACTLR_EL3
MISCREG_SCR_EL3
MISCREG_SDER32_EL3
MISCREG_CPTR_EL3
MISCREG_MDCR_EL3
MISCREG_TTBR0_EL1
MISCREG_TTBR0_EL12
MISCREG_TTBR1_EL1
MISCREG_TTBR1_EL12
MISCREG_TCR_EL1
MISCREG_TCR_EL12
MISCREG_TCR2_EL1
MISCREG_TCR2_EL12
MISCREG_TTBR0_EL2
MISCREG_TCR_EL2
MISCREG_TCR2_EL2
MISCREG_VTTBR_EL2
MISCREG_VTCR_EL2
MISCREG_VSTTBR_EL2
MISCREG_VSTCR_EL2
MISCREG_TTBR0_EL3
MISCREG_TCR_EL3
MISCREG_DACR32_EL2
MISCREG_SPSR_EL1
MISCREG_SPSR_EL12
MISCREG_ELR_EL1
MISCREG_ELR_EL12
MISCREG_SP_EL0
MISCREG_SPSEL
MISCREG_CURRENTEL
MISCREG_NZCV
MISCREG_DAIF
MISCREG_FPCR
MISCREG_FPSR
MISCREG_DSPSR_EL0
MISCREG_DLR_EL0
MISCREG_SPSR_EL2
MISCREG_ELR_EL2
MISCREG_SP_EL1
MISCREG_SPSR_IRQ_AA64
MISCREG_SPSR_ABT_AA64
MISCREG_SPSR_UND_AA64
MISCREG_SPSR_FIQ_AA64
MISCREG_SPSR_EL3
MISCREG_ELR_EL3
MISCREG_SP_EL2
MISCREG_AFSR0_EL1
MISCREG_AFSR0_EL12
MISCREG_AFSR1_EL1
MISCREG_AFSR1_EL12
MISCREG_ESR_EL1
MISCREG_ESR_EL12
MISCREG_IFSR32_EL2
MISCREG_AFSR0_EL2
MISCREG_AFSR1_EL2
MISCREG_ESR_EL2
MISCREG_FPEXC32_EL2
MISCREG_AFSR0_EL3
MISCREG_AFSR1_EL3
MISCREG_ESR_EL3
MISCREG_FAR_EL1
MISCREG_FAR_EL12
MISCREG_FAR_EL2
MISCREG_HPFAR_EL2
MISCREG_FAR_EL3
MISCREG_IC_IALLUIS
MISCREG_PAR_EL1
MISCREG_IC_IALLU
MISCREG_DC_IVAC_Xt
MISCREG_DC_ISW_Xt
MISCREG_AT_S1E1R_Xt
MISCREG_AT_S1E1W_Xt
MISCREG_AT_S1E0R_Xt
MISCREG_AT_S1E0W_Xt
MISCREG_DC_CSW_Xt
MISCREG_DC_CISW_Xt
MISCREG_DC_ZVA_Xt
MISCREG_IC_IVAU_Xt
MISCREG_DC_CVAC_Xt
MISCREG_DC_CVAU_Xt
MISCREG_DC_CIVAC_Xt
MISCREG_AT_S1E2R_Xt
MISCREG_AT_S1E2W_Xt
MISCREG_AT_S12E1R_Xt
MISCREG_AT_S12E1W_Xt
MISCREG_AT_S12E0R_Xt
MISCREG_AT_S12E0W_Xt
MISCREG_AT_S1E3R_Xt
MISCREG_AT_S1E3W_Xt
MISCREG_TLBI_VMALLE1IS
MISCREG_TLBI_VMALLE1OS
MISCREG_TLBI_VAE1IS
MISCREG_TLBI_VAE1OS
MISCREG_TLBI_ASIDE1IS
MISCREG_TLBI_ASIDE1OS
MISCREG_TLBI_VAAE1IS
MISCREG_TLBI_VAAE1OS
MISCREG_TLBI_VALE1IS
MISCREG_TLBI_VALE1OS
MISCREG_TLBI_VAALE1IS
MISCREG_TLBI_VAALE1OS
MISCREG_TLBI_VMALLE1
MISCREG_TLBI_VAE1
MISCREG_TLBI_ASIDE1
MISCREG_TLBI_VAAE1
MISCREG_TLBI_VALE1
MISCREG_TLBI_VAALE1
MISCREG_TLBI_IPAS2E1IS
MISCREG_TLBI_IPAS2E1OS
MISCREG_TLBI_IPAS2LE1IS
MISCREG_TLBI_IPAS2LE1OS
MISCREG_TLBI_ALLE2IS
MISCREG_TLBI_ALLE2OS
MISCREG_TLBI_VAE2IS
MISCREG_TLBI_VAE2OS
MISCREG_TLBI_ALLE1IS
MISCREG_TLBI_ALLE1OS
MISCREG_TLBI_VALE2IS
MISCREG_TLBI_VALE2OS
MISCREG_TLBI_VMALLS12E1IS
MISCREG_TLBI_VMALLS12E1OS
MISCREG_TLBI_IPAS2E1
MISCREG_TLBI_IPAS2LE1
MISCREG_TLBI_ALLE2
MISCREG_TLBI_VAE2
MISCREG_TLBI_ALLE1
MISCREG_TLBI_VALE2
MISCREG_TLBI_VMALLS12E1
MISCREG_TLBI_ALLE3IS
MISCREG_TLBI_ALLE3OS
MISCREG_TLBI_VAE3IS
MISCREG_TLBI_VAE3OS
MISCREG_TLBI_VALE3IS
MISCREG_TLBI_VALE3OS
MISCREG_TLBI_ALLE3
MISCREG_TLBI_VAE3
MISCREG_TLBI_VALE3
MISCREG_TLBI_RVAE1
MISCREG_TLBI_RVAAE1
MISCREG_TLBI_RVALE1
MISCREG_TLBI_RVAALE1
MISCREG_TLBI_RIPAS2E1
MISCREG_TLBI_RIPAS2LE1
MISCREG_TLBI_RVAE2
MISCREG_TLBI_RVALE2
MISCREG_TLBI_RVAE3
MISCREG_TLBI_RVALE3
MISCREG_TLBI_RVAE1IS
MISCREG_TLBI_RVAAE1IS
MISCREG_TLBI_RVALE1IS
MISCREG_TLBI_RVAALE1IS
MISCREG_TLBI_RIPAS2E1IS
MISCREG_TLBI_RIPAS2LE1IS
MISCREG_TLBI_RVAE2IS
MISCREG_TLBI_RVALE2IS
MISCREG_TLBI_RVAE3IS
MISCREG_TLBI_RVALE3IS
MISCREG_TLBI_RVAE1OS
MISCREG_TLBI_RVAAE1OS
MISCREG_TLBI_RVALE1OS
MISCREG_TLBI_RVAALE1OS
MISCREG_TLBI_RIPAS2E1OS
MISCREG_TLBI_RIPAS2LE1OS
MISCREG_TLBI_RVAE2OS
MISCREG_TLBI_RVALE2OS
MISCREG_TLBI_RVAE3OS
MISCREG_TLBI_RVALE3OS
MISCREG_PMINTENSET_EL1
MISCREG_PMINTENCLR_EL1
MISCREG_PMCR_EL0
MISCREG_PMCNTENSET_EL0
MISCREG_PMCNTENCLR_EL0
MISCREG_PMOVSCLR_EL0
MISCREG_PMSWINC_EL0
MISCREG_PMSELR_EL0
MISCREG_PMCEID0_EL0
MISCREG_PMCEID1_EL0
MISCREG_PMCCNTR_EL0
MISCREG_PMXEVTYPER_EL0
MISCREG_PMCCFILTR_EL0
MISCREG_PMXEVCNTR_EL0
MISCREG_PMUSERENR_EL0
MISCREG_PMOVSSET_EL0
MISCREG_MAIR_EL1
MISCREG_MAIR_EL12
MISCREG_AMAIR_EL1
MISCREG_AMAIR_EL12
MISCREG_MAIR_EL2
MISCREG_AMAIR_EL2
MISCREG_MAIR_EL3
MISCREG_AMAIR_EL3
MISCREG_L2CTLR_EL1
MISCREG_L2ECTLR_EL1
MISCREG_VBAR_EL1
MISCREG_VBAR_EL12
MISCREG_RVBAR_EL1
MISCREG_ISR_EL1
MISCREG_VBAR_EL2
MISCREG_RVBAR_EL2
MISCREG_VBAR_EL3
MISCREG_RVBAR_EL3
MISCREG_RMR_EL3
MISCREG_CONTEXTIDR_EL1
MISCREG_CONTEXTIDR_EL12
MISCREG_TPIDR_EL1
MISCREG_TPIDR_EL0
MISCREG_TPIDRRO_EL0
MISCREG_TPIDR_EL2
MISCREG_TPIDR_EL3
MISCREG_CNTFRQ_EL0
MISCREG_CNTPCT_EL0
MISCREG_CNTVCT_EL0
MISCREG_CNTP_CTL_EL0
MISCREG_CNTP_CVAL_EL0
MISCREG_CNTP_TVAL_EL0
MISCREG_CNTV_CTL_EL0
MISCREG_CNTV_CVAL_EL0
MISCREG_CNTV_TVAL_EL0
MISCREG_CNTP_CTL_EL02
MISCREG_CNTP_CVAL_EL02
MISCREG_CNTP_TVAL_EL02
MISCREG_CNTV_CTL_EL02
MISCREG_CNTV_CVAL_EL02
MISCREG_CNTV_TVAL_EL02
MISCREG_CNTKCTL_EL1
MISCREG_CNTKCTL_EL12
MISCREG_CNTPS_CTL_EL1
MISCREG_CNTPS_CVAL_EL1
MISCREG_CNTPS_TVAL_EL1
MISCREG_CNTHCTL_EL2
MISCREG_CNTHP_CTL_EL2
MISCREG_CNTHP_CVAL_EL2
MISCREG_CNTHP_TVAL_EL2
MISCREG_CNTHPS_CTL_EL2
MISCREG_CNTHPS_CVAL_EL2
MISCREG_CNTHPS_TVAL_EL2
MISCREG_CNTHV_CTL_EL2
MISCREG_CNTHV_CVAL_EL2
MISCREG_CNTHV_TVAL_EL2
MISCREG_CNTHVS_CTL_EL2
MISCREG_CNTHVS_CVAL_EL2
MISCREG_CNTHVS_TVAL_EL2
MISCREG_CNTVOFF_EL2
MISCREG_PMEVCNTR0_EL0
MISCREG_PMEVCNTR1_EL0
MISCREG_PMEVCNTR2_EL0
MISCREG_PMEVCNTR3_EL0
MISCREG_PMEVCNTR4_EL0
MISCREG_PMEVCNTR5_EL0
MISCREG_PMEVTYPER0_EL0
MISCREG_PMEVTYPER1_EL0
MISCREG_PMEVTYPER2_EL0
MISCREG_PMEVTYPER3_EL0
MISCREG_PMEVTYPER4_EL0
MISCREG_PMEVTYPER5_EL0
MISCREG_IL1DATA0_EL1
MISCREG_IL1DATA1_EL1
MISCREG_IL1DATA2_EL1
MISCREG_IL1DATA3_EL1
MISCREG_DL1DATA0_EL1
MISCREG_DL1DATA1_EL1
MISCREG_DL1DATA2_EL1
MISCREG_DL1DATA3_EL1
MISCREG_DL1DATA4_EL1
MISCREG_L2ACTLR_EL1
MISCREG_CPUACTLR_EL1
MISCREG_CPUECTLR_EL1
MISCREG_CPUMERRSR_EL1
MISCREG_L2MERRSR_EL1
MISCREG_CBAR_EL1
MISCREG_CONTEXTIDR_EL2
MISCREG_TTBR1_EL2
MISCREG_ID_AA64MMFR2_EL1
MISCREG_ID_AA64MMFR3_EL1
MISCREG_APDAKeyHi_EL1
MISCREG_APDAKeyLo_EL1
MISCREG_APDBKeyHi_EL1
MISCREG_APDBKeyLo_EL1
MISCREG_APGAKeyHi_EL1
MISCREG_APGAKeyLo_EL1
MISCREG_APIAKeyHi_EL1
MISCREG_APIAKeyLo_EL1
MISCREG_APIBKeyHi_EL1
MISCREG_APIBKeyLo_EL1
MISCREG_ICC_PMR_EL1
MISCREG_ICC_IAR0_EL1
MISCREG_ICC_EOIR0_EL1
MISCREG_ICC_HPPIR0_EL1
MISCREG_ICC_BPR0_EL1
MISCREG_ICC_AP0R0_EL1
MISCREG_ICC_AP0R1_EL1
MISCREG_ICC_AP0R2_EL1
MISCREG_ICC_AP0R3_EL1
MISCREG_ICC_AP1R0_EL1
MISCREG_ICC_AP1R0_EL1_NS
MISCREG_ICC_AP1R0_EL1_S
MISCREG_ICC_AP1R1_EL1
MISCREG_ICC_AP1R1_EL1_NS
MISCREG_ICC_AP1R1_EL1_S
MISCREG_ICC_AP1R2_EL1
MISCREG_ICC_AP1R2_EL1_NS
MISCREG_ICC_AP1R2_EL1_S
MISCREG_ICC_AP1R3_EL1
MISCREG_ICC_AP1R3_EL1_NS
MISCREG_ICC_AP1R3_EL1_S
MISCREG_ICC_DIR_EL1
MISCREG_ICC_RPR_EL1
MISCREG_ICC_SGI1R_EL1
MISCREG_ICC_ASGI1R_EL1
MISCREG_ICC_SGI0R_EL1
MISCREG_ICC_IAR1_EL1
MISCREG_ICC_EOIR1_EL1
MISCREG_ICC_HPPIR1_EL1
MISCREG_ICC_BPR1_EL1
MISCREG_ICC_BPR1_EL1_NS
MISCREG_ICC_BPR1_EL1_S
MISCREG_ICC_CTLR_EL1
MISCREG_ICC_CTLR_EL1_NS
MISCREG_ICC_CTLR_EL1_S
MISCREG_ICC_SRE_EL1
MISCREG_ICC_SRE_EL1_NS
MISCREG_ICC_SRE_EL1_S
MISCREG_ICC_IGRPEN0_EL1
MISCREG_ICC_IGRPEN1_EL1
MISCREG_ICC_IGRPEN1_EL1_NS
MISCREG_ICC_IGRPEN1_EL1_S
MISCREG_ICC_SRE_EL2
MISCREG_ICC_CTLR_EL3
MISCREG_ICC_SRE_EL3
MISCREG_ICC_IGRPEN1_EL3
MISCREG_ICH_AP0R0_EL2
MISCREG_ICH_AP0R1_EL2
MISCREG_ICH_AP0R2_EL2
MISCREG_ICH_AP0R3_EL2
MISCREG_ICH_AP1R0_EL2
MISCREG_ICH_AP1R1_EL2
MISCREG_ICH_AP1R2_EL2
MISCREG_ICH_AP1R3_EL2
MISCREG_ICH_HCR_EL2
MISCREG_ICH_VTR_EL2
MISCREG_ICH_MISR_EL2
MISCREG_ICH_EISR_EL2
MISCREG_ICH_ELRSR_EL2
MISCREG_ICH_VMCR_EL2
MISCREG_ICH_LR0_EL2
MISCREG_ICH_LR1_EL2
MISCREG_ICH_LR2_EL2
MISCREG_ICH_LR3_EL2
MISCREG_ICH_LR4_EL2
MISCREG_ICH_LR5_EL2
MISCREG_ICH_LR6_EL2
MISCREG_ICH_LR7_EL2
MISCREG_ICH_LR8_EL2
MISCREG_ICH_LR9_EL2
MISCREG_ICH_LR10_EL2
MISCREG_ICH_LR11_EL2
MISCREG_ICH_LR12_EL2
MISCREG_ICH_LR13_EL2
MISCREG_ICH_LR14_EL2
MISCREG_ICH_LR15_EL2
MISCREG_ICV_PMR_EL1
MISCREG_ICV_IAR0_EL1
MISCREG_ICV_EOIR0_EL1
MISCREG_ICV_HPPIR0_EL1
MISCREG_ICV_BPR0_EL1
MISCREG_ICV_AP0R0_EL1
MISCREG_ICV_AP0R1_EL1
MISCREG_ICV_AP0R2_EL1
MISCREG_ICV_AP0R3_EL1
MISCREG_ICV_AP1R0_EL1
MISCREG_ICV_AP1R0_EL1_NS
MISCREG_ICV_AP1R0_EL1_S
MISCREG_ICV_AP1R1_EL1
MISCREG_ICV_AP1R1_EL1_NS
MISCREG_ICV_AP1R1_EL1_S
MISCREG_ICV_AP1R2_EL1
MISCREG_ICV_AP1R2_EL1_NS
MISCREG_ICV_AP1R2_EL1_S
MISCREG_ICV_AP1R3_EL1
MISCREG_ICV_AP1R3_EL1_NS
MISCREG_ICV_AP1R3_EL1_S
MISCREG_ICV_DIR_EL1
MISCREG_ICV_RPR_EL1
MISCREG_ICV_SGI1R_EL1
MISCREG_ICV_ASGI1R_EL1
MISCREG_ICV_SGI0R_EL1
MISCREG_ICV_IAR1_EL1
MISCREG_ICV_EOIR1_EL1
MISCREG_ICV_HPPIR1_EL1
MISCREG_ICV_BPR1_EL1
MISCREG_ICV_BPR1_EL1_NS
MISCREG_ICV_BPR1_EL1_S
MISCREG_ICV_CTLR_EL1
MISCREG_ICV_CTLR_EL1_NS
MISCREG_ICV_CTLR_EL1_S
MISCREG_ICV_SRE_EL1
MISCREG_ICV_SRE_EL1_NS
MISCREG_ICV_SRE_EL1_S
MISCREG_ICV_IGRPEN0_EL1
MISCREG_ICV_IGRPEN1_EL1
MISCREG_ICV_IGRPEN1_EL1_NS
MISCREG_ICV_IGRPEN1_EL1_S
MISCREG_ICC_AP0R0
MISCREG_ICC_AP0R1
MISCREG_ICC_AP0R2
MISCREG_ICC_AP0R3
MISCREG_ICC_AP1R0
MISCREG_ICC_AP1R0_NS
MISCREG_ICC_AP1R0_S
MISCREG_ICC_AP1R1
MISCREG_ICC_AP1R1_NS
MISCREG_ICC_AP1R1_S
MISCREG_ICC_AP1R2
MISCREG_ICC_AP1R2_NS
MISCREG_ICC_AP1R2_S
MISCREG_ICC_AP1R3
MISCREG_ICC_AP1R3_NS
MISCREG_ICC_AP1R3_S
MISCREG_ICC_ASGI1R
MISCREG_ICC_BPR0
MISCREG_ICC_BPR1
MISCREG_ICC_BPR1_NS
MISCREG_ICC_BPR1_S
MISCREG_ICC_CTLR
MISCREG_ICC_CTLR_NS
MISCREG_ICC_CTLR_S
MISCREG_ICC_DIR
MISCREG_ICC_EOIR0
MISCREG_ICC_EOIR1
MISCREG_ICC_HPPIR0
MISCREG_ICC_HPPIR1
MISCREG_ICC_HSRE
MISCREG_ICC_IAR0
MISCREG_ICC_IAR1
MISCREG_ICC_IGRPEN0
MISCREG_ICC_IGRPEN1
MISCREG_ICC_IGRPEN1_NS
MISCREG_ICC_IGRPEN1_S
MISCREG_ICC_MCTLR
MISCREG_ICC_MGRPEN1
MISCREG_ICC_MSRE
MISCREG_ICC_PMR
MISCREG_ICC_RPR
MISCREG_ICC_SGI0R
MISCREG_ICC_SGI1R
MISCREG_ICC_SRE
MISCREG_ICC_SRE_NS
MISCREG_ICC_SRE_S
MISCREG_ICH_AP0R0
MISCREG_ICH_AP0R1
MISCREG_ICH_AP0R2
MISCREG_ICH_AP0R3
MISCREG_ICH_AP1R0
MISCREG_ICH_AP1R1
MISCREG_ICH_AP1R2
MISCREG_ICH_AP1R3
MISCREG_ICH_HCR
MISCREG_ICH_VTR
MISCREG_ICH_MISR
MISCREG_ICH_EISR
MISCREG_ICH_ELRSR
MISCREG_ICH_VMCR
MISCREG_ICH_LR0
MISCREG_ICH_LR1
MISCREG_ICH_LR2
MISCREG_ICH_LR3
MISCREG_ICH_LR4
MISCREG_ICH_LR5
MISCREG_ICH_LR6
MISCREG_ICH_LR7
MISCREG_ICH_LR8
MISCREG_ICH_LR9
MISCREG_ICH_LR10
MISCREG_ICH_LR11
MISCREG_ICH_LR12
MISCREG_ICH_LR13
MISCREG_ICH_LR14
MISCREG_ICH_LR15
MISCREG_ICH_LRC0
MISCREG_ICH_LRC1
MISCREG_ICH_LRC2
MISCREG_ICH_LRC3
MISCREG_ICH_LRC4
MISCREG_ICH_LRC5
MISCREG_ICH_LRC6
MISCREG_ICH_LRC7
MISCREG_ICH_LRC8
MISCREG_ICH_LRC9
MISCREG_ICH_LRC10
MISCREG_ICH_LRC11
MISCREG_ICH_LRC12
MISCREG_ICH_LRC13
MISCREG_ICH_LRC14
MISCREG_ICH_LRC15
MISCREG_ID_AA64ZFR0_EL1
MISCREG_ZCR_EL3
MISCREG_ZCR_EL2
MISCREG_ZCR_EL12
MISCREG_ZCR_EL1
MISCREG_ID_AA64SMFR0_EL1
MISCREG_SVCR
MISCREG_SMIDR_EL1
MISCREG_SMPRI_EL1
MISCREG_SMPRIMAP_EL2
MISCREG_SMCR_EL3
MISCREG_SMCR_EL2
MISCREG_SMCR_EL12
MISCREG_SMCR_EL1
MISCREG_TPIDR2_EL0
MISCREG_MPAMSM_EL1
MISCREG_RNDR
MISCREG_RNDRRS
MISCREG_HFGITR_EL2
MISCREG_HFGRTR_EL2
MISCREG_HFGWTR_EL2
MISCREG_HDFGRTR_EL2
MISCREG_HDFGWTR_EL2
MISCREG_MPAMIDR_EL1
MISCREG_MPAM0_EL1
MISCREG_MPAM1_EL1
MISCREG_MPAM2_EL2
MISCREG_MPAM3_EL3
MISCREG_MPAM1_EL12
MISCREG_MPAMHCR_EL2
MISCREG_MPAMVPMV_EL2
MISCREG_MPAMVPM0_EL2
MISCREG_MPAMVPM1_EL2
MISCREG_MPAMVPM2_EL2
MISCREG_MPAMVPM3_EL2
MISCREG_MPAMVPM4_EL2
MISCREG_MPAMVPM5_EL2
MISCREG_MPAMVPM6_EL2
MISCREG_MPAMVPM7_EL2
NUM_PHYS_MISCREGS
MISCREG_NOP
MISCREG_RAZ
MISCREG_UNKNOWN
MISCREG_IMPDEF_UNIMPL
MISCREG_ERRIDR_EL1
MISCREG_ERRSELR_EL1
MISCREG_ERXFR_EL1
MISCREG_ERXCTLR_EL1
MISCREG_ERXSTATUS_EL1
MISCREG_ERXADDR_EL1
MISCREG_ERXMISC0_EL1
MISCREG_ERXMISC1_EL1
MISCREG_DISR_EL1
MISCREG_VSESR_EL2
MISCREG_VDISR_EL2
MISCREG_PAN
MISCREG_UAO
NUM_MISCREGS

Definition at line 65 of file misc.hh.

MiscRegInfo

enum gem5::ArmISA::MiscRegInfo

Enumerator
MISCREG_IMPLEMENTED
MISCREG_UNVERIFIABLE
MISCREG_UNSERIALIZE
MISCREG_WARN_NOT_FAIL
MISCREG_MUTEX
MISCREG_BANKED
MISCREG_BANKED64
MISCREG_BANKED_CHILD
MISCREG_USR_NS_RD
MISCREG_USR_NS_WR
MISCREG_USR_S_RD
MISCREG_USR_S_WR
MISCREG_PRI_NS_RD
MISCREG_PRI_NS_WR
MISCREG_PRI_S_RD
MISCREG_PRI_S_WR
MISCREG_HYP_NS_RD
MISCREG_HYP_NS_WR
MISCREG_HYP_S_RD
MISCREG_HYP_S_WR
MISCREG_MON_NS0_RD
MISCREG_MON_NS0_WR
MISCREG_MON_NS1_RD
MISCREG_MON_NS1_WR
NUM_MISCREG_INFOS

Definition at line 1201 of file misc.hh.

OperatingMode

enum gem5::ArmISA::OperatingMode

Enumerator
MODE_EL0T
MODE_EL1T
MODE_EL1H
MODE_EL2T
MODE_EL2H
MODE_EL3T
MODE_EL3H
MODE_USER
MODE_FIQ
MODE_IRQ
MODE_SVC
MODE_MON
MODE_ABORT
MODE_HYP
MODE_UNDEFINED
MODE_SYSTEM
MODE_MAXMODE

Definition at line 287 of file types.hh.

RoundMode

enum gem5::ArmISA::RoundMode

Enumerator
RND_ZERO
RND_DOWN
RND_UP
RND_NEAREST

Definition at line 263 of file types.hh.

SvePredType

enum class gem5::ArmISA::SvePredType

strong

Enumerator
NONE
MERGE
ZERO
SELECT

Definition at line 48 of file sve.hh.

TranslationRegime

enum class gem5::ArmISA::TranslationRegime

strong

Enumerator
EL10
EL20
EL2
EL3

Definition at line 279 of file types.hh.

VfpMicroMode

enum gem5::ArmISA::VfpMicroMode

Enumerator
VfpNotAMicroop
VfpMicroop
VfpFirstMicroop
VfpLastMicroop

Definition at line 56 of file vfp.hh.

VfpRoundingMode

enum gem5::ArmISA::VfpRoundingMode

Enumerator
VfpRoundNearest
VfpRoundUpward
VfpRoundDown
VfpRoundZero
VfpRoundAway

Definition at line 106 of file vfp.hh.

Function Documentation

AArch32isUndefinedGenericTimer()

bool gem5::ArmISA::AArch32isUndefinedGenericTimer	(	MiscRegIndex	reg,
		ThreadContext *	tc )

Definition at line 660 of file misc.cc.

References condGenericTimerSystemAccessTrapEL1(), currEL(), EL0, EL1, EL2Enabled(), ELIs32(), MISCREG_HCR_EL2, gem5::ThreadContext::readMiscReg(), and gem5::X86ISA::reg.

Referenced by canReadCoprocReg(), and canWriteCoprocReg().

AArch64AArch32SystemAccessTrap()

Fault gem5::ArmISA::AArch64AArch32SystemAccessTrap	(	const MiscRegIndex	misc_reg,
		ExtMachInst	mach_inst,
		ThreadContext *	tc,
		uint32_t	imm,
		ExceptionClass	ec )

Definition at line 786 of file utility.cc.

References currEL(), ec, EL1, EL2, EL2Enabled(), ELIs32(), imm, isAArch64AArch32SystemAccessTrapEL1(), isAArch64AArch32SystemAccessTrapEL2(), and gem5::NoFault.

Referenced by mcrMrc15Trap(), and mcrrMrrc15Trap().

aarch64SysRegReadOnly()

bool gem5::ArmISA::aarch64SysRegReadOnly

(

MiscRegIndex

miscReg

)

add128()

static void gem5::ArmISA::add128 ( uint64_t * x0, uint64_t * x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )

inlinestatic

Definition at line 197 of file fplib.cc.

References gem5::MipsISA::a0, a1, gem5::QARMA::b0, and gem5::QARMA::b1.

Referenced by fp64_muladd().

addPAC()

uint64_t gem5::ArmISA::addPAC	(	ThreadContext *	tc,
		ExceptionLevel	el,
		uint64_t	ptr,
		uint64_t	modifier,
		uint64_t	k1,
		uint64_t	k0,
		bool	data )

Definition at line 135 of file pauth_helpers.cc.

References gem5::bits(), calculateBottomPACBit(), calculateTBI(), gem5::QARMA::computePAC(), data, el, EL1, EL2, gem5::ArmSystem::haveEL(), gem5::MipsISA::k0, mask, MISCREG_TCR_EL1, MISCREG_TCR_EL2, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), t, tbi, and upperAndLowerRange().

Referenced by addPACDA(), addPACDB(), addPACIA(), and addPACIB().

addPACDA()

Fault gem5::ArmISA::addPACDA	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 572 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDAKeyHi_EL1, MISCREG_APDAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

addPACDB()

Fault gem5::ArmISA::addPACDB	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 636 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

addPACGA()

Fault gem5::ArmISA::addPACGA	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 697 of file pauth_helpers.cc.

References gem5::QARMA::computePAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::ArmSystem::haveEL(), MISCREG_APGAKeyHi_EL1, MISCREG_APGAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), and trapPACUse().

addPACIA()

Fault gem5::ArmISA::addPACIA	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 745 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

addPACIB()

Fault gem5::ArmISA::addPACIB	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 804 of file pauth_helpers.cc.

References addPAC(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIBKeyHi_EL1, MISCREG_APIBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

auth()

uint64_t gem5::ArmISA::auth	(	ThreadContext *	tc,
		ExceptionLevel	el,
		uint64_t	ptr,
		uint64_t	modifier,
		uint64_t	k1,
		uint64_t	K0,
		bool	data,
		uint8_t	errorcode )

Definition at line 227 of file pauth_helpers.cc.

References gem5::bits(), calculateBottomPACBit(), calculateTBI(), gem5::QARMA::computePAC(), data, el, gem5::MipsISA::k0, mask, and tbi.

Referenced by authDA(), authDB(), authIA(), and authIB().

authDA()

Fault gem5::ArmISA::authDA	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 284 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDAKeyHi_EL1, MISCREG_APDAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

authDB()

Fault gem5::ArmISA::authDB	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 352 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

authIA()

Fault gem5::ArmISA::authIA	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 422 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

authIB()

Fault gem5::ArmISA::authIB	(	ThreadContext *	tc,
		uint64_t	X,
		uint64_t	Y,
		uint64_t *	out )

Definition at line 496 of file pauth_helpers.cc.

References auth(), currEL(), el, EL0, EL1, EL2, EL2Enabled(), EL3, gem5::X86ISA::enable, gem5::ArmSystem::haveEL(), MISCREG_APIBKeyHi_EL1, MISCREG_APIBKeyLo_EL1, MISCREG_HCR_EL2, MISCREG_SCR_EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, gem5::NoFault, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), sc2, trapPACUse(), and gem5::X86ISA::X.

badMode()

bool gem5::ArmISA::badMode	(	ThreadContext *	tc,
		OperatingMode	mode )

badMode is checking if the execution mode provided as an argument is valid and implemented.

Parameters

tc	ThreadContext
mode	OperatingMode to check

Returns

false if mode is valid and implemented, true otherwise

Definition at line 406 of file utility.cc.

References gem5::ArmSystem::haveEL(), mode, opModeToEL(), and unknownMode().

Referenced by gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr().

badMode32()

bool gem5::ArmISA::badMode32	(	ThreadContext *	tc,
		OperatingMode	mode )

badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32

Parameters

tc	ThreadContext
mode	OperatingMode to check

Returns

false if mode is valid and implemented, true otherwise

Definition at line 400 of file utility.cc.

References gem5::ArmSystem::haveEL(), mode, opModeToEL(), and unknownMode32().

bitsToFp() [1/2]

static double gem5::ArmISA::bitsToFp ( uint64_t bits, double junk )

inlinestatic

Definition at line 196 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

bitsToFp() [2/2]

static float gem5::ArmISA::bitsToFp ( uint64_t bits, float junk )

inlinestatic

Definition at line 184 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::FpOp::dbl(), flushToZero(), fpMulAdd(), and makeDouble().

BitUnion32() [1/2]

gem5::ArmISA::BitUnion32

(

CPSR

)

BitUnion32() [2/2]

gem5::ArmISA::BitUnion32

(

PackedIntReg

)

BitUnion64() [1/2]

gem5::ArmISA::BitUnion64

(

CNTKCTL

)

BitUnion64() [2/2]

gem5::ArmISA::BitUnion64

(

ExtMachInst

)

BitUnion8() [1/2]

gem5::ArmISA::BitUnion8

(

ITSTATE

)

BitUnion8() [2/2]

gem5::ArmISA::BitUnion8

(

OperatingMode64

)

byteOrder()

ByteOrder gem5::ArmISA::byteOrder ( const ThreadContext * tc )

inline

Definition at line 359 of file utility.hh.

References isBigEndian64().

Referenced by gem5::PowerProcess::argsInit(), gem5::ArmSemihosting::byteOrder(), gem5::ArmISA::TableWalker::doL1Descriptor(), gem5::ArmISA::TableWalker::doL2Descriptor(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > sizeof(uint32_t)) > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::PowerProcess::initState(), gem5::guest_abi::Aapcs32ArgumentBase::loadFromStack(), gem5::guest_abi::Aapcs64ArgumentBase::loadFromStack(), gem5::VirtDescriptor::operator=(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store(), and gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store().

calculateBottomPACBit()

int gem5::ArmISA::calculateBottomPACBit	(	ThreadContext *	tc,
		ExceptionLevel	el,
		bool	top_bit )

Definition at line 80 of file pauth_helpers.cc.

References el, EL1, EL2, gem5::ArmSystem::haveEL(), MISCREG_ID_AA64MMFR2_EL1, MISCREG_TCR_EL1, MISCREG_TCR_EL2, MISCREG_TCR_EL3, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), and upperAndLowerRange().

Referenced by addPAC(), auth(), and stripPAC().

calculateTBI()

bool gem5::ArmISA::calculateTBI	(	ThreadContext *	tc,
		ExceptionLevel	el,
		uint64_t	ptr,
		bool	data )

Definition at line 50 of file pauth_helpers.cc.

References gem5::bits(), data, el, EL1, EL2, EL3, MISCREG_TCR_EL1, MISCREG_TCR_EL2, MISCREG_TCR_EL3, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), tbi, and upperAndLowerRange().

Referenced by addPAC(), auth(), and stripPAC().

canReadCoprocReg()

std::tuple< bool, bool > gem5::ArmISA::canReadCoprocReg	(	MiscRegIndex	reg,
		SCR	scr,
		CPSR	cpsr,
		ThreadContext *	tc )

Check for permission to read coprocessor registers.

Checks whether an instruction at the current program mode has permissions to read the coprocessor registers. This function returns whether the check is undefined and if not whether the read access is permitted.

Parameters

the	misc reg indicating the coprocessor
the	SCR
the	CPSR
the	thread context on the core

Returns

a tuple of booleans: can_read, undefined

Definition at line 566 of file misc.cc.

References AArch32isUndefinedGenericTimer(), lookUpMiscReg, MISCREG_BANKED, MISCREG_CNTFRQ, MISCREG_CNTVOFF, MISCREG_HYP_NS_RD, MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD, MISCREG_PRI_NS_RD, MISCREG_PRI_S_RD, MISCREG_USR_NS_RD, MISCREG_USR_S_RD, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and gem5::X86ISA::reg.

canWriteCoprocReg()

std::tuple< bool, bool > gem5::ArmISA::canWriteCoprocReg	(	MiscRegIndex	reg,
		SCR	scr,
		CPSR	cpsr,
		ThreadContext *	tc )

Check for permission to write coprocessor registers.

Checks whether an instruction at the current program mode has permissions to write the coprocessor registers. This function returns whether the check is undefined and if not whether the write access is permitted.

Parameters

the	misc reg indicating the coprocessor
the	SCR
the	CPSR
the	thread context on the core

Returns

a tuple of booleans: can_write, undefined

Definition at line 613 of file misc.cc.

References AArch32isUndefinedGenericTimer(), lookUpMiscReg, MISCREG_BANKED, MISCREG_CNTFRQ, MISCREG_CNTVOFF, MISCREG_HYP_NS_WR, MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR, MISCREG_PRI_NS_WR, MISCREG_PRI_S_WR, MISCREG_USR_NS_WR, MISCREG_USR_S_WR, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and gem5::X86ISA::reg.

checkFaultAccessAArch64SysReg()

Fault gem5::ArmISA::checkFaultAccessAArch64SysReg	(	MiscRegIndex	reg,
		CPSR	cpsr,
		ThreadContext *	tc,
		const MiscRegOp64 &	inst )

Definition at line 730 of file misc.cc.

References currEL(), lookUpMiscReg, and gem5::X86ISA::reg.

Referenced by gem5::MiscRegImplDefined64::execute().

cmp128()

static int gem5::ArmISA::cmp128 ( uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )

inlinestatic

Definition at line 213 of file fplib.cc.

References gem5::MipsISA::a0, a1, gem5::QARMA::b0, and gem5::QARMA::b1.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

computeAddrTop()

int gem5::ArmISA::computeAddrTop	(	ThreadContext *	tc,
		bool	selbit,
		bool	is_instr,
		TCR	tcr,
		ExceptionLevel	el )

Definition at line 412 of file utility.cc.

References el, EL1, EL2, EL3, ELIs32(), ELIsInHost(), HaveExt(), MISCREG_TCR_EL2, MISCREG_TCR_EL3, gem5::ThreadContext::readMiscReg(), s1TranslationRegime(), tbi, and tbid.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64(), purifyTaggedAddr(), and gem5::ArmISA::MMU::translateMmuOff().

condGenericTimerCommonEL0SystemAccessTrapEL2()

bool gem5::ArmISA::condGenericTimerCommonEL0SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 1044 of file utility.cc.

References MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTHCTL_EL2, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, MISCREG_CNTVCT_EL0, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerCommonEL0SystemAccessTrapEL2().

condGenericTimerCommonEL1SystemAccessTrapEL2()

bool gem5::ArmISA::condGenericTimerCommonEL1SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 1071 of file utility.cc.

References MISCREG_CNTHCTL_EL2, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, MISCREG_CNTVCT_EL0, MISCREG_HCR_EL2, MISCREG_ID_AA64MMFR0_EL1, gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by isGenericTimerPhysEL0SystemAccessTrapEL2(), isGenericTimerPhysEL1SystemAccessTrapEL2(), and isGenericTimerVirtSystemAccessTrapEL2().

condGenericTimerPhysEL1SystemAccessTrapEL2()

bool gem5::ArmISA::condGenericTimerPhysEL1SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 1105 of file utility.cc.

References MISCREG_CNTHCTL_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerPhysEL0SystemAccessTrapEL2(), and isGenericTimerPhysEL1SystemAccessTrapEL2().

condGenericTimerPhysHypTrap()

bool gem5::ArmISA::condGenericTimerPhysHypTrap	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 863 of file utility.cc.

References MISCREG_CNTHCTL_EL2, MISCREG_CNTP_CTL, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerPhysHypTrap().

condGenericTimerSystemAccessTrapEL1()

bool gem5::ArmISA::condGenericTimerSystemAccessTrapEL1	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 897 of file utility.cc.

References MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTKCTL_EL1, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, MISCREG_CNTVCT_EL0, and gem5::ThreadContext::readMiscReg().

Referenced by AArch32isUndefinedGenericTimer(), isGenericTimerCommonEL0HypTrap(), isGenericTimerCommonEL0SystemAccessTrapEL2(), and isGenericTimerSystemAccessTrapEL1().

couldBeSP()

static bool gem5::ArmISA::couldBeSP ( RegIndex reg )

inlinestatic

Definition at line 613 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::Spx, and gem5::ArmISA::int_reg::X31.

couldBeZero()

static bool gem5::ArmISA::couldBeZero ( RegIndex reg )

inlinestatic

Definition at line 625 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::X31, and gem5::ArmISA::int_reg::Zero.

currEL() [1/2]

ExceptionLevel gem5::ArmISA::currEL

(

const ThreadContext *

tc

)

Returns the current Exception Level (EL) of the provided ThreadContext.

Definition at line 133 of file utility.cc.

References MISCREG_CPSR, opModeToEL(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), checkFaultAccessAArch64SysReg(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::ArmISA::Interrupts::checkWfiWake(), gem5::Gicv3CPUInterface::currEL(), ELStateUsingAArch32K(), gem5::ArmISA::Interrupts::getISR(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), illegalExceptionReturn(), isAArch64AArch32SystemAccessTrapEL1(), isAArch64AArch32SystemAccessTrapEL2(), isBigEndian64(), gem5::ArmISA::SelfDebug::isDebugEnabled(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL2(), isGenericTimerSystemAccessTrapEL3(), isSecure(), isUnpriviledgeAccess(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::TLBIALL::operator()(), gem5::TlbiOp::performTlbi(), readMPIDR(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::SPAlignmentFault::routeToHyp(), gem5::ArmISA::SupervisorTrap::routeToHyp(), gem5::ArmISA::SelfDebug::setAArch32(), SPAlignmentCheckEnabled(), stripPAC(), gem5::ArmISA::Interrupts::takeInt32(), gem5::ArmISA::Interrupts::takeInt64(), gem5::ArmISA::Interrupts::takeVirtualInt32(), gem5::ArmISA::Interrupts::takeVirtualInt64(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::BrkPoint::testContextMatch(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::ArmISA::SelfDebug::testWatchPoints(), gem5::fastmodel::CortexA76TC::translateAddress(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::tranTypeEL(), trapPACUse(), and gem5::ArmISA::ArmStaticInst::trapWFx().

currEL() [2/2]

ExceptionLevel gem5::ArmISA::currEL ( CPSR cpsr )

inline

Definition at line 119 of file utility.hh.

References opModeToEL().

debugTargetFrom()

ExceptionLevel gem5::ArmISA::debugTargetFrom	(	ThreadContext *	tc,
		bool	secure )

Definition at line 102 of file utility.cc.

References EL1, EL2, EL3, gem5::ArmSystem::haveEL(), HaveExt(), gem5::ArmSystem::highestELIs64(), MISCREG_HCR_EL2, MISCREG_MDCR_EL2, gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by gem5::ArmISA::SoftwareStep::debugExceptionReturnSS(), and gem5::ArmISA::SelfDebug::targetAArch32().

decode_fp_data_type()

static FpDataType gem5::ArmISA::decode_fp_data_type ( uint8_t encoding )

inlinestatic

Definition at line 201 of file pred_inst.hh.

References encoding, Fp16, Fp32, Fp64, and panic.

decodeAArch64SysReg() [1/2]

MiscRegIndex gem5::ArmISA::decodeAArch64SysReg

(

const MiscRegNum64 &

sys_reg

)

Definition at line 2758 of file misc.cc.

References gem5::ArmISA::MiscRegNum64::crn, MISCREG_IMPDEF_UNIMPL, MISCREG_UNKNOWN, and gem5::ArmISA::MiscRegNum64::op0.

decodeAArch64SysReg() [2/2]

MiscRegIndex gem5::ArmISA::decodeAArch64SysReg	(	unsigned	op0,
		unsigned	op1,
		unsigned	crn,
		unsigned	crm,
		unsigned	op2 )

Definition at line 2749 of file misc.cc.

References decodeAArch64SysReg().

Referenced by decodeAArch64SysReg(), gem5::ArmV8KvmCPU::dump(), gem5::ArmV8KvmCPU::getSysRegMap(), and gem5::MiscRegImplDefined64::MiscRegImplDefined64().

decodeCP14Reg()

MiscRegIndex gem5::ArmISA::decodeCP14Reg	(	unsigned	crn,
		unsigned	opc1,
		unsigned	crm,
		unsigned	opc2 )

Definition at line 521 of file misc.cc.

References MISCREG_UNKNOWN, opc2, and warn.

Referenced by gem5::ArmKvmCPU::decodeCoProcReg().

decodeCP15Reg()

MiscRegIndex gem5::ArmISA::decodeCP15Reg	(	unsigned	crn,
		unsigned	opc1,
		unsigned	crm,
		unsigned	opc2 )

Definition at line 535 of file misc.cc.

References MISCREG_IMPDEF_UNIMPL, MISCREG_UNKNOWN, and opc2.

Referenced by gem5::ArmKvmCPU::decodeCoProcReg().

decodeCP15Reg64()

MiscRegIndex gem5::ArmISA::decodeCP15Reg64	(	unsigned	crm,
		unsigned	opc1 )

Definition at line 554 of file misc.cc.

References MISCREG_UNKNOWN.

decodeMrsMsrBankedIntRegIndex()

static int gem5::ArmISA::decodeMrsMsrBankedIntRegIndex ( uint8_t sysM, bool r )

inlinestatic

Definition at line 337 of file utility.hh.

References decodeMrsMsrBankedReg(), gem5::MipsISA::r, and gem5::ArmISA::int_reg::Zero.

decodeMrsMsrBankedReg()

bool gem5::ArmISA::decodeMrsMsrBankedReg	(	uint8_t	sysM,
		bool	r,
		bool &	isIntReg,
		int &	regIdx,
		CPSR	cpsr,
		SCR	scr,
		NSACR	nsacr,
		bool	checkSecurity )

Definition at line 1129 of file utility.cc.

References gem5::bits(), MISCREG_ELR_HYP, MISCREG_SPSR_ABT, MISCREG_SPSR_FIQ, MISCREG_SPSR_HYP, MISCREG_SPSR_IRQ, MISCREG_SPSR_MON, MISCREG_SPSR_SVC, MISCREG_SPSR_UND, mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, panic, gem5::MipsISA::r, and gem5::ArmISA::int_reg::regInMode().

Referenced by decodeMrsMsrBankedIntRegIndex().

decodePhysAddrRange64()

int gem5::ArmISA::decodePhysAddrRange64

(

uint8_t

pa_enc

)

Returns the n.

of PA bits corresponding to the specified encoding.

Definition at line 1288 of file utility.cc.

References panic.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64().

defaultFaultE2H_EL2()

static Fault gem5::ArmISA::defaultFaultE2H_EL2 ( const MiscRegLUTEntry & entry, ThreadContext * tc, const MiscRegOp64 & inst )

static

Definition at line 2806 of file misc.cc.

References MISCREG_HCR_EL2, gem5::NoFault, gem5::ThreadContext::readMiscRegNoEffect(), and gem5::ArmISA::ArmStaticInst::undefined().

defaultFaultE2H_EL3()

static Fault gem5::ArmISA::defaultFaultE2H_EL3 ( const MiscRegLUTEntry & entry, ThreadContext * tc, const MiscRegOp64 & inst )

static

Definition at line 2818 of file misc.cc.

References EL2Enabled(), MISCREG_HCR_EL2, gem5::NoFault, gem5::ThreadContext::readMiscRegNoEffect(), and gem5::ArmISA::ArmStaticInst::undefined().

EL2Enabled()

bool gem5::ArmISA::EL2Enabled

(

ThreadContext *

tc

)

Definition at line 267 of file utility.cc.

References EL2, EL3, gem5::ArmSystem::haveEL(), IsSecureEL2Enabled(), MISCREG_SCR_EL3, ns, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::ArmISA::Interrupts::checkWfiWake(), defaultFaultE2H_EL3(), fgtEnabled(), gem5::ArmISA::Interrupts::getISR(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL1(), isHcrxEL2Enabled(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::ArmFaultVals< T >::offset64(), gem5::ArmISA::DTLBIALL::operator()(), gem5::ArmISA::DTLBIASID::operator()(), gem5::ArmISA::ITLBIALL::operator()(), gem5::ArmISA::ITLBIASID::operator()(), gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::TLBIVMALL::operator()(), gem5::TlbiOp::performTlbi(), gem5::ArmISA::ISA::readMiscReg(), readMPIDR(), gem5::ArmISA::DataAbort::routeToHyp(), gem5::ArmISA::FastInterrupt::routeToHyp(), gem5::ArmISA::HardwareBreakpoint::routeToHyp(), gem5::ArmISA::IllegalInstSetStateFault::routeToHyp(), gem5::ArmISA::Interrupt::routeToHyp(), gem5::ArmISA::PCAlignmentFault::routeToHyp(), gem5::ArmISA::SoftwareBreakpoint::routeToHyp(), gem5::ArmISA::SoftwareStepFault::routeToHyp(), gem5::ArmISA::SPAlignmentFault::routeToHyp(), gem5::ArmISA::SupervisorCall::routeToHyp(), gem5::ArmISA::SupervisorTrap::routeToHyp(), gem5::ArmISA::SystemError::routeToHyp(), gem5::ArmISA::UndefinedInstruction::routeToHyp(), gem5::ArmISA::Watchpoint::routeToHyp(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), gem5::ArmISA::BrkPoint::test(), gem5::TlbiOp64::tlbiIpaS2(), gem5::TlbiOp64::tlbiRipaS2(), gem5::ArmISA::ArmStaticInst::trapWFx(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

ELIs32()

bool gem5::ArmISA::ELIs32	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 282 of file utility.cc.

References el, ELUsingAArch32K(), and panic_if.

Referenced by AArch32isUndefinedGenericTimer(), AArch64AArch32SystemAccessTrap(), computeAddrTop(), gem5::ArmISA::SoftwareStep::debugExceptionReturnSS(), ELIs64(), ELIsInHost(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), isGenericTimerCommonEL0HypTrap(), isGenericTimerCommonEL0SystemAccessTrapEL2(), isGenericTimerHypTrap(), isGenericTimerSystemAccessTrapEL1(), isGenericTimerVirtSystemAccessTrapEL2(), IsSecureEL2Enabled(), gem5::ArmISA::ArmFaultVals< T >::offset64(), gem5::ArmISA::ISA::readMiscReg(), s1TranslationRegime(), gem5::ArmISA::SelfDebug::setAArch32(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), and gem5::ArmISA::SelfDebug::targetAArch32().

ELIs64()

bool gem5::ArmISA::ELIs64	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 276 of file utility.cc.

References el, and ELIs32().

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::Stage2LookUp::getTe(), gem5::ArmISA::MMU::CachedState::getVMID(), illegalExceptionReturn(), gem5::ArmISA::ArmFault::update(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

ELIsInHost()

bool gem5::ArmISA::ELIsInHost	(	ThreadContext *	tc,
		ExceptionLevel	el )

Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions).

Definition at line 290 of file utility.cc.

References el, EL0, EL2, ELIs32(), gem5::ArmSystem::haveEL(), HaveExt(), isSecureBelowEL3(), IsSecureEL2Enabled(), MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), computeAddrTop(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), maskTaggedAddr(), gem5::ArmISA::ArmFaultVals< T >::offset64(), gem5::ArmISA::ISA::redirectRegVHE(), s1TranslationRegime(), gem5::ArmISA::BrkPoint::test(), and translationRegime().

ELStateUsingAArch32()

bool gem5::ArmISA::ELStateUsingAArch32	(	ThreadContext *	tc,
		ExceptionLevel	el,
		bool	secure )

Definition at line 374 of file utility.cc.

References el, ELStateUsingAArch32K(), and panic_if.

Referenced by gem5::ArmISA::SelfDebug::isDebugEnabledForEL32().

ELStateUsingAArch32K()

std::pair< bool, bool > gem5::ArmISA::ELStateUsingAArch32K	(	ThreadContext *	tc,
		ExceptionLevel	el,
		bool	secure )

Definition at line 322 of file utility.cc.

References currEL(), el, EL0, EL1, EL2, EL3, haveAArch32EL(), gem5::ArmSystem::haveEL(), HaveExt(), gem5::ArmSystem::highestEL(), gem5::ArmSystem::highestELIs64(), MISCREG_CPSR, MISCREG_HCR_EL2, MISCREG_SCR_EL3, panic_if, and gem5::ThreadContext::readMiscReg().

Referenced by ELStateUsingAArch32(), and ELUsingAArch32K().

ELUsingAArch32K()

std::pair< bool, bool > gem5::ArmISA::ELUsingAArch32K	(	ThreadContext *	tc,
		ExceptionLevel	el )

This function checks whether selected EL provided as an argument is using the AArch32 ISA.

This information might be unavailable at the current EL status: it hence returns a pair of boolean values: a first boolean, true if information is available (known), and a second one, true if EL is using AArch32, false for AArch64.

Parameters

tc	The thread context.
el	The target exception level.

Return values

known	is FALSE for EL0 if the current Exception level is not EL0 and EL1 is using AArch64, since it cannot determine the state of EL0; TRUE otherwise.
aarch32	is TRUE if the specified Exception level is using AArch32; FALSE otherwise.

Definition at line 301 of file utility.cc.

References el, ELStateUsingAArch32K(), and isSecureBelowEL3().

Referenced by ELIs32(), and illegalExceptionReturn().

encodeAArch64SysReg()

std::optional< MiscRegNum64 > gem5::ArmISA::encodeAArch64SysReg

(

MiscRegIndex

misc_reg

)

Definition at line 2775 of file misc.cc.

Referenced by gem5::ArmISA::SysDC64::iss(), gem5::MiscRegRegImmOp64::iss(), gem5::RegMiscRegImmOp64::iss(), gem5::KvmKernelGicV3::readCpu(), and gem5::KvmKernelGicV3::writeCpu().

encodePhysAddrRange64()

uint8_t gem5::ArmISA::encodePhysAddrRange64

(

int

pa_size

)

Returns the encoding corresponding to the specified n.

of PA bits.

Definition at line 1311 of file utility.cc.

References panic.

EndBitUnion() [1/63]

gem5::ArmISA::EndBitUnion

(

AA64DFR0

)

EndBitUnion() [2/63]

gem5::ArmISA::EndBitUnion

(

AA64ISAR0

)

EndBitUnion() [3/63]

gem5::ArmISA::EndBitUnion

(

AA64ISAR1

)

EndBitUnion() [4/63]

gem5::ArmISA::EndBitUnion

(

AA64MMFR0

)

EndBitUnion() [5/63]

gem5::ArmISA::EndBitUnion

(

AA64MMFR1

)

EndBitUnion() [6/63]

gem5::ArmISA::EndBitUnion

(

AA64MMFR2

)

EndBitUnion() [7/63]

gem5::ArmISA::EndBitUnion

(

AA64MMFR3

)

EndBitUnion() [8/63]

gem5::ArmISA::EndBitUnion

(

AA64PFR0

)

EndBitUnion() [9/63]

gem5::ArmISA::EndBitUnion

(

AA64PFR1

)

EndBitUnion() [10/63]

gem5::ArmISA::EndBitUnion

(

AA64SMFR0

)

EndBitUnion() [11/63]

gem5::ArmISA::EndBitUnion

(

AA64ZFR0

)

EndBitUnion() [12/63]

gem5::ArmISA::EndBitUnion

(

Affinity

)

Definition at line 210 of file types.hh.

EndBitUnion() [13/63]

gem5::ArmISA::EndBitUnion

(

CNTHCTL

)

EndBitUnion() [14/63]

gem5::ArmISA::EndBitUnion

(

CNTKCTL

)

EndBitUnion() [15/63]

gem5::ArmISA::EndBitUnion

(

CONTEXTIDR

)

EndBitUnion() [16/63]

gem5::ArmISA::EndBitUnion

(

CPACR

)

EndBitUnion() [17/63]

gem5::ArmISA::EndBitUnion

(

CPSR

)

EndBitUnion() [18/63]

gem5::ArmISA::EndBitUnion

(

CPTR

)

EndBitUnion() [19/63]

gem5::ArmISA::EndBitUnion

(

CTR

)

EndBitUnion() [20/63]

gem5::ArmISA::EndBitUnion

(

DBGBCR

)

EndBitUnion() [21/63]

gem5::ArmISA::EndBitUnion

(

DBGDS32

)

EndBitUnion() [22/63]

gem5::ArmISA::EndBitUnion

(

DBGVCR

)

EndBitUnion() [23/63]

gem5::ArmISA::EndBitUnion

(

DBGWCR

)

EndBitUnion() [24/63]

gem5::ArmISA::EndBitUnion

(

DEVID

)

EndBitUnion() [25/63]

gem5::ArmISA::EndBitUnion

(

ExtMachInst

)

EndBitUnion() [26/63]

gem5::ArmISA::EndBitUnion

(

FPEXC

)

EndBitUnion() [27/63]

gem5::ArmISA::EndBitUnion

(

FPSCR

)

EndBitUnion() [28/63]

gem5::ArmISA::EndBitUnion

(

FSR

)

EndBitUnion() [29/63]

gem5::ArmISA::EndBitUnion

(

HCPTR

)

EndBitUnion() [30/63]

gem5::ArmISA::EndBitUnion

(

HCR

)

EndBitUnion() [31/63]

gem5::ArmISA::EndBitUnion

(

HCRX

)

EndBitUnion() [32/63]

gem5::ArmISA::EndBitUnion

(

HDCR

)

EndBitUnion() [33/63]

gem5::ArmISA::EndBitUnion

(

HDFGTR

)

EndBitUnion() [34/63]

gem5::ArmISA::EndBitUnion

(

HFGITR

)

EndBitUnion() [35/63]

gem5::ArmISA::EndBitUnion

(

HFGTR

)

EndBitUnion() [36/63]

gem5::ArmISA::EndBitUnion

(

HSTR

)

EndBitUnion() [37/63]

gem5::ArmISA::EndBitUnion

(

HTCR

)

EndBitUnion() [38/63]

gem5::ArmISA::EndBitUnion

(

ISAR5

)

EndBitUnion() [39/63]

gem5::ArmISA::EndBitUnion

(

ISAR6

)

EndBitUnion() [40/63]

gem5::ArmISA::EndBitUnion

(

ISR

)

EndBitUnion() [41/63]

gem5::ArmISA::EndBitUnion

(

L2CTLR

)

EndBitUnion() [42/63]

gem5::ArmISA::EndBitUnion

(

MPAM

)

EndBitUnion() [43/63]

gem5::ArmISA::EndBitUnion

(

MPAMIDR

)

EndBitUnion() [44/63]

gem5::ArmISA::EndBitUnion

(

MVFR0

)

EndBitUnion() [45/63]

gem5::ArmISA::EndBitUnion

(

MVFR1

)

EndBitUnion() [46/63]

gem5::ArmISA::EndBitUnion

(

NMRR

)

EndBitUnion() [47/63]

gem5::ArmISA::EndBitUnion

(

NSACR

)

EndBitUnion() [48/63]

gem5::ArmISA::EndBitUnion

(

OperatingMode64

)

Definition at line 378 of file types.hh.

References mode.

EndBitUnion() [49/63]

gem5::ArmISA::EndBitUnion

(

OSL

)

EndBitUnion() [50/63]

gem5::ArmISA::EndBitUnion

(

PackedIntReg

)

Definition at line 65 of file int.hh.

EndBitUnion() [51/63]

gem5::ArmISA::EndBitUnion

(

PAR

)

EndBitUnion() [52/63]

gem5::ArmISA::EndBitUnion

(

PMSELR

)

EndBitUnion() [53/63]

gem5::ArmISA::EndBitUnion

(

PRRR

)

EndBitUnion() [54/63]

gem5::ArmISA::EndBitUnion

(

SCR

)

EndBitUnion() [55/63]

gem5::ArmISA::EndBitUnion

(

SCTLR

)

EndBitUnion() [56/63]

gem5::ArmISA::EndBitUnion

(

SMCR

)

EndBitUnion() [57/63]

gem5::ArmISA::EndBitUnion

(

SMIDR

)

EndBitUnion() [58/63]

gem5::ArmISA::EndBitUnion

(

SMPRI

)

EndBitUnion() [59/63]

gem5::ArmISA::EndBitUnion

(

SVCR

)

EndBitUnion() [60/63]

gem5::ArmISA::EndBitUnion

(

TCR

)

EndBitUnion() [61/63]

gem5::ArmISA::EndBitUnion

(

TTBCR

)

EndBitUnion() [62/63]

gem5::ArmISA::EndBitUnion

(

VTCR_t

)

EndBitUnion() [63/63]

gem5::ArmISA::EndBitUnion

(

ZCR

)

EndSubBitUnion() [1/9]

gem5::ArmISA::EndSubBitUnion

(

cond_iss

)

EndSubBitUnion() [2/9]

gem5::ArmISA::EndSubBitUnion

(

data_abort_iss

)

EndSubBitUnion() [3/9]

gem5::ArmISA::EndSubBitUnion

(

el1

)

EndSubBitUnion() [4/9]

gem5::ArmISA::EndSubBitUnion

(

el2

)

EndSubBitUnion() [5/9]

gem5::ArmISA::EndSubBitUnion

(

el3

)

EndSubBitUnion() [6/9]

gem5::ArmISA::EndSubBitUnion

(

instruction_abort_iss

)

EndSubBitUnion() [7/9]

gem5::ArmISA::EndSubBitUnion

(

puswl

)

EndSubBitUnion() [8/9]

gem5::ArmISA::EndSubBitUnion

(

software_step_iss

)

EndSubBitUnion() [9/9]

gem5::ArmISA::EndSubBitUnion

(

watchpoint_iss

)

fgtEnabled()

bool gem5::ArmISA::fgtEnabled

(

ThreadContext *

tc

)

Definition at line 1360 of file utility.cc.

References EL2Enabled(), EL3, fgten, gem5::ArmSystem::haveEL(), HaveExt(), MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscReg().

finishVfp()

void gem5::ArmISA::finishVfp	(	FPSCR &	fpscr,
		VfpSavedState	state,
		bool	flush,
		FPSCR	mask )

Definition at line 205 of file vfp.cc.

References FeAllExceptions, FeDivByZero, FeInexact, FeInvalid, FeOverflow, FeUnderflow, finishVfp(), mask, and state.

Referenced by gem5::ArmISA::FpOp::binaryOp(), finishVfp(), gem5::ArmISA::FpOp::ternaryOp(), and gem5::ArmISA::FpOp::unaryOp().

fixDest() [1/4]

template<class fpType >

fpType gem5::ArmISA::fixDest	(	bool	flush,
		bool	defaultNan,
		fpType	val,
		fpType	op1 )

Definition at line 231 of file vfp.cc.

References FeInexact, FeUnderflow, fixDest(), std::isnan(), and gem5::X86ISA::val.

Referenced by fixDest(), fixDest(), fixDivDest(), fixFpDFpSDest(), and fixFpSFpDDest().

fixDest() [2/4]

template<class fpType >

fpType gem5::ArmISA::fixDest	(	bool	flush,
		bool	defaultNan,
		fpType	val,
		fpType	op1,
		fpType	op2 )

Definition at line 261 of file vfp.cc.

References FeInexact, FeUnderflow, fixDest(), std::isnan(), and gem5::X86ISA::val.

fixDest() [3/4]

template<class fpType >

fpType gem5::ArmISA::fixDest	(	FPSCR	fpscr,
		fpType	val,
		fpType	op1 )

fixDest() [4/4]

template<class fpType >

fpType gem5::ArmISA::fixDest	(	FPSCR	fpscr,
		fpType	val,
		fpType	op1,
		fpType	op2 )

fixDest< double >() [1/2]

template double gem5::ArmISA::fixDest< double >	(	bool	flush,
		bool	defaultNan,
		double	val,
		double	op1 )

fixDest< double >() [2/2]

template double gem5::ArmISA::fixDest< double >	(	bool	flush,
		bool	defaultNan,
		double	val,
		double	op1,
		double	op2 )

fixDest< float >() [1/2]

template float gem5::ArmISA::fixDest< float >	(	bool	flush,
		bool	defaultNan,
		float	val,
		float	op1 )

fixDest< float >() [2/2]

template float gem5::ArmISA::fixDest< float >	(	bool	flush,
		bool	defaultNan,
		float	val,
		float	op1,
		float	op2 )

fixDivDest() [1/2]

template<class fpType >

fpType gem5::ArmISA::fixDivDest	(	bool	flush,
		bool	defaultNan,
		fpType	val,
		fpType	op1,
		fpType	op2 )

Definition at line 302 of file vfp.cc.

References FeInexact, FeRoundZero, FeUnderflow, fixDest(), fixDivDest(), flushToZero, and gem5::X86ISA::val.

Referenced by fixDivDest(), vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), and vfpUFixedToFpS().

fixDivDest() [2/2]

template<class fpType >

fpType gem5::ArmISA::fixDivDest	(	FPSCR	fpscr,
		fpType	val,
		fpType	op1,
		fpType	op2 )

fixDivDest< double >()

template double gem5::ArmISA::fixDivDest< double >	(	bool	flush,
		bool	defaultNan,
		double	val,
		double	op1,
		double	op2 )

fixDivDest< float >()

template float gem5::ArmISA::fixDivDest< float >	(	bool	flush,
		bool	defaultNan,
		float	val,
		float	op1,
		float	op2 )

fixFpDFpSDest()

float gem5::ArmISA::fixFpDFpSDest	(	FPSCR	fpscr,
		double	val )

Definition at line 337 of file vfp.cc.

References gem5::bits(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), fixFpDFpSDest(), flushToZero, std::isnan(), mask, and gem5::X86ISA::val.

Referenced by fixFpDFpSDest().

fixFpSFpDDest()

double gem5::ArmISA::fixFpSFpDDest	(	FPSCR	fpscr,
		float	val )

Definition at line 373 of file vfp.cc.

References gem5::bits(), FeInexact, FeRoundZero, FeUnderflow, fixDest(), fixFpSFpDDest(), flushToZero, std::isnan(), mask, and gem5::X86ISA::val.

Referenced by fixFpSFpDDest().

flattenIntRegModeIndex()

static const RegId & gem5::ArmISA::flattenIntRegModeIndex ( int reg )

inlinestatic

Definition at line 575 of file int.hh.

References gem5::ArmISA::int_reg::abt(), gem5::curTick(), gem5::ArmISA::int_reg::fiq(), gem5::ArmISA::int_reg::hyp(), gem5::ArmISA::int_reg::irq(), mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, gem5::ArmISA::int_reg::mon(), panic, gem5::X86ISA::reg, gem5::ArmISA::int_reg::regsPerMode, gem5::ArmISA::int_reg::svc(), gem5::ArmISA::int_reg::und(), and gem5::ArmISA::int_reg::usr().

Referenced by gem5::ArmISA::IntRegClassOps::flatten().

flushToZero() [1/2]

template<class fpType >

static bool gem5::ArmISA::flushToZero ( fpType & op )

inlinestatic

Definition at line 122 of file vfp.hh.

References bitsToFp(), fpToBits(), and gem5::X86ISA::op.

flushToZero() [2/2]

template<class fpType >

static bool gem5::ArmISA::flushToZero ( fpType & op1, fpType & op2 )

inlinestatic

Definition at line 135 of file vfp.hh.

References flushToZero.

fp128_normalise()

static void gem5::ArmISA::fp128_normalise ( uint64_t * mnt0, uint64_t * mnt1, int * exp )

inlinestatic

Definition at line 273 of file fplib.cc.

References shift.

Referenced by fp64_mul(), and fp64_muladd().

fp16_add()

static uint16_t gem5::ArmISA::fp16_add ( uint16_t a, uint16_t b, int neg, int mode, int * flags )

static

Definition at line 1223 of file fplib.cc.

References a, b, flags, fp16_defaultNaN(), FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_normalise(), fp16_process_NaNs(), fp16_round(), fp16_unpack(), fp16_zero(), FPLIB_IOC, lsl16(), lsr16(), mode, and gem5::RiscvISA::x.

Referenced by fplibAdd(), and fplibSub().

fp16_compare_eq()

static int gem5::ArmISA::fp16_compare_eq ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 959 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

fp16_compare_ge()

static int gem5::ArmISA::fp16_compare_ge ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 978 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

fp16_compare_gt()

static int gem5::ArmISA::fp16_compare_gt ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 1003 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

fp16_compare_un()

static int gem5::ArmISA::fp16_compare_un ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 1028 of file fplib.cc.

References a, b, flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

fp16_cvtf()

static uint16_t gem5::ArmISA::fp16_cvtf ( uint64_t a, int fbits, int u, int mode, int * flags )

static

Definition at line 4908 of file fplib.cc.

References a, flags, FP16_BITS, FP16_EXP_BIAS, fp16_round(), fp16_zero(), FP64_BITS, fp64_normalise(), mode, and u.

Referenced by fplibFixedToFP().

fp16_defaultNaN()

static uint16_t gem5::ArmISA::fp16_defaultNaN ( )

inlinestatic

Definition at line 374 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, and fp16_pack().

Referenced by fp16_add(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_sqrt(), fplibConvert(), fplibConvert(), fplibDefaultNaN(), and fplibRSqrtEstimate().

fp16_div()

static uint16_t gem5::ArmISA::fp16_div ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 1776 of file fplib.cc.

References a, b, flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), FP16_MANT_BITS, fp16_normalise(), fp16_process_NaNs(), fp16_round(), fp16_unpack(), fp16_zero(), fp32_normalise(), FPLIB_DZC, FPLIB_IOC, mode, and gem5::RiscvISA::x.

Referenced by fplibDiv().

fp16_FPConvertNaN_32()

static uint16_t gem5::ArmISA::fp16_FPConvertNaN_32 ( uint32_t op )

static

Definition at line 2524 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, fp16_pack(), FP32_BITS, FP32_MANT_BITS, and gem5::X86ISA::op.

Referenced by fplibConvert().

fp16_FPConvertNaN_64()

static uint16_t gem5::ArmISA::fp16_FPConvertNaN_64 ( uint64_t op )

static

Definition at line 2532 of file fplib.cc.

References FP16_EXP_INF, FP16_MANT_BITS, fp16_pack(), FP64_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

Referenced by fplibConvert().

fp16_FPOnePointFive()

static uint16_t gem5::ArmISA::fp16_FPOnePointFive ( int sgn )

static

Definition at line 2572 of file fplib.cc.

References FP16_EXP_BIAS, FP16_MANT_BITS, and fp16_pack().

Referenced by fplibRSqrtStepFused().

fp16_FPThree()

static uint16_t gem5::ArmISA::fp16_FPThree ( int sgn )

static

Definition at line 2590 of file fplib.cc.

References FP16_EXP_BIAS, FP16_MANT_BITS, and fp16_pack().

Referenced by fplibRSqrtStepFused().

fp16_FPTwo()

static uint16_t gem5::ArmISA::fp16_FPTwo ( int sgn )

static

Definition at line 2608 of file fplib.cc.

References FP16_EXP_BIAS, and fp16_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

fp16_infinity()

static uint16_t gem5::ArmISA::fp16_infinity ( int sgn )

inlinestatic

Definition at line 356 of file fplib.cc.

References FP16_EXP_INF, and fp16_pack().

Referenced by fp16_add(), fp16_div(), fp16_minmaxnum(), fp16_mul(), fp16_muladd(), fp16_round_(), fp16_scale(), fp16_sqrt(), fplibConvert(), fplibConvert(), fplibInfinity(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

fp16_is_infinity()

static int gem5::ArmISA::fp16_is_infinity ( int exp, uint16_t mnt )

inlinestatic

Definition at line 517 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT.

Referenced by fp16_muladd().

fp16_is_NaN()

static int gem5::ArmISA::fp16_is_NaN ( int exp, uint16_t mnt )

inlinestatic

Definition at line 463 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT.

Referenced by fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_is_signalling_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibTrigSMul().

fp16_is_quiet_NaN()

static int gem5::ArmISA::fp16_is_quiet_NaN ( int exp, uint16_t mnt )

inlinestatic

Definition at line 499 of file fplib.cc.

References FP16_EXP_INF, and FP16_MANT_BITS.

Referenced by fp16_muladd().

fp16_is_signalling_NaN()

static int gem5::ArmISA::fp16_is_signalling_NaN ( int exp, uint16_t mnt )

inlinestatic

Definition at line 481 of file fplib.cc.

References fp16_is_NaN(), and FP16_MANT_BITS.

Referenced by fp16_compare_eq(), fp16_compare_un(), fp16_process_NaNs(), fp16_process_NaNs3(), and fplibCompare().

fp16_max_normal()

static uint16_t gem5::ArmISA::fp16_max_normal ( int sgn )

inlinestatic

Definition at line 338 of file fplib.cc.

References FP16_EXP_INF, and fp16_pack().

Referenced by fp16_round_(), and fplibRecipEstimate().

fp16_minmaxnum()

static void gem5::ArmISA::fp16_minmaxnum ( uint16_t * op1, uint16_t * op2, int sgn )

static

Definition at line 3145 of file fplib.cc.

References fp16_infinity(), and FP16_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

fp16_mul()

static uint16_t gem5::ArmISA::fp16_mul ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 1403 of file fplib.cc.

References a, b, flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_process_NaNs(), fp16_round(), fp16_unpack(), fp16_zero(), fp32_normalise(), FPLIB_IOC, lsl32(), lsr32(), mode, and gem5::RiscvISA::x.

Referenced by fplibMul(), fplibMulX(), and fplibTrigSMul().

fp16_muladd()

static uint16_t gem5::ArmISA::fp16_muladd ( uint16_t a, uint16_t b, uint16_t c, int scale, int mode, int * flags )

static

Definition at line 1514 of file fplib.cc.

References a, b, c, flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_infinity(), fp16_is_quiet_NaN(), FP16_MANT_BITS, fp16_process_NaNs3(), fp16_round(), fp16_unpack(), fp16_zero(), fp32_normalise(), FPLIB_IOC, lsl32(), lsr32(), mode, gem5::X86ISA::scale, and gem5::RiscvISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), fplibRSqrtStepFused(), and fplibTrigMulAdd().

fp16_normalise()

static uint16_t gem5::ArmISA::fp16_normalise ( uint16_t mnt, int * exp )

inlinestatic

Definition at line 219 of file fplib.cc.

References shift.

Referenced by fp16_add(), fp16_div(), fp16_scale(), fp16_sqrt(), fplibConvert(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

fp16_pack()

static uint16_t gem5::ArmISA::fp16_pack ( uint16_t sgn, uint16_t exp, uint16_t mnt )

inlinestatic

Definition at line 302 of file fplib.cc.

References FP16_BITS, FP16_MANT, and FP16_MANT_BITS.

Referenced by fp16_defaultNaN(), fp16_FPConvertNaN_32(), fp16_FPConvertNaN_64(), fp16_FPOnePointFive(), fp16_FPThree(), fp16_FPTwo(), fp16_infinity(), fp16_max_normal(), fp16_repack(), fp16_round_(), fp16_zero(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

fp16_process_NaN()

static uint16_t gem5::ArmISA::fp16_process_NaN ( uint16_t a, int mode, int * flags )

inlinestatic

Definition at line 535 of file fplib.cc.

References a, flags, fp16_defaultNaN(), FP16_MANT_BITS, FPLIB_DN, FPLIB_IOC, and mode.

Referenced by fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

fp16_process_NaNs()

static uint16_t gem5::ArmISA::fp16_process_NaNs ( uint16_t a, uint16_t b, int mode, int * flags )

static

Definition at line 565 of file fplib.cc.

References a, b, flags, FP16_EXP, fp16_is_NaN(), fp16_is_signalling_NaN(), FP16_MANT, fp16_process_NaN(), and mode.

Referenced by fp16_add(), fp16_div(), fp16_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

fp16_process_NaNs3()

static uint16_t gem5::ArmISA::fp16_process_NaNs3 ( uint16_t a, uint16_t b, uint16_t c, int mode, int * flags )

static

Definition at line 634 of file fplib.cc.

References a, b, c, flags, FP16_EXP, fp16_is_NaN(), fp16_is_signalling_NaN(), FP16_MANT, fp16_process_NaN(), and mode.

Referenced by fp16_muladd().

fp16_repack()

static uint16_t gem5::ArmISA::fp16_repack ( int sgn, int exp, uint16_t mnt )

static

Definition at line 3127 of file fplib.cc.

References FP16_MANT_BITS, and fp16_pack().

Referenced by fplibMax(), and fplibMin().

fp16_round()

static uint16_t gem5::ArmISA::fp16_round ( int sgn, int exp, uint16_t mnt, int mode, int * flags )

static

Definition at line 799 of file fplib.cc.

References flags, fp16_round_(), and mode.

Referenced by fp16_add(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_scale(), and fp16_sqrt().

fp16_round_()

static uint16_t gem5::ArmISA::fp16_round_ ( int sgn, int exp, uint16_t mnt, int rm, int mode, int * flags )

static

Definition at line 721 of file fplib.cc.

References error, flags, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), FP16_MANT_BITS, fp16_max_normal(), fp16_pack(), fp16_zero(), FPLIB_AHP, FPLIB_FZ16, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl16(), lsr16(), mode, and rm.

Referenced by fp16_round(), fplibConvert(), and fplibConvert().

fp16_scale()

static uint16_t gem5::ArmISA::fp16_scale ( uint16_t a, int16_t b, int mode, int * flags )

static

Definition at line 1938 of file fplib.cc.

References a, b, flags, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), fp16_normalise(), fp16_process_NaN(), fp16_round(), fp16_unpack(), fp16_zero(), and mode.

Referenced by fplibScale().

fp16_sqrt()

static uint16_t gem5::ArmISA::fp16_sqrt ( uint16_t a, int mode, int * flags )

static

Definition at line 2040 of file fplib.cc.

References a, flags, fp16_defaultNaN(), FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), fp16_normalise(), fp16_process_NaN(), fp16_round(), fp16_unpack(), fp16_zero(), FPLIB_IOC, mode, t0, t1, and gem5::RiscvISA::x.

Referenced by fplibSqrt().

fp16_unpack()

static void gem5::ArmISA::fp16_unpack ( int * sgn, int * exp, uint16_t * mnt, uint16_t x, int mode, int * flags )

inlinestatic

Definition at line 392 of file fplib.cc.

References FP16_BITS, FP16_EXP, FP16_MANT, FP16_MANT_BITS, FPLIB_FZ16, mode, and gem5::RiscvISA::x.

Referenced by fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_scale(), fp16_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), and fplibTrigSMul().

fp16_zero()

static uint16_t gem5::ArmISA::fp16_zero ( int sgn )

inlinestatic

Definition at line 320 of file fplib.cc.

References fp16_pack().

Referenced by fp16_add(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_round_(), fp16_scale(), fp16_sqrt(), fplibConvert(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

fp32_add()

static uint32_t gem5::ArmISA::fp32_add ( uint32_t a, uint32_t b, int neg, int mode, int * flags )

static

Definition at line 1283 of file fplib.cc.

References a, b, flags, fp32_defaultNaN(), FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_normalise(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), FPLIB_IOC, lsl32(), lsr32(), mode, and gem5::RiscvISA::x.

Referenced by fplibAdd(), and fplibSub().

fp32_compare_eq()

static int gem5::ArmISA::fp32_compare_eq ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 1047 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

fp32_compare_ge()

static int gem5::ArmISA::fp32_compare_ge ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 1066 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

fp32_compare_gt()

static int gem5::ArmISA::fp32_compare_gt ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 1091 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

fp32_compare_un()

static int gem5::ArmISA::fp32_compare_un ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 1116 of file fplib.cc.

References a, b, flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

fp32_cvtf()

static uint32_t gem5::ArmISA::fp32_cvtf ( uint64_t a, int fbits, int u, int mode, int * flags )

static

Definition at line 4928 of file fplib.cc.

References a, flags, FP32_BITS, FP32_EXP_BIAS, fp32_round(), fp32_zero(), FP64_BITS, fp64_normalise(), mode, and u.

Referenced by fplibFixedToFP().

fp32_defaultNaN()

static uint32_t gem5::ArmISA::fp32_defaultNaN ( )

inlinestatic

Definition at line 380 of file fplib.cc.

References FP32_EXP_INF, FP32_MANT_BITS, and fp32_pack().

Referenced by fp32_add(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_sqrt(), fplibConvert(), fplibConvert(), fplibDefaultNaN(), and fplibRSqrtEstimate().

fp32_div()

static uint32_t gem5::ArmISA::fp32_div ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 1818 of file fplib.cc.

References a, b, flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), FP32_MANT_BITS, fp32_normalise(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_DZC, FPLIB_IOC, mode, and gem5::RiscvISA::x.

Referenced by fplibDiv().

fp32_FPConvertNaN_16()

static uint32_t gem5::ArmISA::fp32_FPConvertNaN_16 ( uint16_t op )

static

Definition at line 2540 of file fplib.cc.

References FP16_BITS, FP16_MANT_BITS, FP32_EXP_INF, FP32_MANT_BITS, fp32_pack(), and gem5::X86ISA::op.

Referenced by fplibConvert().

fp32_FPConvertNaN_64()

static uint32_t gem5::ArmISA::fp32_FPConvertNaN_64 ( uint64_t op )

static

Definition at line 2548 of file fplib.cc.

References FP32_EXP_INF, FP32_MANT_BITS, fp32_pack(), FP64_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

Referenced by fplibConvert().

fp32_FPOnePointFive()

static uint32_t gem5::ArmISA::fp32_FPOnePointFive ( int sgn )

static

Definition at line 2578 of file fplib.cc.

References FP32_EXP_BIAS, FP32_MANT_BITS, and fp32_pack().

Referenced by fplibRSqrtStepFused().

fp32_FPThree()

static uint32_t gem5::ArmISA::fp32_FPThree ( int sgn )

static

Definition at line 2596 of file fplib.cc.

References FP32_EXP_BIAS, FP32_MANT_BITS, and fp32_pack().

Referenced by fplibRSqrtStepFused().

fp32_FPTwo()

static uint32_t gem5::ArmISA::fp32_FPTwo ( int sgn )

static

Definition at line 2614 of file fplib.cc.

References FP32_EXP_BIAS, and fp32_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

fp32_infinity()

static uint32_t gem5::ArmISA::fp32_infinity ( int sgn )

inlinestatic

Definition at line 362 of file fplib.cc.

References FP32_EXP_INF, and fp32_pack().

Referenced by fp32_add(), fp32_div(), fp32_minmaxnum(), fp32_mul(), fp32_muladd(), fp32_round_(), fp32_scale(), fp32_sqrt(), fplibConvert(), fplibConvert(), fplibInfinity(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

fp32_is_infinity()

static int gem5::ArmISA::fp32_is_infinity ( int exp, uint32_t mnt )

inlinestatic

Definition at line 523 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT.

Referenced by fp32_muladd().

fp32_is_NaN()

static int gem5::ArmISA::fp32_is_NaN ( int exp, uint32_t mnt )

inlinestatic

Definition at line 469 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT.

Referenced by fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_is_signalling_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibTrigSMul().

fp32_is_quiet_NaN()

static int gem5::ArmISA::fp32_is_quiet_NaN ( int exp, uint32_t mnt )

inlinestatic

Definition at line 505 of file fplib.cc.

References FP32_EXP_INF, and FP32_MANT_BITS.

Referenced by fp32_muladd().

fp32_is_signalling_NaN()

static int gem5::ArmISA::fp32_is_signalling_NaN ( int exp, uint32_t mnt )

inlinestatic

Definition at line 487 of file fplib.cc.

References fp32_is_NaN(), and FP32_MANT_BITS.

Referenced by fp32_compare_eq(), fp32_compare_un(), fp32_process_NaNs(), fp32_process_NaNs3(), and fplibCompare().

fp32_max_normal()

static uint32_t gem5::ArmISA::fp32_max_normal ( int sgn )

inlinestatic

Definition at line 344 of file fplib.cc.

References FP32_EXP_INF, and fp32_pack().

Referenced by fp32_round_(), and fplibRecipEstimate().

fp32_minmaxnum()

static void gem5::ArmISA::fp32_minmaxnum ( uint32_t * op1, uint32_t * op2, int sgn )

static

Definition at line 3157 of file fplib.cc.

References fp32_infinity(), and FP32_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

fp32_mul()

static uint32_t gem5::ArmISA::fp32_mul ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 1440 of file fplib.cc.

References a, b, flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_process_NaNs(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_IOC, lsl64(), lsr64(), mode, and gem5::RiscvISA::x.

Referenced by fplibMul(), fplibMulX(), and fplibTrigSMul().

fp32_muladd()

static uint32_t gem5::ArmISA::fp32_muladd ( uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int * flags )

static

Definition at line 1599 of file fplib.cc.

References a, b, c, flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_infinity(), fp32_is_quiet_NaN(), FP32_MANT_BITS, fp32_process_NaNs3(), fp32_round(), fp32_unpack(), fp32_zero(), fp64_normalise(), FPLIB_IOC, lsl64(), lsr64(), mode, gem5::X86ISA::scale, and gem5::RiscvISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), fplibRSqrtStepFused(), and fplibTrigMulAdd().

fp32_normalise()

static uint32_t gem5::ArmISA::fp32_normalise ( uint32_t mnt, int * exp )

inlinestatic

Definition at line 237 of file fplib.cc.

References shift.

Referenced by fp16_div(), fp16_mul(), fp16_muladd(), fp32_add(), fp32_div(), fp32_scale(), fp32_sqrt(), fplibConvert(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

fp32_pack()

static uint32_t gem5::ArmISA::fp32_pack ( uint32_t sgn, uint32_t exp, uint32_t mnt )

inlinestatic

Definition at line 308 of file fplib.cc.

References FP32_BITS, FP32_MANT, and FP32_MANT_BITS.

Referenced by fp32_defaultNaN(), fp32_FPConvertNaN_16(), fp32_FPConvertNaN_64(), fp32_FPOnePointFive(), fp32_FPThree(), fp32_FPTwo(), fp32_infinity(), fp32_max_normal(), fp32_repack(), fp32_round_(), fp32_zero(), fplibConvert(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

fp32_process_NaN()

static uint32_t gem5::ArmISA::fp32_process_NaN ( uint32_t a, int mode, int * flags )

inlinestatic

Definition at line 545 of file fplib.cc.

References a, flags, fp32_defaultNaN(), FP32_MANT_BITS, FPLIB_DN, FPLIB_IOC, and mode.

Referenced by fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

fp32_process_NaNs()

static uint32_t gem5::ArmISA::fp32_process_NaNs ( uint32_t a, uint32_t b, int mode, int * flags )

static

Definition at line 588 of file fplib.cc.

References a, b, flags, FP32_EXP, fp32_is_NaN(), fp32_is_signalling_NaN(), FP32_MANT, fp32_process_NaN(), and mode.

Referenced by fp32_add(), fp32_div(), fp32_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

fp32_process_NaNs3()

static uint32_t gem5::ArmISA::fp32_process_NaNs3 ( uint32_t a, uint32_t b, uint32_t c, int mode, int * flags )

static

Definition at line 663 of file fplib.cc.

References a, b, c, flags, FP32_EXP, fp32_is_NaN(), fp32_is_signalling_NaN(), FP32_MANT, fp32_process_NaN(), and mode.

Referenced by fp32_muladd().

fp32_repack()

static uint32_t gem5::ArmISA::fp32_repack ( int sgn, int exp, uint32_t mnt )

static

Definition at line 3133 of file fplib.cc.

References FP32_MANT_BITS, and fp32_pack().

Referenced by fplibMax(), and fplibMin().

fp32_round()

static uint32_t gem5::ArmISA::fp32_round ( int sgn, int exp, uint32_t mnt, int mode, int * flags )

static

Definition at line 876 of file fplib.cc.

References flags, fp32_round_(), and mode.

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_scale(), and fp32_sqrt().

fp32_round_()

static uint32_t gem5::ArmISA::fp32_round_ ( int sgn, int exp, uint32_t mnt, int rm, int mode, int * flags )

static

Definition at line 805 of file fplib.cc.

References error, flags, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), FP32_MANT_BITS, fp32_max_normal(), fp32_pack(), fp32_zero(), FPLIB_FZ, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl32(), lsr32(), mode, and rm.

Referenced by fp32_round(), and fplibConvert().

fp32_scale()

static uint32_t gem5::ArmISA::fp32_scale ( uint32_t a, int32_t b, int mode, int * flags )

static

Definition at line 1972 of file fplib.cc.

References a, b, flags, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), fp32_normalise(), fp32_process_NaN(), fp32_round(), fp32_unpack(), fp32_zero(), and mode.

Referenced by fplibScale().

fp32_sqrt()

static uint32_t gem5::ArmISA::fp32_sqrt ( uint32_t a, int mode, int * flags )

static

Definition at line 2092 of file fplib.cc.

References a, flags, fp32_defaultNaN(), FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), fp32_normalise(), fp32_process_NaN(), fp32_round(), fp32_unpack(), fp32_zero(), FPLIB_IOC, mode, t0, t1, and gem5::RiscvISA::x.

Referenced by fplibSqrt().

fp32_unpack()

static void gem5::ArmISA::fp32_unpack ( int * sgn, int * exp, uint32_t * mnt, uint32_t x, int mode, int * flags )

inlinestatic

Definition at line 415 of file fplib.cc.

References flags, FP32_BITS, FP32_EXP, FP32_MANT, FP32_MANT_BITS, FPLIB_FZ, FPLIB_IDC, mode, and gem5::RiscvISA::x.

Referenced by fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_scale(), fp32_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), and fplibTrigSMul().

fp32_zero()

static uint32_t gem5::ArmISA::fp32_zero ( int sgn )

inlinestatic

Definition at line 326 of file fplib.cc.

References fp32_pack().

Referenced by fp32_add(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_round_(), fp32_scale(), fp32_sqrt(), fplibConvert(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtEstimate().

fp64_add()

static uint64_t gem5::ArmISA::fp64_add ( uint64_t a, uint64_t b, int neg, int mode, int * flags )

static

Definition at line 1343 of file fplib.cc.

References a, b, flags, fp64_defaultNaN(), FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_normalise(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl64(), lsr64(), mode, and gem5::RiscvISA::x.

Referenced by fplibAdd(), and fplibSub().

fp64_compare_eq()

static int gem5::ArmISA::fp64_compare_eq ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 1135 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareEQ().

fp64_compare_ge()

static int gem5::ArmISA::fp64_compare_ge ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 1154 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGE().

fp64_compare_gt()

static int gem5::ArmISA::fp64_compare_gt ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 1179 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareGT().

fp64_compare_un()

static int gem5::ArmISA::fp64_compare_un ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 1204 of file fplib.cc.

References a, b, flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, and mode.

Referenced by fplibCompareUN().

fp64_cvtf()

static uint64_t gem5::ArmISA::fp64_cvtf ( uint64_t a, int fbits, int u, int mode, int * flags )

static

Definition at line 4948 of file fplib.cc.

References a, flags, FP64_BITS, FP64_EXP_BIAS, fp64_normalise(), fp64_round(), fp64_zero(), mode, and u.

Referenced by fplibFixedToFP().

fp64_defaultNaN()

static uint64_t gem5::ArmISA::fp64_defaultNaN ( )

inlinestatic

Definition at line 386 of file fplib.cc.

References FP64_EXP_INF, FP64_MANT_BITS, and fp64_pack().

Referenced by fp64_add(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_sqrt(), fplibConvert(), fplibConvert(), fplibDefaultNaN(), and fplibRSqrtEstimate().

fp64_div()

static uint64_t gem5::ArmISA::fp64_div ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 1860 of file fplib.cc.

References a, b, c, cmp128(), flags, fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_INF, fp64_infinity(), fp64_normalise(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_DZC, FPLIB_IOC, lsr128(), mode, mul62x62(), mul64x32(), sub128(), and gem5::RiscvISA::x.

Referenced by fplibDiv().

fp64_FPConvertNaN_16()

static uint64_t gem5::ArmISA::fp64_FPConvertNaN_16 ( uint16_t op )

static

Definition at line 2556 of file fplib.cc.

References FP16_BITS, FP16_MANT_BITS, FP64_EXP_INF, FP64_MANT_BITS, fp64_pack(), and gem5::X86ISA::op.

Referenced by fplibConvert().

fp64_FPConvertNaN_32()

static uint64_t gem5::ArmISA::fp64_FPConvertNaN_32 ( uint32_t op )

static

Definition at line 2564 of file fplib.cc.

References FP32_BITS, FP32_MANT_BITS, FP64_EXP_INF, FP64_MANT_BITS, fp64_pack(), and gem5::X86ISA::op.

Referenced by fplibConvert().

fp64_FPOnePointFive()

static uint64_t gem5::ArmISA::fp64_FPOnePointFive ( int sgn )

static

Definition at line 2584 of file fplib.cc.

References FP64_EXP_BIAS, FP64_MANT_BITS, and fp64_pack().

Referenced by fplibRSqrtStepFused().

fp64_FPThree()

static uint64_t gem5::ArmISA::fp64_FPThree ( int sgn )

static

Definition at line 2602 of file fplib.cc.

References FP64_EXP_BIAS, FP64_MANT_BITS, and fp64_pack().

Referenced by fplibRSqrtStepFused().

fp64_FPTwo()

static uint64_t gem5::ArmISA::fp64_FPTwo ( int sgn )

static

Definition at line 2620 of file fplib.cc.

References FP64_EXP_BIAS, and fp64_pack().

Referenced by fplibMulX(), and fplibRecipStepFused().

fp64_infinity()

static uint64_t gem5::ArmISA::fp64_infinity ( int sgn )

inlinestatic

Definition at line 368 of file fplib.cc.

References FP64_EXP_INF, and fp64_pack().

Referenced by fp64_add(), fp64_div(), fp64_minmaxnum(), fp64_mul(), fp64_muladd(), fp64_round_(), fp64_scale(), fp64_sqrt(), fplibConvert(), fplibConvert(), fplibInfinity(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibRSqrtStepFused().

fp64_is_infinity()

static int gem5::ArmISA::fp64_is_infinity ( int exp, uint64_t mnt )

inlinestatic

Definition at line 529 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT.

Referenced by fp64_muladd().

fp64_is_NaN()

static int gem5::ArmISA::fp64_is_NaN ( int exp, uint64_t mnt )

inlinestatic

Definition at line 475 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT.

Referenced by fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_is_signalling_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), and fplibTrigSMul().

fp64_is_quiet_NaN()

static int gem5::ArmISA::fp64_is_quiet_NaN ( int exp, uint64_t mnt )

inlinestatic

Definition at line 511 of file fplib.cc.

References FP64_EXP_INF, and FP64_MANT_BITS.

Referenced by fp64_muladd().

fp64_is_signalling_NaN()

static int gem5::ArmISA::fp64_is_signalling_NaN ( int exp, uint64_t mnt )

inlinestatic

Definition at line 493 of file fplib.cc.

References fp64_is_NaN(), and FP64_MANT_BITS.

Referenced by fp64_compare_eq(), fp64_compare_un(), fp64_process_NaNs(), fp64_process_NaNs3(), and fplibCompare().

fp64_max_normal()

static uint64_t gem5::ArmISA::fp64_max_normal ( int sgn )

inlinestatic

Definition at line 350 of file fplib.cc.

References FP64_EXP_INF, and fp64_pack().

Referenced by fp64_round_(), and fplibRecipEstimate().

fp64_minmaxnum()

static void gem5::ArmISA::fp64_minmaxnum ( uint64_t * op1, uint64_t * op2, int sgn )

static

Definition at line 3169 of file fplib.cc.

References fp64_infinity(), and FP64_MANT_BITS.

Referenced by fplibMaxNum(), and fplibMinNum().

fp64_mul()

static uint64_t gem5::ArmISA::fp64_mul ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 1477 of file fplib.cc.

References a, b, flags, fp128_normalise(), fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_process_NaNs(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, mode, mul62x62(), and gem5::RiscvISA::x.

Referenced by fplibMul(), fplibMulX(), and fplibTrigSMul().

fp64_muladd()

static uint64_t gem5::ArmISA::fp64_muladd ( uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int * flags )

static

Definition at line 1684 of file fplib.cc.

References a, add128(), b, c, cmp128(), flags, fp128_normalise(), fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_infinity(), fp64_is_quiet_NaN(), fp64_process_NaNs3(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl128(), lsr128(), mode, mul62x62(), gem5::X86ISA::scale, sub128(), t0, t1, and gem5::RiscvISA::x.

Referenced by fplibMulAdd(), fplibRecipStepFused(), fplibRSqrtStepFused(), and fplibTrigMulAdd().

fp64_normalise()

static uint64_t gem5::ArmISA::fp64_normalise ( uint64_t mnt, int * exp )

inlinestatic

Definition at line 255 of file fplib.cc.

References shift.

Referenced by fp16_cvtf(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp64_add(), fp64_cvtf(), fp64_div(), fp64_scale(), fp64_sqrt(), fplibRecipEstimate(), fplibRoundInt(), and fplibRSqrtEstimate().

fp64_pack()

static uint64_t gem5::ArmISA::fp64_pack ( uint64_t sgn, uint64_t exp, uint64_t mnt )

inlinestatic

Definition at line 314 of file fplib.cc.

References FP64_BITS, FP64_MANT, and FP64_MANT_BITS.

Referenced by fp64_defaultNaN(), fp64_FPConvertNaN_16(), fp64_FPConvertNaN_32(), fp64_FPOnePointFive(), fp64_FPThree(), fp64_FPTwo(), fp64_infinity(), fp64_max_normal(), fp64_repack(), fp64_round_(), fp64_zero(), fplibConvert(), fplibConvert(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

fp64_process_NaN()

static uint64_t gem5::ArmISA::fp64_process_NaN ( uint64_t a, int mode, int * flags )

inlinestatic

Definition at line 555 of file fplib.cc.

References a, flags, fp64_defaultNaN(), FP64_MANT_BITS, FPLIB_DN, FPLIB_IOC, and mode.

Referenced by fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fplibRecipEstimate(), fplibRecpX(), fplibRoundInt(), and fplibRSqrtEstimate().

fp64_process_NaNs()

static uint64_t gem5::ArmISA::fp64_process_NaNs ( uint64_t a, uint64_t b, int mode, int * flags )

static

Definition at line 611 of file fplib.cc.

References a, b, flags, FP64_EXP, fp64_is_NaN(), fp64_is_signalling_NaN(), FP64_MANT, fp64_process_NaN(), and mode.

Referenced by fp64_add(), fp64_div(), fp64_mul(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipStepFused(), and fplibRSqrtStepFused().

fp64_process_NaNs3()

static uint64_t gem5::ArmISA::fp64_process_NaNs3 ( uint64_t a, uint64_t b, uint64_t c, int mode, int * flags )

static

Definition at line 692 of file fplib.cc.

References a, b, c, flags, FP64_EXP, fp64_is_NaN(), fp64_is_signalling_NaN(), FP64_MANT, fp64_process_NaN(), and mode.

Referenced by fp64_muladd().

fp64_repack()

static uint64_t gem5::ArmISA::fp64_repack ( int sgn, int exp, uint64_t mnt )

static

Definition at line 3139 of file fplib.cc.

References FP64_MANT_BITS, and fp64_pack().

Referenced by fplibMax(), and fplibMin().

fp64_round()

static uint64_t gem5::ArmISA::fp64_round ( int sgn, int exp, uint64_t mnt, int mode, int * flags )

static

Definition at line 953 of file fplib.cc.

References flags, fp64_round_(), and mode.

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_scale(), and fp64_sqrt().

fp64_round_()

static uint64_t gem5::ArmISA::fp64_round_ ( int sgn, int exp, uint64_t mnt, int rm, int mode, int * flags )

static

Definition at line 882 of file fplib.cc.

References error, flags, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), FP64_MANT_BITS, fp64_max_normal(), fp64_pack(), fp64_zero(), FPLIB_FZ, FPLIB_IXC, FPLIB_OFC, FPLIB_RM, FPLIB_RN, FPLIB_RP, FPLIB_UFC, FPRounding_ODD, FPRounding_TIEAWAY, lsl64(), lsr64(), mode, and rm.

Referenced by fp64_round().

fp64_scale()

static uint64_t gem5::ArmISA::fp64_scale ( uint64_t a, int64_t b, int mode, int * flags )

static

Definition at line 2006 of file fplib.cc.

References a, b, flags, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), fp64_normalise(), fp64_process_NaN(), fp64_round(), fp64_unpack(), fp64_zero(), and mode.

Referenced by fplibScale().

fp64_sqrt()

static uint64_t gem5::ArmISA::fp64_sqrt ( uint64_t a, int mode, int * flags )

static

Definition at line 2147 of file fplib.cc.

References a, c, cmp128(), flags, fp64_defaultNaN(), FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), fp64_normalise(), fp64_process_NaN(), fp64_round(), fp64_unpack(), fp64_zero(), FPLIB_IOC, lsl128(), lsr128(), mode, mul62x62(), mul64x32(), gem5::MipsISA::r, and gem5::RiscvISA::x.

Referenced by fplibSqrt().

fp64_unpack()

static void gem5::ArmISA::fp64_unpack ( int * sgn, int * exp, uint64_t * mnt, uint64_t x, int mode, int * flags )

inlinestatic

Definition at line 438 of file fplib.cc.

References flags, FP64_BITS, FP64_EXP, FP64_MANT, FP64_MANT_BITS, FPLIB_FZ, FPLIB_IDC, mode, and gem5::RiscvISA::x.

Referenced by fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_scale(), fp64_sqrt(), fplibCompare(), fplibConvert(), fplibFPToFixed(), fplibMax(), fplibMin(), fplibMulX(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecpX(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), and fplibTrigSMul().

fp64_zero()

static uint64_t gem5::ArmISA::fp64_zero ( int sgn )

inlinestatic

Definition at line 332 of file fplib.cc.

References fp64_pack().

Referenced by fp64_add(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_round_(), fp64_scale(), fp64_sqrt(), fplibConvert(), fplibConvert(), fplibMulX(), fplibRecipEstimate(), and fplibRoundInt().

fpAdd()

template<typename T >

static T gem5::ArmISA::fpAdd ( T a, T b )

inlinestatic

Definition at line 482 of file vfp.hh.

References a, and b.

fpAddD()

static double gem5::ArmISA::fpAddD ( double a, double b )

inlinestatic

Definition at line 501 of file vfp.hh.

References a, and b.

fpAddS()

static float gem5::ArmISA::fpAddS ( float a, float b )

inlinestatic

Definition at line 495 of file vfp.hh.

References a, and b.

FPCRRounding()

static FPRounding gem5::ArmISA::FPCRRounding ( FPSCR & fpscr )

inlinestatic

Definition at line 71 of file fplib.hh.

Referenced by fplibRecipEstimate(), fplibRecipEstimate(), and fplibRecipEstimate().

fpDiv()

template<typename T >

static T gem5::ArmISA::fpDiv ( T a, T b )

inlinestatic

Definition at line 532 of file vfp.hh.

References a, and b.

fpDivD()

static double gem5::ArmISA::fpDivD ( double a, double b )

inlinestatic

Definition at line 525 of file vfp.hh.

References a, and b.

fpDivS()

static float gem5::ArmISA::fpDivS ( float a, float b )

inlinestatic

Definition at line 519 of file vfp.hh.

References a, and b.

fplibAbs() [1/7]

template<class T >

T gem5::ArmISA::fplibAbs

(

T

op

)

Floating-point absolute value.

fplibAbs() [2/7]

template<>

uint16_t gem5::ArmISA::fplibAbs

(

uint16_t

op

)

Definition at line 2372 of file fplib.cc.

References FP16_BITS, and gem5::X86ISA::op.

Referenced by fplibTrigMulAdd(), fplibTrigMulAdd(), and fplibTrigMulAdd().

fplibAbs() [3/7]

template<>

uint16_t gem5::ArmISA::fplibAbs

(

uint16_t

op

)

Definition at line 2372 of file fplib.cc.

References FP16_BITS, and gem5::X86ISA::op.

Referenced by fplibTrigMulAdd(), fplibTrigMulAdd(), and fplibTrigMulAdd().

fplibAbs() [4/7]

template<>

uint32_t gem5::ArmISA::fplibAbs

(

uint32_t

op

)

Definition at line 2379 of file fplib.cc.

References FP32_BITS, and gem5::X86ISA::op.

fplibAbs() [5/7]

template<>

uint32_t gem5::ArmISA::fplibAbs

(

uint32_t

op

)

Definition at line 2379 of file fplib.cc.

References FP32_BITS, and gem5::X86ISA::op.

fplibAbs() [6/7]

template<>

uint64_t gem5::ArmISA::fplibAbs

(

uint64_t

op

)

Definition at line 2386 of file fplib.cc.

References FP64_BITS, and gem5::X86ISA::op.

fplibAbs() [7/7]

template<>

uint64_t gem5::ArmISA::fplibAbs

(

uint64_t

op

)

Definition at line 2386 of file fplib.cc.

References FP64_BITS, and gem5::X86ISA::op.

fplibAdd() [1/7]

template<class T >

T gem5::ArmISA::fplibAdd	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point add.

fplibAdd() [2/7]

template<>

uint16_t gem5::ArmISA::fplibAdd	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2393 of file fplib.cc.

References flags, fp16_add(), modeConv(), and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_ADD_F16::execute().

fplibAdd() [3/7]

template<>

uint16_t gem5::ArmISA::fplibAdd	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2393 of file fplib.cc.

References flags, fp16_add(), modeConv(), and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_ADD_F16::execute().

fplibAdd() [4/7]

template<>

uint32_t gem5::ArmISA::fplibAdd	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2403 of file fplib.cc.

References flags, fp32_add(), modeConv(), and set_fpscr0().

fplibAdd() [5/7]

template<>

uint32_t gem5::ArmISA::fplibAdd	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2403 of file fplib.cc.

References flags, fp32_add(), modeConv(), and set_fpscr0().

fplibAdd() [6/7]

template<>

uint64_t gem5::ArmISA::fplibAdd	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2413 of file fplib.cc.

References flags, fp64_add(), modeConv(), and set_fpscr0().

fplibAdd() [7/7]

template<>

uint64_t gem5::ArmISA::fplibAdd	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2413 of file fplib.cc.

References flags, fp64_add(), modeConv(), and set_fpscr0().

fplibCompare() [1/7]

template<class T >

int gem5::ArmISA::fplibCompare	(	T	op1,
		T	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Floating-point compare (quiet and signaling).

fplibCompare() [2/7]

template<>

int gem5::ArmISA::fplibCompare	(	uint16_t	op1,
		uint16_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Definition at line 2423 of file fplib.cc.

References flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

fplibCompare() [3/7]

template<>

int gem5::ArmISA::fplibCompare	(	uint16_t	op1,
		uint16_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Definition at line 2423 of file fplib.cc.

References flags, fp16_is_NaN(), fp16_is_signalling_NaN(), fp16_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

fplibCompare() [4/7]

template<>

int gem5::ArmISA::fplibCompare	(	uint32_t	op1,
		uint32_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Definition at line 2457 of file fplib.cc.

References flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

fplibCompare() [5/7]

template<>

int gem5::ArmISA::fplibCompare	(	uint32_t	op1,
		uint32_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Definition at line 2457 of file fplib.cc.

References flags, fp32_is_NaN(), fp32_is_signalling_NaN(), fp32_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

fplibCompare() [6/7]

template<>

int gem5::ArmISA::fplibCompare	(	uint64_t	op1,
		uint64_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Definition at line 2491 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

fplibCompare() [7/7]

template<>

int gem5::ArmISA::fplibCompare	(	uint64_t	op1,
		uint64_t	op2,
		bool	signal_nans,
		FPSCR &	fpscr )

Definition at line 2491 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_is_signalling_NaN(), fp64_unpack(), FPLIB_IOC, mode, modeConv(), and set_fpscr0().

fplibCompareEQ() [1/7]

template<class T >

bool gem5::ArmISA::fplibCompareEQ	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point compare equal.

fplibCompareEQ() [2/7]

template<>

bool gem5::ArmISA::fplibCompareEQ	(	uint16_t	a,
		uint16_t	b,
		FPSCR &	fpscr )

Definition at line 2252 of file fplib.cc.

References a, b, flags, fp16_compare_eq(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareEQ() [3/7]

template<>

bool gem5::ArmISA::fplibCompareEQ	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2252 of file fplib.cc.

References a, b, flags, fp16_compare_eq(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareEQ() [4/7]

template<>

bool gem5::ArmISA::fplibCompareEQ	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr )

Definition at line 2292 of file fplib.cc.

References a, b, flags, fp32_compare_eq(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareEQ() [5/7]

template<>

bool gem5::ArmISA::fplibCompareEQ	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2292 of file fplib.cc.

References a, b, flags, fp32_compare_eq(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareEQ() [6/7]

template<>

bool gem5::ArmISA::fplibCompareEQ	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr )

Definition at line 2332 of file fplib.cc.

References a, b, flags, fp64_compare_eq(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareEQ() [7/7]

template<>

bool gem5::ArmISA::fplibCompareEQ	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2332 of file fplib.cc.

References a, b, flags, fp64_compare_eq(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGE() [1/7]

template<class T >

bool gem5::ArmISA::fplibCompareGE	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point compare greater than or equal.

fplibCompareGE() [2/7]

template<>

bool gem5::ArmISA::fplibCompareGE	(	uint16_t	a,
		uint16_t	b,
		FPSCR &	fpscr )

Definition at line 2262 of file fplib.cc.

References a, b, flags, fp16_compare_ge(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGE() [3/7]

template<>

bool gem5::ArmISA::fplibCompareGE	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2262 of file fplib.cc.

References a, b, flags, fp16_compare_ge(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGE() [4/7]

template<>

bool gem5::ArmISA::fplibCompareGE	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr )

Definition at line 2302 of file fplib.cc.

References a, b, flags, fp32_compare_ge(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGE() [5/7]

template<>

bool gem5::ArmISA::fplibCompareGE	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2302 of file fplib.cc.

References a, b, flags, fp32_compare_ge(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGE() [6/7]

template<>

bool gem5::ArmISA::fplibCompareGE	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr )

Definition at line 2342 of file fplib.cc.

References a, b, flags, fp64_compare_ge(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGE() [7/7]

template<>

bool gem5::ArmISA::fplibCompareGE	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2342 of file fplib.cc.

References a, b, flags, fp64_compare_ge(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGT() [1/7]

template<class T >

bool gem5::ArmISA::fplibCompareGT	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point compare greater than.

fplibCompareGT() [2/7]

template<>

bool gem5::ArmISA::fplibCompareGT	(	uint16_t	a,
		uint16_t	b,
		FPSCR &	fpscr )

Definition at line 2272 of file fplib.cc.

References a, b, flags, fp16_compare_gt(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGT() [3/7]

template<>

bool gem5::ArmISA::fplibCompareGT	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2272 of file fplib.cc.

References a, b, flags, fp16_compare_gt(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGT() [4/7]

template<>

bool gem5::ArmISA::fplibCompareGT	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr )

Definition at line 2312 of file fplib.cc.

References a, b, flags, fp32_compare_gt(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGT() [5/7]

template<>

bool gem5::ArmISA::fplibCompareGT	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2312 of file fplib.cc.

References a, b, flags, fp32_compare_gt(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGT() [6/7]

template<>

bool gem5::ArmISA::fplibCompareGT	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr )

Definition at line 2352 of file fplib.cc.

References a, b, flags, fp64_compare_gt(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareGT() [7/7]

template<>

bool gem5::ArmISA::fplibCompareGT	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2352 of file fplib.cc.

References a, b, flags, fp64_compare_gt(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareUN() [1/7]

template<class T >

bool gem5::ArmISA::fplibCompareUN	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point compare unordered.

fplibCompareUN() [2/7]

template<>

bool gem5::ArmISA::fplibCompareUN	(	uint16_t	a,
		uint16_t	b,
		FPSCR &	fpscr )

Definition at line 2282 of file fplib.cc.

References a, b, flags, fp16_compare_un(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareUN() [3/7]

template<>

bool gem5::ArmISA::fplibCompareUN	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2282 of file fplib.cc.

References a, b, flags, fp16_compare_un(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareUN() [4/7]

template<>

bool gem5::ArmISA::fplibCompareUN	(	uint32_t	a,
		uint32_t	b,
		FPSCR &	fpscr )

Definition at line 2322 of file fplib.cc.

References a, b, flags, fp32_compare_un(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareUN() [5/7]

template<>

bool gem5::ArmISA::fplibCompareUN	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2322 of file fplib.cc.

References a, b, flags, fp32_compare_un(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareUN() [6/7]

template<>

bool gem5::ArmISA::fplibCompareUN	(	uint64_t	a,
		uint64_t	b,
		FPSCR &	fpscr )

Definition at line 2362 of file fplib.cc.

References a, b, flags, fp64_compare_un(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibCompareUN() [7/7]

template<>

bool gem5::ArmISA::fplibCompareUN	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2362 of file fplib.cc.

References a, b, flags, fp64_compare_un(), modeConv(), set_fpscr(), and gem5::RiscvISA::x.

fplibConvert() [1/13]

template<class T1 , class T2 >

T2 gem5::ArmISA::fplibConvert	(	T1	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Floating-point convert precision.

fplibConvert() [2/13]

template<>

uint32_t gem5::ArmISA::fplibConvert	(	uint16_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2725 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_unpack(), fp32_defaultNaN(), FP32_EXP_BIAS, fp32_FPConvertNaN_16(), fp32_infinity(), FP32_MANT_BITS, fp32_pack(), fp32_zero(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibConvert() [3/13]

template<>

uint64_t gem5::ArmISA::fplibConvert	(	uint16_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2802 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_unpack(), fp64_defaultNaN(), FP64_EXP_BIAS, fp64_FPConvertNaN_16(), fp64_infinity(), FP64_MANT_BITS, fp64_pack(), fp64_zero(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibConvert() [4/13]

template<>

uint32_t gem5::ArmISA::fplibConvert	(	uint16_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2725 of file fplib.cc.

fplibConvert() [5/13]

template<>

uint64_t gem5::ArmISA::fplibConvert	(	uint16_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2725 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_unpack(), fp32_defaultNaN(), FP32_EXP_BIAS, fp32_FPConvertNaN_16(), fp32_infinity(), FP32_MANT_BITS, fp32_pack(), fp32_zero(), fp64_defaultNaN(), FP64_EXP_BIAS, fp64_FPConvertNaN_16(), fp64_infinity(), FP64_MANT_BITS, fp64_pack(), fp64_zero(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibConvert() [6/13]

template<>

uint16_t gem5::ArmISA::fplibConvert	(	uint32_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2627 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, fp16_FPConvertNaN_32(), fp16_infinity(), fp16_round_(), fp16_zero(), FP32_EXP_BIAS, FP32_EXP_INF, fp32_is_NaN(), FP32_MANT_BITS, fp32_unpack(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_DOT2_F32_F16::execute().

fplibConvert() [7/13]

template<>

uint64_t gem5::ArmISA::fplibConvert	(	uint32_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2840 of file fplib.cc.

References flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_unpack(), fp64_defaultNaN(), FP64_EXP_BIAS, fp64_FPConvertNaN_32(), fp64_infinity(), FP64_MANT_BITS, fp64_pack(), fp64_zero(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibConvert() [8/13]

template<>

uint16_t gem5::ArmISA::fplibConvert	(	uint32_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2627 of file fplib.cc.

fplibConvert() [9/13]

template<>

uint64_t gem5::ArmISA::fplibConvert	(	uint32_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2627 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, fp16_FPConvertNaN_32(), fp16_infinity(), fp16_round_(), fp16_zero(), FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_unpack(), fp64_defaultNaN(), FP64_EXP_BIAS, fp64_FPConvertNaN_32(), fp64_infinity(), FP64_MANT_BITS, fp64_pack(), fp64_zero(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_DOT2_F32_F16::execute().

fplibConvert() [10/13]

template<>

uint16_t gem5::ArmISA::fplibConvert	(	uint64_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2676 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, fp16_FPConvertNaN_64(), fp16_infinity(), fp16_round_(), fp16_zero(), FP64_EXP_BIAS, FP64_EXP_INF, fp64_is_NaN(), FP64_MANT_BITS, fp64_unpack(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibConvert() [11/13]

template<>

uint32_t gem5::ArmISA::fplibConvert	(	uint64_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2763 of file fplib.cc.

References flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, fp32_FPConvertNaN_64(), fp32_infinity(), fp32_round_(), fp32_zero(), FP64_EXP_BIAS, FP64_EXP_INF, fp64_is_NaN(), FP64_MANT_BITS, fp64_unpack(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibConvert() [12/13]

template<>

uint16_t gem5::ArmISA::fplibConvert	(	uint64_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2676 of file fplib.cc.

fplibConvert() [13/13]

template<>

uint32_t gem5::ArmISA::fplibConvert	(	uint64_t	op,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 2676 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, fp16_FPConvertNaN_64(), fp16_infinity(), fp16_round_(), fp16_zero(), FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, fp32_FPConvertNaN_64(), fp32_infinity(), fp32_round_(), fp32_zero(), FP64_EXP_BIAS, FP64_EXP_INF, fp64_is_NaN(), FP64_MANT_BITS, fp64_unpack(), FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibDefaultNaN() [1/7]

template<>

uint16_t gem5::ArmISA::fplibDefaultNaN

(

)

Definition at line 5024 of file fplib.cc.

References fp16_defaultNaN().

fplibDefaultNaN() [2/7]

template<>

uint32_t gem5::ArmISA::fplibDefaultNaN

(

)

Definition at line 5031 of file fplib.cc.

References fp32_defaultNaN().

fplibDefaultNaN() [3/7]

template<>

uint64_t gem5::ArmISA::fplibDefaultNaN

(

)

Definition at line 5038 of file fplib.cc.

References fp64_defaultNaN().

fplibDefaultNaN() [4/7]

template<class T >

T gem5::ArmISA::fplibDefaultNaN

(

)

Foating-point value for default NaN.

fplibDefaultNaN() [5/7]

template<>

uint16_t gem5::ArmISA::fplibDefaultNaN

(

)

Definition at line 5024 of file fplib.cc.

fplibDefaultNaN() [6/7]

template<>

uint32_t gem5::ArmISA::fplibDefaultNaN

(

)

Definition at line 5024 of file fplib.cc.

fplibDefaultNaN() [7/7]

template<>

uint64_t gem5::ArmISA::fplibDefaultNaN

(

)

Definition at line 5024 of file fplib.cc.

References fp16_defaultNaN(), fp32_defaultNaN(), and fp64_defaultNaN().

fplibDiv() [1/7]

template<class T >

T gem5::ArmISA::fplibDiv	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point division.

fplibDiv() [2/7]

template<>

uint16_t gem5::ArmISA::fplibDiv	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2908 of file fplib.cc.

References flags, fp16_div(), modeConv(), and set_fpscr0().

fplibDiv() [3/7]

template<>

uint16_t gem5::ArmISA::fplibDiv	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2908 of file fplib.cc.

References flags, fp16_div(), modeConv(), and set_fpscr0().

fplibDiv() [4/7]

template<>

uint32_t gem5::ArmISA::fplibDiv	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2918 of file fplib.cc.

References flags, fp32_div(), modeConv(), and set_fpscr0().

fplibDiv() [5/7]

template<>

uint32_t gem5::ArmISA::fplibDiv	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2918 of file fplib.cc.

References flags, fp32_div(), modeConv(), and set_fpscr0().

fplibDiv() [6/7]

template<>

uint64_t gem5::ArmISA::fplibDiv	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2928 of file fplib.cc.

References flags, fp64_div(), modeConv(), and set_fpscr0().

fplibDiv() [7/7]

template<>

uint64_t gem5::ArmISA::fplibDiv	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2928 of file fplib.cc.

References flags, fp64_div(), modeConv(), and set_fpscr0().

fplibExpA() [1/7]

template<class T >

T gem5::ArmISA::fplibExpA

(

T

op

)

Floating-point exponential accelerator.

fplibExpA() [2/7]

template<>

uint16_t gem5::ArmISA::fplibExpA

(

uint16_t

op

)

Definition at line 2938 of file fplib.cc.

References FP16_EXP_BITS, FP16_MANT_BITS, and gem5::X86ISA::op.

fplibExpA() [3/7]

template<>

uint16_t gem5::ArmISA::fplibExpA

(

uint16_t

op

)

Definition at line 2938 of file fplib.cc.

References FP16_EXP_BITS, FP16_MANT_BITS, and gem5::X86ISA::op.

fplibExpA() [4/7]

template<>

uint32_t gem5::ArmISA::fplibExpA

(

uint32_t

op

)

Definition at line 2980 of file fplib.cc.

References FP32_EXP_BITS, FP32_MANT_BITS, and gem5::X86ISA::op.

fplibExpA() [5/7]

template<>

uint32_t gem5::ArmISA::fplibExpA

(

uint32_t

op

)

Definition at line 2980 of file fplib.cc.

References FP32_EXP_BITS, FP32_MANT_BITS, and gem5::X86ISA::op.

fplibExpA() [6/7]

template<>

uint64_t gem5::ArmISA::fplibExpA

(

uint64_t

op

)

Definition at line 3054 of file fplib.cc.

References FP64_EXP_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

fplibExpA() [7/7]

template<>

uint64_t gem5::ArmISA::fplibExpA

(

uint64_t

op

)

Definition at line 3054 of file fplib.cc.

References FP64_EXP_BITS, FP64_MANT_BITS, and gem5::X86ISA::op.

fplibFixedToFP() [1/7]

template<>

uint16_t gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4966 of file fplib.cc.

References flags, fp16_cvtf(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFixedToFP() [2/7]

template<>

uint32_t gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4979 of file fplib.cc.

References flags, fp32_cvtf(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFixedToFP() [3/7]

template<>

uint64_t gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4991 of file fplib.cc.

References flags, fp64_cvtf(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFixedToFP() [4/7]

template<class T >

T gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Floating-point convert from fixed-point.

fplibFixedToFP() [5/7]

template<>

uint16_t gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4966 of file fplib.cc.

fplibFixedToFP() [6/7]

template<>

uint32_t gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4966 of file fplib.cc.

fplibFixedToFP() [7/7]

template<>

uint64_t gem5::ArmISA::fplibFixedToFP	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4966 of file fplib.cc.

References flags, fp16_cvtf(), fp32_cvtf(), fp64_cvtf(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [1/15]

template<class T1 , class T2 >

T2 gem5::ArmISA::fplibFPToFixed	(	T1	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Floating-point convert to fixed-point.

fplibFPToFixed() [2/15]

template<>

uint16_t gem5::ArmISA::fplibFPToFixed	(	uint16_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4638 of file fplib.cc.

References flags, FP16_EXP_BIAS, fp16_is_NaN(), FP16_MANT_BITS, fp16_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_16(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [3/15]

template<>

uint32_t gem5::ArmISA::fplibFPToFixed	(	uint16_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4668 of file fplib.cc.

References flags, FP16_EXP_BIAS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_32(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [4/15]

template<>

uint64_t gem5::ArmISA::fplibFPToFixed	(	uint16_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4821 of file fplib.cc.

References flags, FP16_EXP_BIAS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_64(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [5/15]

template<>

uint16_t gem5::ArmISA::fplibFPToFixed	(	uint16_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4638 of file fplib.cc.

fplibFPToFixed() [6/15]

template<>

uint32_t gem5::ArmISA::fplibFPToFixed	(	uint16_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4638 of file fplib.cc.

fplibFPToFixed() [7/15]

template<>

uint64_t gem5::ArmISA::fplibFPToFixed	(	uint16_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4638 of file fplib.cc.

References flags, FP16_EXP_BIAS, FP16_EXP_INF, fp16_is_NaN(), FP16_MANT_BITS, fp16_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_16(), FPToFixed_32(), FPToFixed_64(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [8/15]

template<>

uint32_t gem5::ArmISA::fplibFPToFixed	(	uint32_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4700 of file fplib.cc.

References flags, FP32_EXP_BIAS, fp32_is_NaN(), FP32_MANT_BITS, fp32_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_32(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [9/15]

template<>

uint64_t gem5::ArmISA::fplibFPToFixed	(	uint32_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4853 of file fplib.cc.

References flags, FP32_EXP_BIAS, fp32_is_NaN(), FP32_MANT_BITS, fp32_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_64(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [10/15]

template<>

uint32_t gem5::ArmISA::fplibFPToFixed	(	uint32_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4700 of file fplib.cc.

fplibFPToFixed() [11/15]

template<>

uint64_t gem5::ArmISA::fplibFPToFixed	(	uint32_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4700 of file fplib.cc.

References flags, FP32_EXP_BIAS, fp32_is_NaN(), FP32_MANT_BITS, fp32_unpack(), FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IOC, FPToFixed_32(), FPToFixed_64(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [12/15]

template<>

uint32_t gem5::ArmISA::fplibFPToFixed	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4729 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, FPToFixed_32(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [13/15]

template<>

uint64_t gem5::ArmISA::fplibFPToFixed	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4883 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, FPToFixed_64(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixed() [14/15]

template<>

uint32_t gem5::ArmISA::fplibFPToFixed	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4729 of file fplib.cc.

fplibFPToFixed() [15/15]

template<>

uint64_t gem5::ArmISA::fplibFPToFixed	(	uint64_t	op,
		int	fbits,
		bool	u,
		FPRounding	rounding,
		FPSCR &	fpscr )

Definition at line 4729 of file fplib.cc.

References flags, fp64_is_NaN(), fp64_unpack(), FPLIB_IOC, FPToFixed_32(), FPToFixed_64(), modeConv(), gem5::X86ISA::op, set_fpscr0(), and u.

fplibFPToFixedJS()

uint32_t gem5::ArmISA::fplibFPToFixedJS	(	uint64_t	op,
		FPSCR &	fpscr,
		bool	is64,
		uint8_t &	nz )

Floating-point JS convert to a signed integer, with rounding to zero.

Definition at line 4755 of file fplib.cc.

References gem5::bits(), err, flags, FP32_BITS, FP64_BITS, FP64_EXP_BIAS, FP64_MANT_BITS, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, lsl64(), lsr64(), nz, gem5::X86ISA::op, and set_fpscr0().

fplibInfinity() [1/7]

template<>

uint16_t gem5::ArmISA::fplibInfinity

(

int

sgn

)

Definition at line 5003 of file fplib.cc.

References fp16_infinity().

fplibInfinity() [2/7]

template<>

uint32_t gem5::ArmISA::fplibInfinity

(

int

sgn

)

Definition at line 5010 of file fplib.cc.

References fp32_infinity().

fplibInfinity() [3/7]

template<>

uint64_t gem5::ArmISA::fplibInfinity

(

int

sgn

)

Definition at line 5017 of file fplib.cc.

References fp64_infinity().

fplibInfinity() [4/7]

template<class T >

T gem5::ArmISA::fplibInfinity

(

int

sgn

)

Floating-point value for +/- infinity.

fplibInfinity() [5/7]

template<>

uint16_t gem5::ArmISA::fplibInfinity

(

int

sgn

)

Definition at line 5003 of file fplib.cc.

fplibInfinity() [6/7]

template<>

uint32_t gem5::ArmISA::fplibInfinity

(

int

sgn

)

Definition at line 5003 of file fplib.cc.

fplibInfinity() [7/7]

template<>

uint64_t gem5::ArmISA::fplibInfinity

(

int

sgn

)

Definition at line 5003 of file fplib.cc.

References fp16_infinity(), fp32_infinity(), and fp64_infinity().

fplibMax() [1/7]

template<class T >

T gem5::ArmISA::fplibMax	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point maximum.

fplibMax() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMax	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3182 of file fplib.cc.

References flags, fp16_process_NaNs(), fp16_repack(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

Referenced by gem5::VegaISA::clampF16(), gem5::VegaISA::Inst_VOP3P__V_PK_MAX_F16::execute(), fplibMaxNum(), fplibMaxNum(), and fplibMaxNum().

fplibMax() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMax	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3182 of file fplib.cc.

References flags, fp16_process_NaNs(), fp16_repack(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

Referenced by gem5::VegaISA::clampF16(), gem5::VegaISA::Inst_VOP3P__V_PK_MAX_F16::execute(), fplibMaxNum(), fplibMaxNum(), and fplibMaxNum().

fplibMax() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMax	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3205 of file fplib.cc.

References flags, fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMax() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMax	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3205 of file fplib.cc.

References flags, fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMax() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMax	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3228 of file fplib.cc.

References flags, fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMax() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMax	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3228 of file fplib.cc.

References flags, fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMaxNum() [1/7]

template<class T >

T gem5::ArmISA::fplibMaxNum	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point maximum number.

fplibMaxNum() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMaxNum	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3251 of file fplib.cc.

References fp16_minmaxnum(), and fplibMax().

fplibMaxNum() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMaxNum	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3251 of file fplib.cc.

References fp16_minmaxnum(), and fplibMax().

fplibMaxNum() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMaxNum	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3259 of file fplib.cc.

References fp32_minmaxnum(), and fplibMax().

fplibMaxNum() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMaxNum	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3259 of file fplib.cc.

References fp32_minmaxnum(), and fplibMax().

fplibMaxNum() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMaxNum	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3267 of file fplib.cc.

References fp64_minmaxnum(), and fplibMax().

fplibMaxNum() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMaxNum	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3267 of file fplib.cc.

References fp64_minmaxnum(), and fplibMax().

fplibMin() [1/7]

template<class T >

T gem5::ArmISA::fplibMin	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point minimum.

fplibMin() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMin	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3275 of file fplib.cc.

References flags, fp16_process_NaNs(), fp16_repack(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

Referenced by gem5::VegaISA::clampF16(), gem5::VegaISA::Inst_VOP3P__V_PK_MIN_F16::execute(), fplibMinNum(), fplibMinNum(), and fplibMinNum().

fplibMin() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMin	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3275 of file fplib.cc.

References flags, fp16_process_NaNs(), fp16_repack(), fp16_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

Referenced by gem5::VegaISA::clampF16(), gem5::VegaISA::Inst_VOP3P__V_PK_MIN_F16::execute(), fplibMinNum(), fplibMinNum(), and fplibMinNum().

fplibMin() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMin	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3298 of file fplib.cc.

References flags, fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMin() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMin	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3298 of file fplib.cc.

References flags, fp32_process_NaNs(), fp32_repack(), fp32_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMin() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMin	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3321 of file fplib.cc.

References flags, fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMin() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMin	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3321 of file fplib.cc.

References flags, fp64_process_NaNs(), fp64_repack(), fp64_unpack(), mode, modeConv(), set_fpscr0(), and gem5::RiscvISA::x.

fplibMinNum() [1/7]

template<class T >

T gem5::ArmISA::fplibMinNum	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point minimum number.

fplibMinNum() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMinNum	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3344 of file fplib.cc.

References fp16_minmaxnum(), and fplibMin().

fplibMinNum() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMinNum	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3344 of file fplib.cc.

References fp16_minmaxnum(), and fplibMin().

fplibMinNum() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMinNum	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3352 of file fplib.cc.

References fp32_minmaxnum(), and fplibMin().

fplibMinNum() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMinNum	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3352 of file fplib.cc.

References fp32_minmaxnum(), and fplibMin().

fplibMinNum() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMinNum	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3360 of file fplib.cc.

References fp64_minmaxnum(), and fplibMin().

fplibMinNum() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMinNum	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3360 of file fplib.cc.

References fp64_minmaxnum(), and fplibMin().

fplibMul() [1/7]

template<class T >

T gem5::ArmISA::fplibMul	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point multiply.

fplibMul() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMul	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3368 of file fplib.cc.

References flags, fp16_mul(), modeConv(), and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_DOT2_F32_F16::execute(), and gem5::VegaISA::Inst_VOP3P__V_PK_MUL_F16::execute().

fplibMul() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMul	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3368 of file fplib.cc.

References flags, fp16_mul(), modeConv(), and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_DOT2_F32_F16::execute(), and gem5::VegaISA::Inst_VOP3P__V_PK_MUL_F16::execute().

fplibMul() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMul	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3378 of file fplib.cc.

References flags, fp32_mul(), modeConv(), and set_fpscr0().

fplibMul() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMul	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3378 of file fplib.cc.

References flags, fp32_mul(), modeConv(), and set_fpscr0().

fplibMul() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMul	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3388 of file fplib.cc.

References flags, fp64_mul(), modeConv(), and set_fpscr0().

fplibMul() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMul	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3388 of file fplib.cc.

References flags, fp64_mul(), modeConv(), and set_fpscr0().

fplibMulAdd() [1/7]

template<class T >

T gem5::ArmISA::fplibMulAdd	(	T	addend,
		T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point multiply-add.

fplibMulAdd() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMulAdd	(	uint16_t	addend,
		uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2878 of file fplib.cc.

References flags, fp16_muladd(), modeConv(), and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_FMA_F16::execute().

fplibMulAdd() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMulAdd	(	uint16_t	addend,
		uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 2878 of file fplib.cc.

References flags, fp16_muladd(), modeConv(), and set_fpscr0().

Referenced by gem5::VegaISA::Inst_VOP3P__V_PK_FMA_F16::execute().

fplibMulAdd() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMulAdd	(	uint32_t	addend,
		uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2888 of file fplib.cc.

References flags, fp32_muladd(), modeConv(), and set_fpscr0().

fplibMulAdd() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMulAdd	(	uint32_t	addend,
		uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 2888 of file fplib.cc.

References flags, fp32_muladd(), modeConv(), and set_fpscr0().

fplibMulAdd() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMulAdd	(	uint64_t	addend,
		uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2898 of file fplib.cc.

References flags, fp64_muladd(), modeConv(), and set_fpscr0().

fplibMulAdd() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMulAdd	(	uint64_t	addend,
		uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 2898 of file fplib.cc.

References flags, fp64_muladd(), modeConv(), and set_fpscr0().

fplibMulX() [1/7]

template<class T >

T gem5::ArmISA::fplibMulX	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point multiply extended.

fplibMulX() [2/7]

template<>

uint16_t gem5::ArmISA::fplibMulX	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3398 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPTwo(), fp16_infinity(), fp16_mul(), fp16_process_NaNs(), fp16_unpack(), fp16_zero(), mode, modeConv(), and set_fpscr0().

fplibMulX() [3/7]

template<>

uint16_t gem5::ArmISA::fplibMulX	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3398 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPTwo(), fp16_infinity(), fp16_mul(), fp16_process_NaNs(), fp16_unpack(), fp16_zero(), mode, modeConv(), and set_fpscr0().

fplibMulX() [4/7]

template<>

uint32_t gem5::ArmISA::fplibMulX	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3429 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPTwo(), fp32_infinity(), fp32_mul(), fp32_process_NaNs(), fp32_unpack(), fp32_zero(), mode, modeConv(), and set_fpscr0().

fplibMulX() [5/7]

template<>

uint32_t gem5::ArmISA::fplibMulX	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3429 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPTwo(), fp32_infinity(), fp32_mul(), fp32_process_NaNs(), fp32_unpack(), fp32_zero(), mode, modeConv(), and set_fpscr0().

fplibMulX() [6/7]

template<>

uint64_t gem5::ArmISA::fplibMulX	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3460 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPTwo(), fp64_infinity(), fp64_mul(), fp64_process_NaNs(), fp64_unpack(), fp64_zero(), mode, modeConv(), and set_fpscr0().

fplibMulX() [7/7]

template<>

uint64_t gem5::ArmISA::fplibMulX	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3460 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPTwo(), fp64_infinity(), fp64_mul(), fp64_process_NaNs(), fp64_unpack(), fp64_zero(), mode, modeConv(), and set_fpscr0().

fplibNeg() [1/7]

template<class T >

T gem5::ArmISA::fplibNeg

(

T

op

)

Floating-point negate.

fplibNeg() [2/7]

template<>

uint16_t gem5::ArmISA::fplibNeg

(

uint16_t

op

)

Definition at line 3491 of file fplib.cc.

References FP16_BITS, and gem5::X86ISA::op.

Referenced by fplibRecipStepFused(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), and fplibRSqrtStepFused().

fplibNeg() [3/7]

template<>

uint16_t gem5::ArmISA::fplibNeg

(

uint16_t

op

)

Definition at line 3491 of file fplib.cc.

References FP16_BITS, and gem5::X86ISA::op.

Referenced by fplibRecipStepFused(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), and fplibRSqrtStepFused().

fplibNeg() [4/7]

template<>

uint32_t gem5::ArmISA::fplibNeg

(

uint32_t

op

)

Definition at line 3498 of file fplib.cc.

References FP32_BITS, and gem5::X86ISA::op.

fplibNeg() [5/7]

template<>

uint32_t gem5::ArmISA::fplibNeg

(

uint32_t

op

)

Definition at line 3498 of file fplib.cc.

References FP32_BITS, and gem5::X86ISA::op.

fplibNeg() [6/7]

template<>

uint64_t gem5::ArmISA::fplibNeg

(

uint64_t

op

)

Definition at line 3505 of file fplib.cc.

References FP64_BITS, and gem5::X86ISA::op.

fplibNeg() [7/7]

template<>

uint64_t gem5::ArmISA::fplibNeg

(

uint64_t

op

)

Definition at line 3505 of file fplib.cc.

References FP64_BITS, and gem5::X86ISA::op.

fplibRecipEstimate() [1/7]

template<class T >

T gem5::ArmISA::fplibRecipEstimate	(	T	op,
		FPSCR &	fpscr )

Floating-point reciprocal estimate.

fplibRecipEstimate() [2/7]

template<>

uint16_t gem5::ArmISA::fplibRecipEstimate	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 3726 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_max_normal(), fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

fplibRecipEstimate() [3/7]

template<>

uint16_t gem5::ArmISA::fplibRecipEstimate	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 3726 of file fplib.cc.

References flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_max_normal(), fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

fplibRecipEstimate() [4/7]

template<>

uint32_t gem5::ArmISA::fplibRecipEstimate	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 3788 of file fplib.cc.

References flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_max_normal(), fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

fplibRecipEstimate() [5/7]

template<>

uint32_t gem5::ArmISA::fplibRecipEstimate	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 3788 of file fplib.cc.

References flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_max_normal(), fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

fplibRecipEstimate() [6/7]

template<>

uint64_t gem5::ArmISA::fplibRecipEstimate	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 3850 of file fplib.cc.

References flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_max_normal(), fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

fplibRecipEstimate() [7/7]

template<>

uint64_t gem5::ArmISA::fplibRecipEstimate	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 3850 of file fplib.cc.

References flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_max_normal(), fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPCRRounding(), FPLIB_DZC, FPLIB_IXC, FPLIB_OFC, FPLIB_UFC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, and set_fpscr0().

fplibRecipStepFused() [1/7]

template<class T >

T gem5::ArmISA::fplibRecipStepFused	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point reciprocal step.

fplibRecipStepFused() [2/7]

template<>

uint16_t gem5::ArmISA::fplibRecipStepFused	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3912 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPTwo(), fp16_infinity(), fp16_muladd(), fp16_process_NaNs(), fp16_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRecipStepFused() [3/7]

template<>

uint16_t gem5::ArmISA::fplibRecipStepFused	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3912 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPTwo(), fp16_infinity(), fp16_muladd(), fp16_process_NaNs(), fp16_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRecipStepFused() [4/7]

template<>

uint32_t gem5::ArmISA::fplibRecipStepFused	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3942 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPTwo(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRecipStepFused() [5/7]

template<>

uint32_t gem5::ArmISA::fplibRecipStepFused	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3942 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPTwo(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRecipStepFused() [6/7]

template<>

uint64_t gem5::ArmISA::fplibRecipStepFused	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3972 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPTwo(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRecipStepFused() [7/7]

template<>

uint64_t gem5::ArmISA::fplibRecipStepFused	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3972 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPTwo(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRecpX() [1/7]

template<class T >

T gem5::ArmISA::fplibRecpX	(	T	op,
		FPSCR &	fpscr )

Floating-point reciprocal exponent.

fplibRecpX() [2/7]

template<>

uint16_t gem5::ArmISA::fplibRecpX	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 4002 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_is_NaN(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibRecpX() [3/7]

template<>

uint16_t gem5::ArmISA::fplibRecpX	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 4002 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_is_NaN(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibRecpX() [4/7]

template<>

uint32_t gem5::ArmISA::fplibRecpX	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 4029 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_is_NaN(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibRecpX() [5/7]

template<>

uint32_t gem5::ArmISA::fplibRecpX	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 4029 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_is_NaN(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibRecpX() [6/7]

template<>

uint64_t gem5::ArmISA::fplibRecpX	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 4056 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_is_NaN(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibRecpX() [7/7]

template<>

uint64_t gem5::ArmISA::fplibRecpX	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 4056 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_is_NaN(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), mode, modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibRoundInt() [1/7]

template<class T >

T gem5::ArmISA::fplibRoundInt	(	T	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Floating-point convert to integer.

fplibRoundInt() [2/7]

template<>

uint16_t gem5::ArmISA::fplibRoundInt	(	uint16_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Definition at line 4083 of file fplib.cc.

References err, flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::RiscvISA::x.

fplibRoundInt() [3/7]

template<>

uint16_t gem5::ArmISA::fplibRoundInt	(	uint16_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Definition at line 4083 of file fplib.cc.

References err, flags, FP16_BITS, FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::RiscvISA::x.

fplibRoundInt() [4/7]

template<>

uint32_t gem5::ArmISA::fplibRoundInt	(	uint32_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Definition at line 4148 of file fplib.cc.

References err, flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::RiscvISA::x.

fplibRoundInt() [5/7]

template<>

uint32_t gem5::ArmISA::fplibRoundInt	(	uint32_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Definition at line 4148 of file fplib.cc.

References err, flags, FP32_BITS, FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::RiscvISA::x.

fplibRoundInt() [6/7]

template<>

uint64_t gem5::ArmISA::fplibRoundInt	(	uint64_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Definition at line 4213 of file fplib.cc.

References err, flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::RiscvISA::x.

fplibRoundInt() [7/7]

template<>

uint64_t gem5::ArmISA::fplibRoundInt	(	uint64_t	op,
		FPRounding	rounding,
		bool	exact,
		FPSCR &	fpscr )

Definition at line 4213 of file fplib.cc.

References err, flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), fp64_zero(), FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, mode, modeConv(), gem5::X86ISA::op, panic, set_fpscr0(), and gem5::RiscvISA::x.

fplibRSqrtEstimate() [1/7]

template<class T >

T gem5::ArmISA::fplibRSqrtEstimate	(	T	op,
		FPSCR &	fpscr )

Floating-point reciprocal square root estimate.

fplibRSqrtEstimate() [2/7]

template<>

uint16_t gem5::ArmISA::fplibRSqrtEstimate	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 3531 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

fplibRSqrtEstimate() [3/7]

template<>

uint16_t gem5::ArmISA::fplibRSqrtEstimate	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 3531 of file fplib.cc.

References flags, FP16_BITS, fp16_defaultNaN(), FP16_EXP_BIAS, FP16_EXP_BITS, FP16_EXP_INF, fp16_infinity(), fp16_is_NaN(), FP16_MANT_BITS, fp16_normalise(), fp16_pack(), fp16_process_NaN(), fp16_unpack(), fp16_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

fplibRSqrtEstimate() [4/7]

template<>

uint32_t gem5::ArmISA::fplibRSqrtEstimate	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 3566 of file fplib.cc.

References flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

fplibRSqrtEstimate() [5/7]

template<>

uint32_t gem5::ArmISA::fplibRSqrtEstimate	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 3566 of file fplib.cc.

References flags, FP32_BITS, fp32_defaultNaN(), FP32_EXP_BIAS, FP32_EXP_BITS, FP32_EXP_INF, fp32_infinity(), fp32_is_NaN(), FP32_MANT_BITS, fp32_normalise(), fp32_pack(), fp32_process_NaN(), fp32_unpack(), fp32_zero(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

fplibRSqrtEstimate() [6/7]

template<>

uint64_t gem5::ArmISA::fplibRSqrtEstimate	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 3601 of file fplib.cc.

References flags, fp32_zero(), FP64_BITS, fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

fplibRSqrtEstimate() [7/7]

template<>

uint64_t gem5::ArmISA::fplibRSqrtEstimate	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 3601 of file fplib.cc.

References flags, fp32_zero(), FP64_BITS, fp64_defaultNaN(), FP64_EXP_BIAS, FP64_EXP_BITS, FP64_EXP_INF, fp64_infinity(), fp64_is_NaN(), FP64_MANT_BITS, fp64_normalise(), fp64_pack(), fp64_process_NaN(), fp64_unpack(), FPLIB_DZC, FPLIB_IOC, mode, modeConv(), gem5::X86ISA::op, recip_sqrt_estimate, and set_fpscr0().

fplibRSqrtStepFused() [1/7]

template<class T >

T gem5::ArmISA::fplibRSqrtStepFused	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point reciprocal square root step.

fplibRSqrtStepFused() [2/7]

template<>

uint16_t gem5::ArmISA::fplibRSqrtStepFused	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3636 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPOnePointFive(), fp16_FPThree(), fp16_infinity(), fp16_muladd(), fp16_process_NaNs(), fp16_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRSqrtStepFused() [3/7]

template<>

uint16_t gem5::ArmISA::fplibRSqrtStepFused	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 3636 of file fplib.cc.

References flags, FP16_EXP_INF, fp16_FPOnePointFive(), fp16_FPThree(), fp16_infinity(), fp16_muladd(), fp16_process_NaNs(), fp16_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRSqrtStepFused() [4/7]

template<>

uint32_t gem5::ArmISA::fplibRSqrtStepFused	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3666 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPOnePointFive(), fp32_FPThree(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRSqrtStepFused() [5/7]

template<>

uint32_t gem5::ArmISA::fplibRSqrtStepFused	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 3666 of file fplib.cc.

References flags, FP32_EXP_INF, fp32_FPOnePointFive(), fp32_FPThree(), fp32_infinity(), fp32_muladd(), fp32_process_NaNs(), fp32_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRSqrtStepFused() [6/7]

template<>

uint64_t gem5::ArmISA::fplibRSqrtStepFused	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3696 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPOnePointFive(), fp64_FPThree(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibRSqrtStepFused() [7/7]

template<>

uint64_t gem5::ArmISA::fplibRSqrtStepFused	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 3696 of file fplib.cc.

References flags, FP64_EXP_INF, fp64_FPOnePointFive(), fp64_FPThree(), fp64_infinity(), fp64_muladd(), fp64_process_NaNs(), fp64_unpack(), fplibNeg(), mode, modeConv(), and set_fpscr0().

fplibScale() [1/7]

template<class T >

T gem5::ArmISA::fplibScale	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point adjust exponent.

fplibScale() [2/7]

template<>

uint16_t gem5::ArmISA::fplibScale	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4278 of file fplib.cc.

References flags, fp16_scale(), modeConv(), and set_fpscr0().

fplibScale() [3/7]

template<>

uint16_t gem5::ArmISA::fplibScale	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4278 of file fplib.cc.

References flags, fp16_scale(), modeConv(), and set_fpscr0().

fplibScale() [4/7]

template<>

uint32_t gem5::ArmISA::fplibScale	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4288 of file fplib.cc.

References flags, fp32_scale(), modeConv(), and set_fpscr0().

fplibScale() [5/7]

template<>

uint32_t gem5::ArmISA::fplibScale	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4288 of file fplib.cc.

References flags, fp32_scale(), modeConv(), and set_fpscr0().

fplibScale() [6/7]

template<>

uint64_t gem5::ArmISA::fplibScale	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4298 of file fplib.cc.

References flags, fp64_scale(), modeConv(), and set_fpscr0().

fplibScale() [7/7]

template<>

uint64_t gem5::ArmISA::fplibScale	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4298 of file fplib.cc.

References flags, fp64_scale(), modeConv(), and set_fpscr0().

fplibSqrt() [1/7]

template<class T >

T gem5::ArmISA::fplibSqrt	(	T	op,
		FPSCR &	fpscr )

Floating-point square root.

fplibSqrt() [2/7]

template<>

uint16_t gem5::ArmISA::fplibSqrt	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 4308 of file fplib.cc.

References flags, fp16_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibSqrt() [3/7]

template<>

uint16_t gem5::ArmISA::fplibSqrt	(	uint16_t	op,
		FPSCR &	fpscr )

Definition at line 4308 of file fplib.cc.

References flags, fp16_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibSqrt() [4/7]

template<>

uint32_t gem5::ArmISA::fplibSqrt	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 4318 of file fplib.cc.

References flags, fp32_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibSqrt() [5/7]

template<>

uint32_t gem5::ArmISA::fplibSqrt	(	uint32_t	op,
		FPSCR &	fpscr )

Definition at line 4318 of file fplib.cc.

References flags, fp32_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibSqrt() [6/7]

template<>

uint64_t gem5::ArmISA::fplibSqrt	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 4328 of file fplib.cc.

References flags, fp64_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibSqrt() [7/7]

template<>

uint64_t gem5::ArmISA::fplibSqrt	(	uint64_t	op,
		FPSCR &	fpscr )

Definition at line 4328 of file fplib.cc.

References flags, fp64_sqrt(), modeConv(), gem5::X86ISA::op, and set_fpscr0().

fplibSub() [1/7]

template<class T >

T gem5::ArmISA::fplibSub	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point subtract.

fplibSub() [2/7]

template<>

uint16_t gem5::ArmISA::fplibSub	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4338 of file fplib.cc.

References flags, fp16_add(), modeConv(), and set_fpscr0().

fplibSub() [3/7]

template<>

uint16_t gem5::ArmISA::fplibSub	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4338 of file fplib.cc.

References flags, fp16_add(), modeConv(), and set_fpscr0().

fplibSub() [4/7]

template<>

uint32_t gem5::ArmISA::fplibSub	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4348 of file fplib.cc.

References flags, fp32_add(), modeConv(), and set_fpscr0().

fplibSub() [5/7]

template<>

uint32_t gem5::ArmISA::fplibSub	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4348 of file fplib.cc.

References flags, fp32_add(), modeConv(), and set_fpscr0().

fplibSub() [6/7]

template<>

uint64_t gem5::ArmISA::fplibSub	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4358 of file fplib.cc.

References flags, fp64_add(), modeConv(), and set_fpscr0().

fplibSub() [7/7]

template<>

uint64_t gem5::ArmISA::fplibSub	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4358 of file fplib.cc.

References flags, fp64_add(), modeConv(), and set_fpscr0().

fplibTrigMulAdd() [1/7]

template<class T >

T gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point trigonometric multiply-add coefficient.

fplibTrigMulAdd() [2/7]

template<>

uint16_t gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4368 of file fplib.cc.

References flags, FP16_BITS, fp16_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

fplibTrigMulAdd() [3/7]

template<>

uint16_t gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4368 of file fplib.cc.

References flags, FP16_BITS, fp16_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

fplibTrigMulAdd() [4/7]

template<>

uint32_t gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4402 of file fplib.cc.

References flags, FP32_BITS, fp32_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

fplibTrigMulAdd() [5/7]

template<>

uint32_t gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4402 of file fplib.cc.

References flags, FP32_BITS, fp32_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

fplibTrigMulAdd() [6/7]

template<>

uint64_t gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4436 of file fplib.cc.

References flags, FP64_BITS, fp64_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

fplibTrigMulAdd() [7/7]

template<>

uint64_t gem5::ArmISA::fplibTrigMulAdd	(	uint8_t	coeff_index,
		uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4436 of file fplib.cc.

References flags, FP64_BITS, fp64_muladd(), fplibAbs(), modeConv(), and set_fpscr0().

fplibTrigSMul() [1/7]

template<class T >

T gem5::ArmISA::fplibTrigSMul	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point trigonometric starting value.

fplibTrigSMul() [2/7]

template<>

uint16_t gem5::ArmISA::fplibTrigSMul	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4470 of file fplib.cc.

References flags, FP16_BITS, fp16_is_NaN(), fp16_mul(), fp16_unpack(), mode, modeConv(), and set_fpscr0().

fplibTrigSMul() [3/7]

template<>

uint16_t gem5::ArmISA::fplibTrigSMul	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4470 of file fplib.cc.

References flags, FP16_BITS, fp16_is_NaN(), fp16_mul(), fp16_unpack(), mode, modeConv(), and set_fpscr0().

fplibTrigSMul() [4/7]

template<>

uint32_t gem5::ArmISA::fplibTrigSMul	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4490 of file fplib.cc.

References flags, FP32_BITS, fp32_is_NaN(), fp32_mul(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

fplibTrigSMul() [5/7]

template<>

uint32_t gem5::ArmISA::fplibTrigSMul	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4490 of file fplib.cc.

References flags, FP32_BITS, fp32_is_NaN(), fp32_mul(), fp32_unpack(), mode, modeConv(), and set_fpscr0().

fplibTrigSMul() [6/7]

template<>

uint64_t gem5::ArmISA::fplibTrigSMul	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4509 of file fplib.cc.

References flags, FP64_BITS, fp64_is_NaN(), fp64_mul(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

fplibTrigSMul() [7/7]

template<>

uint64_t gem5::ArmISA::fplibTrigSMul	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4509 of file fplib.cc.

References flags, FP64_BITS, fp64_is_NaN(), fp64_mul(), fp64_unpack(), mode, modeConv(), and set_fpscr0().

fplibTrigSSel() [1/7]

template<class T >

T gem5::ArmISA::fplibTrigSSel	(	T	op1,
		T	op2,
		FPSCR &	fpscr )

Floating-point trigonometric select coefficient.

fplibTrigSSel() [2/7]

template<>

uint16_t gem5::ArmISA::fplibTrigSSel	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4528 of file fplib.cc.

References FP16_BITS, FP16_EXP_BIAS, and FP16_MANT_BITS.

fplibTrigSSel() [3/7]

template<>

uint16_t gem5::ArmISA::fplibTrigSSel	(	uint16_t	op1,
		uint16_t	op2,
		FPSCR &	fpscr )

Definition at line 4528 of file fplib.cc.

References FP16_BITS, FP16_EXP_BIAS, and FP16_MANT_BITS.

fplibTrigSSel() [4/7]

template<>

uint32_t gem5::ArmISA::fplibTrigSSel	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4539 of file fplib.cc.

References FP32_BITS, FP32_EXP_BIAS, and FP32_MANT_BITS.

fplibTrigSSel() [5/7]

template<>

uint32_t gem5::ArmISA::fplibTrigSSel	(	uint32_t	op1,
		uint32_t	op2,
		FPSCR &	fpscr )

Definition at line 4539 of file fplib.cc.

References FP32_BITS, FP32_EXP_BIAS, and FP32_MANT_BITS.

fplibTrigSSel() [6/7]

template<>

uint64_t gem5::ArmISA::fplibTrigSSel	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4550 of file fplib.cc.

References FP64_BITS, FP64_EXP_BIAS, and FP64_MANT_BITS.

fplibTrigSSel() [7/7]

template<>

uint64_t gem5::ArmISA::fplibTrigSSel	(	uint64_t	op1,
		uint64_t	op2,
		FPSCR &	fpscr )

Definition at line 4550 of file fplib.cc.

References FP64_BITS, FP64_EXP_BIAS, and FP64_MANT_BITS.

fpMax()

template<typename T >

static T gem5::ArmISA::fpMax ( T a, T b )

inlinestatic

Definition at line 643 of file vfp.hh.

References a, b, fpMaxNum(), and std::isnan().

fpMaxNum()

template<typename T >

static T gem5::ArmISA::fpMaxNum ( T a, T b )

inlinestatic

Definition at line 626 of file vfp.hh.

References a, b, gem5::RiscvISA::fmax(), fpToBits(), and std::isnan().

Referenced by fpMax().

fpMin()

template<typename T >

static T gem5::ArmISA::fpMin ( T a, T b )

inlinestatic

Definition at line 671 of file vfp.hh.

References a, b, fpMinNum(), and std::isnan().

fpMinNum()

template<typename T >

static T gem5::ArmISA::fpMinNum ( T a, T b )

inlinestatic

Definition at line 654 of file vfp.hh.

References a, b, gem5::RiscvISA::fmin(), fpToBits(), and std::isnan().

Referenced by fpMin().

fpMul()

template<typename T >

static T gem5::ArmISA::fpMul ( T a, T b )

inlinestatic

Definition at line 573 of file vfp.hh.

References a, and b.

fpMulAdd()

template<typename T >

static T gem5::ArmISA::fpMulAdd ( T op1, T op2, T addend )

inlinestatic

Definition at line 593 of file vfp.hh.

References bitsToFp(), fpToBits(), and std::isnan().

fpMulD()

static double gem5::ArmISA::fpMulD ( double a, double b )

inlinestatic

Definition at line 585 of file vfp.hh.

References a, and b.

fpMulS()

static float gem5::ArmISA::fpMulS ( float a, float b )

inlinestatic

Definition at line 579 of file vfp.hh.

References a, and b.

fpMulX()

template<typename T >

static T gem5::ArmISA::fpMulX ( T a, T b )

inlinestatic

Definition at line 539 of file vfp.hh.

References a, b, and fpToBits().

fpRecipEstimate()

float gem5::ArmISA::fpRecipEstimate	(	FPSCR &	fpscr,
		float	op )

Definition at line 853 of file vfp.cc.

References gem5::bits(), fpRecipEstimate(), gem5::X86ISA::op, and recipEstimate().

Referenced by fpRecipEstimate().

fpRecps()

template<typename T >

static T gem5::ArmISA::fpRecps ( T a, T b )

inlinestatic

Definition at line 704 of file vfp.hh.

References a, b, and FeUnderflow.

fpRecpsS()

static float gem5::ArmISA::fpRecpsS ( float a, float b )

inlinestatic

Definition at line 747 of file vfp.hh.

References a, b, and FeUnderflow.

fpRIntX()

template<typename T >

static T gem5::ArmISA::fpRIntX ( T a, FPSCR & fpscr )

inlinestatic

Definition at line 614 of file vfp.hh.

References a, and std::isnan().

fprSqrtEstimate()

float gem5::ArmISA::fprSqrtEstimate	(	FPSCR &	fpscr,
		float	op )

Definition at line 771 of file vfp.cc.

References gem5::bits(), fprSqrtEstimate(), gem5::X86ISA::op, and recipSqrtEstimate().

Referenced by fprSqrtEstimate().

fpRSqrts()

template<typename T >

static T gem5::ArmISA::fpRSqrts ( T a, T b )

inlinestatic

Definition at line 682 of file vfp.hh.

References a, b, and FeUnderflow.

fpRSqrtsS()

static float gem5::ArmISA::fpRSqrtsS ( float a, float b )

inlinestatic

Definition at line 726 of file vfp.hh.

References a, b, and FeUnderflow.

fpStandardFPSCRValue()

FPSCR gem5::ArmISA::fpStandardFPSCRValue

(

const FPSCR &

fpscr

)

Definition at line 905 of file vfp.cc.

References fpStandardFPSCRValue().

Referenced by fpStandardFPSCRValue().

fpSub()

template<typename T >

static T gem5::ArmISA::fpSub ( T a, T b )

inlinestatic

Definition at line 489 of file vfp.hh.

References a, and b.

fpSubD()

static double gem5::ArmISA::fpSubD ( double a, double b )

inlinestatic

Definition at line 513 of file vfp.hh.

References a, and b.

fpSubS()

static float gem5::ArmISA::fpSubS ( float a, float b )

inlinestatic

Definition at line 507 of file vfp.hh.

References a, and b.

fpToBits() [1/2]

static uint64_t gem5::ArmISA::fpToBits ( double fp )

inlinestatic

Definition at line 172 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

fpToBits() [2/2]

static uint32_t gem5::ArmISA::fpToBits ( float fp )

inlinestatic

Definition at line 160 of file vfp.hh.

References gem5::bits(), fp, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::FpOp::dblHi(), gem5::ArmISA::FpOp::dblLow(), flushToZero(), fpMaxNum(), fpMinNum(), fpMulAdd(), fpMulX(), highFromDouble(), isSnan(), and lowFromDouble().

FPToFixed_16()

static uint16_t gem5::ArmISA::FPToFixed_16 ( int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int * flags )

static

Definition at line 4623 of file fplib.cc.

References flags, FP16_BITS, FPLIB_IOC, FPToFixed_64(), u, and gem5::RiscvISA::x.

Referenced by fplibFPToFixed().

FPToFixed_32()

static uint32_t gem5::ArmISA::FPToFixed_32 ( int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int * flags )

static

Definition at line 4609 of file fplib.cc.

References flags, FP32_BITS, FPLIB_IOC, FPToFixed_64(), u, and gem5::RiscvISA::x.

Referenced by fplibFPToFixed(), fplibFPToFixed(), and fplibFPToFixed().

FPToFixed_64()

static uint64_t gem5::ArmISA::FPToFixed_64 ( int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int * flags )

static

Definition at line 4560 of file fplib.cc.

References err, flags, FP64_BITS, FP64_EXP_BIAS, FP64_EXP_BITS, FPLIB_IOC, FPLIB_IXC, FPRounding_NEGINF, FPRounding_POSINF, FPRounding_TIEAWAY, FPRounding_TIEEVEN, FPRounding_ZERO, lsl64(), lsr64(), panic, u, and gem5::RiscvISA::x.

Referenced by fplibFPToFixed(), fplibFPToFixed(), fplibFPToFixed(), FPToFixed_16(), and FPToFixed_32().

getAff0()

static RegVal gem5::ArmISA::getAff0 ( ArmSystem * arm_sys, ThreadContext * tc )

static

Definition at line 215 of file utility.cc.

References gem5::ThreadContext::cpuId(), gem5::System::multiThread, and gem5::ThreadContext::threadId().

Referenced by getAffinity().

getAff1()

static RegVal gem5::ArmISA::getAff1 ( ArmSystem * arm_sys, ThreadContext * tc )

static

Definition at line 209 of file utility.cc.

References gem5::ThreadContext::cpuId(), gem5::System::multiThread, and gem5::ThreadContext::socketId().

Referenced by getAffinity().

getAff2()

static RegVal gem5::ArmISA::getAff2 ( ArmSystem * arm_sys, ThreadContext * tc )

static

Definition at line 203 of file utility.cc.

References gem5::System::multiThread, and gem5::ThreadContext::socketId().

Referenced by getAffinity().

getAffinity()

Affinity gem5::ArmISA::getAffinity	(	ArmSystem *	arm_sys,
		ThreadContext *	tc )

Retrieves MPIDR_EL1.

{Aff2,Aff1,Aff0} affinity numbers

Definition at line 221 of file utility.cc.

References getAff0(), getAff1(), and getAff2().

Referenced by gem5::Gicv3Redistributor::getAffinity(), getMPIDR(), and gem5::FVPBasePwrCtrl::getThreadContextByMPID().

getFaultVAddr()

bool gem5::ArmISA::getFaultVAddr	(	Fault	fault,
		Addr &	va )

Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise.

If true it is storing the faulting address in the va argument

Parameters

fault	generated fault
va	function will modify this passed-by-reference parameter with the correct faulting virtual address

Returns

true if va contains a valid value, false otherwise

Definition at line 1782 of file faults.cc.

References gem5::ArmISA::ArmFault::getFaultVAddr(), gem5::GenericAlignmentFault::getFaultVAddr(), gem5::GenericPageTableFault::getFaultVAddr(), and va.

getHSlice()

template<typename ElemType >

MatRow< ElemType > gem5::ArmISA::getHSlice	(	MatRegContainer &	reg,
		uint8_t	row_idx )

Definition at line 122 of file mat.hh.

References gem5::X86ISA::reg.

getMMUPtr()

template<typename T >

MMU * gem5::ArmISA::getMMUPtr

(

T *

tc

)

Definition at line 510 of file mmu.hh.

Referenced by gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::ArmISA::ISA::clear(), gem5::ArmISA::DTLBIALL::operator()(), gem5::ArmISA::DTLBIASID::operator()(), gem5::ArmISA::DTLBIMVA::operator()(), gem5::ArmISA::ITLBIALL::operator()(), gem5::ArmISA::ITLBIASID::operator()(), gem5::ArmISA::ITLBIMVA::operator()(), gem5::ArmISA::TLBIALL::operator()(), gem5::ArmISA::TLBIALLEL::operator()(), gem5::ArmISA::TLBIALLN::operator()(), gem5::ArmISA::TLBIASID::operator()(), gem5::ArmISA::TLBIIPA::operator()(), gem5::ArmISA::TLBIMVA::operator()(), gem5::ArmISA::TLBIMVAA::operator()(), gem5::ArmISA::TLBIVMALL::operator()(), and gem5::ArmISA::ISA::setMiscReg().

getMPIDR()

RegVal gem5::ArmISA::getMPIDR	(	ArmSystem *	arm_sys,
		ThreadContext *	tc )

This helper function is returning the value of MPIDR_EL1.

Definition at line 173 of file utility.cc.

References gem5::ThreadContext::cpuId(), getAffinity(), gem5::ArmSystem::multiProc, gem5::System::multiThread, gem5::replaceBits(), and gem5::ThreadContext::socketId().

Referenced by gem5::ArmISA::Reset::invoke(), and readMPIDR().

getPageTableOps()

const PageTableOps * gem5::ArmISA::getPageTableOps

(

GrainSize

trans_granule

)

Definition at line 476 of file pagetable.cc.

References Grain16KB, Grain4KB, Grain64KB, and panic.

Referenced by gem5::ArmISA::TableWalker::LongDescriptor::offsetBits(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), gem5::ArmISA::TableWalker::walkAddresses(), and gem5::SMMUTranslationProcess::walkCacheLookup().

getRestoredITBits()

static uint8_t gem5::ArmISA::getRestoredITBits ( ThreadContext * tc, CPSR spsr )

static

Definition at line 1204 of file static_inst.cc.

References gem5::bits(), el, EL2, itd, itState(), MISCREG_HSCTLR, MISCREG_SCTLR, opModeToEL(), and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR().

getTile()

template<typename ElemType >

MatTile< ElemType > gem5::ArmISA::getTile	(	MatRegContainer &	reg,
		uint8_t	tile_idx )

Definition at line 104 of file mat.hh.

References gem5::X86ISA::reg.

getTileHSlice()

template<typename ElemType >

MatTileRow< ElemType > gem5::ArmISA::getTileHSlice	(	MatRegContainer &	reg,
		uint8_t	tile_idx,
		uint8_t	row_idx )

Definition at line 110 of file mat.hh.

References gem5::X86ISA::reg.

getTileVSlice()

template<typename ElemType >

MatTileCol< ElemType > gem5::ArmISA::getTileVSlice	(	MatRegContainer &	reg,
		uint8_t	tile_idx,
		uint8_t	col_idx )

Definition at line 116 of file mat.hh.

References gem5::X86ISA::reg.

getVSlice()

template<typename ElemType >

MatCol< ElemType > gem5::ArmISA::getVSlice	(	MatRegContainer &	reg,
		uint8_t	col_idx )

Definition at line 128 of file mat.hh.

References gem5::X86ISA::reg.

haveAArch32EL()

bool gem5::ArmISA::haveAArch32EL	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 308 of file utility.cc.

References el, EL0, gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestEL(), and gem5::ArmSystem::highestELIs64().

Referenced by ELStateUsingAArch32K().

HaveExt()

bool gem5::ArmISA::HaveExt	(	ThreadContext *	tc,
		ArmExtension	ext )

Returns true if the provided ThreadContext supports the ArmExtension passed as a second argument.

Definition at line 231 of file utility.cc.

References ext, gem5::ThreadContext::getIsaPtr(), gem5::ArmISA::ISA::getRelease(), and gem5::ArmRelease::has().

Referenced by gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDTrap64(), gem5::ArmISA::MMU::checkPAN(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), gem5::ArmISA::TableWalker::checkVAddrSizeFaultAArch64(), computeAddrTop(), debugTargetFrom(), ELIsInHost(), ELStateUsingAArch32K(), fgtEnabled(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), IsSecureEL2Enabled(), isUnpriviledgeAccess(), gem5::ArmISA::DataAbort::routeToHyp(), s1TranslationRegime(), gem5::ArmISA::mpam::tagRequest(), gem5::ArmISA::Interrupts::takeVirtualInt32(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::ArmFault::update(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

highFromDouble()

static uint32_t gem5::ArmISA::highFromDouble ( double val )

inlinestatic

Definition at line 256 of file vfp.hh.

References fpToBits(), and gem5::X86ISA::val.

illegalExceptionReturn()

static bool gem5::ArmISA::illegalExceptionReturn ( ThreadContext * tc, CPSR cpsr, CPSR spsr )

static

Definition at line 1233 of file static_inst.cc.

References currEL(), EL0, EL1, EL2, EL3, ELIs64(), ELUsingAArch32K(), gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestELIs64(), isSecureBelowEL3(), IsSecureEL2Enabled(), MISCREG_HCR_EL2, MISCREG_SCR_EL3, mode, opModeToEL(), gem5::ThreadContext::readMiscReg(), unknownMode(), and unknownMode32().

Referenced by gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR().

inAArch64()

bool gem5::ArmISA::inAArch64

(

ThreadContext *

tc

)

Definition at line 126 of file utility.cc.

References MISCREG_CPSR, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmSystem::callSemihosting(), gem5::ArmISA::MMU::finalizePhysical(), gem5::ArmISA::RemoteGDB::gdbRegs(), gem5::fastmodel::FastmodelRemoteGDB::gdbRegs(), gem5::ArmISA::RemoteGDB::getXferFeaturesRead(), gem5::Gicv3CPUInterface::isAA64(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

inPrivilegedMode()

static bool gem5::ArmISA::inPrivilegedMode ( CPSR cpsr )

inlinestatic

Definition at line 103 of file utility.hh.

References inUserMode().

inUserMode()

static bool gem5::ArmISA::inUserMode ( CPSR cpsr )

inlinestatic

Definition at line 97 of file utility.hh.

References MODE_EL0T, and MODE_USER.

Referenced by inPrivilegedMode(), gem5::ArmISA::ISA::inUserMode(), and gem5::Iris::ISA::inUserMode().

isAArch64AArch32SystemAccessTrapEL1()

bool gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL1	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 800 of file utility.cc.

References currEL(), EL0, isGenericTimerSystemAccessTrapEL1(), MISCREG_CNTFRQ, and MISCREG_CNTVOFF.

Referenced by AArch64AArch32SystemAccessTrap().

isAArch64AArch32SystemAccessTrapEL2()

bool gem5::ArmISA::isAArch64AArch32SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 924 of file utility.cc.

References currEL(), EL1, isGenericTimerSystemAccessTrapEL2(), MISCREG_CNTFRQ, and MISCREG_CNTVOFF.

Referenced by AArch64AArch32SystemAccessTrap().

isBigEndian64()

bool gem5::ArmISA::isBigEndian64

(

const ThreadContext *

tc

)

Definition at line 382 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, panic, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by byteOrder().

isGenericTimerCommonEL0HypTrap()

bool gem5::ArmISA::isGenericTimerCommonEL0HypTrap	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc,
		ExceptionClass *	ec )

Definition at line 840 of file utility.cc.

References condGenericTimerSystemAccessTrapEL1(), ec, EL1, ELIs32(), MISCREG_HCR_EL2, gem5::ThreadContext::readMiscReg(), and UNKNOWN.

Referenced by isGenericTimerHypTrap().

isGenericTimerCommonEL0SystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerCommonEL0SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 972 of file utility.cc.

References condGenericTimerCommonEL0SystemAccessTrapEL2(), condGenericTimerSystemAccessTrapEL1(), EL1, ELIs32(), MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

isGenericTimerHypTrap()

bool gem5::ArmISA::isGenericTimerHypTrap	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc,
		ExceptionClass *	ec )

Definition at line 814 of file utility.cc.

References currEL(), ec, EL0, EL1, EL2, EL2Enabled(), ELIs32(), isGenericTimerCommonEL0HypTrap(), isGenericTimerPhysHypTrap(), MISCREG_CNTFRQ, MISCREG_CNTP_CTL, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, and MISCREG_CNTV_TVAL.

Referenced by mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

isGenericTimerPhysEL0SystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerPhysEL0SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 985 of file utility.cc.

References condGenericTimerCommonEL1SystemAccessTrapEL2(), condGenericTimerPhysEL1SystemAccessTrapEL2(), MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

isGenericTimerPhysEL1SystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerPhysEL1SystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 1010 of file utility.cc.

References condGenericTimerCommonEL1SystemAccessTrapEL2(), condGenericTimerPhysEL1SystemAccessTrapEL2(), MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

isGenericTimerPhysHypTrap()

bool gem5::ArmISA::isGenericTimerPhysHypTrap	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc,
		ExceptionClass *	ec )

Definition at line 856 of file utility.cc.

References condGenericTimerPhysHypTrap().

Referenced by isGenericTimerHypTrap().

isGenericTimerSystemAccessTrapEL1()

bool gem5::ArmISA::isGenericTimerSystemAccessTrapEL1	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 878 of file utility.cc.

References condGenericTimerSystemAccessTrapEL1(), EL2, EL2Enabled(), ELIs32(), MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isAArch64AArch32SystemAccessTrapEL1().

isGenericTimerSystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerSystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 938 of file utility.cc.

References currEL(), EL0, EL1, isGenericTimerCommonEL0SystemAccessTrapEL2(), isGenericTimerPhysEL0SystemAccessTrapEL2(), isGenericTimerPhysEL1SystemAccessTrapEL2(), isGenericTimerVirtSystemAccessTrapEL2(), MISCREG_CNTFRQ, MISCREG_CNTFRQ_EL0, MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_TVAL_EL0, MISCREG_CNTP_TVAL_S, MISCREG_CNTPCT, MISCREG_CNTPCT_EL0, MISCREG_CNTV_CTL, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_TVAL, MISCREG_CNTV_TVAL_EL0, MISCREG_CNTVCT, and MISCREG_CNTVCT_EL0.

Referenced by isAArch64AArch32SystemAccessTrapEL2().

isGenericTimerSystemAccessTrapEL3()

bool gem5::ArmISA::isGenericTimerSystemAccessTrapEL3	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 1113 of file utility.cc.

References currEL(), EL1, MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_TVAL_EL1, MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscReg().

isGenericTimerVirtSystemAccessTrapEL2()

bool gem5::ArmISA::isGenericTimerVirtSystemAccessTrapEL2	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc )

Definition at line 1034 of file utility.cc.

References condGenericTimerCommonEL1SystemAccessTrapEL2(), EL1, ELIs32(), MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by isGenericTimerSystemAccessTrapEL2().

isHcrxEL2Enabled()

bool gem5::ArmISA::isHcrxEL2Enabled

(

ThreadContext *

tc

)

Definition at line 1368 of file utility.cc.

References EL2Enabled(), EL3, gem5::ArmSystem::has(), gem5::ArmSystem::haveEL(), MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscReg().

isSecure()

bool gem5::ArmISA::isSecure

(

ThreadContext *

tc

)

Definition at line 74 of file utility.cc.

References currEL(), EL3, gem5::ArmSystem::haveEL(), isSecureBelowEL3(), MISCREG_CPSR, MODE_MON, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::ArmISA::ArmStaticInst::generalExceptionsToAArch64(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), gem5::Gicv3CPUInterface::inSecureState(), gem5::ArmISA::SelfDebug::isDebugEnabled(), IsSecureEL2Enabled(), gem5::ArmSemihosting::portProxyImpl(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::PrefetchAbort::routeToHyp(), gem5::ArmISA::SelfDebug::securityStateMatch(), gem5::Iris::ThreadContext::sendFunctional(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::mpam::tagRequest(), gem5::ArmISA::Interrupts::takeInt32(), gem5::ArmISA::Interrupts::takeVirtualInt32(), gem5::ArmISA::SelfDebug::targetAArch32(), gem5::ArmISA::BrkPoint::test(), gem5::trace::TarmacTracerRecord::TraceInstEntry::TraceInstEntry(), gem5::fastmodel::CortexA76TC::translateAddress(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

isSecureAtEL()

bool gem5::ArmISA::isSecureAtEL	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 93 of file utility.cc.

References el, EL3, gem5::ArmSystem::haveEL(), and isSecureBelowEL3().

isSecureBelowEL3()

bool gem5::ArmISA::isSecureBelowEL3

(

ThreadContext *

tc

)

Definition at line 86 of file utility.cc.

References EL3, gem5::ArmSystem::haveEL(), MISCREG_SCR_EL3, ns, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by gem5::ArmISA::SoftwareStep::debugExceptionReturnSS(), gem5::ArmISA::MiscRegLUTEntry::defaultFault(), ELIsInHost(), ELUsingAArch32K(), illegalExceptionReturn(), isSecure(), isSecureAtEL(), gem5::Gicv3CPUInterface::isSecureBelowEL3(), gem5::ArmISA::Interrupts::takeInt64(), and gem5::ArmISA::Interrupts::takeVirtualInt64().

IsSecureEL2Enabled()

bool gem5::ArmISA::IsSecureEL2Enabled

(

ThreadContext *

tc

)

Definition at line 253 of file utility.cc.

References eel2, EL2, EL3, ELIs32(), gem5::ArmSystem::haveEL(), HaveExt(), isSecure(), MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by EL2Enabled(), ELIsInHost(), and illegalExceptionReturn().

issetugidFunc()

static SyscallReturn gem5::ArmISA::issetugidFunc ( SyscallDesc * desc, ThreadContext * tc )

static

Definition at line 86 of file se_workload.cc.

isSnan()

template<class fpType >

static bool gem5::ArmISA::isSnan ( fpType val )

inlinestatic

Definition at line 209 of file vfp.hh.

References fpToBits(), std::isnan(), and gem5::X86ISA::val.

isSP()

static bool gem5::ArmISA::isSP ( RegIndex reg )

inlinestatic

Definition at line 619 of file int.hh.

References gem5::X86ISA::reg, and gem5::ArmISA::int_reg::Spx.

Referenced by gem5::ArmISA::Memory64::Memory64(), gem5::ArmISA::SveContigMemSI::SveContigMemSI(), gem5::ArmISA::SveContigMemSS::SveContigMemSS(), gem5::ArmISA::SveMemPredFillSpill::SveMemPredFillSpill(), gem5::ArmISA::SveMemVecFillSpill::SveMemVecFillSpill(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

isUnpriviledgeAccess()

bool gem5::ArmISA::isUnpriviledgeAccess

(

ThreadContext *

tc

)

Definition at line 1246 of file utility.cc.

References currEL(), EL1, EL2, gem5::ArmSystem::haveEL(), HaveExt(), MISCREG_CPSR, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

isZero()

static bool gem5::ArmISA::isZero ( RegIndex reg )

inlinestatic

Definition at line 631 of file int.hh.

References gem5::X86ISA::reg, and gem5::ArmISA::int_reg::Zero.

itState()

static uint8_t gem5::ArmISA::itState ( CPSR psr )

inlinestatic

Definition at line 191 of file utility.hh.

Referenced by getRestoredITBits(), and gem5::Iris::ThreadContext::pcState().

lockedSnoopHandler()

template<class XC >

static void gem5::ArmISA::lockedSnoopHandler ( ThreadContext * tc, XC * xc, PacketPtr pkt, Addr cacheBlockMask )

inlinestatic

Definition at line 1718 of file isa.cc.

References DPRINTF, gem5::Packet::getAddr(), gem5::ThreadContext::getCpuPtr(), gem5::Packet::isInvalidate(), gem5::Packet::isWrite(), MISCREG_LOCKADDR, MISCREG_LOCKFLAG, MISCREG_SEV_MAILBOX, gem5::Named::name(), and sendEvent().

Referenced by gem5::ArmISA::ISA::handleLockedSnoop(), and gem5::ArmISA::ISA::handleLockedSnoop().

lockedWriteHandler()

template<class XC >

static bool gem5::ArmISA::lockedWriteHandler ( ThreadContext * tc, XC * xc, const RequestPtr & req, Addr cacheBlockMask )

inlinestatic

Definition at line 1797 of file isa.cc.

References gem5::ThreadContext::contextId(), DPRINTF, gem5::ThreadContext::getCpuPtr(), MISCREG_LOCKADDR, MISCREG_LOCKFLAG, gem5::Named::name(), and warn.

Referenced by gem5::ArmISA::ISA::handleLockedWrite(), and gem5::ArmISA::ISA::handleLockedWrite().

longDescFormatInUse()

bool gem5::ArmISA::longDescFormatInUse

(

ThreadContext *

tc

)

Definition at line 140 of file utility.cc.

References gem5::ArmSystem::has(), MISCREG_TTBCR, and gem5::ThreadContext::readMiscReg().

Referenced by gem5::ArmISA::AbortFault< T >::invoke(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

lowFromDouble()

static uint32_t gem5::ArmISA::lowFromDouble ( double val )

inlinestatic

Definition at line 250 of file vfp.hh.

References fpToBits(), and gem5::X86ISA::val.

lsl128()

static void gem5::ArmISA::lsl128 ( uint64_t * r0, uint64_t * r1, uint64_t x0, uint64_t x1, uint32_t shift )

inlinestatic

Definition at line 134 of file fplib.cc.

References gem5::MipsISA::r0, and shift.

Referenced by fp64_muladd(), and fp64_sqrt().

lsl16()

static uint16_t gem5::ArmISA::lsl16 ( uint16_t x, uint32_t shift )

inlinestatic

Definition at line 98 of file fplib.cc.

References shift, and gem5::RiscvISA::x.

Referenced by fp16_add(), and fp16_round_().

lsl32()

static uint32_t gem5::ArmISA::lsl32 ( uint32_t x, uint32_t shift )

inlinestatic

Definition at line 110 of file fplib.cc.

References shift, and gem5::RiscvISA::x.

Referenced by fp16_mul(), fp16_muladd(), fp32_add(), and fp32_round_().

lsl64()

static uint64_t gem5::ArmISA::lsl64 ( uint64_t x, uint32_t shift )

inlinestatic

Definition at line 122 of file fplib.cc.

References shift, and gem5::RiscvISA::x.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), fplibFPToFixedJS(), and FPToFixed_64().

lsr128()

static void gem5::ArmISA::lsr128 ( uint64_t * r0, uint64_t * r1, uint64_t x0, uint64_t x1, uint32_t shift )

inlinestatic

Definition at line 152 of file fplib.cc.

References gem5::MipsISA::r0, and shift.

Referenced by fp64_div(), fp64_muladd(), and fp64_sqrt().

lsr16()

static uint16_t gem5::ArmISA::lsr16 ( uint16_t x, uint32_t shift )

inlinestatic

Definition at line 104 of file fplib.cc.

References shift.

Referenced by fp16_add(), and fp16_round_().

lsr32()

static uint32_t gem5::ArmISA::lsr32 ( uint32_t x, uint32_t shift )

inlinestatic

Definition at line 116 of file fplib.cc.

References shift.

Referenced by fp16_mul(), fp16_muladd(), fp32_add(), and fp32_round_().

lsr64()

static uint64_t gem5::ArmISA::lsr64 ( uint64_t x, uint32_t shift )

inlinestatic

Definition at line 128 of file fplib.cc.

References shift.

Referenced by fp32_mul(), fp32_muladd(), fp64_add(), fp64_round_(), fplibFPToFixedJS(), and FPToFixed_64().

makeDouble()

static double gem5::ArmISA::makeDouble ( uint32_t low, uint32_t high )

inlinestatic

Definition at line 243 of file vfp.hh.

References bitsToFp().

makeSP()

static RegIndex gem5::ArmISA::makeSP ( RegIndex reg )

inlinestatic

Definition at line 605 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::Spx, and gem5::ArmISA::int_reg::X31.

Referenced by gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

makeZero()

static RegIndex gem5::ArmISA::makeZero ( RegIndex reg )

inlinestatic

Definition at line 637 of file int.hh.

References gem5::X86ISA::reg, gem5::ArmISA::int_reg::X31, and gem5::ArmISA::int_reg::Zero.

maskTaggedAddr()

Addr gem5::ArmISA::maskTaggedAddr	(	Addr	addr,
		ThreadContext *	tc,
		ExceptionLevel	el,
		int	topbit )

Definition at line 458 of file utility.cc.

References gem5::X86ISA::addr, gem5::bits(), el, EL1, ELIsInHost(), and mask.

Referenced by gem5::ArmISA::MMU::purifyTaggedAddr(), and purifyTaggedAddr().

mcrMrc14TrapToHyp()

bool gem5::ArmISA::mcrMrc14TrapToHyp	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc,
		uint32_t	iss )

Definition at line 661 of file utility.cc.

References currEL(), EL2, EL2Enabled(), inform, iss, mcrMrcIssExtract(), MISCREG_DBGDRAR, MISCREG_DBGDSAR, MISCREG_DBGOSDLR, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR, MISCREG_DBGPRCR, MISCREG_HCPTR, MISCREG_HCR_EL2, MISCREG_HDCR, MISCREG_HSTR, MISCREG_JIDR, MISCREG_JMCR, MISCREG_JOSCR, MISCREG_TEECR, MISCREG_TEEHBR, opc2, gem5::ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

mcrMrc15Trap()

Fault gem5::ArmISA::mcrMrc15Trap	(	const MiscRegIndex	misc_reg,
		ExtMachInst	mach_inst,
		ThreadContext *	tc,
		uint32_t	imm )

Definition at line 504 of file utility.cc.

References AArch64AArch32SystemAccessTrap(), ec, imm, mcrMrc15TrapToHyp(), and TRAPPED_CP15_MCR_MRC.

Referenced by gem5::McrMrcImplDefined::execute(), and gem5::McrMrcMiscInst::execute().

mcrMrc15TrapToHyp()

bool gem5::ArmISA::mcrMrc15TrapToHyp	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc,
		uint32_t	iss,
		ExceptionClass *	ec )

Definition at line 514 of file utility.cc.

References currEL(), ec, EL2, EL2Enabled(), isGenericTimerHypTrap(), iss, mcrMrcIssExtract(), MISCREG_ACTLR, MISCREG_ADFSR, MISCREG_AIDR, MISCREG_AIFSR, MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_CNTFRQ, MISCREG_CNTV_TVAL, MISCREG_CNTVCT, MISCREG_CONTEXTIDR, MISCREG_CPACR, MISCREG_CSSELR, MISCREG_CTR, MISCREG_DACR, MISCREG_DCCIMVAC, MISCREG_DCCISW, MISCREG_DCCMVAC, MISCREG_DCCMVAU, MISCREG_DCCSW, MISCREG_DCIMVAC, MISCREG_DCISW, MISCREG_DFAR, MISCREG_DFSR, MISCREG_DTLBIALL, MISCREG_DTLBIASID, MISCREG_DTLBIMVA, MISCREG_HCPTR, MISCREG_HCR_EL2, MISCREG_HDCR, MISCREG_HSTR, MISCREG_ICC_ASGI1R, MISCREG_ICC_SGI0R, MISCREG_ICC_SGI1R, MISCREG_ICIALLU, MISCREG_ICIALLUIS, MISCREG_ICIMVAU, MISCREG_ID_AFR0, MISCREG_ID_DFR0, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2, MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_ISAR6, MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3, MISCREG_ID_MMFR4, MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_IFAR, MISCREG_IFSR, MISCREG_ITLBIALL, MISCREG_ITLBIASID, MISCREG_ITLBIMVA, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PMCR, MISCREG_PRRR, MISCREG_REVIDR, MISCREG_SCTLR, MISCREG_TCMTR, MISCREG_TLBIALL, MISCREG_TLBIALLIS, MISCREG_TLBIASID, MISCREG_TLBIASIDIS, MISCREG_TLBIMVA, MISCREG_TLBIMVAA, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVAAL, MISCREG_TLBIMVAALIS, MISCREG_TLBIMVAIS, MISCREG_TLBIMVAL, MISCREG_TLBIMVALIS, MISCREG_TLBTR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, opc2, gem5::ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

Referenced by mcrMrc15Trap().

mcrMrcIssBuild()

static uint32_t gem5::ArmISA::mcrMrcIssBuild ( bool isRead, uint32_t crm, RegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2 )

inlinestatic

Definition at line 236 of file utility.hh.

References opc2, and rt.

mcrMrcIssExtract()

static void gem5::ArmISA::mcrMrcIssExtract ( uint32_t iss, bool & isRead, uint32_t & crm, RegIndex & rt, uint32_t & crn, uint32_t & opc1, uint32_t & opc2 )

inlinestatic

Definition at line 248 of file utility.hh.

References iss, opc2, and rt.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), and mcrrMrrc15TrapToHyp().

mcrrMrrc15Trap()

Fault gem5::ArmISA::mcrrMrrc15Trap	(	const MiscRegIndex	misc_reg,
		ExtMachInst	mach_inst,
		ThreadContext *	tc,
		uint32_t	imm )

Definition at line 716 of file utility.cc.

References AArch64AArch32SystemAccessTrap(), ec, imm, mcrrMrrc15TrapToHyp(), and TRAPPED_CP15_MCRR_MRRC.

mcrrMrrc15TrapToHyp()

bool gem5::ArmISA::mcrrMrrc15TrapToHyp	(	const MiscRegIndex	misc_reg,
		ThreadContext *	tc,
		uint32_t	iss,
		ExceptionClass *	ec )

Definition at line 726 of file utility.cc.

References currEL(), ec, EL2, EL2Enabled(), isGenericTimerHypTrap(), iss, mcrMrcIssExtract(), MISCREG_ADFSR, MISCREG_AIFSR, MISCREG_CNTFRQ, MISCREG_CNTV_TVAL, MISCREG_CNTVCT, MISCREG_CONTEXTIDR, MISCREG_DACR, MISCREG_DFAR, MISCREG_DFSR, MISCREG_HCR_EL2, MISCREG_HSTR, MISCREG_IFAR, MISCREG_IFSR, MISCREG_MAIR0, MISCREG_MAIR1, MISCREG_NMRR, MISCREG_PRRR, MISCREG_SCTLR, MISCREG_TTBCR, MISCREG_TTBR0, MISCREG_TTBR1, opc2, gem5::ThreadContext::readMiscReg(), rt, and unflattenMiscReg().

Referenced by mcrrMrrc15Trap().

mcrrMrrcIssBuild()

static uint32_t gem5::ArmISA::mcrrMrrcIssBuild ( bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2, uint32_t opc1 )

inlinestatic

Definition at line 260 of file utility.hh.

References rt.

modeConv()

static int gem5::ArmISA::modeConv ( FPSCR fpscr )

static

Definition at line 2217 of file fplib.cc.

References FPLIB_FZ16, and gem5::RiscvISA::x.

Referenced by fplibAdd(), fplibAdd(), fplibAdd(), fplibCompare(), fplibCompare(), fplibCompare(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGE(), fplibCompareGE(), fplibCompareGT(), fplibCompareGT(), fplibCompareGT(), fplibCompareUN(), fplibCompareUN(), fplibCompareUN(), fplibConvert(), fplibConvert(), fplibConvert(), fplibDiv(), fplibDiv(), fplibDiv(), fplibFPToFixed(), fplibFPToFixed(), fplibFPToFixed(), fplibMax(), fplibMax(), fplibMax(), fplibMin(), fplibMin(), fplibMin(), fplibMul(), fplibMul(), fplibMul(), fplibMulAdd(), fplibMulAdd(), fplibMulAdd(), fplibMulX(), fplibMulX(), fplibMulX(), fplibRecipEstimate(), fplibRecipEstimate(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRecpX(), fplibRecpX(), fplibRecpX(), fplibRoundInt(), fplibRoundInt(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtEstimate(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), fplibScale(), fplibScale(), fplibScale(), fplibSqrt(), fplibSqrt(), fplibSqrt(), fplibSub(), fplibSub(), fplibSub(), fplibTrigMulAdd(), fplibTrigMulAdd(), fplibTrigMulAdd(), fplibTrigSMul(), fplibTrigSMul(), and fplibTrigSMul().

modified_imm()

static uint32_t gem5::ArmISA::modified_imm ( uint8_t ctrlImm, uint8_t dataImm )

inlinestatic

Definition at line 65 of file pred_inst.hh.

mul62x62()

static void gem5::ArmISA::mul62x62 ( uint64_t * x0, uint64_t * x1, uint64_t a, uint64_t b )

inlinestatic

Definition at line 170 of file fplib.cc.

References a, gem5::MipsISA::a0, a1, b, gem5::QARMA::b0, gem5::QARMA::b1, and mask.

Referenced by fp64_div(), fp64_mul(), fp64_muladd(), and fp64_sqrt().

mul64x32()

static void gem5::ArmISA::mul64x32 ( uint64_t * x0, uint64_t * x1, uint64_t a, uint32_t b )

inlinestatic

Definition at line 188 of file fplib.cc.

References a, b, t0, and t1.

Referenced by fp64_div(), and fp64_sqrt().

number_of_ones()

static unsigned int gem5::ArmISA::number_of_ones ( int32_t val )

inlinestatic

Definition at line 56 of file macromem.hh.

References i, and gem5::X86ISA::val.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp().

opModeIsH()

static bool gem5::ArmISA::opModeIsH ( OperatingMode mode )

inlinestatic

Definition at line 387 of file types.hh.

References mode, MODE_EL1H, MODE_EL2H, and MODE_EL3H.

opModeIsT()

static bool gem5::ArmISA::opModeIsT ( OperatingMode mode )

inlinestatic

Definition at line 393 of file types.hh.

References mode, MODE_EL0T, MODE_EL1T, MODE_EL2T, and MODE_EL3T.

Referenced by gem5::ArmISA::ArmFaultVals< T >::offset64().

opModeToEL()

static ExceptionLevel gem5::ArmISA::opModeToEL ( OperatingMode mode )

inlinestatic

Definition at line 400 of file types.hh.

References EL0, EL1, EL2, EL3, mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, MODE_USER, and panic.

Referenced by badMode(), badMode32(), currEL(), currEL(), gem5::ArmISA::ISA::currEL(), gem5::ArmISA::IntRegClassOps::flatten(), getRestoredITBits(), illegalExceptionReturn(), and gem5::ArmISA::ArmFault::update().

prepFpState()

VfpSavedState gem5::ArmISA::prepFpState

(

uint32_t

rMode

)

Definition at line 183 of file vfp.cc.

References FeAllExceptions, FeRoundDown, FeRoundNearest, FeRoundUpward, FeRoundZero, prepFpState(), rMode, VfpRoundDown, VfpRoundNearest, VfpRoundUpward, and VfpRoundZero.

Referenced by gem5::ArmISA::FpOp::binaryOp(), prepFpState(), gem5::ArmISA::FpOp::ternaryOp(), and gem5::ArmISA::FpOp::unaryOp().

preUnflattenMiscReg()

void gem5::ArmISA::preUnflattenMiscReg

(

)

Definition at line 708 of file misc.cc.

References i, lookUpMiscReg, MISCREG_BANKED, MISCREG_BANKED_CHILD, NUM_MISCREGS, gem5::X86ISA::reg, and unflattenResultMiscReg.

Referenced by gem5::ArmISA::ISA::ISA().

purifyTaggedAddr() [1/2]

Addr gem5::ArmISA::purifyTaggedAddr	(	Addr	addr,
		ThreadContext *	tc,
		ExceptionLevel	el,
		bool	is_instr )

Definition at line 483 of file utility.cc.

References gem5::X86ISA::addr, el, MISCREG_TCR_EL1, purifyTaggedAddr(), and gem5::ThreadContext::readMiscReg().

purifyTaggedAddr() [2/2]

Addr gem5::ArmISA::purifyTaggedAddr	(	Addr	addr,
		ThreadContext *	tc,
		ExceptionLevel	el,
		TCR	tcr,
		bool	isInstr )

Removes the tag from tagged addresses if that mode is enabled.

Parameters

addr	The address to be purified.
tc	The thread context.
el	The controlled exception level.

Returns

The purified address.

Definition at line 473 of file utility.cc.

References gem5::X86ISA::addr, gem5::bits(), computeAddrTop(), el, and maskTaggedAddr().

Referenced by gem5::ArmISA::ArmFault::invoke64(), purifyTaggedAddr(), and gem5::ArmISA::TableWalker::walk().

readMPIDR()

RegVal gem5::ArmISA::readMPIDR	(	ArmSystem *	arm_sys,
		ThreadContext *	tc )

This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems)

Definition at line 147 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL2Enabled(), EL3, getMPIDR(), MISCREG_VMPIDR_EL2, panic, gem5::ThreadContext::readMiscReg(), and warn_once.

Referenced by gem5::ArmISA::ISA::readMiscReg().

readVecElem()

XReg gem5::ArmISA::readVecElem ( VReg src, int index, int eSize )

inline

Read a single NEON vector element.

Definition at line 98 of file neon64_mem.hh.

References data, gem5::ArmISA::VReg::hi, gem5::MipsISA::index, and gem5::ArmISA::VReg::lo.

recipEstimate()

static double gem5::ArmISA::recipEstimate ( double a )

static

Definition at line 840 of file vfp.cc.

References a, q, and recipEstimate().

Referenced by fpRecipEstimate(), recipEstimate(), and unsignedRecipEstimate().

recipSqrtEstimate()

static double gem5::ArmISA::recipSqrtEstimate ( double a )

static

Definition at line 753 of file vfp.cc.

References a, and recipSqrtEstimate().

Referenced by fprSqrtEstimate(), recipSqrtEstimate(), and unsignedRSqrtEstimate().

regimeToStr()

static const char * gem5::ArmISA::regimeToStr ( TranslationRegime regime )

inlinestatic

Definition at line 474 of file types.hh.

References EL10, EL2, EL20, and EL3.

Referenced by gem5::ArmISA::TLB::insert(), gem5::ArmISA::TLB::lookup(), and gem5::ArmISA::TlbEntry::print().

resetCPSR()

static CPSR gem5::ArmISA::resetCPSR ( ArmSystem * system )

static

Definition at line 2843 of file misc.cc.

References EL1, EL2, EL3, gem5::FullSystem, MODE_EL1H, MODE_EL2H, MODE_EL3H, MODE_USER, panic, and gem5::X86ISA::system.

Referenced by gem5::ArmISA::ISA::initializeMiscRegMetadata().

rotate_imm()

static uint32_t gem5::ArmISA::rotate_imm ( uint32_t immValue, uint32_t rotateValue )

inlinestatic

Definition at line 57 of file pred_inst.hh.

Referenced by gem5::ArmISA::PredImmOp::PredImmOp().

roundNEven()

template<typename T >

static T gem5::ArmISA::roundNEven ( T a )

inlinestatic

Definition at line 769 of file vfp.hh.

References a, and gem5::X86ISA::val.

roundPage()

Addr gem5::ArmISA::roundPage

(

Addr

addr

)

Definition at line 498 of file utility.cc.

References gem5::X86ISA::addr, and PageBytes.

s1TranslationRegime()

ExceptionLevel gem5::ArmISA::s1TranslationRegime	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 238 of file utility.cc.

References el, EL0, EL1, EL2, EL3, ELIs32(), ELIsInHost(), gem5::ArmSystem::haveEL(), HaveExt(), MISCREG_SCR_EL3, and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by addPAC(), addPACDA(), addPACDB(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), authIB(), calculateBottomPACBit(), calculateTBI(), computeAddrTop(), and SPAlignmentCheckEnabled().

sendEvent()

void gem5::ArmISA::sendEvent

(

ThreadContext *

tc

)

Send an event (SEV) to a specific PE if there isn't already a pending event.

Definition at line 65 of file utility.cc.

References gem5::ThreadContext::getCpuPtr(), INT_SEV, MISCREG_SEV_MAILBOX, gem5::BaseCPU::postInterrupt(), gem5::ThreadContext::readMiscReg(), and gem5::ThreadContext::threadId().

Referenced by gem5::GenericTimer::CoreTimers::eventStreamCallback(), gem5::ArmISA::ISA::globalClearExclusive(), gem5::ArmISA::ISA::globalClearExclusive(), lockedSnoopHandler(), gem5::Bridge::BridgeRequestPort::schedTimingReq(), gem5::SerialLink::SerialLinkRequestPort::schedTimingReq(), gem5::Bridge::BridgeResponsePort::schedTimingResp(), gem5::SerialLink::SerialLinkResponsePort::schedTimingResp(), gem5::Bridge::BridgeRequestPort::trySendTiming(), gem5::Bridge::BridgeResponsePort::trySendTiming(), gem5::SerialLink::SerialLinkRequestPort::trySendTiming(), and gem5::SerialLink::SerialLinkResponsePort::trySendTiming().

set_fpscr()

static void gem5::ArmISA::set_fpscr ( FPSCR & fpscr, int flags )

static

Definition at line 2225 of file fplib.cc.

References flags, FPLIB_DZC, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, and FPLIB_UFC.

Referenced by fplibCompareEQ(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGE(), fplibCompareGE(), fplibCompareGT(), fplibCompareGT(), fplibCompareGT(), fplibCompareUN(), fplibCompareUN(), and fplibCompareUN().

set_fpscr0()

static void gem5::ArmISA::set_fpscr0 ( FPSCR & fpscr, int flags )

static

Definition at line 1915 of file fplib.cc.

References flags, FPLIB_DZC, FPLIB_IDC, FPLIB_IOC, FPLIB_IXC, FPLIB_OFC, and FPLIB_UFC.

Referenced by fplibAdd(), fplibAdd(), fplibAdd(), fplibCompare(), fplibCompare(), fplibCompare(), fplibConvert(), fplibConvert(), fplibConvert(), fplibDiv(), fplibDiv(), fplibDiv(), fplibFixedToFP(), fplibFPToFixed(), fplibFPToFixed(), fplibFPToFixed(), fplibFPToFixedJS(), fplibMax(), fplibMax(), fplibMax(), fplibMin(), fplibMin(), fplibMin(), fplibMul(), fplibMul(), fplibMul(), fplibMulAdd(), fplibMulAdd(), fplibMulAdd(), fplibMulX(), fplibMulX(), fplibMulX(), fplibRecipEstimate(), fplibRecipEstimate(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRecpX(), fplibRecpX(), fplibRecpX(), fplibRoundInt(), fplibRoundInt(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtEstimate(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), fplibScale(), fplibScale(), fplibScale(), fplibSqrt(), fplibSqrt(), fplibSqrt(), fplibSub(), fplibSub(), fplibSub(), fplibTrigMulAdd(), fplibTrigMulAdd(), fplibTrigMulAdd(), fplibTrigSMul(), fplibTrigSMul(), and fplibTrigSMul().

setFPExceptions()

static void gem5::ArmISA::setFPExceptions ( int exceptions )

inlinestatic

Definition at line 262 of file vfp.hh.

References FeAllExceptions.

Referenced by vfpFpToFixed().

setTLSFunc32()

static SyscallReturn gem5::ArmISA::setTLSFunc32 ( SyscallDesc * desc, ThreadContext * tc, uint32_t tlsPtr )

static

Target set_tls() handler.

Definition at line 131 of file se_workload.cc.

References gem5::ArmLinuxProcess32::commPage, MISCREG_TPIDRURO, gem5::ThreadContext::setMiscReg(), and gem5::PortProxy::writeBlob().

setTLSFunc64()

static SyscallReturn gem5::ArmISA::setTLSFunc64 ( SyscallDesc * desc, ThreadContext * tc, uint32_t tlsPtr )

static

Definition at line 140 of file se_workload.cc.

References MISCREG_TPIDRRO_EL0, and gem5::ThreadContext::setMiscReg().

setVfpMicroFlags()

template<class T >

static void gem5::ArmISA::setVfpMicroFlags ( VfpMicroMode mode, T & flags )

inlinestatic

Definition at line 66 of file vfp.hh.

References flags, mode, VfpFirstMicroop, VfpLastMicroop, VfpMicroop, and VfpNotAMicroop.

Referenced by gem5::ArmISA::FpRegImmOp::FpRegImmOp(), gem5::ArmISA::FpRegRegImmOp::FpRegRegImmOp(), gem5::ArmISA::FpRegRegOp::FpRegRegOp(), gem5::ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), gem5::ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), gem5::ArmISA::FpRegRegRegOp::FpRegRegRegOp(), and gem5::ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp().

simd_modified_imm()

static uint64_t gem5::ArmISA::simd_modified_imm ( bool op, uint8_t cmode, uint8_t data, bool & immValid, bool isAarch64 = false )

inlinestatic

Definition at line 88 of file pred_inst.hh.

References gem5::bits(), data, i, and gem5::X86ISA::op.

snsBankedIndex() [1/2]

int gem5::ArmISA::snsBankedIndex	(	MiscRegIndex	reg,
		ThreadContext *	tc )

Definition at line 672 of file misc.cc.

References MISCREG_SCR_EL3, gem5::ThreadContext::readMiscReg(), gem5::X86ISA::reg, and snsBankedIndex().

Referenced by gem5::ArmISA::ArmStaticInst::checkSETENDEnabled(), gem5::ArmISA::TableWalker::memAttrs(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::ArmISA::TableWalker::processWalk(), gem5::ArmISA::TableWalker::processWalkLPAE(), snsBankedIndex(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

snsBankedIndex() [2/2]

int gem5::ArmISA::snsBankedIndex	(	MiscRegIndex	reg,
		ThreadContext *	tc,
		bool	ns )

Definition at line 679 of file misc.cc.

References EL3, gem5::ArmSystem::haveEL(), gem5::ArmSystem::highestELIs64(), lookUpMiscReg, MISCREG_BANKED, ns, and gem5::X86ISA::reg.

snsBankedIndex64()

int gem5::ArmISA::snsBankedIndex64	(	MiscRegIndex	reg,
		ThreadContext *	tc )

Definition at line 690 of file misc.cc.

References gem5::ThreadContext::getIsaPtr(), MISCREG_SCR_EL3, gem5::ThreadContext::readMiscReg(), and gem5::X86ISA::reg.

SPAlignmentCheckEnabled()

bool gem5::ArmISA::SPAlignmentCheckEnabled

(

ThreadContext *

tc

)

Definition at line 1264 of file utility.cc.

References currEL(), EL0, EL1, EL2, EL3, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL2, MISCREG_SCTLR_EL3, panic, gem5::ThreadContext::readMiscReg(), and s1TranslationRegime().

stripPAC()

void gem5::ArmISA::stripPAC	(	ThreadContext *	tc,
		uint64_t	A,
		bool	data,
		uint64_t *	out )

Definition at line 866 of file pauth_helpers.cc.

References gem5::bits(), calculateBottomPACBit(), calculateTBI(), currEL(), data, el, mask, and tbi.

sub128()

static void gem5::ArmISA::sub128 ( uint64_t * x0, uint64_t * x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1 )

inlinestatic

Definition at line 205 of file fplib.cc.

References gem5::MipsISA::a0, a1, gem5::QARMA::b0, and gem5::QARMA::b1.

Referenced by fp64_div(), and fp64_muladd().

SubBitUnion() [1/3]

gem5::ArmISA::SubBitUnion	(	cond_iss	,
		24	,
		0	)

SubBitUnion() [2/3]

gem5::ArmISA::SubBitUnion	(	el1	,
		62	,
		48	)

SubBitUnion() [3/3]

gem5::ArmISA::SubBitUnion	(	puswl	,
		24	,
		20	)

sveDecodePredCount()

unsigned int gem5::ArmISA::sveDecodePredCount	(	uint8_t	imm,
		unsigned int	num_elems )

Returns the actual number of elements active for PTRUE(S) instructions.

Parameters

imm	5-bit immediate encoding the predicate pattern.
num_elems	Current number of elements per vector (depending on current vector length and element size).

Definition at line 913 of file sve.cc.

References imm.

sveDisasmPredCountImm()

std::string gem5::ArmISA::sveDisasmPredCountImm

(

uint8_t

imm

)

Returns the symbolic name associated with pattern imm for PTRUE(S) instructions.

Definition at line 881 of file sve.cc.

References imm.

Referenced by gem5::ArmISA::SveElemCountOp::generateDisassembly(), and gem5::ArmISA::SvePtrueOp::generateDisassembly().

sveExpandFpImmAddSub()

uint64_t gem5::ArmISA::sveExpandFpImmAddSub	(	uint8_t	imm,
		uint8_t	size )

Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR).

Parameters

imm	1-bit immediate.
size	Encoding of the vector element size.

Returns

Encoding of the expanded value.

Definition at line 956 of file sve.cc.

References imm, and panic.

sveExpandFpImmMaxMin()

uint64_t gem5::ArmISA::sveExpandFpImmMaxMin	(	uint8_t	imm,
		uint8_t	size )

Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM).

Parameters

imm	1-bit immediate.
size	Encoding of the vector element size.

Returns

Encoding of the expanded value.

Definition at line 978 of file sve.cc.

References imm, and panic.

sveExpandFpImmMul()

uint64_t gem5::ArmISA::sveExpandFpImmMul	(	uint8_t	imm,
		uint8_t	size )

Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL).

Parameters

imm	1-bit immediate.
size	Encoding of the vector element size.

Returns

Encoding of the expanded value.

Definition at line 997 of file sve.cc.

References imm, and panic.

svePredTypeToStr()

const char * gem5::ArmISA::svePredTypeToStr

(

SvePredType

pt

)

Returns the specifier for the predication type pt as a string.

Definition at line 48 of file sve.cc.

References MERGE, gem5::pt, and ZERO.

Referenced by gem5::ArmISA::SveBinConstrPredOp::generateDisassembly().

syncVecElemsToRegs()

void gem5::ArmISA::syncVecElemsToRegs

(

ThreadContext *

tc

)

Definition at line 1346 of file utility.cc.

References gem5::ThreadContext::getReg(), NumVecElemPerVecReg, NumVecRegs, gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::ThreadContext::setReg(), vecElemClass, and vecRegClass.

Referenced by gem5::ArmISA::ArmFault::invoke(), and gem5::ArmV8KvmCPU::updateKvmState().

syncVecRegsToElems()

void gem5::ArmISA::syncVecRegsToElems

(

ThreadContext *

tc

)

Definition at line 1334 of file utility.cc.

References gem5::ThreadContext::getReg(), NumVecElemPerVecReg, NumVecRegs, gem5::X86ISA::reg, gem5::PowerISA::ri, gem5::ThreadContext::setReg(), vecElemClass, and vecRegClass.

Referenced by gem5::ArmISA::ArmFault::invoke(), and gem5::ArmV8KvmCPU::updateThreadContext().

sysctlFunc()

static SyscallReturn gem5::ArmISA::sysctlFunc ( SyscallDesc * desc, ThreadContext * tc, VPtr<> namep, size_t nameLen, VPtr<> oldp, VPtr<> oldlenp, VPtr<> newp, size_t newlen )

static

Definition at line 93 of file se_workload.cc.

References gem5::BufferArg::bufferPtr(), gem5::BaseBufferArg::copyIn(), and gem5::BaseBufferArg::copyOut().

testPredicate()

bool gem5::ArmISA::testPredicate ( uint32_t nz, uint32_t c, uint32_t v, ConditionCode code )

inline

Definition at line 65 of file utility.hh.

References c, COND_AL, COND_CC, COND_CS, COND_EQ, COND_GE, COND_GT, COND_HI, COND_LE, COND_LS, COND_LT, COND_MI, COND_NE, COND_PL, COND_UC, COND_VC, COND_VS, n, nz, panic, v, and z.

translationEl()

ExceptionLevel gem5::ArmISA::translationEl

(

TranslationRegime

regime

)

Definition at line 1398 of file utility.cc.

References EL1, EL10, EL2, EL20, and EL3.

Referenced by gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

translationRegime()

TranslationRegime gem5::ArmISA::translationRegime	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 1379 of file utility.cc.

References el, EL0, EL1, EL10, EL2, EL20, EL3, ELIsInHost(), and panic.

Referenced by gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::ArmISA::TableWalker::walk().

trapPACUse()

Fault gem5::ArmISA::trapPACUse	(	ThreadContext *	tc,
		ExceptionLevel	el )

Definition at line 117 of file pauth_helpers.cc.

References currEL(), EL0, EL2, EL3, gem5::ArmSystem::haveEL(), and gem5::NoFault.

Referenced by addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), and authIB().

truncPage()

Addr gem5::ArmISA::truncPage

(

Addr

addr

)

Definition at line 492 of file utility.cc.

References gem5::X86ISA::addr, and PageBytes.

unameFunc32()

static SyscallReturn gem5::ArmISA::unameFunc32 ( SyscallDesc * desc, ThreadContext * tc, VPtr< Linux::utsname > name )

static

Target uname() handler.

Definition at line 101 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

Referenced by gem5::ArmISA::SyscallTable32::SyscallTable32().

unameFunc64()

static SyscallReturn gem5::ArmISA::unameFunc64 ( SyscallDesc * desc, ThreadContext * tc, VPtr< Linux::utsname > name )

static

Target uname() handler.

Definition at line 116 of file se_workload.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

Referenced by gem5::ArmISA::SyscallTable64::SyscallTable64().

unflattenMiscReg()

int gem5::ArmISA::unflattenMiscReg

(

int

reg

)

Definition at line 724 of file misc.cc.

References gem5::X86ISA::reg, and unflattenResultMiscReg.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::PMU::readMiscReg(), gem5::ArmISA::PMU::readMiscRegInt(), gem5::ArmISA::ISA::setMiscReg(), and gem5::ArmISA::PMU::setMiscReg().

unknownMode()

static bool gem5::ArmISA::unknownMode ( OperatingMode mode )

inlinestatic

Definition at line 429 of file types.hh.

References mode, MODE_ABORT, MODE_EL0T, MODE_EL1H, MODE_EL1T, MODE_EL2H, MODE_EL2T, MODE_EL3H, MODE_EL3T, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, and MODE_USER.

Referenced by badMode(), and illegalExceptionReturn().

unknownMode32()

static bool gem5::ArmISA::unknownMode32 ( OperatingMode mode )

inlinestatic

Definition at line 455 of file types.hh.

References mode, MODE_ABORT, MODE_FIQ, MODE_HYP, MODE_IRQ, MODE_MON, MODE_SVC, MODE_SYSTEM, MODE_UNDEFINED, and MODE_USER.

Referenced by badMode32(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), and illegalExceptionReturn().

unsignedRecipEstimate()

uint32_t gem5::ArmISA::unsignedRecipEstimate

(

uint32_t

op

)

Definition at line 889 of file vfp.cc.

References gem5::bits(), gem5::X86ISA::op, recipEstimate(), and unsignedRecipEstimate().

Referenced by unsignedRecipEstimate().

unsignedRSqrtEstimate()

uint32_t gem5::ArmISA::unsignedRSqrtEstimate

(

uint32_t

op

)

Definition at line 814 of file vfp.cc.

References gem5::bits(), gem5::X86ISA::op, recipSqrtEstimate(), and unsignedRSqrtEstimate().

Referenced by unsignedRSqrtEstimate().

upperAndLowerRange()

bool gem5::ArmISA::upperAndLowerRange ( ThreadContext * tc, ExceptionLevel el )

inline

Definition at line 57 of file pauth_helpers.hh.

References el, EL0, EL1, EL2, MISCREG_HCR_EL2, and gem5::ThreadContext::readMiscReg().

Referenced by addPAC(), calculateBottomPACBit(), and calculateTBI().

useVMID()

static bool gem5::ArmISA::useVMID ( TranslationRegime regime )

inlinestatic

Definition at line 376 of file utility.hh.

References EL10.

Referenced by gem5::ArmISA::TlbEntry::match(), gem5::ArmISA::TLBIASID::match(), and gem5::ArmISA::TLBIVMALL::match().

vcvtFpDFpH()

uint16_t gem5::ArmISA::vcvtFpDFpH	(	FPSCR &	fpscr,
		bool	flush,
		bool	defaultNan,
		uint32_t	rMode,
		bool	ahp,
		double	op )

Definition at line 585 of file vfp.cc.

References ahp, gem5::X86ISA::op, rMode, vcvtFpDFpH(), and vcvtFpFpH().

Referenced by vcvtFpDFpH().

vcvtFpFpH()

static uint16_t gem5::ArmISA::vcvtFpFpH ( FPSCR & fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble )

inlinestatic

Definition at line 405 of file vfp.cc.

References ahp, gem5::bits(), mask, mode, gem5::replaceBits(), rMode, vcvtFpFpH(), VfpRoundDown, VfpRoundNearest, and VfpRoundUpward.

Referenced by vcvtFpDFpH(), vcvtFpFpH(), and vcvtFpSFpH().

vcvtFpHFp()

static uint64_t gem5::ArmISA::vcvtFpHFp ( FPSCR & fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble )

inlinestatic

Definition at line 593 of file vfp.cc.

References ahp, gem5::bits(), mask, gem5::X86ISA::op, gem5::replaceBits(), and vcvtFpHFp().

Referenced by vcvtFpHFp(), vcvtFpHFpD(), and vcvtFpHFpS().

vcvtFpHFpD()

double gem5::ArmISA::vcvtFpHFpD	(	FPSCR &	fpscr,
		bool	defaultNan,
		bool	ahp,
		uint16_t	op )

Definition at line 655 of file vfp.cc.

References ahp, gem5::X86ISA::op, vcvtFpHFp(), and vcvtFpHFpD().

Referenced by vcvtFpHFpD().

vcvtFpHFpS()

float gem5::ArmISA::vcvtFpHFpS	(	FPSCR &	fpscr,
		bool	defaultNan,
		bool	ahp,
		uint16_t	op )

Definition at line 665 of file vfp.cc.

References ahp, gem5::X86ISA::op, vcvtFpHFp(), and vcvtFpHFpS().

Referenced by vcvtFpHFpS().

vcvtFpSFpH()

uint16_t gem5::ArmISA::vcvtFpSFpH	(	FPSCR &	fpscr,
		bool	flush,
		bool	defaultNan,
		uint32_t	rMode,
		bool	ahp,
		float	op )

Definition at line 577 of file vfp.cc.

References ahp, gem5::X86ISA::op, rMode, vcvtFpFpH(), and vcvtFpSFpH().

Referenced by vcvtFpSFpH().

vfp_modified_imm()

static uint64_t gem5::ArmISA::vfp_modified_imm ( uint8_t data, FpDataType dtype )

inlinestatic

Definition at line 171 of file pred_inst.hh.

References gem5::bits(), data, Fp16, Fp32, Fp64, and panic.

vfpFlushToZero() [1/2]

template<class fpType >

static void gem5::ArmISA::vfpFlushToZero ( FPSCR & fpscr, fpType & op )

inlinestatic

Definition at line 144 of file vfp.hh.

References flushToZero, and gem5::X86ISA::op.

Referenced by vfpFlushToZero().

vfpFlushToZero() [2/2]

template<class fpType >

static void gem5::ArmISA::vfpFlushToZero ( FPSCR & fpscr, fpType & op1, fpType & op2 )

inlinestatic

Definition at line 153 of file vfp.hh.

References vfpFlushToZero().

vfpFpToFixed()

template<typename T >

uint64_t gem5::ArmISA::vfpFpToFixed	(	T	val,
		bool	isSigned,
		uint8_t	width,
		uint8_t	imm,
		bool	useRmode = true,
		VfpRoundingMode	roundMode = VfpRoundZero,
		bool	aarch64 = false )

Definition at line 269 of file vfp.hh.

References aarch64, error, FeAllExceptions, FeInexact, FeInvalid, FeRoundDown, FeRoundNearest, FeRoundUpward, FeRoundZero, imm, mask, panic, setFPExceptions(), gem5::X86ISA::val, VfpRoundAway, VfpRoundDown, VfpRoundNearest, VfpRoundUpward, VfpRoundZero, and width.

vfpSFixedToFpD()

double gem5::ArmISA::vfpSFixedToFpD	(	bool	flush,
		bool	defaultNan,
		int64_t	val,
		uint8_t	width,
		uint8_t	imm )

Definition at line 732 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, vfpSFixedToFpD(), and width.

Referenced by vfpSFixedToFpD().

vfpSFixedToFpS()

float gem5::ArmISA::vfpSFixedToFpS	(	bool	flush,
		bool	defaultNan,
		int64_t	val,
		uint8_t	width,
		uint8_t	imm )

Definition at line 693 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, vfpSFixedToFpS(), and width.

Referenced by vfpSFixedToFpS().

vfpUFixedToFpD()

double gem5::ArmISA::vfpUFixedToFpD	(	bool	flush,
		bool	defaultNan,
		uint64_t	val,
		uint8_t	width,
		uint8_t	imm )

Definition at line 713 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, vfpUFixedToFpD(), and width.

Referenced by vfpUFixedToFpD().

vfpUFixedToFpS()

float gem5::ArmISA::vfpUFixedToFpS	(	bool	flush,
		bool	defaultNan,
		uint64_t	val,
		uint8_t	width,
		uint8_t	imm )

Definition at line 675 of file vfp.cc.

References FeAllExceptions, FeRoundNearest, fixDivDest(), imm, panic, gem5::X86ISA::scale, gem5::X86ISA::val, vfpUFixedToFpS(), and width.

Referenced by vfpUFixedToFpS().

writeVecElem()

void gem5::ArmISA::writeVecElem ( VReg * dest, XReg src, int index, int eSize )

inline

Write a single NEON vector element leaving the others untouched.

Definition at line 64 of file neon64_mem.hh.

References gem5::ArmISA::VReg::hi, gem5::MipsISA::index, and gem5::ArmISA::VReg::lo.

Variable Documentation

a

Bitfield< 1 > gem5::ArmISA::a

Definition at line 66 of file misc_types.hh.

Referenced by a(), gem5::SMMUTranslationProcess::abortTransaction(), gem5::AddrRange::addIntlvBits(), addSubColumns(), gem5::ArmISA::Crypto::aesFFMul(), gem5::ArmISA::Crypto::aesFFMul2(), gem5::SMMUv3DeviceInterface::atsRecvAtomic(), b(), gem5::prefetch::Base::blockAddress(), gem5::prefetch::Base::blockIndex(), c(), gem5::branch_prediction::TAGE_SC_L_TAGE::calcDep(), gem5::PowerISA::IntTrapOp::checkTrap(), gem5::ruby::MN_TBETable::chooseNewDistributor(), gem5::GicV2Registers::clearBankedDistRange(), gem5::GicV2Registers::clearDistRange(), gem5::Gicv3Registers::clearDistRange(), gem5::SMMUTranslationProcess::completePrefetch(), gem5::SMMUTranslationProcess::completeTransaction(), gem5::IGbE::TxDescCache::completionWriteback(), gem5::AddrRange::contains(), gem5::ChannelAddrRange::contains(), gem5::VMA::contains(), gem5::GicV2Registers::copyBankedDistRange(), gem5::GicV2Registers::copyDistRange(), gem5::Gicv3Registers::copyDistRange(), gem5::Gicv3Registers::copyRedistRange(), gem5::divCeil(), gem5::SMMUProcess::doDelay(), gem5::ItsProcess::doRead(), gem5::SMMUProcess::doRead(), gem5::SMMUProcess::doSleep(), gem5::ItsProcess::doWrite(), gem5::SMMUProcess::doWrite(), gem5::MipsISA::dspAbs(), gem5::MipsISA::dspAdd(), gem5::MipsISA::dspAddh(), gem5::MipsISA::dspCmp(), gem5::MipsISA::dspCmpg(), gem5::MipsISA::dspCmpgd(), gem5::MipsISA::dspDpa(), gem5::MipsISA::dspDpaq(), gem5::MipsISA::dspDps(), gem5::MipsISA::dspDpsq(), gem5::MipsISA::dspMaq(), gem5::MipsISA::dspMul(), gem5::MipsISA::dspMuleq(), gem5::MipsISA::dspMuleu(), gem5::MipsISA::dspMulq(), gem5::MipsISA::dspMulsa(), gem5::MipsISA::dspMulsaq(), gem5::MipsISA::dspPack(), gem5::MipsISA::dspPick(), gem5::MipsISA::dspPrece(), gem5::MipsISA::dspPrecrq(), gem5::MipsISA::dspPrecrqu(), gem5::MipsISA::dspPrecrSra(), gem5::MipsISA::dspShll(), gem5::MipsISA::dspShra(), gem5::MipsISA::dspShrl(), gem5::MipsISA::dspSub(), gem5::MipsISA::dspSubh(), expected(), gem5::branch_prediction::TAGE_SC_L_TAGE::F(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp16_sqrt(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp32_sqrt(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fp64_sqrt(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGE(), fplibCompareGE(), fplibCompareGT(), fplibCompareGT(), fplibCompareGT(), fplibCompareUN(), fplibCompareUN(), fplibCompareUN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpMulX(), fpRecps(), fpRecpsS(), fpRIntX(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), gem5::Gicv2m::frameFromAddr(), gem5::fastmodel::ScxEvsCortexR52< Types >::gem5_getPort(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::AddrRange::getOffset(), gem5::branch_prediction::MPP_TAGE::handleAllocAndUReset(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hash1(), gem5::stl_helpers::hash_impl::hash_combine(), gem5::KernelWorkload::initState(), gem5::KernelWorkload::KernelWorkload(), gem5::pseudo_inst::m5sum(), gem5::ItsCommand::main(), gem5::SMMUCommandExecProcess::main(), gem5::SMMUTranslationProcess::main(), gem5::PowerISA::FloatOp::makeCRField(), gem5::PowerISA::IntOp::makeCRFieldSigned(), gem5::PowerISA::IntOp::makeCRFieldUnsigned(), gem5::loader::MemoryImage::mask(), gem5::MathExpr::MathExpr(), mul62x62(), mul64x32(), multiply2Op(), multiply3Op(), gem5::mulUnsignedManual(), gem5::loader::MemoryImage::offset(), gem5::AMDGPU::operator!=(), gem5::operator!=(), gem5::SNHash::operator()(), gem5::AMDGPU::operator*(), gem5::AMDGPU::operator*=(), gem5::AMDGPU::operator+(), gem5::AMDGPU::operator+(), gem5::ConstProxyPtr< T, Proxy >::operator+(), gem5::operator+(), gem5::operator+(), gem5::AMDGPU::operator++(), gem5::AMDGPU::operator++(), gem5::AMDGPU::operator+=(), gem5::AMDGPU::operator-(), gem5::AMDGPU::operator-(), gem5::ConstProxyPtr< T, Proxy >::operator-(), gem5::AMDGPU::operator--(), gem5::AMDGPU::operator--(), gem5::AMDGPU::operator-=(), gem5::AMDGPU::operator/(), gem5::AMDGPU::operator/=(), gem5::AMDGPU::operator<(), gem5::networking::operator<<(), gem5::AMDGPU::operator<=(), gem5::ConstProxyPtr< T, Proxy >::operator=(), gem5::AMDGPU::operator==(), gem5::operator==(), gem5::AMDGPU::operator>(), gem5::AMDGPU::operator>=(), gem5::prefetch::Base::pageAddress(), gem5::EmulationPageTable::pageAlign(), gem5::EmulationPageTable::pageOffset(), gem5::prefetch::Base::pageOffset(), gem5::IGbE::DescCache< T >::pciToDma(), gem5::AtomicSimpleCPU::printAddr(), gem5::GarnetSyntheticTraffic::printAddr(), gem5::RequestPort::printAddr(), gem5::TimingSimpleCPU::printAddr(), gem5::StackDistCalc::printStack(), gem5::SMMUv3::processCommands(), gem5::SMMUv3DeviceInterface::recvAtomic(), gem5::Gicv3Its::recvReqRetry(), gem5::SMMUv3::recvReqRetry(), gem5::AddrRange::removeIntlvBits(), roundNEven(), gem5::prefetch::Base::samePage(), gem5::trace::InstRecord::setMem(), gem5::ruby::WeightBased::sortLinks(), gem5::swap_byte(), gem5::SMMUv3::tableWalkRecvReqRetry(), gem5::ItsProcess::terminate(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), testTcInit(), gem5::MemTest::tick(), gem5::trace::InstPBTrace::traceMem(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::StackDistCalc::verifyStackDist(), and gem5::SparcISA::TLB::writeSfsr().

a1

Bitfield< 22 > gem5::ArmISA::a1

Definition at line 585 of file misc_types.hh.

Referenced by add128(), cmp128(), gem5::branch_prediction::TAGE_SC_L_TAGE::F(), mul62x62(), and sub128().

aarch64

Bitfield<34> gem5::ArmISA::aarch64

Definition at line 81 of file types.hh.

Referenced by gem5::BaseSemihosting::gatherHeapInfo(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and vfpFpToFixed().

advsimd

Bitfield<23, 20> gem5::ArmISA::advsimd

Definition at line 221 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32().

advSimdHalfPrecision

Bitfield<23, 20> gem5::ArmISA::advSimdHalfPrecision

Definition at line 566 of file misc_types.hh.

advSimdInteger

Bitfield<15, 12> gem5::ArmISA::advSimdInteger

Definition at line 564 of file misc_types.hh.

advSimdLoadStore

Bitfield<11, 8> gem5::ArmISA::advSimdLoadStore

Definition at line 563 of file misc_types.hh.

advSimdRegisters

gem5::ArmISA::advSimdRegisters

Definition at line 550 of file misc_types.hh.

advSimdSinglePrecision

Bitfield<19, 16> gem5::ArmISA::advSimdSinglePrecision

Definition at line 565 of file misc_types.hh.

aes

Bitfield< 7, 4 > gem5::ArmISA::aes

Definition at line 90 of file misc_types.hh.

afe

Bitfield<29> gem5::ArmISA::afe

Definition at line 424 of file misc_types.hh.

aff0

Bitfield<7, 0> gem5::ArmISA::aff0

Definition at line 209 of file types.hh.

aff1

Bitfield<15, 8> gem5::ArmISA::aff1

Definition at line 208 of file types.hh.

Referenced by gem5::Gicv3CPUInterface::generateSGI().

aff2

Bitfield<23, 16> gem5::ArmISA::aff2

Definition at line 207 of file types.hh.

Referenced by gem5::Gicv3CPUInterface::generateSGI().

aff3

gem5::ArmISA::aff3

Definition at line 206 of file types.hh.

Referenced by gem5::Gicv3CPUInterface::generateSGI().

affinity

Bitfield<11, 0> gem5::ArmISA::affinity

Definition at line 855 of file misc_types.hh.

Referenced by gem5::Gicv3CPUInterface::copy(), gem5::Gicv3Redistributor::copy(), gem5::Gicv3Redistributor::read(), and gem5::Gicv3Distributor::route().

afsr0EL1

Bitfield<0> gem5::ArmISA::afsr0EL1

Definition at line 1069 of file misc_types.hh.

afsr1EL1

Bitfield<1> gem5::ArmISA::afsr1EL1

Definition at line 1068 of file misc_types.hh.

ahp

Bitfield<26> gem5::ArmISA::ahp

Definition at line 535 of file misc_types.hh.

Referenced by vcvtFpDFpH(), vcvtFpFpH(), vcvtFpHFp(), vcvtFpHFpD(), vcvtFpHFpS(), and vcvtFpSFpH().

aidrEL1

Bitfield<2> gem5::ArmISA::aidrEL1

Definition at line 1067 of file misc_types.hh.

aie

Bitfield<27, 24> gem5::ArmISA::aie

Definition at line 202 of file misc_types.hh.

aif

Bitfield<8, 6> gem5::ArmISA::aif

Definition at line 69 of file misc_types.hh.

amairEL1

Bitfield<3> gem5::ArmISA::amairEL1

Definition at line 1066 of file misc_types.hh.

amo

Bitfield<5> gem5::ArmISA::amo

Definition at line 360 of file misc_types.hh.

Referenced by gem5::ArmISA::DataAbort::routeToHyp(), and gem5::ArmISA::Interrupts::takeVirtualInt32().

amu

Bitfield<47, 44> gem5::ArmISA::amu

Definition at line 215 of file misc_types.hh.

anerr

gem5::ArmISA::anerr

Definition at line 197 of file misc_types.hh.

apa

Bitfield<7, 4> gem5::ArmISA::apa

Definition at line 146 of file misc_types.hh.

apdaKey

Bitfield<4> gem5::ArmISA::apdaKey

Definition at line 1065 of file misc_types.hh.

apdbKey

Bitfield<5> gem5::ArmISA::apdbKey

Definition at line 1064 of file misc_types.hh.

apgaKey

Bitfield<6> gem5::ArmISA::apgaKey

Definition at line 1063 of file misc_types.hh.

api

Bitfield< 17 > gem5::ArmISA::api

Definition at line 145 of file misc_types.hh.

apiaKey

Bitfield<7> gem5::ArmISA::apiaKey

Definition at line 1062 of file misc_types.hh.

apibKey

Bitfield<8> gem5::ArmISA::apibKey

Definition at line 1061 of file misc_types.hh.

apk

Bitfield< 16 > gem5::ArmISA::apk

Definition at line 325 of file misc_types.hh.

ApsrMask

const uint32_t gem5::ArmISA::ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0

static

Definition at line 2953 of file misc.hh.

ar

Bitfield<14> gem5::ArmISA::ar

Definition at line 776 of file misc_types.hh.

ArgumentReg0

auto & gem5::ArmISA::ArgumentReg0 = int_reg::X0

Definition at line 650 of file int.hh.

Referenced by gem5::ArmProcess::argsInit().

ArgumentReg1

auto & gem5::ArmISA::ArgumentReg1 = int_reg::X1

Definition at line 651 of file int.hh.

Referenced by gem5::ArmProcess::argsInit().

ArgumentReg2

auto & gem5::ArmISA::ArgumentReg2 = int_reg::X2

Definition at line 652 of file int.hh.

Referenced by gem5::ArmProcess::argsInit().

as

Bitfield< 36 > gem5::ArmISA::as

Definition at line 592 of file misc_types.hh.

Referenced by gem5::MipsISA::haltThread(), gem5::ProxyPtr< T, Proxy >::operator T*(), gem5::ProxyPtr< T, Proxy >::operator*(), gem5::ProxyPtr< T, Proxy >::operator->(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::operator[](), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::operator[](), gem5::ParseParam< VecRegContainer< Sz > >::parse(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::read(), and gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::write().

asedis

Bitfield<31> gem5::ArmISA::asedis

Definition at line 502 of file misc_types.hh.

asid

gem5::ArmISA::asid

Definition at line 702 of file misc_types.hh.

Referenced by gem5::buildKey(), gem5::ArmISA::TLB::insert(), gem5::ARMArchTLB::invalidateASID(), gem5::SMMUTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::ARMArchTLB::invalidateVA(), gem5::SMMUTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::ARMArchTLB::lookup(), gem5::ArmISA::MMU::lookup(), gem5::RiscvISA::TLB::lookup(), gem5::WalkCache::lookup(), gem5::ARMArchTLB::pickSetIdx(), gem5::RiscvISA::TLB::remove(), gem5::TlbiOp64::tlbiAsid(), gem5::TlbiOp64::tlbiRva(), gem5::TlbiOp64::tlbiVa(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::ArmISA::MMU::CachedState::updateMiscReg(), and gem5::SMMUTranslationProcess::walkCacheLookup().

asidbits

Bitfield<7, 4> gem5::ArmISA::asidbits

Definition at line 162 of file misc_types.hh.

at

Bitfield< 44 > gem5::ArmISA::at

Definition at line 185 of file misc_types.hh.

Referenced by gem5::fastmodel::PL330::gem5_getPort(), and gem5::X86KvmCPU::updateThreadContextMSRs().

atomic

Bitfield<23, 20> gem5::ArmISA::atomic

Definition at line 128 of file misc_types.hh.

Referenced by gem5::SDMAEngine::decodeHeader(), gem5::ArmISA::WatchPoint::test(), and gem5::ArmISA::SelfDebug::testWatchPoints().

ats1e0r

Bitfield<14> gem5::ArmISA::ats1e0r

Definition at line 999 of file misc_types.hh.

ats1e0w

Bitfield<15> gem5::ArmISA::ats1e0w

Definition at line 998 of file misc_types.hh.

ats1e1r

Bitfield<12> gem5::ArmISA::ats1e1r

Definition at line 1001 of file misc_types.hh.

ats1e1rp

Bitfield<16> gem5::ArmISA::ats1e1rp

Definition at line 997 of file misc_types.hh.

ats1e1w

Bitfield<13> gem5::ArmISA::ats1e1w

Definition at line 1000 of file misc_types.hh.

ats1e1wp

Bitfield<17> gem5::ArmISA::ats1e1wp

Definition at line 996 of file misc_types.hh.

attr

gem5::ArmISA::attr

Definition at line 740 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::addressTranslation64(), gem5::MemCmd::buildAttributes(), gem5::KvmDevice::getAttr(), gem5::KvmDevice::getAttrPtr(), gem5::KvmKernelGicV2::getGicReg(), gem5::KvmKernelGicV3::getGicReg(), gem5::KvmDevice::hasAttr(), gem5::X86ISA::installSegDesc(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::ArmISA::MMU::setAttr(), gem5::KvmDevice::setAttr(), gem5::KvmDevice::setAttrPtr(), gem5::setContextSegment(), gem5::KvmKernelGicV2::setGicReg(), gem5::KvmKernelGicV3::setGicReg(), gem5::setKvmSegmentReg(), gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

auxregs

Bitfield<27,24> gem5::ArmISA::auxregs

Definition at line 952 of file misc_types.hh.

aw

Bitfield<5> gem5::ArmISA::aw

Definition at line 412 of file misc_types.hh.

b

Bitfield<7> gem5::ArmISA::b

Definition at line 467 of file misc_types.hh.

Referenced by gem5::RiscvISA::_rvk_emu_clmul_32(), gem5::RiscvISA::_rvk_emu_clmul_64(), gem5::RiscvISA::_rvk_emu_clmulh_32(), gem5::RiscvISA::_rvk_emu_clmulh_64(), a(), addSubColumns(), gem5::ArmISA::Crypto::aesFFMul(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::b_transport(), gem5::PowerISA::IntTrapOp::checkTrap(), gem5::ruby::MN_TBETable::chooseNewDistributor(), gem5::branch_prediction::StatisticalCorrector::condBranchUpdate(), gem5::divCeil(), gem5::MipsISA::dspAdd(), gem5::MipsISA::dspAddh(), gem5::MipsISA::dspCmp(), gem5::MipsISA::dspCmpg(), gem5::MipsISA::dspCmpgd(), gem5::MipsISA::dspDpa(), gem5::MipsISA::dspDpaq(), gem5::MipsISA::dspDps(), gem5::MipsISA::dspDpsq(), gem5::MipsISA::dspMaq(), gem5::MipsISA::dspMul(), gem5::MipsISA::dspMuleq(), gem5::MipsISA::dspMuleu(), gem5::MipsISA::dspMulq(), gem5::MipsISA::dspMulsa(), gem5::MipsISA::dspMulsaq(), gem5::MipsISA::dspPack(), gem5::MipsISA::dspPick(), gem5::MipsISA::dspPrecrq(), gem5::MipsISA::dspPrecrqu(), gem5::MipsISA::dspPrecrSra(), gem5::MipsISA::dspSub(), gem5::MipsISA::dspSubh(), gem5::o3::DynInst::effAddrValid(), gem5::AtomicGeneric2Op< T >::execute(), gem5::AtomicGeneric3Op< T >::execute(), gem5::AtomicGenericPair3Op< T >::execute(), gem5::AtomicOpAdd< T >::execute(), gem5::AtomicOpAnd< T >::execute(), gem5::AtomicOpCAS< T >::execute(), gem5::AtomicOpDec< T >::execute(), gem5::AtomicOpExch< T >::execute(), gem5::AtomicOpInc< T >::execute(), gem5::AtomicOpMax< T >::execute(), gem5::AtomicOpMin< T >::execute(), gem5::AtomicOpOr< T >::execute(), gem5::AtomicOpSub< T >::execute(), gem5::AtomicOpXor< T >::execute(), gem5::RiscvISA::AtomicGenericOp< T >::execute(), gem5::AtomicOpAnd< T >::executeImpl(), gem5::AtomicOpOr< T >::executeImpl(), gem5::AtomicOpXor< T >::executeImpl(), gem5::execveFunc(), expected(), gem5::RiscvISA::fadd(), gem5::RiscvISA::fdiv(), gem5::RiscvISA::feq(), gem5::RiscvISA::fle(), gem5::RiscvISA::flt(), gem5::RiscvISA::fmadd(), gem5::RiscvISA::fmax(), gem5::RiscvISA::fmin(), gem5::RiscvISA::fmul(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_scale(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_scale(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_scale(), fpAdd(), fpAddD(), fpAddS(), fpDiv(), fpDivD(), fpDivS(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareEQ(), fplibCompareGE(), fplibCompareGE(), fplibCompareGE(), fplibCompareGT(), fplibCompareGT(), fplibCompareGT(), fplibCompareUN(), fplibCompareUN(), fplibCompareUN(), fpMax(), fpMaxNum(), fpMin(), fpMinNum(), fpMul(), fpMulD(), fpMulS(), fpMulX(), fpRecps(), fpRecpsS(), fpRSqrts(), fpRSqrtsS(), fpSub(), fpSubD(), fpSubS(), gem5::RiscvISA::fsgnj(), gem5::RiscvISA::fsgnj16(), gem5::RiscvISA::fsgnj32(), gem5::RiscvISA::fsgnj64(), gem5::RiscvISA::fsub(), gem5::BaseRemoteGDB::getbyte(), gem5::ruby::AbstractCacheEntry::getDataBlk(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::VecRegContainer< SIZE >::getString(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::stl_helpers::hash_impl::hash_combine(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::insertRecency(), gem5::pseudo_inst::m5sum(), gem5::PowerISA::FloatOp::makeCRField(), gem5::PowerISA::IntOp::makeCRFieldSigned(), gem5::PowerISA::IntOp::makeCRFieldUnsigned(), gem5::MathExpr::MathExpr(), mul62x62(), mul64x32(), multiply2Op(), multiply3Op(), gem5::mulUnsignedManual(), gem5::AMDGPU::operator!=(), gem5::ChannelAddr::operator!=(), gem5::operator!=(), gem5::ChannelAddr::operator%(), gem5::ChannelAddr::operator&(), gem5::ChannelAddr::operator&(), gem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >::operator()(), gem5::AMDGPU::operator*(), gem5::ChannelAddr::operator*(), gem5::AMDGPU::operator*=(), gem5::AMDGPU::operator+(), gem5::ChannelAddr::operator+(), gem5::ChannelAddr::operator+(), gem5::Cycles::operator+(), gem5::AMDGPU::operator+=(), gem5::AMDGPU::operator-(), gem5::ChannelAddr::operator-(), gem5::ChannelAddr::operator-(), gem5::Cycles::operator-(), gem5::AMDGPU::operator-=(), gem5::AMDGPU::operator/(), gem5::ChannelAddr::operator/(), gem5::AMDGPU::operator/=(), gem5::AMDGPU::operator<(), gem5::ChannelAddr::operator<(), gem5::ChannelAddr::operator<<(), gem5::AMDGPU::operator<=(), gem5::ChannelAddr::operator<=(), gem5::AMDGPU::operator==(), gem5::ChannelAddr::operator==(), gem5::operator==(), gem5::AMDGPU::operator>(), gem5::ChannelAddr::operator>(), gem5::AMDGPU::operator>=(), gem5::ChannelAddr::operator>=(), gem5::ChannelAddr::operator>>(), gem5::ChannelAddr::operator^(), gem5::ChannelAddr::operator^(), gem5::ChannelAddr::operator|(), gem5::ChannelAddr::operator|(), gem5::QARMA::PACInvSub(), gem5::QARMA::PACSub(), gem5::Gicv3Its::pageAddress(), gem5::ParseParam< MatStore< X, Y > >::parse(), gem5::ParseParam< VecRegContainer< Sz > >::parse(), gem5::branch_prediction::LTAGE::predict(), gem5::branch_prediction::TAGE::predict(), gem5::branch_prediction::TAGE_SC_L::predict(), gem5::memory::DRAMInterface::Rank::processRefreshEvent(), gem5::BaseRemoteGDB::putbyte(), gem5::memory::NVMInterface::Rank::Rank(), gem5::prefetch::Base::samePage(), gem5::memory::DRAMInterface::Rank::scheduleWakeUpEvent(), gem5::ArmISA::SelfDebug::securityStateMatch(), gem5::ruby::Network::setFromNetQueue(), gem5::ruby::Network::setToNetQueue(), gem5::ShowParam< MatStore< X, Y > >::show(), gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show(), gem5::ShowParam< VecRegContainer< Sz > >::show(), gem5::ruby::WeightBased::sortLinks(), BitUnionData::templatedFunction(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), test2DVoid(), testIntVoid(), testPrepareInt(), testPrepareVoid(), gem5::MemTest::tick(), and gem5::ruby::garnet::NetworkInterface::wakeup().

b16b16

Bitfield<27, 24> gem5::ArmISA::b16b16

Definition at line 240 of file misc_types.hh.

b16f32

Bitfield<34> gem5::ArmISA::b16f32

Definition at line 254 of file misc_types.hh.

bas

Bitfield< 12, 5 > gem5::ArmISA::bas

Definition at line 878 of file misc_types.hh.

Referenced by gem5::ArmISA::WatchPoint::compareAddress(), gem5::ArmISA::BrkPoint::testAddrMatch(), and gem5::ArmISA::BrkPoint::testAddrMissMatch().

bbm

Bitfield<55, 52> gem5::ArmISA::bbm

Definition at line 181 of file misc_types.hh.

bf16

Bitfield< 23, 20 > gem5::ArmISA::bf16

Definition at line 97 of file misc_types.hh.

bigend

Bitfield<11, 8> gem5::ArmISA::bigend

Definition at line 161 of file misc_types.hh.

bigendEL0

Bitfield<19, 16> gem5::ArmISA::bigendEL0

Definition at line 159 of file misc_types.hh.

bigThumb

Bitfield<35> gem5::ArmISA::bigThumb

Definition at line 80 of file types.hh.

bitPerm

Bitfield<19, 16> gem5::ArmISA::bitPerm

Definition at line 242 of file misc_types.hh.

bottom2

Bitfield<1, 0> gem5::ArmISA::bottom2

Definition at line 66 of file pcstate.hh.

bpaddremask

Bitfield<11,8> gem5::ArmISA::bpaddremask

Definition at line 956 of file misc_types.hh.

brps

Bitfield<15, 12> gem5::ArmISA::brps

Definition at line 111 of file misc_types.hh.

bsu

Bitfield<11, 10> gem5::ArmISA::bsu

Definition at line 354 of file misc_types.hh.

bt

Bitfield<23, 20> gem5::ArmISA::bt

Definition at line 873 of file misc_types.hh.

c

Bitfield< 29 > gem5::ArmISA::c

Definition at line 53 of file misc_types.hh.

Referenced by a(), gem5::ThermalModel::addCapacitor(), addSubColumns(), gem5::trace::TarmacParserRecord::advanceTrace(), b(), gem5::BaseCache::CacheStats::CacheStats(), gem5::BaseSemihosting::callWriteC(), gem5::SrcClockDomain::clockPeriod(), gem5::ruby::GPUCoalescer::coalescePacket(), gem5::Clocked::cyclesToTicks(), gem5::PowerISA::IntArithOp::divide(), gem5::trace::Logger::dump(), gem5::BaseRemoteGDB::encodeBinaryData(), gem5::ExecStage::ExecStageStats::ExecStageStats(), expected(), gem5::AddrRangeMap< V, max_cache_size >::find(), fp16_muladd(), fp16_process_NaNs3(), fp32_muladd(), fp32_process_NaNs3(), fp64_div(), fp64_muladd(), fp64_process_NaNs3(), fp64_sqrt(), gem5::o3::FUPool::FUPool(), gem5::bloom_filter::Bulk::hash(), gem5::ps2::Device::hostRegDataAvailable(), gem5::ps2::Device::hostWrite(), gem5::Plic::initContextFromHartConfig(), gem5::ruby::intToCycles(), gem5::ruby::intToTick(), gem5::ps2::PS2Keyboard::keyPress(), gem5::LupioTTY::lupioTTYWrite(), gem5::pseudo_inst::m5sum(), gem5::PowerISA::FloatOp::makeCRField(), gem5::PowerISA::IntArithOp::multiply(), multiply3Op(), gem5::LinearEquation::operator*=(), gem5::MathExpr::parse(), gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >::parse(), gem5::memory::PhysicalMemory::PhysicalMemory(), gem5::linux::printk(), gem5::Terminal::read(), gem5::Terminal::readData(), gem5::BaseRemoteGDB::recv(), gem5::ClockDomain::registerWithClockDomain(), gem5::BaseRemoteGDB::send(), gem5::ruby::Message::setMsgCounter(), gem5::split_first(), gem5::split_last(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), test2DVoid(), testIntVoid(), testPredicate(), gem5::MemTest::tick(), gem5::to_lower(), gem5::trace::TarmacTracerRecord::TraceInstEntry::TraceInstEntry(), gem5::BaseRemoteGDB::try_getbyte(), gem5::ps2::Device::unserialize(), gem5::DerivedClockDomain::updateClockPeriod(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updatePartial(), gem5::statistics::validateStatName(), gem5::Terminal::write(), and gem5::Terminal::writeData().

ccidx

Bitfield<23, 20> gem5::ArmISA::ccidx

Definition at line 188 of file misc_types.hh.

ccRegClass

RegClass gem5::ArmISA::ccRegClass

inlineconstexpr

Initial value:

= RegClass(CCRegClass, CCRegClassName,
        cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps)

Definition at line 87 of file cc.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::X86ISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::X86ISA::ISA::ISA(), and gem5::Iris::ThreadContext::setCCRegFlat().

ccRegClassOps

CCRegClassOps gem5::ArmISA::ccRegClassOps

inlinestatic

Definition at line 85 of file cc.hh.

ccsidrEL1

Bitfield<9> gem5::ArmISA::ccsidrEL1

Definition at line 1060 of file misc_types.hh.

cd

Bitfield<32> gem5::ArmISA::cd

Definition at line 332 of file misc_types.hh.

Referenced by gem5::ClockDomain::ClockDomainStats::ClockDomainStats(), gem5::SMMUTranslationProcess::doReadCD(), and gem5::SMMUTranslationProcess::findConfig().

cidmask

gem5::ArmISA::cidmask

Definition at line 951 of file misc_types.hh.

clidrEL1

Bitfield<10> gem5::ArmISA::clidrEL1

Definition at line 1059 of file misc_types.hh.

clrbhb

gem5::ArmISA::clrbhb

Definition at line 95 of file misc_types.hh.

cm

Bitfield< 8 > gem5::ArmISA::cm

Definition at line 513 of file misc_types.hh.

Referenced by gem5::ArmISA::SelfDebug::testWatchPoints(), and gem5::ArmISA::SelfDebug::triggerWatchpointException().

cnp

Bitfield<3, 0> gem5::ArmISA::cnp

Definition at line 193 of file misc_types.hh.

cond

Bitfield< 23, 20 > gem5::ArmISA::cond

Definition at line 62 of file pcstate.hh.

Referenced by gem5::AddrRangeMap< V, max_cache_size >::find(), and gem5::AddrRangeMap< V, max_cache_size >::find().

condCode

Bitfield<31, 28> gem5::ArmISA::condCode

Definition at line 111 of file types.hh.

CondCodesMask

const uint32_t gem5::ArmISA::CondCodesMask = 0xF00F0000

static

Definition at line 2944 of file misc.hh.

contextidrEL1

Bitfield<11> gem5::ArmISA::contextidrEL1

Definition at line 1058 of file misc_types.hh.

cp0

gem5::ArmISA::cp0

Definition at line 386 of file misc_types.hh.

cp1

Bitfield< 3, 2 > gem5::ArmISA::cp1

Definition at line 385 of file misc_types.hh.

cp10

Bitfield< 21, 20 > gem5::ArmISA::cp10

Definition at line 376 of file misc_types.hh.

cp11

Bitfield< 23, 22 > gem5::ArmISA::cp11

Definition at line 375 of file misc_types.hh.

cp12

Bitfield< 25, 24 > gem5::ArmISA::cp12

Definition at line 374 of file misc_types.hh.

cp13

Bitfield< 27, 26 > gem5::ArmISA::cp13

Definition at line 373 of file misc_types.hh.

cp15ben

Bitfield<5> gem5::ArmISA::cp15ben

Definition at line 471 of file misc_types.hh.

cp2

Bitfield< 5, 4 > gem5::ArmISA::cp2

Definition at line 384 of file misc_types.hh.

cp3

Bitfield< 7, 6 > gem5::ArmISA::cp3

Definition at line 383 of file misc_types.hh.

cp4

Bitfield< 9, 8 > gem5::ArmISA::cp4

Definition at line 382 of file misc_types.hh.

cp5

Bitfield< 11, 10 > gem5::ArmISA::cp5

Definition at line 381 of file misc_types.hh.

cp6

Bitfield< 13, 12 > gem5::ArmISA::cp6

Definition at line 380 of file misc_types.hh.

cp7

Bitfield< 15, 14 > gem5::ArmISA::cp7

Definition at line 379 of file misc_types.hh.

cp8

Bitfield< 17, 16 > gem5::ArmISA::cp8

Definition at line 378 of file misc_types.hh.

cp9

Bitfield< 19, 18 > gem5::ArmISA::cp9

Definition at line 377 of file misc_types.hh.

cpacrEL1

Bitfield<12> gem5::ArmISA::cpacrEL1

Definition at line 1057 of file misc_types.hh.

cpNum

Bitfield<11, 8> gem5::ArmISA::cpNum

Definition at line 148 of file types.hh.

CpsrMask

const uint32_t gem5::ArmISA::CpsrMask = ApsrMask | 0x00F003DF

static

Definition at line 2956 of file misc.hh.

CpsrMaskQ

const uint32_t gem5::ArmISA::CpsrMaskQ = 0x08000000

static

Definition at line 2945 of file misc.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

crc32

Bitfield< 19, 16 > gem5::ArmISA::crc32

Definition at line 87 of file misc_types.hh.

csselrEL1

Bitfield<13> gem5::ArmISA::csselrEL1

Definition at line 1056 of file misc_types.hh.

csv2

Bitfield<59, 56> gem5::ArmISA::csv2

Definition at line 213 of file misc_types.hh.

csv3

gem5::ArmISA::csv3

Definition at line 212 of file misc_types.hh.

ctrEL0

Bitfield<14> gem5::ArmISA::ctrEL0

Definition at line 1055 of file misc_types.hh.

ctx_cmps

Bitfield<31, 28> gem5::ArmISA::ctx_cmps

Definition at line 109 of file misc_types.hh.

cwg

Bitfield<27,24> gem5::ArmISA::cwg

Definition at line 729 of file misc_types.hh.

d

Bitfield<9> gem5::ArmISA::d

Definition at line 64 of file misc_types.hh.

Referenced by gem5::statistics::DistBase< Derived, Stor >::add(), gem5::ThermalModel::addDomain(), gem5::prefetch::IrregularStreamBuffer::calculatePrefetch(), gem5::prefetch::Stride::calculatePrefetch(), gem5::prefetch::Tagged::calculatePrefetch(), gem5::DVFSHandler::clkPeriodAtPerfLevel(), gem5::Wavefront::computeActualWgSz(), gem5::VirtQueue::consumeDescriptor(), gem5::RefCountingPtr< T >::copy(), gem5::trace::Logger::dump(), gem5::VirtQueue::dump(), gem5::DVFSHandler::DVFSHandler(), gem5::igbreg::txd_op::eop(), gem5::Process::findDriver(), gem5::igbreg::txd_op::getBuf(), gem5::igbreg::txd_op::getCso(), gem5::igbreg::txd_op::getCss(), gem5::igbreg::txd_op::getLen(), gem5::igbreg::txd_op::getTsoLen(), gem5::igbreg::txd_op::getType(), gem5::o3::LSQ::SplitDataRequest::handleLocalAccess(), gem5::ComputeUnit::hasDispResources(), gem5::igbreg::txd_op::hdrlen(), gem5::I2CBus::I2CBus(), gem5::igbreg::txd_op::ic(), gem5::igbreg::txd_op::ide(), gem5::igbreg::txd_op::ifcs(), gem5::AddrRangeMap< V, max_cache_size >::insert(), gem5::SparcISA::TlbMap::insert(), gem5::igbreg::txd_op::ip(), gem5::igbreg::txd_op::ipcse(), gem5::igbreg::txd_op::ipcso(), gem5::igbreg::txd_op::ipcss(), gem5::igbreg::txd_op::isAdvDesc(), gem5::igbreg::txd_op::isContext(), gem5::igbreg::txd_op::isData(), gem5::igbreg::txd_op::isLegacy(), gem5::igbreg::txd_op::isType(), gem5::igbreg::txd_op::isTypes(), gem5::igbreg::txd_op::ixsm(), gem5::pseudo_inst::m5sum(), gem5::igbreg::txd_op::mss(), gem5::VirtQueue::onNotify(), gem5::copy_engine_reg::Reg< T >::operator()(), gem5::igbreg::Regs::Reg< T >::operator()(), gem5::copy_engine_reg::Reg< T >::operator=(), gem5::igbreg::Regs::Reg< T >::operator=(), gem5::copy_engine_reg::Reg< T >::operator==(), gem5::igbreg::Regs::Reg< T >::operator==(), gem5::DVFSHandler::perfLevel(), gem5::DistIface::RecvScheduler::resumeRecvTicks(), gem5::igbreg::txd_op::rs(), gem5::VoltageDomain::sanitiseVoltages(), gem5::RefCountingPtr< T >::set(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::igbreg::txd_op::setDd(), gem5::OutputDirectory::setDirectory(), gem5::ruby::Topology::shortest_path_to_node(), gem5::igbreg::txd_op::tcp(), TEST(), TEST(), test2DVoid(), testIntVoid(), gem5::ArmISA::SelfDebug::triggerWatchpointException(), gem5::VirtIOConsole::TermRecvQueue::trySend(), gem5::VirtIORng::RngQueue::trySend(), gem5::igbreg::txd_op::tse(), gem5::igbreg::txd_op::tucse(), gem5::igbreg::txd_op::tucso(), gem5::igbreg::txd_op::tucss(), gem5::igbreg::txd_op::txsm(), gem5::DVFSHandler::UpdateEvent::updatePerfLevel(), gem5::igbreg::txd_op::utcmd(), gem5::igbreg::txd_op::vle(), gem5::DVFSHandler::voltageAtPerfLevel(), gem5::I2CBus::write(), and gem5::VGic::writeCtrl().

d128

Bitfield<35, 32> gem5::ArmISA::d128

Definition at line 200 of file misc_types.hh.

d128_2

Bitfield<39, 36> gem5::ArmISA::d128_2

Definition at line 199 of file misc_types.hh.

d32dis

Bitfield<30> gem5::ArmISA::d32dis

Definition at line 501 of file misc_types.hh.

daif

Bitfield<9, 6> gem5::ArmISA::daif

Definition at line 70 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), and gem5::ArmISA::ISA::setMiscReg().

dataRAMSetup

Bitfield<5> gem5::ArmISA::dataRAMSetup

Definition at line 709 of file misc_types.hh.

dataRAMSlice

Bitfield<11,10> gem5::ArmISA::dataRAMSlice

Definition at line 712 of file misc_types.hh.

dbgauthstatusEL1

Bitfield<6> gem5::ArmISA::dbgauthstatusEL1

Definition at line 1079 of file misc_types.hh.

dbgbcrnEL1

Bitfield<0> gem5::ArmISA::dbgbcrnEL1

Definition at line 1085 of file misc_types.hh.

dbgbvrnEL1

Bitfield<1> gem5::ArmISA::dbgbvrnEL1

Definition at line 1084 of file misc_types.hh.

dbgclaim

Bitfield<5> gem5::ArmISA::dbgclaim

Definition at line 1080 of file misc_types.hh.

dbgprcrEL1

Bitfield<7> gem5::ArmISA::dbgprcrEL1

Definition at line 1078 of file misc_types.hh.

dbgwcrnEL1

Bitfield<2> gem5::ArmISA::dbgwcrnEL1

Definition at line 1083 of file misc_types.hh.

dbgwvrnEL1

Bitfield<3> gem5::ArmISA::dbgwvrnEL1

Definition at line 1082 of file misc_types.hh.

dc

Bitfield<12> gem5::ArmISA::dc

Definition at line 353 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::translateMmuOff().

dCacheLineSize

Bitfield<19,16> gem5::ArmISA::dCacheLineSize

Definition at line 727 of file misc_types.hh.

dccisw

Bitfield<6> gem5::ArmISA::dccisw

Definition at line 1007 of file misc_types.hh.

dccivac

Bitfield<10> gem5::ArmISA::dccivac

Definition at line 1003 of file misc_types.hh.

dccsw

Bitfield<5> gem5::ArmISA::dccsw

Definition at line 1008 of file misc_types.hh.

dccvap

Bitfield<8> gem5::ArmISA::dccvap

Definition at line 1005 of file misc_types.hh.

dccvapd

Bitfield<9> gem5::ArmISA::dccvapd

Definition at line 1004 of file misc_types.hh.

dccvau

Bitfield<7> gem5::ArmISA::dccvau

Definition at line 1006 of file misc_types.hh.

dcisw

Bitfield<4> gem5::ArmISA::dcisw

Definition at line 1009 of file misc_types.hh.

dcivac

Bitfield<3> gem5::ArmISA::dcivac

Definition at line 1010 of file misc_types.hh.

dczidEL0

Bitfield<15> gem5::ArmISA::dczidEL0

Definition at line 1054 of file misc_types.hh.

dczva

Bitfield<11> gem5::ArmISA::dczva

Definition at line 1002 of file misc_types.hh.

debugStep

Bitfield<60> gem5::ArmISA::debugStep

Definition at line 63 of file types.hh.

debugver

Bitfield<3, 0> gem5::ArmISA::debugver

Definition at line 114 of file misc_types.hh.

decoderFault

gem5::ArmISA::decoderFault

Definition at line 61 of file types.hh.

defaultNaN

Bitfield<7, 4> gem5::ArmISA::defaultNaN

Definition at line 562 of file misc_types.hh.

dfsc

Bitfield< 5, 0 > gem5::ArmISA::dfsc

Definition at line 783 of file misc_types.hh.

dit

Bitfield< 51, 48 > gem5::ArmISA::dit

Definition at line 57 of file misc_types.hh.

Referenced by gem5::DVFSHandler::DVFSHandler(), and gem5::VoltageDomain::sanitiseVoltages().

divide

Bitfield<19, 16> gem5::ArmISA::divide

Definition at line 554 of file misc_types.hh.

Referenced by gem5::PowerISA::IntArithOp::divide().

dn

Bitfield<25> gem5::ArmISA::dn

Definition at line 534 of file misc_types.hh.

domain

Bitfield<7, 4> gem5::ArmISA::domain

Definition at line 508 of file misc_types.hh.

Referenced by gem5::ArmISA::AbortFault< T >::getFsr(), gem5::ListenSocket::socketCloexec(), gem5::socketFunc(), gem5::socketpairFunc(), gem5::ArmISA::MMU::testAndFinalize(), gem5::ArmISA::MMU::testTranslation(), and gem5::ArmISA::TableWalker::testWalk().

doublelock

Bitfield< 23, 20 > gem5::ArmISA::doublelock

Definition at line 107 of file misc_types.hh.

doublePrecision

Bitfield<11, 8> gem5::ArmISA::doublePrecision

Definition at line 552 of file misc_types.hh.

dp

Bitfield< 47, 44 > gem5::ArmISA::dp

Definition at line 101 of file misc_types.hh.

Referenced by gem5::prefetch::Queued::processMissingTranslations(), gem5::PacketQueue::sendDeferredPacket(), and gem5::prefetch::Queued::translationComplete().

dpb

Bitfield<3, 0> gem5::ArmISA::dpb

Definition at line 147 of file misc_types.hh.

ds0

Bitfield<16> gem5::ArmISA::ds0

Definition at line 668 of file misc_types.hh.

ds1

Bitfield<17> gem5::ArmISA::ds1

Definition at line 669 of file misc_types.hh.

dz

Bitfield<19> gem5::ArmISA::dz

Definition at line 443 of file misc_types.hh.

dzc

Bitfield<1> gem5::ArmISA::dzc

Definition at line 518 of file misc_types.hh.

dze

Bitfield< 9 > gem5::ArmISA::dze

Definition at line 455 of file misc_types.hh.

e

Bitfield< 0 > gem5::ArmISA::e

Definition at line 65 of file misc_types.hh.

Referenced by gem5::Workload::addFuncEventOrPanic(), gem5::KernelWorkload::addKernelFuncEventOrPanic(), gem5::statistics::Hdf5::appendStat(), gem5::ARMArchTLB::ARMArchTLB(), gem5::statistics::Hdf5::beginGroup(), SwitchingFiber::checkExpected(), gem5::BaseRemoteGDB::cmdMultiLetter(), gem5::ConfigCache::ConfigCache(), gem5::SMMUTranslationProcess::configCacheLookup(), gem5::SMMUTranslationProcess::configCacheUpdate(), gem5::fastmodel::CortexA76Cluster::CortexA76Cluster(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::ruby::countBoolVec(), gem5::DmaReadFifo::DmaReadFifo(), gem5::ThermalModel::doStep(), gem5::RiscvISA::TLB::doTranslate(), gem5::PCEventQueue::dump(), gem5::o3::LSQUnit::dumpInsts(), gem5::dumpKvm(), gem5::X86KvmCPU::dumpMSRs(), gem5::ruby::RubySystem::enqueueRubyEvent(), gem5::AddrRange::exclude(), gem5::qemu::FwCfgItemE820::FwCfgItemE820(), gem5::SMMUTranslationProcess::ifcTLBLookup(), gem5::SMMUTranslationProcess::ifcTLBUpdate(), gem5::ARMArchTLB::invalidateASID(), gem5::SMMUTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPA(), gem5::IPACache::invalidateIPAA(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSID(), gem5::ConfigCache::invalidateSSID(), gem5::SMMUTLB::invalidateSSID(), gem5::ARMArchTLB::invalidateVA(), gem5::SMMUTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::ARMArchTLB::invalidateVAA(), gem5::SMMUTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::SMMUTLB::invalidateVMID(), gem5::WalkCache::invalidateVMID(), gem5::IPACache::IPACache(), gem5::ARMArchTLB::lookup(), gem5::ConfigCache::lookup(), gem5::IPACache::lookup(), gem5::SMMUTLB::lookup(), gem5::WalkCache::lookup(), gem5::SMMUTLB::lookupAnyVA(), gem5::pseudo_inst::m5sum(), main(), gem5::makeKvmCpuid(), gem5::SMMUTranslationProcess::microTLBLookup(), gem5::SMMUTranslationProcess::microTLBUpdate(), gem5::Time::operator double(), gem5::stl_helpers::hash_impl::hash< std::tuple< T... > >::operator()(), gem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >::operator()(), gem5::ruby::operator<<(), gem5::SparcISA::PageTableEntry::operator=(), gem5::SparcISA::PageTableEntry::operator=(), gem5::SparcISA::TteTag::operator=(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::SparcISA::PageTableEntry::populate(), gem5::BaseRemoteGDB::processCommands(), gem5::memory::qos::MemSinkCtrl::processNextReqEvent(), gem5::VirtQueue::produceDescriptor(), gem5::pybind_init_event(), gem5::System::registerThreadContext(), gem5::CheckerThreadContext< TC >::remove(), gem5::Iris::ThreadContext::remove(), gem5::o3::ThreadContext::remove(), gem5::SimpleThread::remove(), gem5::System::replaceThreadContext(), gem5::DmaReadFifo::resumeFillTiming(), gem5::BaseSemihosting::retError(), gem5::CheckerThreadContext< TC >::schedule(), gem5::Iris::ThreadContext::schedule(), gem5::o3::ThreadContext::schedule(), gem5::SimpleThread::schedule(), gem5::Iris::ThreadContext::simulationTimeEvent(), gem5::SMMUTLB::SMMUTLB(), gem5::SMMUTranslationProcess::smmuTLBLookup(), gem5::SMMUTranslationProcess::smmuTLBUpdate(), gem5::RiscvISA::Walker::startWalkWrapper(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::ArmISA::MMU::translateFunctional(), gem5::SMMUTranslationProcess::translateStage2(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::prefetch::STeMS::ActiveGenerationTableEntry::update(), gem5::X86KvmCPU::updateKvmStateMSRs(), gem5::WalkCache::WalkCache(), gem5::SMMUTranslationProcess::walkCacheUpdate(), and gem5::DmaReadFifo::~DmaReadFifo().

e0e

Bitfield<24> gem5::ArmISA::e0e

Definition at line 432 of file misc_types.hh.

e0pd

gem5::ArmISA::e0pd

Definition at line 179 of file misc_types.hh.

e2h

Bitfield<34> gem5::ArmISA::e2h

Definition at line 330 of file misc_types.hh.

ea

Bitfield< 9 > gem5::ArmISA::ea

Definition at line 414 of file misc_types.hh.

Referenced by gem5::networking::EthAddr::EthAddr(), gem5::networking::EthAddr::EthAddr(), gem5::networking::operator<<(), and gem5::networking::EthAddr::operator=().

eae

Bitfield<31> gem5::ArmISA::eae

Definition at line 596 of file misc_types.hh.

ease

Bitfield<19> gem5::ArmISA::ease

Definition at line 397 of file misc_types.hh.

ec

gem5::ArmISA::ec

Definition at line 754 of file misc_types.hh.

Referenced by AArch64AArch32SystemAccessTrap(), gem5::ArmISA::DataAbort::ec(), gem5::ArmISA::PrefetchAbort::ec(), gem5::MiscRegOp64::generateTrap(), gem5::ArmISA::ArmFaultVals< T >::il(), isGenericTimerCommonEL0HypTrap(), isGenericTimerHypTrap(), gem5::ListenSocketUnixFile::listen(), mcrMrc15Trap(), mcrMrc15TrapToHyp(), mcrrMrrc15Trap(), mcrrMrrc15TrapToHyp(), and gem5::ArmISA::ArmFault::setSyndrome().

eccandParityEnable

Bitfield<21> gem5::ArmISA::eccandParityEnable

Definition at line 715 of file misc_types.hh.

ecv

Bitfield< 12 > gem5::ArmISA::ecv

Definition at line 151 of file misc_types.hh.

ee

Bitfield<25> gem5::ArmISA::ee

Definition at line 431 of file misc_types.hh.

eel2

Bitfield<18> gem5::ArmISA::eel2

Definition at line 398 of file misc_types.hh.

Referenced by IsSecureEL2Enabled().

el

Bitfield< 3, 2 > gem5::ArmISA::el

Definition at line 73 of file misc_types.hh.

Referenced by addPAC(), addPACDA(), addPACDB(), addPACGA(), addPACIA(), addPACIB(), gem5::ArmISA::ArmStaticInst::advSIMDFPAccessTrap64(), auth(), authDA(), authDB(), authIA(), authIB(), calculateBottomPACBit(), calculateTBI(), gem5::ArmISA::MiscRegLUTEntry::checkFault(), gem5::ArmISA::ArmStaticInst::checkFPAdvSIMDEnabled64(), gem5::ArmISA::ArmStaticInst::checkSmeAccess(), gem5::ArmISA::ArmStaticInst::checkSmeEnabled(), gem5::ArmISA::ArmStaticInst::checkSveEnabled(), computeAddrTop(), ELIs32(), ELIs64(), ELIsInHost(), ELStateUsingAArch32(), ELStateUsingAArch32K(), ELUsingAArch32K(), gem5::ArmISA::MiscRegLUTEntryInitializer::fault(), gem5::ArmISA::MiscRegLUTEntryInitializer::faultRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::faultWrite(), gem5::ArmISA::IntRegClassOps::flatten(), gem5::MiscRegOp64::generateTrap(), gem5::MiscRegOp64::generateTrap(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), gem5::ArmISA::misc_regs::getRegVersion(), getRestoredITBits(), haveAArch32EL(), gem5::ArmSystem::haveEL(), gem5::Gicv3CPUInterface::haveEL(), gem5::ArmISA::SelfDebug::isDebugEnabled(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), gem5::ArmISA::PMU::CounterState::isFiltered(), isSecureAtEL(), maskTaggedAddr(), gem5::ArmISA::MMU::purifyTaggedAddr(), purifyTaggedAddr(), purifyTaggedAddr(), gem5::ArmISA::misc_regs::readRegister(), gem5::ArmISA::misc_regs::readRegisterNoEffect(), s1TranslationRegime(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ArmStaticInst::smeAccessTrap(), stripPAC(), gem5::ArmISA::ArmStaticInst::sveAccessTrap(), gem5::ArmISA::Interrupts::takeInt32(), gem5::ArmISA::Interrupts::takeInt64(), gem5::ArmISA::Interrupts::takeVirtualInt64(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::WatchPoint::test(), gem5::ArmISA::SelfDebug::testBreakPoints(), gem5::ArmISA::BrkPoint::testContextMatch(), gem5::ArmISA::BrkPoint::testLinkedBk(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::ArmISA::SelfDebug::testWatchPoints(), translationRegime(), upperAndLowerRange(), and gem5::ArmISA::misc_regs::writeRegister().

el0

Bitfield<3, 0> gem5::ArmISA::el0

Definition at line 226 of file misc_types.hh.

el0pcten

Bitfield< 0 > gem5::ArmISA::el0pcten

Definition at line 58 of file generic_timer_miscregs_types.hh.

el0pten

Bitfield< 9 > gem5::ArmISA::el0pten

Definition at line 52 of file generic_timer_miscregs_types.hh.

el0vcten

Bitfield< 1 > gem5::ArmISA::el0vcten

Definition at line 57 of file generic_timer_miscregs_types.hh.

el0Vpmen

Bitfield<0> gem5::ArmISA::el0Vpmen

Definition at line 1137 of file misc_types.hh.

el0vten

Bitfield< 8 > gem5::ArmISA::el0vten

Definition at line 53 of file generic_timer_miscregs_types.hh.

el1

Bitfield<7, 4> gem5::ArmISA::el1

Definition at line 225 of file misc_types.hh.

el1nvpct

Bitfield< 15 > gem5::ArmISA::el1nvpct

Definition at line 65 of file generic_timer_miscregs_types.hh.

el1nvvct

Bitfield< 16 > gem5::ArmISA::el1nvvct

Definition at line 64 of file generic_timer_miscregs_types.hh.

el1pcen

Bitfield<1> gem5::ArmISA::el1pcen

Definition at line 73 of file generic_timer_miscregs_types.hh.

el1pcten

Bitfield< 10 > gem5::ArmISA::el1pcten

Definition at line 74 of file generic_timer_miscregs_types.hh.

el1pten

Bitfield<11> gem5::ArmISA::el1pten

Definition at line 86 of file generic_timer_miscregs_types.hh.

el1tvct

Bitfield< 14 > gem5::ArmISA::el1tvct

Definition at line 66 of file generic_timer_miscregs_types.hh.

el1tvt

Bitfield< 13 > gem5::ArmISA::el1tvt

Definition at line 67 of file generic_timer_miscregs_types.hh.

el1Vpmen

Bitfield<1> gem5::ArmISA::el1Vpmen

Definition at line 1136 of file misc_types.hh.

el2

Bitfield<11, 8> gem5::ArmISA::el2

Definition at line 224 of file misc_types.hh.

el3

Bitfield<15, 12> gem5::ArmISA::el3

Definition at line 223 of file misc_types.hh.

en

Bitfield<30> gem5::ArmISA::en

Definition at line 545 of file misc_types.hh.

Referenced by gem5::Root::timeSyncEnable(), gem5::Root::timeSyncPeriod(), and gem5::Root::timeSyncSpinThreshold().

encoding

Bitfield<27, 25> gem5::ArmISA::encoding

Definition at line 90 of file types.hh.

Referenced by decode_fp_data_type(), gem5::UnknownOp::generateDisassembly(), and gem5::VncServer::setEncodings().

enda

Bitfield<27> gem5::ArmISA::enda

Definition at line 427 of file misc_types.hh.

endb

Bitfield<13> gem5::ArmISA::endb

Definition at line 458 of file misc_types.hh.

enib

Bitfield<30> gem5::ArmISA::enib

Definition at line 422 of file misc_types.hh.

enMpamSm

Bitfield<50> gem5::ArmISA::enMpamSm

Definition at line 1115 of file misc_types.hh.

epd0

Bitfield< 7 > gem5::ArmISA::epd0

Definition at line 579 of file misc_types.hh.

epd1

Bitfield< 23 > gem5::ArmISA::epd1

Definition at line 586 of file misc_types.hh.

eret

Bitfield<51> gem5::ArmISA::eret

Definition at line 965 of file misc_types.hh.

erg

Bitfield<23,20> gem5::ArmISA::erg

Definition at line 728 of file misc_types.hh.

err

Bitfield<6> gem5::ArmISA::err

Definition at line 919 of file misc_types.hh.

Referenced by gem5::statistics::Hdf5::appendStat(), gem5::ArmSemihosting::call32(), gem5::RiscvSemihosting::call32(), gem5::ArmSemihosting::call64(), gem5::RiscvSemihosting::call64(), gem5::VncServer::checkProtocolVersion(), fplibFPToFixedJS(), fplibRoundInt(), fplibRoundInt(), fplibRoundInt(), FPToFixed_64(), gem5::NoMaliGpu::gpuPanic(), gem5::NoMaliGpu::panicOnErr(), gem5::IGbE::RxDescCache::pktComplete(), gem5::Iris::ThreadContext::readMem(), gem5::guest_abi::Result< Abi, RiscvSemihosting::RetErrno >::store(), gem5::guest_abi::Result< ArmSemihosting::Abi32, ArmSemihosting::RetErrno >::store(), gem5::guest_abi::Result< ArmSemihosting::Abi64, ArmSemihosting::RetErrno >::store(), TEST_F(), gem5::Globals::unserialize(), and gem5::Iris::ThreadContext::writeMem().

erridrEL1

Bitfield<40> gem5::ArmISA::erridrEL1

Definition at line 1029 of file misc_types.hh.

errselrEL1

Bitfield<41> gem5::ArmISA::errselrEL1

Definition at line 1028 of file misc_types.hh.

erxaddrEL1

Bitfield<49> gem5::ArmISA::erxaddrEL1

Definition at line 1020 of file misc_types.hh.

erxctlrEL1

Bitfield<43> gem5::ArmISA::erxctlrEL1

Definition at line 1026 of file misc_types.hh.

erxfrEL1

Bitfield<42> gem5::ArmISA::erxfrEL1

Definition at line 1027 of file misc_types.hh.

erxmiscNEL1

Bitfield<45> gem5::ArmISA::erxmiscNEL1

Definition at line 1024 of file misc_types.hh.

erxpfgcdnEL1

Bitfield<48> gem5::ArmISA::erxpfgcdnEL1

Definition at line 1021 of file misc_types.hh.

erxpfgctlEL1

Bitfield<47> gem5::ArmISA::erxpfgctlEL1

Definition at line 1022 of file misc_types.hh.

erxpfgfEL1

Bitfield<46> gem5::ArmISA::erxpfgfEL1

Definition at line 1023 of file misc_types.hh.

erxstatusEL1

Bitfield<44> gem5::ArmISA::erxstatusEL1

Definition at line 1025 of file misc_types.hh.

esm

Bitfield<12> gem5::ArmISA::esm

Definition at line 821 of file misc_types.hh.

esrEL1

Bitfield<16> gem5::ArmISA::esrEL1

Definition at line 1053 of file misc_types.hh.

evntdir

Bitfield< 3 > gem5::ArmISA::evntdir

Definition at line 55 of file generic_timer_miscregs_types.hh.

evnten

Bitfield< 2 > gem5::ArmISA::evnten

Definition at line 56 of file generic_timer_miscregs_types.hh.

Referenced by gem5::GenericTimer::handleStream().

evnti

Bitfield< 7, 4 > gem5::ArmISA::evnti

Definition at line 54 of file generic_timer_miscregs_types.hh.

evt

Bitfield<59, 56> gem5::ArmISA::evt

Definition at line 180 of file misc_types.hh.

ex

Bitfield<6> gem5::ArmISA::ex

Definition at line 798 of file misc_types.hh.

exs

Bitfield<47, 44> gem5::ArmISA::exs

Definition at line 152 of file misc_types.hh.

ext

Bitfield<12> gem5::ArmISA::ext

Definition at line 512 of file misc_types.hh.

Referenced by gem5::RequestPort::addTrace(), gem5::ArmRelease::ArmRelease(), Gem5SystemC::AtomicExtension::copy_from(), Gem5SystemC::ControlExtension::copy_from(), Gem5SystemC::Gem5Extension::copy_from(), gem5::X86ISA::X86CPUID::doCpuid(), gem5::Extensible< Target >::Extensible(), gem5::networking::Ip6Hdr::extensionLength(), gem5::BaseXBar::findPort(), gem5::PowerISA::IntImmTrapOp::generateDisassembly(), gem5::PowerISA::IntTrapOp::generateDisassembly(), gem5::ArmRelease::has(), gem5::ArmSystem::has(), gem5::ArmSystem::has(), HaveExt(), gem5::networking::Ip6Hdr::proto(), gem5::mpam::MSC::readPacketPartitionID(), gem5::RequestPort::removeTrace(), gem5::Extensible< Target >::setExtension(), gem5::ArmISA::mpam::tagRequest(), TEST(), and TEST().

ez

Bitfield<8> gem5::ArmISA::ez

Definition at line 826 of file misc_types.hh.

f

Bitfield< 0 > gem5::ArmISA::f

Definition at line 68 of file misc_types.hh.

Referenced by gem5::BaseRemoteGDB::attach(), gem5::BaseGlobalEventTemplate< Derived >::BaseGlobalEventTemplate(), gem5::bitsToFloat32(), gem5::bitsToFloat64(), gem5::debug::changeFlag(), gem5::dumpDebugFlags(), gem5::Event::Event(), gem5::MemBackdoor::flags(), gem5::AMDGPU::mxfp< FMT >::float_to_mxfp(), gem5::AMDGPU::mxfp< FMT >::float_to_mxfp_nocheck(), gem5::floatToBits32(), gem5::floatToBits64(), gem5::RiscvISA::freg(), gem5::RiscvISA::freg(), gem5::RiscvISA::freg(), gem5::RiscvISA::freg(), gem5::BaseSemihosting::getSTDIO(), gem5::ruby::garnet::flitBuffer::getTopFlit(), gem5::o3::DynInst::hitExternalSnoop(), gem5::IniFile::load(), gem5::IniFile::load(), gem5::branch_prediction::MultiperspectivePerceptron::lookup(), gem5::pseudo_inst::m5sum(), gem5::o3::DynInst::memOpDone(), gem5::AMDGPU::mxfp< FMT >::mxfp(), gem5::AMDGPU::mxfp< FMT >::mxfp(), gem5::Linux::openSpecialFile(), gem5::AMDGPU::mxfp< FMT >::operator=(), gem5::AMDGPU::mxfp< FMT >::operator=(), gem5::memory::PhysicalMemory::PhysicalMemory(), gem5::o3::DynInst::possibleLoadViolation(), gem5::CallbackQueue::process(), gem5::o3::DynInst::recordResult(), gem5::PybindSimObjectResolver::resolveSimObject(), gem5::AMDGPU::mxfp< FMT >::scale(), gem5::StaticInst::setFlag(), gem5::trace::InstRecord::setMem(), gem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), gem5::guest_abi::Result< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > >::store(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), RegisterBankTest::TestReg::TestReg(), gem5::trace::InstPBTrace::traceMem(), gem5::ArmISA::MMU::translateMmuOff(), gem5::o3::DynInst::translationCompleted(), gem5::o3::DynInst::translationStarted(), gem5::branch_prediction::MultiperspectivePerceptron::update(), and gem5::OutputDirectory::~OutputDirectory().

f16f32

Bitfield<35> gem5::ArmISA::f16f32

Definition at line 253 of file misc_types.hh.

f32f32

Bitfield<32> gem5::ArmISA::f32f32

Definition at line 255 of file misc_types.hh.

f32mm

Bitfield<55, 52> gem5::ArmISA::f32mm

Definition at line 236 of file misc_types.hh.

f64f64

Bitfield<48> gem5::ArmISA::f64f64

Definition at line 251 of file misc_types.hh.

f64mm

gem5::ArmISA::f64mm

Definition at line 235 of file misc_types.hh.

fa64

Bitfield<31, 31> gem5::ArmISA::fa64

Definition at line 837 of file misc_types.hh.

farEL1

Bitfield<17> gem5::ArmISA::farEL1

Definition at line 1052 of file misc_types.hh.

fb

Bitfield<9> gem5::ArmISA::fb

Definition at line 355 of file misc_types.hh.

Referenced by gem5::FrameBuffer::copyIn(), gem5::FrameBuffer::copyIn(), gem5::FrameBuffer::copyOut(), gem5::FrameBuffer::copyOut(), and gem5::createImgWriter().

fcma

Bitfield<19, 16> gem5::ArmISA::fcma

Definition at line 143 of file misc_types.hh.

fd

Bitfield<14, 12> gem5::ArmISA::fd

Definition at line 150 of file types.hh.

Referenced by gem5::Terminal::accept(), gem5::VncServer::accept(), gem5::atomic_read(), gem5::atomic_write(), gem5::EtherTapStub::attach(), gem5::KvmVM::createVCPU(), gem5::loader::doGzipLoad(), gem5::fcntlHelper(), gem5::fcntlHelper(), gem5::loader::DtbFile::findReleaseAddr(), gem5::loader::hasGzipMagic(), gem5::loader::ImageFileData::ImageFileData(), gem5::VMA::MappedFileBuffer::MappedFileBuffer(), gem5::Linux::openSpecialFile(), gem5::EtherTapBase::pollFd(), gem5::pollFunc(), gem5::ruby::RubySystem::readCompressedTrace(), gem5::pseudo_inst::readfile(), gem5::FDArray::serialize(), gem5::PollQueue::setupAsyncIO(), TEST(), TEST(), gem5::VMA::VMA(), gem5::ruby::RubySystem::writeCompressedTrace(), gem5::ListenSocketUnixFile::~ListenSocketUnixFile(), and gem5::PollQueue::~PollQueue().

fgten

Bitfield<27> gem5::ArmISA::fgten

Definition at line 394 of file misc_types.hh.

Referenced by fgtEnabled().

fhm

Bitfield< 51, 48 > gem5::ArmISA::fhm

Definition at line 100 of file misc_types.hh.

fi

Bitfield<21> gem5::ArmISA::fi

Definition at line 439 of file misc_types.hh.

Referenced by gem5::MathExprPowerModel::getStatValue().

fien

Bitfield< 21 > gem5::ArmISA::fien

Definition at line 318 of file misc_types.hh.

fiq

Bitfield<2> gem5::ArmISA::fiq

Definition at line 415 of file misc_types.hh.

flatIntRegClass

RegClass gem5::ArmISA::flatIntRegClass

inlineconstexpr

Initial value:

=
    RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs)

Definition at line 178 of file int.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::ArmISA::IntRegClassOps::flatten(), gem5::ArmISA::ISA::ISA(), gem5::ArmKvmCPU::updateKvmStateCore(), and gem5::ArmV8KvmCPU::updateThreadContext().

flushToZero

gem5::ArmISA::flushToZero

Definition at line 561 of file misc_types.hh.

Referenced by gem5::ArmISA::FpOp::binaryOp(), fixDivDest(), fixFpDFpSDest(), fixFpSFpDDest(), flushToZero(), gem5::ArmISA::FpOp::ternaryOp(), gem5::ArmISA::FpOp::unaryOp(), and vfpFlushToZero().

fm

Bitfield<3, 0> gem5::ArmISA::fm

Definition at line 152 of file types.hh.

fmo

Bitfield<3> gem5::ArmISA::fmo

Definition at line 362 of file misc_types.hh.

Referenced by gem5::ArmISA::Interrupts::takeVirtualInt32().

fn

Bitfield<18, 16> gem5::ArmISA::fn

Definition at line 149 of file types.hh.

Referenced by gem5::MathExpr::eval(), and gem5::MathExpr::eval().

fnv

Bitfield< 10 > gem5::ArmISA::fnv

Definition at line 778 of file misc_types.hh.

forceNs

Bitfield<60> gem5::ArmISA::forceNs

Definition at line 1124 of file misc_types.hh.

format

Bitfield<31,29> gem5::ArmISA::format

Definition at line 731 of file misc_types.hh.

Referenced by gem5::ccprintf(), gem5::ccprintf(), gem5::cprintf(), gem5::cprintf(), gem5::loader::createObjectFile(), gem5::csprintf(), gem5::csprintf(), gem5::Time::date(), gem5::Logger::print(), gem5::Logger::print(), gem5::linux::printk(), gem5::procInfo(), gem5::BaseRemoteGDB::send(), and gem5::BaseSemihosting::unrecognizedCall().

fp

Bitfield<19, 16> gem5::ArmISA::fp

Definition at line 222 of file misc_types.hh.

Referenced by bitsToFp(), bitsToFp(), fpToBits(), fpToBits(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::procInfo(), gem5::X86ISA::FsWorkload::writeOutACPITables(), and gem5::X86ISA::FsWorkload::writeOutMPTable().

FpCondCodesMask

const uint32_t gem5::ArmISA::FpCondCodesMask = 0xF0000000

static

Definition at line 2960 of file misc.hh.

fpen

Bitfield< 21, 20 > gem5::ArmISA::fpen

Definition at line 494 of file misc_types.hh.

fpImm

Bitfield<2, 0> gem5::ArmISA::fpImm

Definition at line 153 of file types.hh.

fpRegImm

Bitfield<3> gem5::ArmISA::fpRegImm

Definition at line 151 of file types.hh.

FpscrAhpMask

const uint32_t gem5::ArmISA::FpscrAhpMask = 0x04000000

static

Definition at line 2964 of file misc.hh.

FpscrExcMask

const uint32_t gem5::ArmISA::FpscrExcMask = 0x0000009F

static

Definition at line 2966 of file misc.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

fpscrLen

Bitfield<39, 37> gem5::ArmISA::fpscrLen

Definition at line 76 of file types.hh.

FpscrQcMask

const uint32_t gem5::ArmISA::FpscrQcMask = 0x08000000

static

Definition at line 2962 of file misc.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

fpscrStride

Bitfield<41, 40> gem5::ArmISA::fpscrStride

Definition at line 75 of file types.hh.

FramePointerReg

auto & gem5::ArmISA::FramePointerReg = int_reg::X11

Definition at line 653 of file int.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt(), and gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt().

frintts

Bitfield<35, 32> gem5::ArmISA::frintts

Definition at line 139 of file misc_types.hh.

fs4_0

Bitfield<5, 1> gem5::ArmISA::fs4_0

Definition at line 749 of file misc_types.hh.

fs5

Bitfield<6> gem5::ArmISA::fs5

Definition at line 748 of file misc_types.hh.

fsHigh

Bitfield<10> gem5::ArmISA::fsHigh

Definition at line 510 of file misc_types.hh.

fsLow

gem5::ArmISA::fsLow

Definition at line 506 of file misc_types.hh.

fst

Bitfield<6, 1> gem5::ArmISA::fst

Definition at line 747 of file misc_types.hh.

fw

Bitfield<4> gem5::ArmISA::fw

Definition at line 413 of file misc_types.hh.

fwb

Bitfield< 46 > gem5::ArmISA::fwb

Definition at line 183 of file misc_types.hh.

fz

Bitfield<24> gem5::ArmISA::fz

Definition at line 533 of file misc_types.hh.

fz16

Bitfield<19> gem5::ArmISA::fz16

Definition at line 530 of file misc_types.hh.

ge

Bitfield<19, 16> gem5::ArmISA::ge

Definition at line 62 of file misc_types.hh.

gic

Bitfield<27, 24> gem5::ArmISA::gic

Definition at line 220 of file misc_types.hh.

Referenced by gem5::ArmSystem::setGIC().

gpa

Bitfield<27, 24> gem5::ArmISA::gpa

Definition at line 141 of file misc_types.hh.

gpi

Bitfield<31, 28> gem5::ArmISA::gpi

Definition at line 140 of file misc_types.hh.

GrainMap_tg0

const GrainSize gem5::ArmISA::GrainMap_tg0

Initial value:

=
  { Grain4KB, Grain64KB, Grain16KB, ReservedGrain }

Definition at line 49 of file pagetable.cc.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), and gem5::SMMUTranslationProcess::walkCacheLookup().

GrainMap_tg1

const GrainSize gem5::ArmISA::GrainMap_tg1

Initial value:

=
  { ReservedGrain, Grain16KB, Grain4KB, Grain64KB }

Definition at line 51 of file pagetable.cc.

Referenced by gem5::ArmISA::TableWalker::processWalkAArch64().

gstappPlk

Bitfield<8> gem5::ArmISA::gstappPlk

Definition at line 1135 of file misc_types.hh.

ha

Bitfield< 21 > gem5::ArmISA::ha

Definition at line 628 of file misc_types.hh.

Referenced by gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::guest_abi::Argument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::get(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), and gem5::guest_abi::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::store().

hafdbs

Bitfield<3, 0> gem5::ArmISA::hafdbs

Definition at line 175 of file misc_types.hh.

hasForceNs

Bitfield<60> gem5::ArmISA::hasForceNs

Definition at line 1095 of file misc_types.hh.

hasHcr

Bitfield<17> gem5::ArmISA::hasHcr

Definition at line 1099 of file misc_types.hh.

hasTidr

Bitfield<58> gem5::ArmISA::hasTidr

Definition at line 1096 of file misc_types.hh.

hcd

Bitfield<29> gem5::ArmISA::hcd

Definition at line 335 of file misc_types.hh.

hce

Bitfield<8> gem5::ArmISA::hce

Definition at line 408 of file misc_types.hh.

hcx

gem5::ArmISA::hcx

Definition at line 167 of file misc_types.hh.

hd

Bitfield< 22 > gem5::ArmISA::hd

Definition at line 629 of file misc_types.hh.

hde

Bitfield<14> gem5::ArmISA::hde

Definition at line 914 of file misc_types.hh.

HighVecs

const uint32_t gem5::ArmISA::HighVecs = 0xFFFF0000

Definition at line 64 of file faults.cc.

Referenced by gem5::ArmISA::ArmFault::getVector().

hmc

Bitfield< 13 > gem5::ArmISA::hmc

Definition at line 876 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), and gem5::ArmISA::SelfDebug::securityStateMatch().

hpd

Bitfield< 24 > gem5::ArmISA::hpd

Definition at line 618 of file misc_types.hh.

hpd0

Bitfield< 41 > gem5::ArmISA::hpd0

Definition at line 600 of file misc_types.hh.

hpd1

Bitfield< 42 > gem5::ArmISA::hpd1

Definition at line 601 of file misc_types.hh.

hpds

Bitfield<15, 12> gem5::ArmISA::hpds

Definition at line 172 of file misc_types.hh.

hpme

Bitfield<7> gem5::ArmISA::hpme

Definition at line 264 of file misc_types.hh.

hpmn

Bitfield<4, 0> gem5::ArmISA::hpmn

Definition at line 267 of file misc_types.hh.

htopcode10_9

Bitfield<26, 25> gem5::ArmISA::htopcode10_9

Definition at line 176 of file types.hh.

htopcode12_11

Bitfield<28, 27> gem5::ArmISA::htopcode12_11

Definition at line 175 of file types.hh.

htopcode4

Bitfield<20> gem5::ArmISA::htopcode4

Definition at line 190 of file types.hh.

htopcode5_4

Bitfield<21, 20> gem5::ArmISA::htopcode5_4

Definition at line 189 of file types.hh.

htopcode6

Bitfield<22> gem5::ArmISA::htopcode6

Definition at line 187 of file types.hh.

htopcode6_5

Bitfield<22, 21> gem5::ArmISA::htopcode6_5

Definition at line 188 of file types.hh.

htopcode7

Bitfield<23> gem5::ArmISA::htopcode7

Definition at line 185 of file types.hh.

htopcode7_5

Bitfield<23, 21> gem5::ArmISA::htopcode7_5

Definition at line 186 of file types.hh.

htopcode8

Bitfield<24> gem5::ArmISA::htopcode8

Definition at line 181 of file types.hh.

htopcode8_5

Bitfield<24, 21> gem5::ArmISA::htopcode8_5

Definition at line 184 of file types.hh.

htopcode8_6

Bitfield<24, 22> gem5::ArmISA::htopcode8_6

Definition at line 183 of file types.hh.

htopcode8_7

Bitfield<24, 23> gem5::ArmISA::htopcode8_7

Definition at line 182 of file types.hh.

htopcode9

Bitfield<25> gem5::ArmISA::htopcode9

Definition at line 177 of file types.hh.

htopcode9_4

Bitfield<25, 20> gem5::ArmISA::htopcode9_4

Definition at line 180 of file types.hh.

htopcode9_5

Bitfield<25, 21> gem5::ArmISA::htopcode9_5

Definition at line 179 of file types.hh.

htopcode9_8

Bitfield<25, 24> gem5::ArmISA::htopcode9_8

Definition at line 178 of file types.hh.

htrn

Bitfield<19, 16> gem5::ArmISA::htrn

Definition at line 192 of file types.hh.

hts

Bitfield<20> gem5::ArmISA::hts

Definition at line 193 of file types.hh.

hxen

Bitfield<38> gem5::ArmISA::hxen

Definition at line 393 of file misc_types.hh.

i

Bitfield< 12 > gem5::ArmISA::i

Definition at line 67 of file misc_types.hh.

Referenced by gem5::System::_getRequestorId(), gem5::ArmISA::Crypto::_sha1Op(), gem5::MemChecker::abortWrite(), gem5::ListenSocketInet::accept(), gem5::TCPIface::accept(), gem5::Terminal::accept(), gem5::memory::DRAMInterface::activateBank(), gem5::ruby::Histogram::add(), gem5::statistics::HistStor::add(), gem5::CheckTable::addCheck(), gem5::ruby::PerfectSwitch::addInPort(), gem5::AddrRange::addIntlvBits(), gem5::statistics::Hdf5::addMetaData(), gem5::ruby::NetDest::addNetDest(), gem5::ruby::garnet::NetworkInterface::addOutPort(), gem5::ruby::Switch::addOutPort(), gem5::memory::DRAMInterface::addRankToRankDelay(), gem5::memory::NVMInterface::addRankToRankDelay(), gem5::AddressManager::AddressManager(), gem5::AddrRange::AddrRange(), gem5::Queue< Entry >::addToReadyList(), gem5::trace::TarmacParserRecord::advanceTrace(), gem5::ArmISA::Crypto::aesAddRoundKey(), gem5::ArmISA::Crypto::aesInvMixColumns(), gem5::ArmISA::Crypto::aesInvShiftRows(), gem5::ArmISA::Crypto::aesInvSubBytes(), gem5::ArmISA::Crypto::aesShiftRows(), gem5::ArmISA::Crypto::aesSubBytes(), gem5::ruby::CacheRecorder::aggregateRecords(), gem5::Aapcs32Vfp::State::allocate(), gem5::Aapcs32Vfp::State::allocate(), gem5::ruby::CacheMemory::allocate(), gem5::FetchUnit::FetchBufDesc::allocateBuf(), gem5::fastmodel::PL330::allocateIrq(), gem5::FDArray::allocFD(), gem5::AMDGPUGfx::AMDGPUGfx(), gem5::AMDGPUVM::AMDGPUVM(), gem5::ruby::NetDest::AND(), gem5::ruby::WriteMask::andMask(), gem5::FALRU::anyBlk(), gem5::X86ISA::ACPI::apic_checksum(), gem5::ScheduleStage::arbitrateVrfToLdsBus(), gem5::ArmProcess::argsInit(), gem5::MipsProcess::argsInit(), gem5::PowerProcess::argsInit(), gem5::SparcProcess::argsInit(), gem5::X86ISA::X86Process::argsInit(), gem5::ruby::DMASequencer::atomicCallback(), gem5::ruby::DataBlock::atomicPartial(), gem5::BaseGlobalEventTemplate< Derived >::BaseGlobalEventTemplate(), gem5::BaseIndexingPolicy::BaseIndexingPolicy(), gem5::BaseSimpleCPU::BaseSimpleCPU(), gem5::fastmodel::ScxEvsCortexA76< Types >::before_end_of_elaboration(), gem5::CxxConfigManager::bindAllPorts(), gem5::CxxConfigManager::bindObjectPorts(), gem5::MipsISA::bitrev(), gem5::bitsToFloat32(), gem5::bitsToFloat64(), gem5::bloom_filter::Block::Block(), gem5::branch_prediction::BranchTargetBuffer::BranchTargetBufferStats::BranchTargetBufferStats(), gem5::networking::EthAddr::broadcast(), gem5::ruby::broadcast(), gem5::ruby::NetDest::broadcast(), gem5::branch_prediction::TAGEBase::btbUpdate(), gem5::minor::ForwardInstData::bubbleFill(), gem5::o3::LSQ::SplitDataRequest::buildPackets(), gem5::branch_prediction::TAGE_SC_L_TAGE::buildTageTables(), gem5::branch_prediction::TAGEBase::buildTageTables(), gem5::ruby::CacheMemory::cacheAvail(), gem5::ruby::CacheMemory::CacheMemoryStats::CacheMemoryStats(), gem5::ruby::CacheMemory::cacheProbe(), gem5::FALRU::CacheTracking::CacheTracking(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateIndicesAndTags(), gem5::branch_prediction::TAGEBase::calculateIndicesAndTags(), gem5::branch_prediction::MPP_TAGE::calculateParameters(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateParameters(), gem5::branch_prediction::TAGEBase::calculateParameters(), gem5::prefetch::IndirectMemory::calculatePrefetch(), gem5::ruby::garnet::NetworkInterface::calculateVC(), gem5::minor::LSQ::StoreBuffer::canForwardDataToLoad(), gem5::o3::UnifiedRenameMap::canRename(), gem5::PacketFifo::check(), gem5::trace::ArmNativeTrace::check(), gem5::trace::SparcNativeTrace::check(), gem5::ruby::garnet::SwitchAllocator::check_for_wakeup(), checkExpectedDistData(), gem5::memory::AbstractMemory::checkLockedAddrList(), gem5::CheckTable::CheckTable(), gem5::memory::HeteroMemCtrl::chooseNext(), gem5::memory::MemCtrl::chooseNext(), gem5::memory::DRAMInterface::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseNextFRFCFS(), gem5::memory::NVMInterface::chooseRead(), gem5::VegaISA::GpuTLB::cleanup(), gem5::X86ISA::GpuTLB::cleanup(), gem5::o3::StoreSet::clear(), gem5::PacketFifo::clear(), gem5::Plic::clear(), gem5::ruby::Histogram::clear(), gem5::ruby::NetDest::clear(), gem5::SparcISA::Interrupts::clearAll(), gem5::MaltaCChip::clearIntr(), gem5::ruby::CacheMemory::clearLockedAll(), gem5::SparcISA::TLB::clearUsedBits(), gem5::OutputDirectory::close(), gem5::CoherentXBar::CoherentXBar(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::ruby::garnet::Router::collateStats(), gem5::ruby::Profiler::collateStats(), gem5::BaseCPU::CommitCPUStats::CommitCPUStats(), gem5::o3::Commit::commitHead(), gem5::ThreadContext::compare(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::ruby::GPUCoalescer::completeIssue(), gem5::MemChecker::completeRead(), gem5::MemChecker::completeWrite(), gem5::compression::Multi::compress(), gem5::compression::DictionaryCompressor< T >::compressValue(), gem5::branch_prediction::MultiperspectivePerceptron::computeBits(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), gem5::QARMA::computePAC(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::computePartialSum(), gem5::BaseTags::computeStats(), gem5::ComputeUnit::ComputeUnitStats::ComputeUnitStats(), gem5::FunctionProfile::consume(), gem5::AddrRange::contains(), gem5::ruby::WriteMask::containsMask(), gem5::X86ISA::convX87TagsToXTags(), gem5::X86ISA::convX87XTagsToTags(), gem5::PollQueue::copy(), gem5::SparcISA::copyMiscRegs(), gem5::X86ISA::copyMiscRegs(), gem5::PacketFifo::copyout(), gem5::ruby::DataBlock::copyPartial(), gem5::SDMAEngine::copyReadData(), gem5::ArmISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::Checker< class >::copyResult(), gem5::copyStringArray(), gem5::fastmodel::ScxEvsCortexR52< Types >::CorePins::CorePins(), gem5::fastmodel::CortexA76Cluster::CortexA76Cluster(), gem5::fastmodel::CortexR52Cluster::CortexR52Cluster(), gem5::ruby::NetDest::count(), gem5::ruby::WriteMask::count(), gem5::LdsState::countBankConflicts(), gem5::GenericTimerMem::counterCtrlRead(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::PacketFifo::countPacketsAfter(), gem5::PacketFifo::countPacketsBefore(), gem5::ruby::PersistentTable::countReadStarvingForAddress(), gem5::ruby::PersistentTable::countStarvingForAddress(), gem5::crc32(), gem5::ruby::Topology::createLinks(), gem5::SpatterAccess::createPacket(), gem5::BackdoorManager::createRevertedBackdoor(), gem5::GenericTimer::createTimers(), gem5::ArmISA::ArmStaticInst::cSwap(), gem5::ruby::DataBlock::DataBlock(), gem5::ruby::DMASequencer::dataCallback(), gem5::SDMAEngine::decodeHeader(), gem5::FetchUnit::FetchBufDesc::decodeSplitInst(), gem5::compression::DictionaryCompressor< T >::decompress(), gem5::compression::DictionaryCompressor< T >::RepeatedValuePattern< RepT >::decompress(), gem5::compression::DictionaryCompressor< uint16_t >::decompressValue(), gem5::CxxConfigManager::deleteObjects(), gem5::SparcISA::TLB::demapPage(), gem5::BaseGlobalEvent::deschedule(), gem5::SkewedAssociative::deskew(), gem5::o3::DynInst::destRegIdx(), gem5::StaticInst::destRegIdx(), gem5::Linux::devRandom(), gem5::ExecStage::dispStatusToStr(), gem5::ComputeUnit::dispWorkgroup(), gem5::statistics::DistPrint::DistPrint(), gem5::PowerISA::IntArithOp::divide(), gem5::LupioBLK::dmaEventDone(), gem5::memory::DRAMInterface::doBurstAccess(), gem5::memory::NVMInterface::doBurstAccess(), gem5::statistics::VectorBase< Derived, Stor >::doInit(), gem5::statistics::VectorDistBase< Derived, Stor >::doInit(), gem5::ObjectMatch::domatch(), gem5::PCEventQueue::doService(), gem5::ThermalModel::doStep(), gem5::ruby::Histogram::doubleBinSize(), gem5::ArmISA::TableWalker::drain(), gem5::o3::CPU::drain(), gem5::o3::CPU::drainResume(), gem5::o3::Fetch::drainResume(), gem5::o3::Fetch::drainSanityCheck(), gem5::o3::LSQUnit::drainSanityCheck(), gem5::o3::MemDepUnit::drainSanityCheck(), gem5::memory::DRAMInterface::DRAMInterface(), gem5::MipsISA::dspAbs(), gem5::MipsISA::dspAdd(), gem5::MipsISA::dspAddh(), gem5::MipsISA::dspCmp(), gem5::MipsISA::dspCmpg(), gem5::MipsISA::dspCmpgd(), gem5::MipsISA::dspDpa(), gem5::MipsISA::dspDpaq(), gem5::MipsISA::dspDps(), gem5::MipsISA::dspDpsq(), gem5::MipsISA::dspMaq(), gem5::MipsISA::dspMul(), gem5::MipsISA::dspMuleq(), gem5::MipsISA::dspMuleu(), gem5::MipsISA::dspMulq(), gem5::MipsISA::dspMulsaq(), gem5::MipsISA::dspPick(), gem5::MipsISA::dspPrece(), gem5::MipsISA::dspPrecrqu(), gem5::MipsISA::dspPrecrSra(), gem5::MipsISA::dspShll(), gem5::MipsISA::dspShra(), gem5::MipsISA::dspShrl(), gem5::MipsISA::dspSub(), gem5::MipsISA::dspSubh(), gem5::ActivityRecorder::dump(), gem5::ArmV8KvmCPU::dump(), gem5::BaseStackTrace::dump(), gem5::branch_prediction::BPredUnit::dump(), gem5::IniFile::dump(), gem5::o3::DependencyGraph< DynInstPtr >::dump(), gem5::o3::FUPool::dump(), gem5::PCEventQueue::dump(), gem5::RegisterFile::dump(), gem5::trace::Logger::dump(), gem5::Trie< Key, Value >::Node::dump(), gem5::SparcISA::TLB::dumpAll(), gem5::Checker< DynInstPtr >::dumpAndExit(), gem5::dumpDebugFlags(), gem5::ExecStage::dumpDispList(), gem5::dumpFpuCommon(), gem5::dumpKvm(), gem5::dumpKvm(), gem5::dumpKvm(), gem5::o3::InstructionQueue::dumpLists(), gem5::RegisterFileCache::dumpLL(), gem5::dumpMainQueue(), gem5::X86KvmCPU::dumpMSRs(), gem5::loader::ElfObject::ElfObject(), gem5::minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >::empty(), gem5::o3::DependencyGraph< DynInstPtr >::empty(), gem5::ruby::DataBlock::equal(), gem5::networking::EthAddr::EthAddr(), gem5::networking::EthAddr::EthAddr(), gem5::EtherSwitch::EtherSwitch(), gem5::minor::Decode::evaluate(), gem5::minor::Execute::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::eventqDump(), gem5::X86ISA::TLB::evictLRU(), gem5::Shader::execScheduledAdds(), gem5::ExecStage::ExecStageStats::ExecStageStats(), gem5::minor::Execute::Execute(), gem5::VegaISA::Inst_SOPP__S_ENDPGM::execute(), gem5::VegaISA::Inst_VOP3__V_PERM_B32::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT2_F32_F16::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT2_I32_I16::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT2_U32_U16::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT4_I32_I8::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT4_U32_U8::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT8_I32_I4::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT8_U32_U4::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA< _delta, M, N, K, B, T1, T2, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_MXFP< M, N, K, B, MXFPT, MNEMONIC >::execute(), gem5::execveFunc(), gem5::X86ISA::GpuTLB::exitCallback(), gem5::exitImpl(), gem5::ruby::Topology::extend_shortest_path(), gem5::ruby::FaultModel::fault_prob(), gem5::ruby::FaultModel::fault_vector(), gem5::ruby::FaultModel::FaultModel(), gem5::o3::Fetch::Fetch(), gem5::ruby::WriteMask::fillMask(), gem5::AddrRangeMap< V, max_cache_size >::find(), gem5::loader::SymbolTable::find(), gem5::loader::SymbolTable::find(), gem5::OutputDirectory::find(), gem5::SimObject::find(), gem5::SparcISA::TlbMap::find(), gem5::BackdoorManager::findBackdoor(), gem5::branch_prediction::MultiperspectivePerceptron::findBest(), gem5::debug::findFlag(), gem5::VGic::findHighestPendingLR(), gem5::VGic::findLRForVIRQ(), gem5::findLsbSet(), gem5::loader::SymbolTable::findNearest(), gem5::loader::SymbolTable::findNearest(), gem5::CxxConfigManager::findObject(), gem5::CxxConfigManager::findObjectParams(), gem5::BaseXBar::findPort(), gem5::IniFile::findSection(), gem5::ruby::PersistentTable::findSmallest(), gem5::minor::FUPipeline::findTiming(), gem5::CxxConfigManager::findTraversalOrder(), gem5::o3::LSQ::SplitDataRequest::finish(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::firstActive(), gem5::ruby::WriteMask::firstBitSet(), gem5::VegaISA::firstOppositeSignBit(), gem5::VegaISA::firstOppositeSignBit(), gem5::AtagCore::flags(), gem5::ruby::garnet::NetworkBridge::flitisizeAndSend(), gem5::ruby::garnet::NetworkInterface::flitisizeMessage(), gem5::floatToBits32(), gem5::floatToBits64(), gem5::X86ISA::TLB::flushAll(), gem5::FetchUnit::FetchBufDesc::flushBuf(), gem5::X86ISA::TLB::flushNonGlobal(), gem5::BaseCPU::flushTLBs(), gem5::CxxConfigManager::forEachObject(), gem5::formatParamList(), gem5::Gicv2m::frameFromAddr(), gem5::Wavefront::freeRegisterFile(), gem5::StaticRegisterManagerPolicy::freeRegisters(), gem5::compression::Base::fromChunks(), gem5::compression::DictionaryCompressor< T >::fromDictionaryEntry(), gem5::ruby::MessageBuffer::functionalAccess(), gem5::ruby::garnet::flitBuffer::functionalRead(), gem5::ruby::garnet::GarnetNetwork::functionalRead(), gem5::ruby::garnet::Router::functionalRead(), gem5::ruby::SimpleNetwork::functionalRead(), gem5::ruby::SimpleNetwork::functionalRead(), gem5::ruby::Switch::functionalRead(), gem5::ruby::Switch::functionalRead(), gem5::ruby::garnet::flitBuffer::functionalWrite(), gem5::ruby::garnet::GarnetNetwork::functionalWrite(), gem5::ruby::garnet::Router::functionalWrite(), gem5::ruby::RubyRequest::functionalWrite(), gem5::ruby::SimpleNetwork::functionalWrite(), gem5::ruby::Switch::functionalWrite(), gem5::FuncUnit::FuncUnit(), gem5::minor::FUPipeline::FUPipeline(), gem5::o3::FUPool::FUPool(), gem5::futimesatFunc(), gem5::ruby::garnet::GarnetNetwork::GarnetNetwork(), gem5::compression::FrequentValues::generateCodes(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::MrsOp::generateDisassembly(), gem5::GarnetSyntheticTraffic::generatePkt(), gem5::Gicv3CPUInterface::generateSGI(), gem5::GPUStaticInst::generateVirtToPhysMap(), gem5::GenericTimerMem::GenericTimerMem(), gem5::X86ISA::genX87Tags(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::get(), gem5::ruby::garnet::NetworkInterface::get_vnet(), gem5::Gicv2m::getAddrRanges(), gem5::ruby::RubyPort::PioResponsePort::getAddrRanges(), gem5::ruby::NetDest::getAllDest(), gem5::PciDevice::getBAR(), gem5::VecPredRegContainer< NumBits, Packed >::getBits(), gem5::CheckTable::getCheck(), gem5::bloom_filter::MultiBitSel::getCount(), gem5::PowerModel::getDynamicPower(), gem5::branch_prediction::TAGEBase::getGHR(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODHIST::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::Gicv3CPUInterface::getHPPVILR(), gem5::branch_prediction::LoopPredictor::getLoop(), gem5::ruby::RubyPrefetcher::getLRUindex(), gem5::ruby::WriteMask::getMask(), gem5::AMDGPUVM::getMMIOAperture(), gem5::CxxIniFile::getObjectChildren(), gem5::X86ISA::getPackedMem(), gem5::prefetch::PIF::CompactorEntry::getPredictedAddresses(), gem5::ruby::RubyPrefetcher::getPrefetchEntry(), gem5::getrandomFunc(), gem5::ArmKvmCPU::getRegList(), gem5::ArmISA::RemoteGDB::AArch32GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::branch_prediction::SimpleIndirectPredictor::getSetIndex(), gem5::branch_prediction::TAGEBase::getSizeInBits(), gem5::PowerModel::getStaticPower(), gem5::ruby::Throttle::getTotalLinkBandwidth(), gem5::replacement_policy::Dueling::getVictim(), gem5::PowerState::getWeights(), gem5::fastmodel::GIC::GIC(), gem5::Gicv2m::Gicv2m(), gem5::branch_prediction::StatisticalCorrector::gIndex(), gem5::branch_prediction::MPP_StatisticalCorrector::gIndexLogsSubstr(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gIndexLogsSubstr(), gem5::debug::Flag::globalDisable(), gem5::debug::Flag::globalEnable(), gem5::branch_prediction::StatisticalCorrector::gPredict(), gem5::GPUDynInst::GPUDynInst(), gem5::statistics::HistStor::growDown(), gem5::statistics::HistStor::growOut(), gem5::statistics::HistStor::growUp(), gem5::branch_prediction::MPP_StatisticalCorrector::gUpdate(), gem5::branch_prediction::StatisticalCorrector::gUpdate(), gem5::branch_prediction::MPP_TAGE::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_64KB::handleAllocAndUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::handleAllocAndUReset(), gem5::branch_prediction::TAGEBase::handleAllocAndUReset(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::branch_prediction::MPP_TAGE::handleUReset(), gem5::branch_prediction::TAGEBase::handleUReset(), gem5::ComputeUnit::hasDispResources(), gem5::bloom_filter::Block::hash(), gem5::bloom_filter::H3::hash(), gem5::bloom_filter::MultiBitSel::hash(), gem5::branch_prediction::MultiperspectivePerceptron::GHIST::hash(), gem5::branch_prediction::MultiperspectivePerceptron::MPPBranchInfo::hash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::hash(), gem5::o3::InstructionQueue::hasReadyInsts(), gem5::HSAPacketProcessor::HSAPacketProcessor(), gem5::ruby::CacheMemory::htmAbortTransaction(), gem5::ruby::CacheMemory::htmCommitTransaction(), gem5::X86ISA::I8042::I8042(), gem5::X86ISA::I82094AA::I82094AA(), gem5::X86ISA::I8254::I8254(), gem5::X86ISA::I8259::I8259(), gem5::IdeController::IdeController(), gem5::statistics::InfoAccess::info(), gem5::statistics::InfoAccess::info(), gem5::ArmISA::SelfDebug::init(), gem5::branch_prediction::MultiperspectivePerceptron::init(), gem5::branch_prediction::ReturnAddrStack::AddrStack::init(), gem5::Clint::ClintRegisters::init(), gem5::ComputeUnit::init(), gem5::CpuLocalTimer::init(), gem5::FetchUnit::init(), gem5::Gicv3::init(), gem5::o3::StoreSet::init(), gem5::o3::UnifiedRenameMap::init(), gem5::Plic::init(), gem5::Plic::PlicRegisters::init(), gem5::ProtocolTester::init(), gem5::ruby::AbstractController::init(), gem5::ruby::CacheMemory::init(), gem5::ruby::DirectoryMemory::init(), gem5::ruby::garnet::GarnetNetwork::init(), gem5::ruby::garnet::SwitchAllocator::init(), gem5::ruby::PerfectSwitch::init(), gem5::RubyTester::init(), gem5::statistics::Vector2dBase< Derived, Stor >::init(), gem5::Plic::initContextFromNContexts(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::initFoldedHistories(), gem5::branch_prediction::TAGEBase::initFoldedHistories(), gem5::branch_prediction::StatisticalCorrector::initGEHLTable(), gem5::o3::LSQ::SplitDataRequest::initiateTranslation(), gem5::VegaISA::Inst_DS::initMemRead(), gem5::VegaISA::Inst_FLAT::initMemRead(), gem5::VegaISA::Inst_DS::initMemWrite(), gem5::VegaISA::Inst_FLAT::initMemWrite(), gem5::X86ISA::X86_64Process::initState(), gem5::ruby::garnet::InputUnit::InputUnit(), gem5::ArmISA::TLB::insert(), gem5::branch_prediction::MultiperspectivePerceptron::insert(), gem5::SparcISA::TLB::insert(), gem5::Trie< Key, Value >::insert(), gem5::PowerISA::TLB::insertAt(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::insertRecency(), gem5::SparcISA::ISA::installGlobals(), gem5::SparcISA::ISA::installWindow(), gem5::ruby::SubBlock::internalMergeFrom(), gem5::ruby::SubBlock::internalMergeTo(), gem5::SparcISA::TlbMap::intersect(), gem5::ruby::NetDest::intersectionIsNotEmpty(), gem5::ARMArchTLB::invalidateAll(), gem5::ConfigCache::invalidateAll(), gem5::IPACache::invalidateAll(), gem5::SMMUTLB::invalidateAll(), gem5::VegaISA::GpuTLB::invalidateAll(), gem5::WalkCache::invalidateAll(), gem5::X86ISA::GpuTLB::invalidateAll(), gem5::ARMArchTLB::invalidateASID(), gem5::SMMUTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPA(), gem5::IPACache::invalidateIPAA(), gem5::X86ISA::GpuTLB::invalidateNonGlobal(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSID(), gem5::ConfigCache::invalidateSSID(), gem5::SMMUTLB::invalidateSSID(), gem5::ARMArchTLB::invalidateVA(), gem5::SMMUTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::ARMArchTLB::invalidateVAA(), gem5::SMMUTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::SMMUTLB::invalidateVMID(), gem5::WalkCache::invalidateVMID(), gem5::ruby::Sequencer::invL1(), gem5::ruby::VIPERCoalescer::invTCP(), gem5::GPUComputeDriver::ioctl(), gem5::o3::InstructionQueue::IQStats::IQStats(), gem5::ruby::NetDest::isBroadcast(), gem5::ComputeUnit::isDone(), gem5::o3::Fetch::isDrained(), gem5::o3::FUPool::isDrained(), gem5::o3::MemDepUnit::isDrained(), gem5::ruby::NetDest::isEmpty(), gem5::ruby::WriteMask::isEmpty(), gem5::ruby::NetDest::isEqual(), gem5::ruby::WriteMask::isFull(), gem5::AQLRingBuffer::isLastOutstandingPkt(), gem5::ruby::WriteMask::isOverlap(), gem5::compression::DictionaryCompressor< T >::RepeatedValuePattern< RepT >::isPattern(), gem5::ruby::DMASequencer::issueNext(), gem5::ruby::VIPERCoalescer::issueRequest(), gem5::ruby::NetDest::isSuperset(), gem5::MSHR::TargetList::isWholeLineWrite(), gem5::KvmVM::KvmVM(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::lastActive(), gem5::statistics::Info::less(), gem5::LinearSystem::LinearSystem(), gem5::HDLcd::lineNext(), gem5::ListenSocketInet::listen(), gem5::ArmISA::Crypto::load2Reg(), gem5::ArmISA::Crypto::load3Reg(), gem5::CxxConfigManager::loadState(), gem5::memory::qos::MemCtrl::logRequest(), gem5::ARMArchTLB::lookup(), gem5::ConfigCache::lookup(), gem5::IPACache::lookup(), gem5::PowerISA::TLB::lookup(), gem5::SMMUTLB::lookup(), gem5::SparcISA::TLB::lookup(), gem5::WalkCache::lookup(), gem5::SMMUTLB::lookupAnyVA(), gem5::System::lookupRequestorId(), gem5::System::lookupRequestorId(), gem5::ruby::lookupTraceForAddress(), gem5::branch_prediction::LoopPredictor::loopUpdate(), gem5::VGic::lrPending(), gem5::VGic::lrValid(), gem5::LupioBLK::lupioBLKCmd(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ruby::GPUCoalescer::makeRequest(), gem5::Malta::Malta(), gem5::ruby::AbstractController::mapAddressToDownstreamMachine(), gem5::mappingParamIn(), gem5::mappingParamOut(), gem5::ruby::PersistentTable::markEntries(), gem5::ArmISA::TLB::match(), gem5::partitioning_policy::MaxCapacityPartitioningPolicy::MaxCapacityPartitioningPolicy(), gem5::branch_prediction::SimpleBTB::memInvalidate(), gem5::AtagMem::memSize(), gem5::AtagMem::memStart(), gem5::bloom_filter::Base::merge(), gem5::bloom_filter::Multi::merge(), gem5::memory::DRAMInterface::minBankPrep(), gem5::MinorCPU::MinorCPU(), gem5::MinorOpClassSet::MinorOpClassSet(), gem5::minor::Execute::minorTrace(), gem5::minor::LSQ::StoreBuffer::minorTrace(), gem5::minor::MinorBuffer< ElemType, ReportTraits, BubbleTraits >::minorTrace(), gem5::minor::Scoreboard::minorTrace(), gem5::FALRU::CacheTracking::moveBlockToHead(), gem5::FALRU::CacheTracking::moveBlockToTail(), gem5::ruby::Network::Network(), gem5::ruby::garnet::NetworkLink::NetworkLink(), gem5::TrafficGen::nextState(), gem5::NoncoherentXBar::NoncoherentXBar(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::noneActive(), number_of_ones(), gem5::BaseCPU::numSimulatedInsts(), gem5::BaseCPU::numSimulatedOps(), gem5::ruby::PersistentTable::okToIssueStarving(), gem5::VirtIOConsole::TermTransQueue::onNotifyDescriptor(), gem5::CowDiskImage::open(), gem5::ruby::PerfectSwitch::operateMessageBuffer(), gem5::ruby::PerfectSwitch::operateVnet(), gem5::statistics::DistPrint::operator()(), gem5::statistics::VectorPrint::operator()(), gem5::LinearEquation::operator+(), gem5::TimeBuffer< T >::wire::operator++(), gem5::TimeBuffer< T >::wire::operator--(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), gem5::minor::ForwardInstData::operator=(), gem5::networking::TcpPtr::operator=(), gem5::networking::UdpPtr::operator=(), gem5::ruby::DataBlock::operator=(), gem5::TimeBuffer< T >::wire::operator=(), gem5::TypedBufferArg< T >::operator[](), gem5::ruby::NetDest::OR(), gem5::ruby::WriteMask::orMask(), gem5::ruby::garnet::OutputUnit::OutputUnit(), gem5::QARMA::PACInvSub(), gem5::QARMA::PACMult(), gem5::QARMA::PACSub(), gem5::AtagCore::pagesize(), gem5::MathExpr::parse(), gem5::networking::EthAddr::parse(), gem5::ParseParam< MatStore< X, Y > >::parse(), gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >::parse(), gem5::ParseParam< VecRegContainer< Sz > >::parse(), gem5::TrafficGen::parseConfig(), gem5::PcCountTracker::PcCountTracker(), gem5::PcCountTrackerManager::PcCountTrackerManager(), gem5::ruby::WriteMask::performAtomic(), gem5::ruby::Profiler::ProfilerStats::PerMachineTypeStats::PerMachineTypeStats(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeMachineTypeStats::PerRequestTypeMachineTypeStats(), gem5::ruby::Profiler::ProfilerStats::PerRequestTypeStats::PerRequestTypeStats(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::ARMArchTLB::pickEntryIdxToReplace(), gem5::ConfigCache::pickEntryIdxToReplace(), gem5::IPACache::pickEntryIdxToReplace(), gem5::SMMUTLB::pickEntryIdxToReplace(), gem5::WalkCache::pickEntryIdxToReplace(), gem5::fastmodel::PL330::PL330(), gem5::PortTerminator::PortTerminator(), gem5::Plic::post(), gem5::MaltaCChip::postIntr(), gem5::memory::DRAMInterface::prechargeBank(), gem5::statistics::DataWrapVec< Derived, InfoProxyType >::prepare(), gem5::statistics::DistStor::prepare(), gem5::statistics::HistStor::prepare(), gem5::statistics::Vector2dBase< Derived, Stor >::prepare(), gem5::statistics::VectorDistBase< Derived, Stor >::prepare(), prepareCheckDistStor(), prepareCheckHistStor(), preUnflattenMiscReg(), gem5::ruby::CacheMemory::print(), gem5::ruby::DataBlock::print(), gem5::ruby::NetDest::print(), gem5::ruby::RubyPrefetcher::print(), gem5::ruby::Throttle::print(), gem5::ruby::WriteMask::print(), gem5::SparcISA::TlbMap::print(), gem5::printByteBuf(), gem5::Packet::PrintReqState::printLabels(), gem5::MsrBase::printMsrBase(), gem5::ruby::printSorted(), gem5::System::printSystems(), gem5::ruby::Histogram::printWithMultiplier(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::SpatterGen::processNextGenEvent(), gem5::memory::qos::MemSinkCtrl::processNextReqEvent(), gem5::SpatterGen::processNextSendEvent(), gem5::HSAPacketProcessor::processPkt(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::VegaTLBCoalescer::processProbeTLBEvent(), gem5::memory::NVMInterface::processReadReadyEvent(), gem5::ruby::Profiler::ProfilerStats::ProfilerStats(), gem5::Plic::propagateOutput(), gem5::ProtocolTester::ProtocolTester(), gem5::SDMAEngine::ptePde(), gem5::Queue< Entry >::Queue(), gem5::MinorCPU::randomPriority(), gem5::CowDiskImage::read(), gem5::Gicv3Distributor::read(), gem5::Gicv3Redistributor::read(), gem5::SimpleDisk::read(), gem5::TraceCPU::ElasticDataGen::InputStream::read(), gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::read(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::read(), gem5::VirtQueue::VirtRing< T >::read(), gem5::VGic::readCtrl(), gem5::X86ISA::readPackedMemAtomic(), gem5::VGic::readVCpu(), gem5::readvFunc(), gem5::PixelConverter::readWord(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >::receivedType(), gem5::FALRU::CacheTracking::recordAccess(), gem5::ruby::CacheMemory::recordCacheContents(), gem5::ruby::RubyPort::PioResponsePort::recvAtomic(), gem5::Bridge::BridgeResponsePort::recvFunctional(), gem5::memory::DRAMSim2::recvFunctional(), gem5::memory::DRAMsim3::recvFunctional(), gem5::SerialLink::SerialLinkResponsePort::recvFunctional(), gem5::recvmsgFunc(), gem5::ComputeUnit::DataPort::recvReqRetry(), gem5::ComputeUnit::DTLBPort::recvReqRetry(), gem5::ComputeUnit::ITLBPort::recvReqRetry(), gem5::ComputeUnit::SQCPort::recvReqRetry(), gem5::memory::CfiMemory::recvTimingReq(), gem5::memory::SimpleMemory::recvTimingReq(), gem5::ruby::RubyPort::PioResponsePort::recvTimingReq(), gem5::TLBCoalescer::CpuSidePort::recvTimingReq(), gem5::VegaTLBCoalescer::CpuSidePort::recvTimingReq(), gem5::BaseMemProbe::regProbeListeners(), gem5::BaseCache::CacheStats::regStats(), gem5::BaseCPU::regStats(), gem5::BaseTags::BaseTagStats::regStats(), gem5::BaseXBar::regStats(), gem5::compression::Base::BaseStats::regStats(), gem5::compression::BaseDictionaryCompressor::DictionaryStats::regStats(), gem5::memory::AbstractMemory::MemStats::regStats(), gem5::memory::MemCtrl::CtrlStats::regStats(), gem5::memory::qos::MemCtrl::MemCtrlStats::regStats(), gem5::PowerState::PowerStateStats::regStats(), gem5::ruby::garnet::GarnetNetwork::regStats(), gem5::SectorTags::SectorTagsStats::regStats(), gem5::BaseCache::CacheCmdStats::regStatsFromParent(), gem5::ComputeUnit::releaseWFsFromBarrier(), gem5::SparcISA::ISA::reloadRegMap(), gem5::RangeAddrMapper::remapAddr(), gem5::OutputDirectory::remove(), gem5::PacketFifo::remove(), gem5::PCEventQueue::remove(), gem5::PollQueue::remove(), gem5::BaseRemoteGDB::removeHardBreak(), gem5::AddrRange::removeIntlvBits(), gem5::ruby::NetDest::removeNetDest(), gem5::o3::CPU::removeThread(), gem5::CxxConfigManager::rename(), gem5::minor::ForwardInstData::reportData(), gem5::BaseGlobalEvent::reschedule(), gem5::ActivityRecorder::reset(), gem5::ArmISA::HTMCheckpoint::reset(), gem5::branch_prediction::SimpleIndirectPredictor::reset(), gem5::MemChecker::reset(), gem5::o3::DependencyGraph< DynInstPtr >::reset(), gem5::sinic::Device::reset(), gem5::statistics::DataWrapVec< Derived, InfoProxyType >::reset(), gem5::statistics::DistStor::reset(), gem5::statistics::HistStor::reset(), gem5::statistics::Vector2dBase< Derived, Stor >::reset(), gem5::VirtIODeviceBase::reset(), gem5::ComputeUnit::resetRegisterPool(), gem5::o3::InstructionQueue::resetState(), gem5::ruby::AbstractController::resetStats(), gem5::ruby::garnet::GarnetNetwork::resetStats(), gem5::ruby::garnet::NetworkLink::resetStats(), gem5::ruby::garnet::Router::resetStats(), gem5::ruby::GPUCoalescer::resetStats(), gem5::ruby::Sequencer::resetStats(), gem5::ruby::NetDest::resize(), gem5::statistics::BinaryNode< Op >::result(), gem5::statistics::SumNode< Op >::result(), gem5::statistics::UnaryNode< Op >::result(), gem5::statistics::VectorBase< Derived, Stor >::result(), gem5::statistics::VectorProxy< Stat >::result(), gem5::branch_prediction::ReturnAddrStack::ReturnAddrStack(), gem5::AtagRev::rev(), gem5::AtagCore::rootdev(), gem5::MinorCPU::roundRobinPriority(), gem5::Gicv3Distributor::route(), gem5::RiscvRTC::RTC::RTC(), gem5::ruby::RubyPort::RubyPort(), gem5::SimulatorThreads::runUntilLocalExit(), gem5::sinic::Device::rxKick(), gem5::StackDistCalc::sanityCheckTree(), gem5::CowDiskImage::save(), gem5::AQLRingBuffer::saveHostDispAddr(), gem5::prefetch::SBOOE::SBOOE(), gem5::fastmodel::SCGIC::SCGIC(), gem5::schedGetaffinityFunc(), gem5::BaseGlobalEvent::schedule(), gem5::BaseGlobalEvent::scheduled(), gem5::ruby::garnet::NetworkInterface::scheduleOutputPort(), gem5::BaseCPU::scheduleSimpointsInstStop(), gem5::VectorRegisterFile::scheduleWriteOperandsFromLoad(), gem5::fastmodel::ScxEvsCortexA76< Types >::ScxEvsCortexA76(), gem5::fastmodel::ScxEvsCortexR52< Types >::ScxEvsCortexR52(), gem5::memory::qos::TurnaroundPolicyIdeal::selectBusState(), gem5::selectFunc(), gem5::minor::SelfStallingPipeline< ElemType, ReportTraits, BubbleTraits >::SelfStallingPipeline(), gem5::o3::LSQ::LSQRequest::sendFragmentToTranslation(), gem5::ps2::TouchKit::sendTouchKit(), gem5::AMDGPUVM::serialize(), gem5::ArmISA::PMU::serialize(), gem5::BaseCPU::serialize(), gem5::BaseSemihosting::serialize(), gem5::CpuLocalTimer::serialize(), gem5::CxxConfigManager::serialize(), gem5::DistIface::RecvScheduler::serialize(), gem5::EtherSwitch::Interface::PortFifo::serialize(), gem5::GenericTimer::serialize(), gem5::GicV2::serialize(), gem5::Iris::Interrupts::serialize(), gem5::Iris::ISA::serialize(), gem5::loader::SymbolTable::serialize(), gem5::MemPools::serialize(), gem5::NoMaliGpu::serialize(), gem5::PacketFifo::serialize(), gem5::PciDevice::serialize(), gem5::Plic::serialize(), gem5::PM4PacketProcessor::serialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< BufBytes >::serialize(), gem5::SDMAEngine::serialize(), gem5::sinic::Device::serialize(), gem5::VirtIODeviceBase::serialize(), gem5::X86ISA::TLB::serialize(), gem5::PollQueue::service(), gem5::bloom_filter::MultiBitSel::set(), gem5::WaitClass::set(), gem5::VecPredRegContainer< NumBits, Packed >::setBits(), gem5::OutputDirectory::setDirectory(), gem5::ObjectMatch::setExpression(), Gem5SystemC::ControlExtension::setInstruction(), gem5::ruby::WriteMask::setInvertedMask(), gem5::DistEtherLink::Link::setLocalInt(), gem5::ruby::WriteMask::setMask(), gem5::RegisterManager::setParent(), gem5::X86ISA::Interrupts::setReg(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::fastmodel::FastmodelRemoteGDB::AArch64GdbRegCache::setRegs(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), gem5::EtherLink::Link::setRxInt(), gem5::Vector2dStatTester::setStats(), gem5::VectorStatTester::setStats(), gem5::X86ISA::setThreadArea32Func(), gem5::EtherLink::Link::setTxInt(), TwoDifferentMatRegs::SetUp(), gem5::ArmISA::Crypto::sha256Op(), gem5::ruby::Topology::shortest_path_to_node(), gem5::X86ISA::I82094AA::signalInterrupt(), simd_modified_imm(), gem5::MipsISA::simdPack(), gem5::MipsISA::simdUnpack(), gem5::branch_prediction::SimpleBTB::SimpleBTB(), gem5::SimpleCache::SimpleCache(), gem5::branch_prediction::SimpleIndirectPredictor::SimpleIndirectPredictor(), gem5::ruby::SimpleNetwork::SimpleNetwork(), gem5::ArmISA::PredMacroOp::size(), gem5::X86ISA::MacroopBase::size(), gem5::SkewedAssociative::skew(), gem5::ruby::NetDest::smallestElement(), gem5::ruby::Set::smallestElement(), gem5::AtagSerial::sn(), gem5::GicV2::softInt(), gem5::LinearSystem::solve(), gem5::o3::Decode::sortInsts(), gem5::o3::IEW::sortInsts(), gem5::o3::Rename::sortInsts(), gem5::branch_prediction::TAGEBase::squash(), gem5::o3::Decode::squash(), gem5::o3::Decode::squash(), gem5::o3::Rename::squash(), gem5::o3::DynInst::srcRegIdx(), gem5::StaticInst::srcRegIdx(), gem5::MemChecker::startRead(), gem5::MemTraceProbe::startup(), gem5::ThermalModel::startup(), gem5::MemChecker::startWrite(), gem5::minor::LSQ::StoreBuffer::step(), gem5::guest_abi::Result< Aapcs32, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)==sizeof(uint64_t))> >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs64, HA, typename std::enable_if_t< IsAapcs64HxaV< HA > > >::store(), gem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> >::store(), gem5::guest_abi::Result< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::store(), gem5::ArmISA::Crypto::store1Reg(), gem5::o3::StoreSet::StoreSet(), gem5::statistics::ConstVectorNode< T >::str(), gem5::ruby::SubBlock::SubBlock(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS(), gem5::branch_prediction::TAGEBase::tagePredict(), gem5::FALRU::tagsInit(), gem5::BaseCPU::takeOverFrom(), gem5::o3::IEW::takeOverFrom(), gem5::ruby::TBEStorage::TBEStorage(), gem5::TCPIface::TCPIface(), gem5::VirtIO9PDiod::terminateDiod(), gem5::fastmodel::SCGIC::Terminator::Terminator(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_P(), gem5::ruby::testAndRead(), gem5::ruby::testAndReadMask(), gem5::ruby::testAndWrite(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::ThreadData(), gem5::trace::ArmNativeTrace::ThreadState::ThreadState(), gem5::AtomicSimpleCPU::tick(), gem5::o3::Fetch::tick(), gem5::TimeBuffer< T >::TimeBuffer(), gem5::GenericTimerMem::timerCtrlRead(), gem5::GenericTimerMem::timerCtrlWrite(), gem5::AddrRange::to_string(), gem5::compression::Base::toChunks(), gem5::ruby::Topology::Topology(), gem5::LinearEquation::toStr(), gem5::branch_prediction::ReturnAddrStack::AddrStack::toString(), gem5::statistics::BinaryNode< Op >::total(), gem5::statistics::ConstVectorNode< T >::total(), gem5::statistics::SumNode< Op >::total(), gem5::statistics::UnaryNode< Op >::total(), gem5::statistics::Vector2dBase< Derived, Stor >::total(), gem5::statistics::VectorBase< Derived, Stor >::total(), gem5::statistics::VectorProxy< Stat >::total(), gem5::MinorCPU::totalInsts(), gem5::o3::CPU::totalInsts(), gem5::MinorCPU::totalOps(), gem5::o3::CPU::totalOps(), gem5::branch_prediction::TournamentBP::TournamentBP(), gem5::memory::AbstractMemory::trackLoadLocked(), gem5::branch_prediction::MultiperspectivePerceptron::train(), gem5::Bridge::BridgeRequestPort::trySatisfyFunctional(), gem5::Packet::trySatisfyFunctional(), gem5::PacketQueue::trySatisfyFunctional(), gem5::SerialLink::SerialLinkRequestPort::trySatisfyFunctional(), gem5::ruby::RubyPort::trySendRetries(), gem5::EtherBus::txDone(), gem5::ruby::PersistentTable::typeOfSmallest(), gem5::CxxConfigManager::unRename(), gem5::AMDGPUVM::unserialize(), gem5::ArmISA::PMU::unserialize(), gem5::BaseCPU::unserialize(), gem5::BaseSemihosting::unserialize(), gem5::CpuLocalTimer::unserialize(), gem5::DistIface::RecvScheduler::unserialize(), gem5::DVFSHandler::unserialize(), gem5::EmulationPageTable::unserialize(), gem5::EtherSwitch::Interface::PortFifo::unserialize(), gem5::GenericTimer::unserialize(), gem5::GicV2::unserialize(), gem5::loader::SymbolTable::unserialize(), gem5::memory::PhysicalMemory::unserialize(), gem5::MemPools::unserialize(), gem5::MemState::unserialize(), gem5::NoMaliGpu::unserialize(), gem5::PacketFifo::unserialize(), gem5::PciDevice::unserialize(), gem5::Plic::unserialize(), gem5::PM4PacketProcessor::unserialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< BufBytes >::unserialize(), gem5::Root::unserialize(), gem5::SDMAEngine::unserialize(), gem5::sinic::Device::unserialize(), gem5::VirtIODeviceBase::unserialize(), gem5::X86ISA::I82094AA::unserialize(), gem5::X86ISA::TLB::unserialize(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::Gicv3Distributor::update(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::trace::X86NativeTrace::ThreadState::update(), gem5::trace::X86NativeTrace::ThreadState::update(), gem5::branch_prediction::MultiperspectivePerceptron::ThreadData::updateAcyclic(), gem5::ArmISA::PMU::updateAllCounters(), gem5::branch_prediction::TAGEBase::updateGHist(), gem5::branch_prediction::MultiperspectivePerceptron::updateHistories(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), gem5::branch_prediction::TAGEBase::updateHistories(), gem5::Plic::updateInt(), gem5::VGic::updateIntState(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::updateKvmStateFPUCommon(), gem5::X86KvmCPU::updateKvmStateXCRs(), gem5::o3::DynInst::updateMiscRegs(), gem5::ruby::TimerTable::updateNext(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updatePartial(), gem5::branch_prediction::MPP_TAGE::updatePathAndGlobalHistory(), gem5::branch_prediction::TAGE_SC_L_TAGE::updatePathAndGlobalHistory(), gem5::TLBCoalescer::updatePhysAddresses(), gem5::VegaTLBCoalescer::updatePhysAddresses(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updatePred(), gem5::ruby::PerfectSwitch::updatePriorityGroups(), gem5::GicV2::updateRunPri(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::updateThreadContextFPUCommon(), gem5::X86KvmCPU::updateThreadContextMSRs(), gem5::X86KvmCPU::updateThreadContextXCRs(), gem5::StackDistCalc::updateTree(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateVec(), gem5::ActivityRecorder::validate(), gem5::Memoizer< Ret, Args >::validateMemoizer(), gem5::o3::Rename::validInsts(), gem5::statistics::VectorBase< Derived, Stor >::value(), gem5::Vector2dStatTester::Vector2dStatTesterStats::Vector2dStatTesterStats(), gem5::VectorStatTester::VectorStatTesterStats::VectorStatTesterStats(), gem5::VirtQueue::VirtQueue(), gem5::Gicv3CPUInterface::virtualDropPriority(), gem5::Gicv3CPUInterface::virtualHighestActivePriority(), gem5::statistics::Text::visit(), gem5::statistics::Text::visit(), gem5::statistics::Text::visit(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), gem5::ArmISA::VstSingleOp64::VstSingleOp64(), gem5::o3::MemDepUnit::wakeDependents(), gem5::WalkCache::WalkCache(), gem5::VectorRegisterFile::waveExecuteInst(), gem5::Wavefront::Wavefront(), gem5::CowDiskImage::write(), gem5::Gicv3Distributor::write(), gem5::Gicv3Redistributor::write(), gem5::VegaISA::ScalarOperand< DataType, Const, NumDwords >::write(), gem5::VirtQueue::VirtRing< T >::write(), gem5::CowDiskImage::writeback(), gem5::o3::IEW::writebackInsts(), gem5::Packet::writeData(), gem5::Plic::writeEnable(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::intelmp::FloatingPointer::writeOut(), gem5::X86ISA::smbios::SMBiosTable::writeOut(), gem5::writeOutString(), gem5::X86ISA::writePackedMem(), gem5::Plic::writePriority(), gem5::SDMAEngine::writeReadData(), gem5::X86ISA::E820Table::writeTo(), gem5::VGic::writeVCpu(), gem5::writevFunc(), gem5::PixelConverter::writeWord(), gem5::X86IdeController::X86IdeController(), gem5::X86ISA::X86MicroopBase::X86MicroopBase(), gem5::X86ISA::Cmos::X86RTC::X86RTC(), gem5::statistics::DataWrapVec2d< Derived, InfoProxyType >::ysubname(), gem5::statistics::DataWrapVec2d< Derived, InfoProxyType >::ysubnames(), gem5::HorizontalSlice< ElemType, Container, FromTile >::zero(), gem5::statistics::Formula::zero(), gem5::statistics::VectorBase< Derived, Stor >::zero(), gem5::statistics::VectorDistBase< Derived, Stor >::zero(), gem5::Tile< ElemType, Container >::zero(), gem5::VerticalSlice< ElemType, Container, FromTile >::zero(), gem5::ArmISA::ISA::zeroSveVecRegUpperPart(), gem5::BaseGlobalEvent::~BaseGlobalEvent(), gem5::ruby::CacheMemory::~CacheMemory(), gem5::CheckTable::~CheckTable(), gem5::ComputeUnit::~ComputeUnit(), gem5::CowDiskImage::~CowDiskImage(), gem5::ruby::DirectoryMemory::~DirectoryMemory(), gem5::o3::DynInst::~DynInst(), gem5::minor::Execute::~Execute(), gem5::o3::FUPool::~FUPool(), gem5::o3::MemDepUnit::MemDepEntry::~MemDepEntry(), gem5::PollQueue::~PollQueue(), gem5::ProtocolTester::~ProtocolTester(), gem5::RubyDirectedTester::~RubyDirectedTester(), gem5::RubyTester::~RubyTester(), gem5::minor::LSQ::SplitDataRequest::~SplitDataRequest(), and gem5::TimeBuffer< T >::~TimeBuffer().

i16i64

Bitfield<55, 52> gem5::ArmISA::i16i64

Definition at line 250 of file misc_types.hh.

i8i32

Bitfield<39, 36> gem5::ArmISA::i8i32

Definition at line 252 of file misc_types.hh.

i8mm

Bitfield< 47, 44 > gem5::ArmISA::i8mm

Definition at line 96 of file misc_types.hh.

iCacheLineSize

gem5::ArmISA::iCacheLineSize

Definition at line 724 of file misc_types.hh.

iccIgrpEnEL1

Bitfield<39> gem5::ArmISA::iccIgrpEnEL1

Definition at line 1030 of file misc_types.hh.

iciallu

Bitfield<1> gem5::ArmISA::iciallu

Definition at line 1012 of file misc_types.hh.

icialluis

Bitfield<0> gem5::ArmISA::icialluis

Definition at line 1013 of file misc_types.hh.

icivau

Bitfield<2> gem5::ArmISA::icivau

Definition at line 1011 of file misc_types.hh.

id

Bitfield<33> gem5::ArmISA::id

Definition at line 331 of file misc_types.hh.

Referenced by gem5::ArmISA::PMU::addEventProbe(), gem5::memory::qos::MemCtrl::addRequestor(), gem5::ArmISA::PMU::addSoftwareIncrementEvent(), gem5::Request::createMemManagement(), gem5::ArmV8KvmCPU::dump(), gem5::memory::qos::MemCtrl::escalateQueues(), gem5::RegClass::flatten(), gem5::RegClassOps::flatten(), gem5::ruby::garnet::flit::flit(), gem5::ArmISA::PMU::getCounter(), gem5::ArmISA::PMU::getCounter(), gem5::RiscvISA::Interrupts::getInterrupt(), gem5::BaseKvmCPU::getOneReg(), gem5::AMDGPUDevice::getSDMAById(), gem5::ruby::IDToInt(), gem5::o3::LSQUnit::init(), gem5::ArmProcess32::initState(), gem5::ArmProcess64::initState(), gem5::Iris::ThreadContext::installBp(), gem5::Iris::ThreadContext::instanceRegistryChanged(), gem5::ruby::intToID(), gem5::Dueler::isSample(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::qos::MemCtrl::logResponse(), gem5::System::lookupRequestorId(), gem5::PM4PacketProcessor::newQueue(), gem5::ruby::garnet::OutVcState::OutVcState(), gem5::TrafficGen::parseConfig(), gem5::ArmISA::PMU::registerEvent(), gem5::ruby::RubySystem::registerRequestorIDs(), gem5::Workload::replaceThreadContext(), gem5::minor::Fetch1::FetchRequest::reportData(), gem5::BaseRemoteGDB::scheduleTrapEvent(), gem5::Iris::ThreadContext::setContextId(), gem5::ThreadState::setContextId(), gem5::BaseKvmCPU::setOneReg(), gem5::ArmISA::mpam::PartitionFieldExtension::setPartitionID(), gem5::ArmISA::mpam::PartitionFieldExtension::setPartitionMonitoringID(), gem5::Dueler::setSample(), gem5::CacheBlk::setSrcRequestorId(), gem5::Iris::ThreadContext::setThreadId(), gem5::ThreadState::setThreadId(), gem5::Request::setVirt(), gem5::ruby::SimpleNetwork::SimpleNetwork(), gem5::BaseCPU::taskId(), gem5::Request::taskId(), gem5::System::Threads::thread(), gem5::System::Threads::thread(), and gem5::PM4PacketProcessor::unmapQueues().

idc

Bitfield<7> gem5::ArmISA::idc

Definition at line 522 of file misc_types.hh.

ide

Bitfield<15> gem5::ArmISA::ide

Definition at line 528 of file misc_types.hh.

ids

Bitfield<39, 36> gem5::ArmISA::ids

Definition at line 184 of file misc_types.hh.

Referenced by gem5::Iris::ThreadContext::extractResourceMap().

iesb

Bitfield<15, 12> gem5::ArmISA::iesb

Definition at line 190 of file misc_types.hh.

ifsc

Bitfield< 5, 0 > gem5::ArmISA::ifsc

Definition at line 792 of file misc_types.hh.

il

Bitfield< 25 > gem5::ArmISA::il

Definition at line 61 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmFault::setSyndrome().

illegalExecution

Bitfield<61> gem5::ArmISA::illegalExecution

Definition at line 62 of file types.hh.

imm

Bitfield<7, 0> gem5::ArmISA::imm

Definition at line 132 of file types.hh.

Referenced by AArch64AArch32SystemAccessTrap(), gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp(), gem5::ArmISA::BigFpMemLitOp::BigFpMemLitOp(), gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp(), gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::VegaISA::clampF16(), gem5::ArmISA::PredIntOp::generateDisassembly(), mcrMrc15Trap(), mcrrMrrc15Trap(), gem5::OperandInfo::OperandInfo(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::softwareBreakpoint32(), sveDecodePredCount(), sveDisasmPredCountImm(), sveExpandFpImmAddSub(), sveExpandFpImmMaxMin(), sveExpandFpImmMul(), vfpFpToFixed(), vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), and vfpUFixedToFpS().

immed11_0

Bitfield<11, 0> gem5::ArmISA::immed11_0

Definition at line 136 of file types.hh.

immed23_0

Bitfield<23, 0> gem5::ArmISA::immed23_0

Definition at line 146 of file types.hh.

immed7_0

Bitfield<7, 0> gem5::ArmISA::immed7_0

Definition at line 137 of file types.hh.

immedHi11_8

Bitfield<11, 8> gem5::ArmISA::immedHi11_8

Definition at line 139 of file types.hh.

immedLo3_0

Bitfield<3, 0> gem5::ArmISA::immedLo3_0

Definition at line 140 of file types.hh.

imo

Bitfield<4> gem5::ArmISA::imo

Definition at line 361 of file misc_types.hh.

Referenced by gem5::ArmISA::Interrupts::takeVirtualInt32().

implementer

Bitfield<31, 24> gem5::ArmISA::implementer

Definition at line 851 of file misc_types.hh.

instBits

uint32_t gem5::ArmISA::instBits

Definition at line 87 of file types.hh.

intdis

Bitfield<23, 22> gem5::ArmISA::intdis

Definition at line 906 of file misc_types.hh.

interptCtrlPresent

Bitfield<23> gem5::ArmISA::interptCtrlPresent

Definition at line 717 of file misc_types.hh.

intRegClass

RegClass gem5::ArmISA::intRegClass

inlineconstexpr

Initial value:

=
    RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs).
    ops(intRegClassOps).
    needsFlattening()

Definition at line 173 of file int.hh.

Referenced by gem5::PowerProcess::argsInit(), gem5::MipsISA::ISA::copyRegsFrom(), gem5::PowerISA::ISA::copyRegsFrom(), gem5::RiscvISA::ISA::copyRegsFrom(), gem5::MipsISA::forkThread(), gem5::RiscvISA::AtomicMemOp::generateDisassembly(), gem5::RiscvISA::LoadReserved::generateDisassembly(), gem5::RiscvISA::StoreCond::generateDisassembly(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > sizeof(uint32_t)) > >::get(), gem5::guest_abi::Argument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=sizeof(uint32_t)) > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > 8)> >::get(), gem5::guest_abi::Argument< Aapcs64, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)<=8)> >::get(), gem5::Iris::ThreadContext::getIntRegRscId(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::getRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::getRegs(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::prepare(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), gem5::Iris::ThreadContext::setIntRegFlat(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARC64GdbRegCache::setRegs(), gem5::SparcISA::RemoteGDB::SPARCGdbRegCache::setRegs(), gem5::ArmISAInst::Tstart64::Tstart64(), gem5::ArmISAInst::Ttest64::Ttest64(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateTCStateCore(), gem5::ArmV8KvmCPU::updateThreadContext(), and gem5::ArmISA::int_reg::x().

intRegClassOps

IntRegClassOps gem5::ArmISA::intRegClassOps

inlineconstexpr

Definition at line 171 of file int.hh.

INTRLVREG0

const int gem5::ArmISA::INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs

Definition at line 88 of file vec.hh.

Referenced by gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSI(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::SveLdStructSS(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSI(), and gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::SveStStructSS().

INTRLVREG1

const int gem5::ArmISA::INTRLVREG1 = INTRLVREG0 + 1

Definition at line 89 of file vec.hh.

INTRLVREG2

const int gem5::ArmISA::INTRLVREG2 = INTRLVREG0 + 2

Definition at line 90 of file vec.hh.

INTRLVREG3

const int gem5::ArmISA::INTRLVREG3 = INTRLVREG0 + 3

Definition at line 91 of file vec.hh.

ioe

Bitfield<8> gem5::ArmISA::ioe

Definition at line 523 of file misc_types.hh.

ips

Bitfield< 34, 32 > gem5::ArmISA::ips

Definition at line 591 of file misc_types.hh.

ir0

gem5::ArmISA::ir0

Definition at line 683 of file misc_types.hh.

ir1

Bitfield<3,2> gem5::ArmISA::ir1

Definition at line 684 of file misc_types.hh.

ir2

Bitfield<5,4> gem5::ArmISA::ir2

Definition at line 685 of file misc_types.hh.

ir3

Bitfield<7,6> gem5::ArmISA::ir3

Definition at line 686 of file misc_types.hh.

ir4

Bitfield<9,8> gem5::ArmISA::ir4

Definition at line 687 of file misc_types.hh.

ir5

Bitfield<11,10> gem5::ArmISA::ir5

Definition at line 688 of file misc_types.hh.

ir6

Bitfield<13,12> gem5::ArmISA::ir6

Definition at line 689 of file misc_types.hh.

ir7

Bitfield<15,14> gem5::ArmISA::ir7

Definition at line 690 of file misc_types.hh.

irgn0

Bitfield< 9, 8 > gem5::ArmISA::irgn0

Definition at line 580 of file misc_types.hh.

irgn1

Bitfield< 25, 24 > gem5::ArmISA::irgn1

Definition at line 587 of file misc_types.hh.

irq

Bitfield<1> gem5::ArmISA::irq

Definition at line 416 of file misc_types.hh.

Referenced by gem5::LupioTTY::lupioTTYUpdateIRQ(), gem5::fastmodel::PL330::PL330(), gem5::KvmKernelGic::setIntState(), and gem5::KvmVM::setIRQLine().

isMisc

Bitfield<32> gem5::ArmISA::isMisc

Definition at line 85 of file types.hh.

isrEL1

Bitfield<18> gem5::ArmISA::isrEL1

Definition at line 1051 of file misc_types.hh.

iss

Bitfield< 19, 0 > gem5::ArmISA::iss

Definition at line 756 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::checkAdvSIMDOrFPEnabled32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap32(), gem5::ArmISA::ArmStaticInst::checkForWFxTrap64(), gem5::memory::DRAMSim2Wrapper::extractConfig(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrMrcIssExtract(), mcrrMrrc15TrapToHyp(), gem5::ArmISA::ArmStaticInst::smeAccessTrap(), and gem5::Random::unserialize().

isv

Bitfield< 24 > gem5::ArmISA::isv

Definition at line 771 of file misc_types.hh.

it1

Bitfield<26, 25> gem5::ArmISA::it1

Definition at line 56 of file misc_types.hh.

Referenced by gem5::FutexMap::requeue().

it2

Bitfield<15, 10> gem5::ArmISA::it2

Definition at line 63 of file misc_types.hh.

Referenced by gem5::FutexMap::requeue().

itd

Bitfield<7> gem5::ArmISA::itd

Definition at line 468 of file misc_types.hh.

Referenced by getRestoredITBits().

itstate

Bitfield<55, 48> gem5::ArmISA::itstate

Definition at line 70 of file types.hh.

Referenced by gem5::ArmISA::ArmFault::invoke64().

itstateCond

Bitfield<55, 52> gem5::ArmISA::itstateCond

Definition at line 71 of file types.hh.

itstateMask

Bitfield<51, 48> gem5::ArmISA::itstateMask

Definition at line 72 of file types.hh.

ixc

Bitfield<4> gem5::ArmISA::ixc

Definition at line 521 of file misc_types.hh.

ixe

Bitfield<12> gem5::ArmISA::ixe

Definition at line 527 of file misc_types.hh.

jscvt

Bitfield< 15, 12 > gem5::ArmISA::jscvt

Definition at line 102 of file misc_types.hh.

l1IndexPolicy

Bitfield<15,14> gem5::ArmISA::l1IndexPolicy

Definition at line 726 of file misc_types.hh.

l2rstDISABLE_monitor

Bitfield<31> gem5::ArmISA::l2rstDISABLE_monitor

Definition at line 720 of file misc_types.hh.

lbn

Bitfield< 19, 16 > gem5::ArmISA::lbn

Definition at line 874 of file misc_types.hh.

len

Bitfield< 3, 0 > gem5::ArmISA::len

Definition at line 529 of file misc_types.hh.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::loader::DtbFile::addBootCmdLine(), gem5::CircularQueue< T >::advance_tail(), gem5::VncServer::checkProtocolVersion(), gem5::AtagCmdline::cmdline(), gem5::BaseRemoteGDB::cmdMemR(), gem5::BaseRemoteGDB::cmdMemW(), gem5::ruby::GPUCoalescer::completeIssue(), gem5::branch_prediction::MultiperspectivePerceptron::computeBits(), gem5::PacketFifo::copyout(), gem5::ruby::DataBlock::copyPartial(), gem5::Terminal::data(), gem5::ruby::DMASequencer::dataCallback(), gem5::trace::Logger::dump(), gem5::cp::Print::endArgs(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::networking::Ip6Hdr::extensionLength(), gem5::fallocateFunc(), gem5::loader::DtbFile::findReleaseAddr(), gem5::BaseSemihosting::File::flen(), gem5::DmaReadFifo::get(), gem5::ArmISA::ISA::getCurSmeVecLenInBits(), gem5::ArmISA::ISA::getCurSveVecLenInBits(), gem5::ruby::DataBlock::getData(), gem5::ruby::WriteMask::getMask(), gem5::getsocknameFunc(), gem5::getsockoptFunc(), gem5::pseudo_inst::initParam(), gem5::ruby::DMASequencer::makeRequest(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::nb_transport_fw(), gem5::networking::TcpHdr::options(), gem5::CircleBuf< T >::peek(), gem5::CircleBuf< T >::peek(), gem5::Fifo< T >::peek(), gem5::linux::printk(), gem5::cp::Print::process(), gem5::VirtQueue::produceDescriptor(), gem5::BaseSemihosting::FileFeatures::read(), gem5::CircleBuf< T >::read(), gem5::Fifo< T >::read(), gem5::Terminal::read(), gem5::VirtIO9PDiod::read(), gem5::VirtIO9PSocket::read(), gem5::VncServer::read(), gem5::VncServer::read1(), gem5::VirtIO9PProxy::readAll(), gem5::pseudo_inst::readfile(), gem5::BaseSemihosting::readString(), gem5::EtherTapStub::recvReal(), gem5::ComputeUnit::DataPort::recvReqRetry(), gem5::ComputeUnit::DTLBPort::recvReqRetry(), gem5::ComputeUnit::ITLBPort::recvReqRetry(), gem5::ComputeUnit::SQCPort::recvReqRetry(), gem5::ps2::TouchKit::recvTouchKit(), gem5::PacketFifo::reserve(), gem5::VncServer::sendError(), gem5::EtherTapStub::sendReal(), gem5::EtherTapBase::sendSimulated(), gem5::ruby::DataBlock::setData(), gem5::ruby::WriteMask::setMask(), gem5::ArmISA::Decoder::setSmeLen(), gem5::setsockoptFunc(), gem5::ArmISA::Decoder::setSveLen(), gem5::KvmVM::setUserMemoryRegion(), gem5::ruby::RubyRequest::setWriteMask(), gem5::to_lower(), gem5::DmaReadFifo::tryGet(), gem5::VirtIOConsole::TermRecvQueue::trySend(), gem5::VirtIORng::RngQueue::trySend(), gem5::CircleBuf< T >::write(), gem5::Fifo< T >::write(), gem5::Terminal::write(), gem5::VirtIO9PDiod::write(), gem5::VirtIO9PSocket::write(), gem5::VncServer::write(), gem5::VirtIO9PProxy::writeAll(), and gem5::pseudo_inst::writefile().

lo

Bitfield<19, 16> gem5::ArmISA::lo

Definition at line 171 of file misc_types.hh.

Referenced by gem5::trace::TarmacParserRecord::advanceTrace().

loadOp

Bitfield<20> gem5::ArmISA::loadOp

Definition at line 127 of file types.hh.

lookUpMiscReg

std::vector< struct MiscRegLUTEntry > gem5::ArmISA::lookUpMiscReg

(

NUM_MISCREGS

)

Definition at line 1694 of file misc.hh.

Referenced by canReadCoprocReg(), canWriteCoprocReg(), checkFaultAccessAArch64SysReg(), gem5::ArmISA::ISA::clear(), gem5::ArmISA::ISA::flattenMiscIndex(), gem5::ArmISA::ISA::getMiscIndices(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::ArmISA::ISA::InitReg(), preUnflattenMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::ISA::readMiscRegReset(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), snsBankedIndex(), gem5::ArmISA::ISA::snsBankedIndex64(), and gem5::ArmISA::ISA::unserialize().

lorcEL1

Bitfield<19> gem5::ArmISA::lorcEL1

Definition at line 1050 of file misc_types.hh.

loreaEL1

Bitfield<20> gem5::ArmISA::loreaEL1

Definition at line 1049 of file misc_types.hh.

loridEL1

Bitfield<21> gem5::ArmISA::loridEL1

Definition at line 1048 of file misc_types.hh.

lornEL1

Bitfield<22> gem5::ArmISA::lornEL1

Definition at line 1047 of file misc_types.hh.

lorsaEL1

Bitfield<23> gem5::ArmISA::lorsaEL1

Definition at line 1046 of file misc_types.hh.

lpae

Bitfield< 11 > gem5::ArmISA::lpae

Definition at line 509 of file misc_types.hh.

Referenced by gem5::ArmISA::TlbEntry::setAttributes().

lrcpc

Bitfield<23, 20> gem5::ArmISA::lrcpc

Definition at line 142 of file misc_types.hh.

lsm

Bitfield<11, 8> gem5::ArmISA::lsm

Definition at line 191 of file misc_types.hh.

lsv

Bitfield<4, 3> gem5::ArmISA::lsv

Definition at line 893 of file misc_types.hh.

ltcoproc

Bitfield<11, 8> gem5::ArmISA::ltcoproc

Definition at line 202 of file types.hh.

ltopcode11_8

Bitfield<11, 8> gem5::ArmISA::ltopcode11_8

Definition at line 196 of file types.hh.

ltopcode15

Bitfield<15> gem5::ArmISA::ltopcode15

Definition at line 195 of file types.hh.

ltopcode4

Bitfield<4> gem5::ArmISA::ltopcode4

Definition at line 199 of file types.hh.

ltopcode7_4

Bitfield<7, 4> gem5::ArmISA::ltopcode7_4

Definition at line 198 of file types.hh.

ltopcode7_6

Bitfield<7, 6> gem5::ArmISA::ltopcode7_6

Definition at line 197 of file types.hh.

ltrd

Bitfield<11, 8> gem5::ArmISA::ltrd

Definition at line 201 of file types.hh.

m

Bitfield<0> gem5::ArmISA::m

Definition at line 478 of file misc_types.hh.

Referenced by gem5::memory::PhysicalMemory::access(), gem5::prefetch::Base::addMMU(), gem5::AMDGPUDevice::AMDGPUDevice(), gem5::RealViewOsc::clockPeriod(), gem5::SrcClockDomain::clockPeriod(), gem5::AMDGPU::convertMXFP(), gem5::memory::PhysicalMemory::createBackingStore(), gem5::ruby::MessageBuffer::delayHead(), gem5::ruby::MessageBuffer::enqueueDeferredMessages(), gem5::GlobalMemPipeline::exec(), gem5::LocalMemPipeline::exec(), gem5::ScalarMemPipeline::exec(), gem5::RiscvISA::VMaskMergeMicroInst::execute(), gem5::ruby::garnet::NetworkInterface::flitisizeMessage(), gem5::memory::PhysicalMemory::functionalAccess(), gem5::init_drain(), gem5::init_loader(), gem5::init_net(), gem5::init_pc(), gem5::init_range(), gem5::init_serialize(), gem5::DistEtherLink::LocalIface::LocalIface(), gem5::loader::MemoryImage::mask(), gem5::loader::SymbolTable::mask(), gem5::memory::PhysicalMemory::PhysicalMemory(), gem5::TesterThread::printOutstandingReqs(), gem5::pybind_init_event(), gem5::pybind_init_stats(), gem5::pybind_init_tracers(), gem5::statistics::pythonDump(), gem5::statistics::pythonReset(), gem5::ruby::MessageBuffer::reanalyzeList(), gem5::PybindSimObjectResolver::resolveSimObject(), gem5::memory::PhysicalMemory::serialize(), gem5::DistEtherLink::RxLink::setDistInt(), gem5::DistEtherLink::TxLink::setDistInt(), gem5::KvmVM::setUserMemoryRegion(), gem5::ruby::Topology::shortest_path_to_node(), gem5::RealViewOsc::startup(), TEST(), TEST(), gem5::memory::PhysicalMemory::unserialize(), gem5::DerivedClockDomain::updateClockPeriod(), gem5::ruby::NetDest::vecIndex(), and gem5::Gicv2m::write().

m5Func

Bitfield<15, 8> gem5::ArmISA::m5Func

Definition at line 156 of file types.hh.

mairEL1

Bitfield<24> gem5::ArmISA::mairEL1

Definition at line 1045 of file misc_types.hh.

mask

Bitfield< 28, 24 > gem5::ArmISA::mask

Definition at line 63 of file pcstate.hh.

Referenced by gem5::FALRU::accessBlock(), gem5::compression::FPC::FPCCompData::addEntry(), addPAC(), gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::AddrRange::AddrRange(), gem5::Flags< T >::allSet(), gem5::ArmProcess::argsInit(), gem5::ruby::DataBlock::atomicPartial(), auth(), gem5::branch_prediction::BiModeBP::BiModeBP(), gem5::PowerISA::IntConcatRotateOp::bitmask(), gem5::PowerISA::IntRotateOp::bitmask(), gem5::bits(), gem5::SparcISA::buildPstateMask(), gem5::ArmSemihosting::call64(), gem5::RiscvSemihosting::call64(), gem5::CopyEngine::CopyEngineChannel::channelWrite(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::TableWalker::checkVAddrSizeFaultAArch64(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::AMDGPU::convertMXFP(), gem5::ruby::DataBlock::copyPartial(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::GenericPciHost::decodeAddress(), gem5::compression::DictionaryCompressor< T >::MaskedPattern< mask >::decompress(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::defaultPartialWriter(), gem5::trace::CapstoneDisassembler::disassemble(), gem5::GPUDynInst::doApertureCheck(), gem5::SparcISA::doNormalFault(), gem5::SMMUTranslationProcess::doReadPTE(), gem5::SparcISA::doREDFault(), gem5::RiscvISA::TLB::doTranslate(), gem5::ArmISA::ArmStaticInst::encoding(), gem5::VegaISA::Inst_SOP2__S_MUL_I32::execute(), gem5::VegaISA::Inst_SOPK__S_GETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT2_I32_I16::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT4_I32_I8::execute(), gem5::VegaISA::Inst_VOP3P__V_DOT8_I32_I4::execute(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::findLsbSet(), gem5::findParity(), gem5::findZero(), finishVfp(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::firstActive(), fixFpDFpSDest(), fixFpSFpDDest(), gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::formatReg(), gem5::ruby::MessageBuffer::functionalAccess(), gem5::ruby::garnet::CrossbarSwitch::functionalRead(), gem5::ruby::garnet::flit::functionalRead(), gem5::ruby::garnet::flitBuffer::functionalRead(), gem5::ruby::garnet::GarnetNetwork::functionalRead(), gem5::ruby::garnet::InputUnit::functionalRead(), gem5::ruby::garnet::NetworkInterface::functionalRead(), gem5::ruby::garnet::NetworkLink::functionalRead(), gem5::ruby::garnet::OutputUnit::functionalRead(), gem5::ruby::garnet::Router::functionalRead(), gem5::ruby::garnet::VirtualChannel::functionalRead(), gem5::ruby::MessageBuffer::functionalRead(), gem5::ruby::SimpleNetwork::functionalRead(), gem5::ruby::Switch::functionalRead(), gem5::guest_abi::Argument< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer) > sizeof(uint32_t)) > >::get(), gem5::prefetch::DeltaCorrelatingPredictionTables::DCPTEntry::getCandidates(), gem5::SparcISA::getHyperVector(), gem5::SparcISA::getPrivVector(), gem5::RiscvISA::Interrupts::globalMask(), gem5::AddrRange::granularity(), gem5::ruby::DMASequencer::init(), gem5::ArmISA::ISA::initializeMiscRegMetadata(), gem5::insertBits(), gem5::PowerISA::PowerStaticInst::insertCRField(), gem5::HDLcd::intMask(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL32(), gem5::ArmISA::SelfDebug::isDebugEnabledForEL64(), gem5::compression::DictionaryCompressor< T >::MaskedPattern< mask >::isPattern(), gem5::compression::DictionaryCompressor< T >::MaskedValuePattern< value, mask >::isPattern(), gem5::compression::FPC::SignExtendedTwoHalfwords::isPattern(), gem5::Flags< T >::isSet(), gem5::compression::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), gem5::KernelWorkload::KernelWorkload(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::lastActive(), gem5::SMMUCommandExecProcess::main(), gem5::SparcISA::TLB::MakeTsbPtr(), maskTaggedAddr(), gem5::mbits(), gem5::ArmISA::Stage2LookUp::mergeTe(), mul62x62(), gem5::BaseCPU::mwait(), gem5::BaseCPU::mwaitAtomic(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::noneActive(), gem5::Flags< T >::noneSet(), sc_gem5::VcdTraceValInt< T >::output(), gem5::VegaISA::GpuTLB::pageAlign(), gem5::ArmSystem::physAddrMask(), gem5::linux::printk(), gem5::SparcISA::ISA::processHSTickCompare(), gem5::SparcISA::ISA::processSTickCompare(), gem5::VegaISA::quadMask(), gem5::ArmISA::MiscRegLUTEntryInitializer::rao(), gem5::ArmISA::MiscRegLUTEntryInitializer::raz(), gem5::MipsISA::readDSPControl(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::Iob::receiveDeviceInterrupt(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::Flags< T >::replace(), gem5::UFSHostDevice::requestHandler(), gem5::ArmISA::MiscRegLUTEntryInitializer::res0(), gem5::ArmISA::MiscRegLUTEntryInitializer::res1(), gem5::GPUDynInst::resolveFlatSegment(), gem5::reverseBits(), gem5::roundDown(), gem5::roundUp(), gem5::VectorRegisterFile::scheduleWriteOperandsFromLoad(), gem5::SMMUTranslationProcess::sendEvent(), gem5::Iob::serialize(), gem5::Flags< T >::set(), gem5::Flags< T >::set(), gem5::ArmISA::SelfDebug::setDebugMask(), gem5::VegaISA::PackedReg< BITS, ELEM_SIZE >::setElem(), gem5::SparcISA::ISA::setFSReg(), gem5::Pl011::setInterruptMask(), gem5::HDLcd::setInterrupts(), gem5::Pl011::setInterrupts(), gem5::ArmISA::ISA::setMiscReg(), gem5::setRegNoEffectWithMask(), gem5::setRegWithMask(), gem5::BaseKvmCPU::setSignalMask(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ArmISA::ArmStaticInst::spsrWriteByInstr(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::WalkerState::startWalk(), stripPAC(), gem5::szext(), gem5::ArmISA::Interrupts::takeInt32(), gem5::ArmISA::Interrupts::takeInt64(), gem5::ArmISA::Interrupts::takeVirtualInt64(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), gem5::ruby::testAndReadMask(), gem5::AddrRange::to_string(), gem5::branch_prediction::TournamentBP::TournamentBP(), gem5::SparcISA::PageTableEntry::translate(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateMmuOn(), gem5::ArmISA::MMU::translateSe(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::Iob::unserialize(), gem5::ArmISA::TlbEntry::updateAttributes(), gem5::prefetch::SignaturePath::updateSignature(), vcvtFpFpH(), vcvtFpHFp(), vfpFpToFixed(), gem5::VegaISA::GpuTLB::walkerResponse(), gem5::VegaISA::Walker::WalkerState::walkStateMachine(), gem5::VectorRegisterFile::waveExecuteInst(), gem5::VegaISA::wholeQuadMode(), gem5::IGbE::write(), gem5::GicV2::writeDistributor(), and gem5::MipsISA::writeDSPControl().

matRegClass

RegClass gem5::ArmISA::matRegClass

inlineconstexpr

Initial value:

=
    RegClass(MatRegClass, MatRegClassName, NumMatrixRegs, debug::MatRegs).
        ops(matRegClassOps).
        regType<MatRegContainer>()

Definition at line 92 of file mat.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), and gem5::X86ISA::ISA::ISA().

matRegClassOps

TypedRegClassOps<ArmISA::MatRegContainer> gem5::ArmISA::matRegClassOps

inlinestatic

Definition at line 90 of file mat.hh.

MaxPhysAddrRange

const unsigned gem5::ArmISA::MaxPhysAddrRange = 52

Definition at line 73 of file pagetable.hh.

Referenced by gem5::ArmSystem::ArmSystem().

MaxSmeVecLenInBits

unsigned gem5::ArmISA::MaxSmeVecLenInBits = 2048

constexpr

Definition at line 502 of file types.hh.

MaxSmeVecLenInBytes

unsigned gem5::ArmISA::MaxSmeVecLenInBytes = MaxSmeVecLenInBits >> 3

constexpr

Definition at line 510 of file types.hh.

MaxSmeVecLenInDWords

unsigned gem5::ArmISA::MaxSmeVecLenInDWords = MaxSmeVecLenInBits >> 6

constexpr

Definition at line 512 of file types.hh.

MaxSmeVecLenInWords

unsigned gem5::ArmISA::MaxSmeVecLenInWords = MaxSmeVecLenInBits >> 5

constexpr

Definition at line 511 of file types.hh.

MaxSveVecLenInBits

unsigned gem5::ArmISA::MaxSveVecLenInBits = 2048

constexpr

Definition at line 490 of file types.hh.

MaxSveVecLenInBytes

unsigned gem5::ArmISA::MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3

constexpr

Definition at line 495 of file types.hh.

MaxSveVecLenInDWords

unsigned gem5::ArmISA::MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6

constexpr

Definition at line 497 of file types.hh.

MaxSveVecLenInWords

unsigned gem5::ArmISA::MaxSveVecLenInWords = MaxSveVecLenInBits >> 5

constexpr

Definition at line 496 of file types.hh.

md

Bitfield<12> gem5::ArmISA::md

Definition at line 936 of file misc_types.hh.

Referenced by gem5::ArmISA::SelfDebug::testDebug().

mdbgen

Bitfield<15> gem5::ArmISA::mdbgen

Definition at line 913 of file misc_types.hh.

mdscrEL1

Bitfield<4> gem5::ArmISA::mdscrEL1

Definition at line 1081 of file misc_types.hh.

mec

Bitfield<31, 28> gem5::ArmISA::mec

Definition at line 201 of file misc_types.hh.

mediaOpcode

Bitfield<24, 20> gem5::ArmISA::mediaOpcode

Definition at line 93 of file types.hh.

mf

Bitfield<15> gem5::ArmISA::mf

Definition at line 933 of file misc_types.hh.

mi

Bitfield<14> gem5::ArmISA::mi

Definition at line 934 of file misc_types.hh.

Referenced by gem5::trace::InstPBTrace::getInstRecord().

midrEL1

Bitfield<25> gem5::ArmISA::midrEL1

Definition at line 1044 of file misc_types.hh.

miocnce

Bitfield<38> gem5::ArmISA::miocnce

Definition at line 326 of file misc_types.hh.

miscOpcode

Bitfield<7, 4> gem5::ArmISA::miscOpcode

Definition at line 105 of file types.hh.

miscRegClass

RegClass gem5::ArmISA::miscRegClass

inlineconstexpr

Initial value:

=
        RegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS,
                debug::MiscRegs).
            ops(miscRegClassOps)

Definition at line 2937 of file misc.hh.

Referenced by gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::MipsISA::forkThread(), gem5::Iris::ThreadContext::getMiscRegRscId(), gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::X86ISA::ISA::ISA(), gem5::trace::TarmacTracerRecord::mergeCCEntry(), gem5::X86ISA::MiscOp< Base >::print(), and gem5::MipsISA::yieldThread().

miscRegClassOps

MiscRegClassOps gem5::ArmISA::miscRegClassOps

inlinestatic

Definition at line 2935 of file misc.hh.

miscRegName

const char* const gem5::ArmISA::miscRegName[]

Definition at line 1815 of file misc.hh.

Referenced by gem5::Gicv3Registers::copyCpuRegister(), gem5::ArmV8KvmCPU::dump(), gem5::ArmKvmCPU::dumpKvmStateCoProc(), gem5::ArmKvmCPU::dumpKvmStateCore(), gem5::ArmKvmCPU::dumpKvmStateVFP(), gem5::getMiscRegName(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::ArmISA::ArmStaticInst::printMiscReg(), gem5::ArmISA::DummyISADevice::readMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::PMU::readMiscReg(), gem5::GenericTimer::readMiscReg(), gem5::GenericTimerISA::readMiscReg(), gem5::Gicv3CPUInterface::readMiscReg(), gem5::ArmISA::PMU::readMiscRegInt(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::ArmISA::MiscRegClassOps::regName(), gem5::ArmISA::ISA::serialize(), gem5::ArmISA::DummyISADevice::setMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::PMU::setMiscReg(), gem5::GenericTimer::setMiscReg(), gem5::GenericTimerISA::setMiscReg(), gem5::Gicv3CPUInterface::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::ArmISA::ISA::unserialize(), gem5::ArmKvmCPU::updateKvmStateCoProc(), gem5::ArmKvmCPU::updateKvmStateVFP(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateMisc(), gem5::ArmKvmCPU::updateTCStateCoProc(), and gem5::ArmKvmCPU::updateTCStateVFP().

mode

Bitfield<4, 0> gem5::ArmISA::mode

Definition at line 74 of file misc_types.hh.

Referenced by gem5::accessFunc(), gem5::accessImpl(), gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), badMode(), badMode32(), gem5::BaseSemihosting::callOpen(), gem5::ArmISA::MMU::checkPAN(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions(), gem5::RiscvISA::TLB::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::TLB::checkPromotion(), gem5::chmodFunc(), gem5::AMDGPU::convertMXFP(), gem5::Intel8254Timer::Counter::Counter(), gem5::BaseSemihosting::FileBase::create(), gem5::OutputDirectory::create(), gem5::RiscvISA::TLB::createPagefault(), gem5::VegaISA::GpuTLB::createPagefault(), gem5::trace::ArmCapstoneDisassembler::currHandle(), decodeMrsMsrBankedReg(), gem5::RiscvISA::TLB::doTranslate(), gem5::MipsISA::dspDpa(), gem5::MipsISA::dspDpaq(), gem5::MipsISA::dspDps(), gem5::MipsISA::dspDpsq(), gem5::MipsISA::dspMaq(), gem5::MipsISA::dspMuleq(), gem5::MipsISA::dspMuleu(), gem5::MipsISA::dspPrece(), EndBitUnion(), gem5::faccessatFunc(), gem5::fallocateFunc(), gem5::ArmISA::MMU::faultPAN(), gem5::fchmodatFunc(), gem5::fchmodFunc(), gem5::ArmISA::MMU::finalizePhysical(), gem5::BaseMMU::finalizePhysical(), gem5::DataTranslation< ExecContextPtr >::finish(), gem5::o3::Fetch::FetchTranslation::finish(), gem5::SETranslatingPortProxy::fixupRange(), flattenIntRegModeIndex(), fp16_add(), fp16_compare_eq(), fp16_compare_ge(), fp16_compare_gt(), fp16_compare_un(), fp16_cvtf(), fp16_div(), fp16_mul(), fp16_muladd(), fp16_process_NaN(), fp16_process_NaNs(), fp16_process_NaNs3(), fp16_round(), fp16_round_(), fp16_scale(), fp16_sqrt(), fp16_unpack(), fp32_add(), fp32_compare_eq(), fp32_compare_ge(), fp32_compare_gt(), fp32_compare_un(), fp32_cvtf(), fp32_div(), fp32_mul(), fp32_muladd(), fp32_process_NaN(), fp32_process_NaNs(), fp32_process_NaNs3(), fp32_round(), fp32_round_(), fp32_scale(), fp32_sqrt(), fp32_unpack(), fp64_add(), fp64_compare_eq(), fp64_compare_ge(), fp64_compare_gt(), fp64_compare_un(), fp64_cvtf(), fp64_div(), fp64_mul(), fp64_muladd(), fp64_process_NaN(), fp64_process_NaNs(), fp64_process_NaNs3(), fp64_round(), fp64_round_(), fp64_scale(), fp64_sqrt(), fp64_unpack(), fplibCompare(), fplibCompare(), fplibCompare(), fplibConvert(), fplibConvert(), fplibConvert(), fplibMax(), fplibMax(), fplibMax(), fplibMin(), fplibMin(), fplibMin(), fplibMulX(), fplibMulX(), fplibMulX(), fplibRecipEstimate(), fplibRecipEstimate(), fplibRecipEstimate(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRecipStepFused(), fplibRecpX(), fplibRecpX(), fplibRecpX(), fplibRoundInt(), fplibRoundInt(), fplibRoundInt(), fplibRSqrtEstimate(), fplibRSqrtEstimate(), fplibRSqrtEstimate(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), fplibRSqrtStepFused(), fplibTrigSMul(), fplibTrigSMul(), fplibTrigSMul(), gem5::ArmISA::FpRegImmOp::FpRegImmOp(), gem5::ArmISA::FpRegRegImmOp::FpRegRegImmOp(), gem5::ArmISA::FpRegRegOp::FpRegRegOp(), gem5::ArmISA::FpRegRegRegCondOp::FpRegRegRegCondOp(), gem5::ArmISA::FpRegRegRegImmOp::FpRegRegRegImmOp(), gem5::ArmISA::FpRegRegRegOp::FpRegRegRegOp(), gem5::ArmISA::FpRegRegRegRegOp::FpRegRegRegRegOp(), gem5::Shader::functionalTLBAccess(), gem5::RiscvISA::TLB::getMemPriv(), gem5::ArmISA::MMU::getResultTe(), gem5::BaseSemihosting::getSTDIO(), gem5::ArmISA::MMU::getTableWalker(), gem5::ArmISA::MMU::getTE(), gem5::ArmISA::MMU::getTE(), gem5::ArmISA::MMU::getTlb(), gem5::BaseMMU::getTlb(), gem5::VegaISA::GpuTLB::handleFuncTranslationReturn(), gem5::VegaISA::GpuTLB::handleTranslationReturn(), gem5::ruby::HTMSequencer::htmCallback(), illegalExceptionReturn(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::VegaISA::Walker::WalkerState::initState(), gem5::ArmISA::ArmFault::invoke64(), gem5::ArmISA::MMU::lookup(), gem5::ArmISA::TLB::lookup(), gem5::RiscvISA::TLB::lookup(), gem5::mkdiratFunc(), gem5::mkdirFunc(), gem5::mkdirImpl(), gem5::mknodatFunc(), gem5::mknodFunc(), gem5::mknodImpl(), gem5::OutputDirectory::open(), gem5::RawDiskImage::open(), gem5::openatFunc(), gem5::FDArray::openFile(), gem5::openFunc(), gem5::BaseSemihosting::File::openImpl(), opModeIsH(), opModeIsT(), opModeToEL(), gem5::VegaISA::Walker::WalkerState::pageFault(), gem5::VegaISA::GpuTLB::pagingProtectionChecks(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::TrafficGen::parseConfig(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), gem5::ArmISA::int_reg::regInMode(), gem5::ArmISA::MMU::s1PermBits64(), gem5::BaseSemihosting::FileBase::serialize(), gem5::FileFDEntry::setFileMode(), gem5::System::setMemoryMode(), setVfpMicroFlags(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::startTiming(), gem5::ArmISA::MMU::testAndFinalize(), gem5::ArmISA::SelfDebug::testDebug(), gem5::ArmISA::MMU::testTranslation(), gem5::BaseMMU::MMUTranslationGen::translate(), gem5::RiscvISA::TLB::translate(), gem5::ArmISA::MMU::translateAtomic(), gem5::ArmISA::MMU::translateAtomic(), gem5::ArmISA::MMU::translateAtomic(), gem5::BaseMMU::translateAtomic(), gem5::Iris::TLB::translateAtomic(), gem5::SparcISA::TLB::translateAtomic(), gem5::ArmISA::MMU::translateComplete(), gem5::ArmISA::MMU::translateComplete(), gem5::ArmISA::MMU::translateFs(), gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateFunctional(), gem5::BaseMMU::translateFunctional(), gem5::Iris::MMU::translateFunctional(), gem5::PowerISA::MMU::translateFunctional(), gem5::SparcISA::MMU::translateFunctional(), gem5::SparcISA::TLB::translateFunctional(), gem5::ArmISA::MMU::translateMmuOff(), gem5::ArmISA::MMU::translateMmuOn(), gem5::ArmISA::MMU::translateSe(), gem5::ArmISA::MMU::translateTiming(), gem5::ArmISA::MMU::translateTiming(), gem5::ArmISA::TableWalker::Stage2Walk::translateTiming(), gem5::BaseMMU::translateTiming(), gem5::Iris::TLB::translateTiming(), gem5::SparcISA::TLB::translateTiming(), gem5::RiscvISA::TLB::translateWithTLB(), gem5::TranslatingPortProxy::tryMemsetBlob(), gem5::TranslatingPortProxy::tryOnBlob(), gem5::TranslatingPortProxy::tryReadBlob(), gem5::TranslatingPortProxy::tryWriteBlob(), unknownMode(), unknownMode32(), gem5::FDArray::unserialize(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt(), gem5::WriteAllocator::updateMode(), vcvtFpFpH(), gem5::VegaISA::Walker::WalkerState::walkStateMachine(), and gem5::TimingSimpleCPU::writeMem().

moe

Bitfield<5, 2> gem5::ArmISA::moe

Definition at line 920 of file misc_types.hh.

mp

Bitfield<11> gem5::ArmISA::mp

Definition at line 937 of file misc_types.hh.

Referenced by gem5::GlobalMemPipeline::acqCoalescerToken(), gem5::GlobalMemPipeline::coalescerReady(), gem5::GlobalMemPipeline::exec(), gem5::ScalarMemPipeline::exec(), gem5::ScheduleStage::fillDispatchList(), and gem5::GlobalMemPipeline::outstandingReqsCheck().

mpam

Bitfield<43, 40> gem5::ArmISA::mpam

Definition at line 216 of file misc_types.hh.

mpamFrac

Bitfield<19, 16> gem5::ArmISA::mpamFrac

Definition at line 231 of file misc_types.hh.

mpidrEL1

Bitfield<26> gem5::ArmISA::mpidrEL1

Definition at line 1043 of file misc_types.hh.

ms

Bitfield<10> gem5::ArmISA::ms

Definition at line 938 of file misc_types.hh.

n

gem5::ArmISA::n

Definition at line 540 of file misc_types.hh.

Referenced by gem5::ThermalModel::addNode(), gem5::memory::DRAMInterface::addRankToRankDelay(), gem5::memory::NVMInterface::addRankToRankDelay(), gem5::ruby::MessageBuffer::areNSlotsAvailable(), gem5::ruby::MN_TBEStorage< RetryEntry >::areNSlotsAvailable(), gem5::ruby::TBEStorage::areNSlotsAvailable(), gem5::ruby::TBETable< ENTRY >::areNSlotsAvailable(), gem5::atomic_read(), gem5::atomic_write(), gem5::ceilLog2(), gem5::DVFSHandler::clkPeriodAtPerfLevel(), gem5::memory::NVMInterface::doBurstAccess(), gem5::ThermalModel::doStep(), gem5::MathExpr::eval(), gem5::CxxConfigManager::findObject(), gem5::RiscvISA::fsgnj(), gem5::RiscvISA::fsgnj16(), gem5::RiscvISA::fsgnj32(), gem5::RiscvISA::fsgnj64(), gem5::ThermalCapacitor::getEquation(), gem5::ThermalDomain::getEquation(), gem5::ThermalResistor::getEquation(), gem5::ThermalModel::getTemperature(), gem5::MathExpr::getVariables(), gem5::ArmISA::V7LPageTableOps::index(), gem5::ruby::NetDest::isEqual(), gem5::isPowerOf2(), SwitchingFiber::main(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::MathExpr::parse(), gem5::ArmISA::TableWalker::pendingChange(), gem5::linux::printk(), gem5::StackDistCalc::printStack(), gem5::prlimitFunc(), gem5::ArmISA::TableWalker::processWalkLPAE(), gem5::X86ISA::smbios::SMBiosStructure::readString(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::RiscvRTC::RTC::RTC(), gem5::statistics::DistBase< Derived, Stor >::sample(), gem5::statistics::DistProxy< Stat >::sample(), gem5::statistics::SparseHistBase< Derived, Stor >::sample(), gem5::ArmISA::HTMCheckpoint::save(), gem5::fastmodel::CortexA76::set_evs_param(), gem5::fastmodel::CortexA76Cluster::set_evs_param(), gem5::fastmodel::CortexR52::set_evs_param(), gem5::fastmodel::CortexR52Cluster::set_evs_param(), gem5::ThermalDomain::setNode(), gem5::ThermalReference::setNode(), gem5::X86ISA::smbios::SMBiosStructure::setString(), gem5::ThermalModel::startup(), testPredicate(), gem5::MathExpr::toStr(), gem5::branch_prediction::ReturnAddrStack::AddrStack::toString(), gem5::DVFSHandler::voltageAtPerfLevel(), and gem5::X86ISA::Cmos::X86RTC::X86RTC().

nEt

Bitfield<6> gem5::ArmISA::nEt

Definition at line 411 of file misc_types.hh.

nmea

Bitfield<20> gem5::ArmISA::nmea

Definition at line 396 of file misc_types.hh.

nmfi

Bitfield<27> gem5::ArmISA::nmfi

Definition at line 426 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr().

nos0

Bitfield<24> gem5::ArmISA::nos0

Definition at line 672 of file misc_types.hh.

nos1

Bitfield<25> gem5::ArmISA::nos1

Definition at line 673 of file misc_types.hh.

nos2

Bitfield<26> gem5::ArmISA::nos2

Definition at line 674 of file misc_types.hh.

nos3

Bitfield<27> gem5::ArmISA::nos3

Definition at line 675 of file misc_types.hh.

nos4

Bitfield<28> gem5::ArmISA::nos4

Definition at line 676 of file misc_types.hh.

nos5

Bitfield<29> gem5::ArmISA::nos5

Definition at line 677 of file misc_types.hh.

nos6

Bitfield<30> gem5::ArmISA::nos6

Definition at line 678 of file misc_types.hh.

nos7

Bitfield<31> gem5::ArmISA::nos7

Definition at line 679 of file misc_types.hh.

ns

Bitfield< 18 > gem5::ArmISA::ns

Definition at line 417 of file misc_types.hh.

Referenced by EL2Enabled(), gem5::Gicv3CPUInterface::generateSGI(), gem5::ArmISA::TLB::insert(), isSecureBelowEL3(), gem5::pseudo_inst::quiesceNs(), gem5::Gicv3Redistributor::sendSGI(), gem5::ArmISA::mpam::PartitionFieldExtension::setMpamNS(), snsBankedIndex(), gem5::ArmISA::ISA::snsBankedIndex64(), and gem5::BaseKvmTimer::ticksFromHostNs().

ns0

Bitfield<18> gem5::ArmISA::ns0

Definition at line 670 of file misc_types.hh.

ns1

Bitfield<19> gem5::ArmISA::ns1

Definition at line 671 of file misc_types.hh.

nsasedis

Bitfield<15> gem5::ArmISA::nsasedis

Definition at line 371 of file misc_types.hh.

nsd

Bitfield<28> gem5::ArmISA::nsd

Definition at line 928 of file misc_types.hh.

nsd32dis

Bitfield<14> gem5::ArmISA::nsd32dis

Definition at line 372 of file misc_types.hh.

nsi

Bitfield<30> gem5::ArmISA::nsi

Definition at line 926 of file misc_types.hh.

nsp

Bitfield<27> gem5::ArmISA::nsp

Definition at line 929 of file misc_types.hh.

nss

Bitfield<26> gem5::ArmISA::nss

Definition at line 930 of file misc_types.hh.

nsu

Bitfield<25> gem5::ArmISA::nsu

Definition at line 931 of file misc_types.hh.

nTT

Bitfield<2> gem5::ArmISA::nTT

Definition at line 866 of file misc_types.hh.

ntwe

Bitfield<18> gem5::ArmISA::ntwe

Definition at line 446 of file misc_types.hh.

ntwi

Bitfield<16> gem5::ArmISA::ntwi

Definition at line 449 of file misc_types.hh.

NumArgumentRegs

size_t gem5::ArmISA::NumArgumentRegs = 4

inlineconstexpr

Definition at line 645 of file int.hh.

NumArgumentRegs64

size_t gem5::ArmISA::NumArgumentRegs64 = 8

inlineconstexpr

Definition at line 646 of file int.hh.

numCPUs

Bitfield<25,24> gem5::ArmISA::numCPUs

Definition at line 718 of file misc_types.hh.

NumFloatV7ArchRegs

const int gem5::ArmISA::NumFloatV7ArchRegs = 64

Definition at line 78 of file vec.hh.

NumMatrixRegs

const int gem5::ArmISA::NumMatrixRegs = 1

Definition at line 88 of file mat.hh.

NumVecElemPerNeonVecReg

unsigned gem5::ArmISA::NumVecElemPerNeonVecReg = 4

constexpr

Definition at line 59 of file vec.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), and gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs().

NumVecElemPerVecReg

unsigned gem5::ArmISA::NumVecElemPerVecReg = MaxSveVecLenInWords

constexpr

Definition at line 61 of file vec.hh.

Referenced by gem5::VegaISA::Inst_FLAT::atomicComplete(), gem5::VegaISA::Inst_FLAT::atomicExecute(), gem5::VegaISA::Inst_DS::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddr(), gem5::VegaISA::Inst_MUBUF::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddrSgpr(), gem5::VegaISA::Inst_FLAT::calcAddrVgpr(), gem5::VegaISA::Inst_DS__DS_READ2_B32::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ2_B64::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ2ST64_B32::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ2ST64_B64::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_B128::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_B32::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_B64::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_B96::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_I8::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16_D16::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16_D16_HI::completeAcc(), gem5::VegaISA::Inst_DS__DS_READ_U8::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_SBYTE::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::completeAcc(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SHORT_D16::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SHORT_D16_HI::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE::completeAcc(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT::completeAcc(), gem5::VegaISA::Inst_VOP3P::dotHelper(), gem5::VegaISA::dppInstImpl(), gem5::VegaISA::Inst_DS__DS_ADD_F32::execute(), gem5::VegaISA::Inst_DS__DS_ADD_U32::execute(), gem5::VegaISA::Inst_DS__DS_ADD_U64::execute(), gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_OR_B32::execute(), gem5::VegaISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_SWIZZLE_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B128::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B16::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B8::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B8_D16_HI::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B96::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT_D16_HI::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT::execute(), gem5::VegaISA::Inst_VOP1__V_ACCVGPR_MOV_B32::execute(), gem5::VegaISA::Inst_VOP1__V_BFREV_B32::execute(), gem5::VegaISA::Inst_VOP1__V_CEIL_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CEIL_F64::execute(), gem5::VegaISA::Inst_VOP1__V_COS_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F16_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_F16::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_F64::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_I32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_U32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE0::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE1::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE2::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F32_UBYTE3::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F64_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F64_I32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_F64_U32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_FLR_I32_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_I32_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_I32_F64::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_RPI_I32_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_U32_F32::execute(), gem5::VegaISA::Inst_VOP1__V_CVT_U32_F64::execute(), gem5::VegaISA::Inst_VOP1__V_EXP_F32::execute(), gem5::VegaISA::Inst_VOP1__V_EXP_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP1__V_FFBH_I32::execute(), gem5::VegaISA::Inst_VOP1__V_FFBH_U32::execute(), gem5::VegaISA::Inst_VOP1__V_FFBL_B32::execute(), gem5::VegaISA::Inst_VOP1__V_FLOOR_F32::execute(), gem5::VegaISA::Inst_VOP1__V_FLOOR_F64::execute(), gem5::VegaISA::Inst_VOP1__V_FRACT_F32::execute(), gem5::VegaISA::Inst_VOP1__V_FRACT_F64::execute(), gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F32::execute(), gem5::VegaISA::Inst_VOP1__V_FREXP_EXP_I32_F64::execute(), gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F32::execute(), gem5::VegaISA::Inst_VOP1__V_FREXP_MANT_F64::execute(), gem5::VegaISA::Inst_VOP1__V_LOG_F32::execute(), gem5::VegaISA::Inst_VOP1__V_LOG_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP1__V_MOV_B32::execute(), gem5::VegaISA::Inst_VOP1__V_MOV_B64::execute(), gem5::VegaISA::Inst_VOP1__V_NOT_B32::execute(), gem5::VegaISA::Inst_VOP1__V_RCP_F32::execute(), gem5::VegaISA::Inst_VOP1__V_RCP_F64::execute(), gem5::VegaISA::Inst_VOP1__V_RCP_IFLAG_F32::execute(), gem5::VegaISA::Inst_VOP1__V_RNDNE_F32::execute(), gem5::VegaISA::Inst_VOP1__V_RNDNE_F64::execute(), gem5::VegaISA::Inst_VOP1__V_RSQ_F32::execute(), gem5::VegaISA::Inst_VOP1__V_RSQ_F64::execute(), gem5::VegaISA::Inst_VOP1__V_SIN_F32::execute(), gem5::VegaISA::Inst_VOP1__V_SQRT_F32::execute(), gem5::VegaISA::Inst_VOP1__V_SQRT_F64::execute(), gem5::VegaISA::Inst_VOP1__V_TRUNC_F32::execute(), gem5::VegaISA::Inst_VOP1__V_TRUNC_F64::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_F32::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U16::execute(), gem5::VegaISA::Inst_VOP2__V_ADD_U32::execute(), gem5::VegaISA::Inst_VOP2__V_ADDC_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_AND_B32::execute(), gem5::VegaISA::Inst_VOP2__V_ASHRREV_I16::execute(), gem5::VegaISA::Inst_VOP2__V_ASHRREV_I32::execute(), gem5::VegaISA::Inst_VOP2__V_CNDMASK_B32::execute(), gem5::VegaISA::Inst_VOP2__V_FMAC_F32::execute(), gem5::VegaISA::Inst_VOP2__V_LSHLREV_B16::execute(), gem5::VegaISA::Inst_VOP2__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_LSHRREV_B16::execute(), gem5::VegaISA::Inst_VOP2__V_LSHRREV_B32::execute(), gem5::VegaISA::Inst_VOP2__V_MAC_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MADAK_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MADMK_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MAX_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MAX_I16::execute(), gem5::VegaISA::Inst_VOP2__V_MAX_I32::execute(), gem5::VegaISA::Inst_VOP2__V_MAX_U16::execute(), gem5::VegaISA::Inst_VOP2__V_MAX_U32::execute(), gem5::VegaISA::Inst_VOP2__V_MIN_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MIN_I16::execute(), gem5::VegaISA::Inst_VOP2__V_MIN_I32::execute(), gem5::VegaISA::Inst_VOP2__V_MIN_U16::execute(), gem5::VegaISA::Inst_VOP2__V_MIN_U32::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_HI_I32_I24::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_HI_U32_U24::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_I32_I24::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_LO_U16::execute(), gem5::VegaISA::Inst_VOP2__V_MUL_U32_U24::execute(), gem5::VegaISA::Inst_VOP2__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_SUB_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_SUB_F32::execute(), gem5::VegaISA::Inst_VOP2__V_SUB_U16::execute(), gem5::VegaISA::Inst_VOP2__V_SUB_U32::execute(), gem5::VegaISA::Inst_VOP2__V_SUBB_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_SUBBREV_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_SUBREV_CO_U32::execute(), gem5::VegaISA::Inst_VOP2__V_SUBREV_F32::execute(), gem5::VegaISA::Inst_VOP2__V_SUBREV_U16::execute(), gem5::VegaISA::Inst_VOP2__V_SUBREV_U32::execute(), gem5::VegaISA::Inst_VOP2__V_XNOR_B32::execute(), gem5::VegaISA::Inst_VOP2__V_XOR_B32::execute(), gem5::VegaISA::Inst_VOP3__V_ADD3_U32::execute(), gem5::VegaISA::Inst_VOP3__V_ADD_CO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_ADD_F32::execute(), gem5::VegaISA::Inst_VOP3__V_ADD_F64::execute(), gem5::VegaISA::Inst_VOP3__V_ADD_LSHL_U32::execute(), gem5::VegaISA::Inst_VOP3__V_ADD_U16::execute(), gem5::VegaISA::Inst_VOP3__V_ADD_U32::execute(), gem5::VegaISA::Inst_VOP3__V_ADDC_CO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_ALIGNBIT_B32::execute(), gem5::VegaISA::Inst_VOP3__V_ALIGNBYTE_B32::execute(), gem5::VegaISA::Inst_VOP3__V_AND_B32::execute(), gem5::VegaISA::Inst_VOP3__V_AND_OR_B32::execute(), gem5::VegaISA::Inst_VOP3__V_ASHRREV_I16::execute(), gem5::VegaISA::Inst_VOP3__V_ASHRREV_I32::execute(), gem5::VegaISA::Inst_VOP3__V_ASHRREV_I64::execute(), gem5::VegaISA::Inst_VOP3__V_BCNT_U32_B32::execute(), gem5::VegaISA::Inst_VOP3__V_BFE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_BFE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_BFI_B32::execute(), gem5::VegaISA::Inst_VOP3__V_BFM_B32::execute(), gem5::VegaISA::Inst_VOP3__V_BFREV_B32::execute(), gem5::VegaISA::Inst_VOP3__V_CEIL_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CEIL_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_CLASS_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_EQ_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_F_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GE_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_GT_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LE_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LG_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LG_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_LT_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NE_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NE_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NE_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NE_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NEQ_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NGE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NGT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NLE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NLG_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_NLT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_O_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_O_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_T_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_T_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_T_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_T_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_T_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_T_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F16::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_TRU_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_U_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMP_U_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_CLASS_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_EQ_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_F16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_F_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GE_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_GT_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LE_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LG_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_LT_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NE_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NE_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NEQ_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NGE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NGT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NLE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NLG_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_NLT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_O_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_O_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_T_I16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_T_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_T_I64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_T_U16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_T_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_T_U64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F16::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_TRU_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_U_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CMPX_U_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CNDMASK_B32::execute(), gem5::VegaISA::Inst_VOP3__V_COS_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F16_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_F16::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE0::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE1::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE2::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F32_UBYTE3::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F64_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F64_I32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_F64_U32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_FLR_I32_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_I32_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_I32_F64::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_PK_FP8_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_PK_U8_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_RPI_I32_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_U32_F32::execute(), gem5::VegaISA::Inst_VOP3__V_CVT_U32_F64::execute(), gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F32::execute(), gem5::VegaISA::Inst_VOP3__V_DIV_FIXUP_F64::execute(), gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F32::execute(), gem5::VegaISA::Inst_VOP3__V_DIV_FMAS_F64::execute(), gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_DIV_SCALE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_EXP_F32::execute(), gem5::VegaISA::Inst_VOP3__V_EXP_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FFBH_I32::execute(), gem5::VegaISA::Inst_VOP3__V_FFBH_U32::execute(), gem5::VegaISA::Inst_VOP3__V_FFBL_B32::execute(), gem5::VegaISA::Inst_VOP3__V_FLOOR_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FLOOR_F64::execute(), gem5::VegaISA::Inst_VOP3__V_FMA_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FMA_F64::execute(), gem5::VegaISA::Inst_VOP3__V_FMAC_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FRACT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FRACT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FREXP_EXP_I32_F64::execute(), gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_FREXP_MANT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_LDEXP_F32::execute(), gem5::VegaISA::Inst_VOP3__V_LDEXP_F64::execute(), gem5::VegaISA::Inst_VOP3__V_LERP_U8::execute(), gem5::VegaISA::Inst_VOP3__V_LOG_F32::execute(), gem5::VegaISA::Inst_VOP3__V_LOG_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP3__V_LSHL_ADD_U32::execute(), gem5::VegaISA::Inst_VOP3__V_LSHL_ADD_U64::execute(), gem5::VegaISA::Inst_VOP3__V_LSHL_OR_B32::execute(), gem5::VegaISA::Inst_VOP3__V_LSHLREV_B16::execute(), gem5::VegaISA::Inst_VOP3__V_LSHLREV_B32::execute(), gem5::VegaISA::Inst_VOP3__V_LSHLREV_B64::execute(), gem5::VegaISA::Inst_VOP3__V_LSHRREV_B16::execute(), gem5::VegaISA::Inst_VOP3__V_LSHRREV_B32::execute(), gem5::VegaISA::Inst_VOP3__V_LSHRREV_B64::execute(), gem5::VegaISA::Inst_VOP3__V_MAC_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_I16::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_I32_I24::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_I64_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_U16::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_U32_U24::execute(), gem5::VegaISA::Inst_VOP3__V_MAD_U64_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MAX3_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MAX3_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MAX3_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MAX_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MAX_F64::execute(), gem5::VegaISA::Inst_VOP3__V_MAX_I16::execute(), gem5::VegaISA::Inst_VOP3__V_MAX_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MAX_U16::execute(), gem5::VegaISA::Inst_VOP3__V_MAX_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MBCNT_HI_U32_B32::execute(), gem5::VegaISA::Inst_VOP3__V_MBCNT_LO_U32_B32::execute(), gem5::VegaISA::Inst_VOP3__V_MED3_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MED3_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MED3_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MIN3_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MIN3_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MIN3_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MIN_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MIN_F64::execute(), gem5::VegaISA::Inst_VOP3__V_MIN_I16::execute(), gem5::VegaISA::Inst_VOP3__V_MIN_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MIN_U16::execute(), gem5::VegaISA::Inst_VOP3__V_MIN_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MOV_B32::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_F64::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_HI_I32_I24::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_HI_U32_U24::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_I32_I24::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_LEGACY_F32::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_LO_U16::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_LO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_MUL_U32_U24::execute(), gem5::VegaISA::Inst_VOP3__V_NOT_B32::execute(), gem5::VegaISA::Inst_VOP3__V_OR3_B32::execute(), gem5::VegaISA::Inst_VOP3__V_OR_B32::execute(), gem5::VegaISA::Inst_VOP3__V_PERM_B32::execute(), gem5::VegaISA::Inst_VOP3__V_RCP_F32::execute(), gem5::VegaISA::Inst_VOP3__V_RCP_F64::execute(), gem5::VegaISA::Inst_VOP3__V_RCP_IFLAG_F32::execute(), gem5::VegaISA::Inst_VOP3__V_RNDNE_F32::execute(), gem5::VegaISA::Inst_VOP3__V_RNDNE_F64::execute(), gem5::VegaISA::Inst_VOP3__V_RSQ_F32::execute(), gem5::VegaISA::Inst_VOP3__V_RSQ_F64::execute(), gem5::VegaISA::Inst_VOP3__V_SAD_HI_U8::execute(), gem5::VegaISA::Inst_VOP3__V_SAD_U16::execute(), gem5::VegaISA::Inst_VOP3__V_SAD_U32::execute(), gem5::VegaISA::Inst_VOP3__V_SAD_U8::execute(), gem5::VegaISA::Inst_VOP3__V_SIN_F32::execute(), gem5::VegaISA::Inst_VOP3__V_SQRT_F32::execute(), gem5::VegaISA::Inst_VOP3__V_SQRT_F64::execute(), gem5::VegaISA::Inst_VOP3__V_SUB_CO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_SUB_F32::execute(), gem5::VegaISA::Inst_VOP3__V_SUB_U16::execute(), gem5::VegaISA::Inst_VOP3__V_SUB_U32::execute(), gem5::VegaISA::Inst_VOP3__V_SUBB_CO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_SUBBREV_CO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_SUBREV_CO_U32::execute(), gem5::VegaISA::Inst_VOP3__V_SUBREV_F32::execute(), gem5::VegaISA::Inst_VOP3__V_SUBREV_U16::execute(), gem5::VegaISA::Inst_VOP3__V_SUBREV_U32::execute(), gem5::VegaISA::Inst_VOP3__V_TRUNC_F32::execute(), gem5::VegaISA::Inst_VOP3__V_TRUNC_F64::execute(), gem5::VegaISA::Inst_VOP3__V_XAD_U32::execute(), gem5::VegaISA::Inst_VOP3__V_XOR_B32::execute(), gem5::VegaISA::Inst_VOP3P__V_ACCVGPR_READ::execute(), gem5::VegaISA::Inst_VOP3P__V_ACCVGPR_WRITE::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_ADD_F32::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_FMA_F32::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_MOV_B32::execute(), gem5::VegaISA::Inst_VOP3P__V_PK_MUL_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_CLASS_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_EQ_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_F_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GE_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_GT_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LE_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LG_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LG_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_LT_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NE_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NE_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NE_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NE_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NE_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NE_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NEQ_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NGE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NGT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NLE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NLG_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_NLT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_O_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_O_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_T_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_T_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_T_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_T_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_T_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_T_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_TRU_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_U_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMP_U_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_CLASS_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_EQ_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_F_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GE_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_GT_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LE_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LG_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_LT_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NE_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NE_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NEQ_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NGE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NGT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NLE_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NLG_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_NLT_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_O_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_O_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_T_I16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_T_I32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_T_I64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_T_U16::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_T_U32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_T_U64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_TRU_F64::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_U_F32::execute(), gem5::VegaISA::Inst_VOPC__V_CMPX_U_F64::execute(), gem5::VegaISA::Inst_DS::initAtomicAccess(), gem5::VegaISA::Inst_FLAT::initAtomicAccess(), gem5::VegaISA::Inst_DS::initDualMemRead(), gem5::VegaISA::Inst_DS::initDualMemWrite(), gem5::VegaISA::Inst_DS::initMemRead(), gem5::VegaISA::Inst_FLAT::initMemRead(), gem5::VegaISA::Inst_DS::initMemWrite(), gem5::VegaISA::Inst_FLAT::initMemWrite(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::operator[](), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::operator[](), gem5::VegaISA::processDPP(), gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::read(), gem5::VegaISA::Inst_VOP2::sdwaDstHelper(), gem5::VegaISA::sdwaInstDstImpl(), gem5::VegaISA::sdwaInstSrcImpl(), syncVecElemsToRegs(), syncVecRegsToElems(), gem5::VegaISA::Inst_VOP2::vop2Helper(), gem5::VegaISA::Inst_VOP3P::vop3pHelper(), gem5::VegaISA::Inst_VOP3P::vop3pHelper(), and gem5::VegaISA::VecOperand< DataType, Const, NumDwords >::write().

NumVecIntrlvRegs

const int gem5::ArmISA::NumVecIntrlvRegs = 4

Definition at line 82 of file vec.hh.

NumVecPredRegs

const int gem5::ArmISA::NumVecPredRegs = 18

Definition at line 84 of file vec.hh.

Referenced by gem5::ArmISA::HTMCheckpoint::reset(), gem5::ArmISA::HTMCheckpoint::restore(), and gem5::ArmISA::HTMCheckpoint::save().

NumVecRegs

const int gem5::ArmISA::NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs

Definition at line 83 of file vec.hh.

Referenced by gem5::ArmISA::HTMCheckpoint::reset(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), syncVecElemsToRegs(), and syncVecRegsToElems().

NumVecSpecialRegs

const int gem5::ArmISA::NumVecSpecialRegs = 8

Definition at line 81 of file vec.hh.

NumVecV7ArchRegs

const int gem5::ArmISA::NumVecV7ArchRegs = 16

Definition at line 79 of file vec.hh.

Referenced by gem5::trace::ArmNativeTrace::ThreadState::update().

NumVecV8ArchRegs

const int gem5::ArmISA::NumVecV8ArchRegs = 32

Definition at line 80 of file vec.hh.

Referenced by gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp64::VstMultOp64(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

nv

Bitfield< 42 > gem5::ArmISA::nv

Definition at line 187 of file misc_types.hh.

nv1

Bitfield<43> gem5::ArmISA::nv1

Definition at line 322 of file misc_types.hh.

nv2

Bitfield<45> gem5::ArmISA::nv2

Definition at line 320 of file misc_types.hh.

nz

gem5::ArmISA::nz

Definition at line 52 of file misc_types.hh.

Referenced by fplibFPToFixedJS(), and testPredicate().

ofc

Bitfield<2> gem5::ArmISA::ofc

Definition at line 519 of file misc_types.hh.

ofe

Bitfield<10> gem5::ArmISA::ofe

Definition at line 525 of file misc_types.hh.

offset

Bitfield<23, 0> gem5::ArmISA::offset

Definition at line 144 of file types.hh.

Referenced by gem5::_llseekFunc(), gem5::IdeController::Channel::accessBMI(), gem5::IdeController::Channel::accessCommand(), gem5::IdeController::Channel::accessControl(), gem5::IniFile::add(), gem5::IniFile::Section::add(), gem5::loader::DtbFile::addBootData(), gem5::prefetch::STeMS::ActiveGenerationTableEntry::addOffset(), gem5::RegisterBank< BankByteOrder >::addRegisters(), gem5::RegisterBank< BankByteOrder >::addRegistersAt(), gem5::ruby::addressOffset(), gem5::ArmISA::VfpMacroOp::addStride(), gem5::TraceCPU::ElasticDataGen::adjustInitTraceOffset(), gem5::ruby::DMASequencer::atomicCallback(), gem5::AddressManager::AtomicStruct::AtomicStruct(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::o3::LSQ::SplitDataRequest::buildPackets(), gem5::VegaISA::Inst_FLAT::calcAddr(), gem5::VegaISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddrSgpr(), gem5::VegaISA::Inst_FLAT::calcAddrVgpr(), gem5::BaseXBar::calcPacketTiming(), gem5::VirtDescriptor::chainRead(), gem5::VirtDescriptor::chainWrite(), gem5::BaseCache::cmpAndSwap(), gem5::PacketFifo::copyout(), gem5::ruby::DataBlock::copyPartial(), gem5::ruby::WriteMask::count(), gem5::GenericTimerMem::counterCtrlRead(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::BaseTrafficGen::createStrided(), gem5::linux::ThreadInfo::curTaskInfo(), gem5::linux::ThreadInfo::curTaskMmFromTaskStruct(), gem5::linux::ThreadInfo::curTaskNameFromTaskStruct(), gem5::linux::ThreadInfo::curTaskPIDFromTaskStruct(), gem5::linux::ThreadInfo::curTaskStartFromTaskStruct(), gem5::linux::ThreadInfo::curTaskTGIDFromTaskStruct(), gem5::ruby::DMASequencer::dataCallback(), gem5::AMDGPUDevice::deallocateAllQueues(), gem5::GenericPciHost::decodeAddress(), gem5::pseudo_inst::decodeAddrOffset(), gem5::IdeController::dispatchAccess(), gem5::BaseRemoteGDB::encodeXferResponse(), gem5::VegaISA::Inst_MUBUF__BUFFER_ATOMIC_CMPSWAP::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORD::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX3::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SHORT_D16::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_SHORT_D16_HI::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_UBYTE::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_LOAD_USHORT::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_BYTE::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORD::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX3::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_MUBUF__BUFFER_STORE_SHORT::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX16::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_BUFFER_LOAD_DWORDX8::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_SOPK__S_GETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_B32::execute(), gem5::VegaISA::Inst_SOPK__S_SETREG_IMM32_B32::execute(), gem5::fallocateFunc(), gem5::NonCachingSimpleCPU::fetchInstMem(), gem5::VMA::fillMemPages(), gem5::SectorTags::findBlock(), gem5::loader::DtbFile::findReleaseAddr(), gem5::CompressedTags::findVictim(), gem5::ruby::WriteMask::firstBitSet(), gem5::VegaISA::Inst_DS::generateDisassembly(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::ruby::SubBlock::getByte(), gem5::ruby::DataBlock::getData(), gem5::ruby::DataBlock::getDataMod(), gem5::KvmKernelGicV2::getGicReg(), gem5::KvmKernelGicV3::getGicReg(), gem5::BaseKvmCPU::getGuestData(), gem5::ruby::UncoalescedTable::getInstPackets(), gem5::ruby::WriteMask::getMask(), gem5::AMDGPUVM::getMMIOAperture(), gem5::PM4PacketProcessor::getQueue(), gem5::AMDGPUDevice::getSDMAEngine(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::o3::LSQ::SplitDataRequest::handleLocalAccess(), gem5::ruby::GPUCoalescer::hitCallback(), gem5::VegaISA::Inst_DS::initAtomicAccess(), gem5::VegaISA::Inst_DS__DS_ADD_F32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_ADD_U32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_ADD_U64::initiateAcc(), gem5::VegaISA::Inst_DS__DS_OR_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B128::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B64::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_B96::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_I8::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16_D16::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_U16_D16_HI::initiateAcc(), gem5::VegaISA::Inst_DS__DS_READ_U8::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B128::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B16::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B32::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B64::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B8::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B8_D16_HI::initiateAcc(), gem5::VegaISA::Inst_DS__DS_WRITE_B96::initiateAcc(), gem5::VegaISA::Inst_DS::initMemRead(), gem5::VegaISA::Inst_DS::initMemWrite(), gem5::Shader::initShHiddenPrivateBase(), gem5::ArmISA::FsFreebsd::initState(), gem5::ArmISA::FsLinux::initState(), gem5::SparcISA::ISA::installGlobals(), gem5::SparcISA::ISA::installWindow(), gem5::ruby::SubBlock::internalMergeFrom(), gem5::ruby::SubBlock::internalMergeTo(), gem5::ruby::Sequencer::issueRequest(), gem5::EmulationPageTable::isUnmapped(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ruby::DMASequencer::makeRequest(), gem5::UFSHostDevice::manageReadTransfer(), gem5::UFSHostDevice::manageWriteTransfer(), gem5::MultiLevelPageTable< EntryTypes >::map(), gem5::PM4PacketProcessor::mapKiq(), gem5::VMA::MappedFileBuffer::MappedFileBuffer(), gem5::PM4PacketProcessor::mapPq(), gem5::MemState::mapRegion(), gem5::GPUComputeDriver::mmap(), gem5::mmap2Func(), gem5::mmapFunc(), gem5::PM4PacketProcessor::newQueue(), gem5::CowDiskImage::open(), gem5::TimeBuffer< T >::wire::operator+=(), gem5::TimeBuffer< T >::wire::operator-=(), gem5::statistics::Vector2dBase< Derived, Stor >::operator[](), gem5::TrafficGen::parseConfig(), gem5::CircleBuf< T >::peek(), gem5::ruby::WriteMask::performAtomic(), gem5::WalkCache::pickSetIdx(), gem5::pread64Func(), gem5::prefetch::Base::PrefetchInfo::PrefetchInfo(), gem5::memory::SharedMemoryServer::ClientSocketEvent::process(), gem5::PM4PacketProcessor::processMQD(), gem5::AMDGPUDevice::processPendingDoorbells(), gem5::pwrite64Func(), gem5::BaseRemoteGDB::queryXfer(), gem5::AMDGPUDevice::read(), gem5::CowDiskImage::read(), gem5::GenericTimerFrame::read(), gem5::Gicv2m::read(), gem5::MmioVirtIO::read(), gem5::MmioVirtIO::read(), gem5::PciVirtIO::read(), gem5::qemu::FwCfgItemFixed::read(), gem5::RawDiskImage::read(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::read(), gem5::RegisterBank< BankByteOrder >::RegisterBuf::read(), gem5::RegisterBank< BankByteOrder >::RegisterRoFill::read(), gem5::RiscvISA::MmioVirtIO::read(), gem5::RiscvISA::MmioVirtIO::read(), gem5::Uart8250::Registers::BankedRegister::read(), gem5::Uart8250::Registers::RWSwitchedRegister::read(), gem5::VirtDescriptor::read(), gem5::VirtIOBlock::read(), gem5::IdeDisk::readCommand(), gem5::AMDGPUDevice::readConfig(), gem5::IdeController::readConfig(), gem5::PciDevice::readConfig(), gem5::IdeDisk::readControl(), gem5::SMMUv3::readControl(), gem5::AMDGPUDevice::readDoorbell(), gem5::pseudo_inst::readfile(), gem5::UFSHostDevice::UFSSCSIDevice::readFlash(), gem5::AMDGPUDevice::readFrame(), gem5::AMDGPUNbio::readFrame(), gem5::AMDMMIOReader::readFromTrace(), gem5::scmi::AgentChannel::readLength(), gem5::scmi::AgentChannel::readMessage(), gem5::AMDGPUDevice::readMMIO(), gem5::AMDGPUGfx::readMMIO(), gem5::AMDGPUNbio::readMMIO(), gem5::AMDGPUVM::readMMIO(), gem5::scmi::AgentChannel::readStatus(), gem5::Iris::ThreadContext::readVecPredReg(), gem5::AMDMMIOReader::recordMtrace(), gem5::memory::HBMCtrl::recvTimingReq(), gem5::memory::HeteroMemCtrl::recvTimingReq(), gem5::memory::MemCtrl::recvTimingReq(), gem5::HWScheduler::registerNewQueue(), gem5::MultiLevelPageTable< EntryTypes >::remap(), gem5::RangeAddrMapper::remapAddr(), gem5::GPUDynInst::resolveFlatSegment(), gem5::BaseCache::satisfyRequest(), gem5::loader::MemoryImage::Segment::Segment(), gem5::DmaPort::sendAtomicBdReq(), gem5::PM4PacketProcessor::serialize(), gem5::networking::TcpPtr::set(), gem5::networking::UdpPtr::set(), gem5::ruby::SubBlock::setByte(), gem5::ruby::DataBlock::setData(), gem5::ruby::DataBlock::setData(), gem5::HSAPacketProcessor::setDeviceQueueDesc(), gem5::AMDGPUDevice::setDoorbellType(), gem5::KvmKernelGicV2::setGicReg(), gem5::KvmKernelGicV3::setGicReg(), gem5::ruby::WriteMask::setMask(), gem5::AMDGPUDevice::setSDMAEngine(), gem5::ruby::RubyRequest::setWriteMask(), gem5::split_first(), gem5::split_last(), gem5::GUPSGen::startup(), gem5::Intel8254Timer::Counter::startup(), subArr(), gem5::VegaISA::Inst_FLAT::swizzle(), TEST(), gem5::ruby::WriteMask::test(), gem5::MemTest::tick(), gem5::memory::SharedMemoryServer::BaseShmPollEvent::tryReadAll(), gem5::MultiLevelPageTable< EntryTypes >::unmap(), gem5::Intel8254Timer::Counter::unserialize(), gem5::MemState::unserialize(), gem5::PM4PacketProcessor::unserialize(), gem5::AMDGPUDevice::unsetDoorbell(), gem5::PM4PacketProcessor::updateReadIndex(), gem5::MSHR::TargetList::updateWriteFlags(), gem5::MipsISA::MipsFaultBase::vect(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VstSingleOp::VstSingleOp(), gem5::AMDGPUDevice::write(), gem5::CowDiskImage::write(), gem5::GenericTimerFrame::write(), gem5::Gicv2m::write(), gem5::Intel8254Timer::Counter::write(), gem5::memory::CfiMemory::ProgramBuffer::write(), gem5::MmioVirtIO::write(), gem5::MmioVirtIO::write(), gem5::PciVirtIO::write(), gem5::RawDiskImage::write(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::write(), gem5::RegisterBank< BankByteOrder >::RegisterBuf::write(), gem5::RiscvISA::MmioVirtIO::write(), gem5::RiscvISA::MmioVirtIO::write(), gem5::Uart8250::Registers::BankedRegister::write(), gem5::Uart8250::Registers::RWSwitchedRegister::write(), gem5::VirtDescriptor::write(), gem5::VirtIOBlock::write(), gem5::IdeDisk::writeCommand(), gem5::AMDGPUDevice::writeConfig(), gem5::IdeController::writeConfig(), gem5::IGbE::writeConfig(), gem5::NSGigE::writeConfig(), gem5::PciDevice::writeConfig(), gem5::IdeDisk::writeControl(), gem5::SMMUv3::writeControl(), gem5::GicV2::writeDistributor(), gem5::AMDGPUDevice::writeDoorbell(), gem5::pseudo_inst::writefile(), gem5::UFSHostDevice::UFSSCSIDevice::writeFlash(), gem5::AMDGPUDevice::writeFrame(), gem5::AMDGPUNbio::writeFrame(), gem5::AMDMMIOReader::writeFromTrace(), gem5::AMDGPUDevice::writeMMIO(), gem5::AMDGPUGfx::writeMMIO(), gem5::AMDGPUNbio::writeMMIO(), and gem5::AMDGPUVM::writeMMIO().

opc2

Bitfield<7,5> gem5::ArmISA::opc2

Definition at line 106 of file types.hh.

Referenced by gem5::ArmKvmCPU::decodeCoProcReg(), decodeCP14Reg(), decodeCP15Reg(), mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrMrcIssBuild(), mcrMrcIssExtract(), and mcrrMrrc15TrapToHyp().

opcode

Bitfield<24, 21> gem5::ArmISA::opcode

Definition at line 92 of file types.hh.

Referenced by gem5::SDMAEngine::decodeHeader(), gem5::trace::TarmacTracerRecord::TraceInstEntry::print(), gem5::trace::TarmacTracerRecordV8::TraceInstEntryV8::print(), and gem5::X86ISA::Decoder::processOpcode().

opcode15

Bitfield<15> gem5::ArmISA::opcode15

Definition at line 104 of file types.hh.

opcode15_12

Bitfield<15, 12> gem5::ArmISA::opcode15_12

Definition at line 103 of file types.hh.

opcode18

Bitfield<18> gem5::ArmISA::opcode18

Definition at line 102 of file types.hh.

opcode19

Bitfield<19> gem5::ArmISA::opcode19

Definition at line 101 of file types.hh.

opcode19_16

Bitfield<19, 16> gem5::ArmISA::opcode19_16

Definition at line 100 of file types.hh.

opcode20

Bitfield<20> gem5::ArmISA::opcode20

Definition at line 98 of file types.hh.

opcode22

Bitfield<22> gem5::ArmISA::opcode22

Definition at line 99 of file types.hh.

opcode23_20

Bitfield<23, 20> gem5::ArmISA::opcode23_20

Definition at line 96 of file types.hh.

opcode23_21

Bitfield<23, 21> gem5::ArmISA::opcode23_21

Definition at line 97 of file types.hh.

opcode24

Bitfield<24> gem5::ArmISA::opcode24

Definition at line 94 of file types.hh.

opcode24_23

Bitfield<24, 23> gem5::ArmISA::opcode24_23

Definition at line 95 of file types.hh.

opcode4

Bitfield<4> gem5::ArmISA::opcode4

Definition at line 109 of file types.hh.

opcode6

Bitfield<6> gem5::ArmISA::opcode6

Definition at line 108 of file types.hh.

opcode7

Bitfield<7> gem5::ArmISA::opcode7

Definition at line 107 of file types.hh.

or0

Bitfield<17,16> gem5::ArmISA::or0

Definition at line 691 of file misc_types.hh.

or1

Bitfield<19,18> gem5::ArmISA::or1

Definition at line 692 of file misc_types.hh.

or2

Bitfield<21,20> gem5::ArmISA::or2

Definition at line 693 of file misc_types.hh.

or3

Bitfield<23,22> gem5::ArmISA::or3

Definition at line 694 of file misc_types.hh.

or4

Bitfield<25,24> gem5::ArmISA::or4

Definition at line 695 of file misc_types.hh.

or5

Bitfield<27,26> gem5::ArmISA::or5

Definition at line 696 of file misc_types.hh.

or6

Bitfield<29,28> gem5::ArmISA::or6

Definition at line 697 of file misc_types.hh.

or7

Bitfield<31,30> gem5::ArmISA::or7

Definition at line 698 of file misc_types.hh.

orgn0

Bitfield< 11, 10 > gem5::ArmISA::orgn0

Definition at line 581 of file misc_types.hh.

orgn1

Bitfield< 27, 26 > gem5::ArmISA::orgn1

Definition at line 588 of file misc_types.hh.

oseccrEL1

Bitfield<10> gem5::ArmISA::oseccrEL1

Definition at line 1075 of file misc_types.hh.

oslarEL1

Bitfield<8> gem5::ArmISA::oslarEL1

Definition at line 1077 of file misc_types.hh.

oslk

Bitfield<1> gem5::ArmISA::oslk

Definition at line 867 of file misc_types.hh.

oslm_0

Bitfield<0> gem5::ArmISA::oslm_0

Definition at line 868 of file misc_types.hh.

oslm_3

Bitfield<3> gem5::ArmISA::oslm_3

Definition at line 865 of file misc_types.hh.

oslsrEL1

Bitfield<9> gem5::ArmISA::oslsrEL1

Definition at line 1076 of file misc_types.hh.

pa

Bitfield<39, 12> gem5::ArmISA::pa

Definition at line 741 of file misc_types.hh.

Referenced by gem5::ArmISA::Stage2LookUp::mergeTe(), gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr(), gem5::ArmISA::MMU::translateFunctional(), gem5::ArmISA::MMU::translateMmuOn(), and gem5::SMMUTranslationProcess::walkCacheUpdate().

pac

Bitfield<2, 1> gem5::ArmISA::pac

Definition at line 894 of file misc_types.hh.

Referenced by gem5::ArmISA::WatchPoint::isEnabled().

PageBytes

const Addr gem5::ArmISA::PageBytes = 1ULL << PageShift

Definition at line 53 of file page_size.hh.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::ArmProcess::argsInit(), gem5::RiscvProcess::argsInit(), gem5::ArmProcess32::ArmProcess32(), gem5::ArmProcess64::ArmProcess64(), gem5::ArmLinuxProcess32::initState(), gem5::ArmProcess32::initState(), gem5::ArmProcess64::initState(), gem5::MipsProcess::initState(), gem5::PowerProcess::initState(), gem5::RiscvProcess32::initState(), gem5::RiscvProcess64::initState(), gem5::Sparc32Process::initState(), gem5::Sparc64Process::initState(), gem5::MipsProcess::MipsProcess(), gem5::PowerProcess::PowerProcess(), gem5::RiscvProcess32::RiscvProcess32(), gem5::RiscvProcess64::RiscvProcess64(), roundPage(), gem5::ArmISA::MMU::translateFunctional(), gem5::Iris::MMU::translateFunctional(), and truncPage().

PageShift

const Addr gem5::ArmISA::PageShift = 12

Definition at line 52 of file page_size.hh.

Referenced by gem5::ArmISA::TlbEntry::pageStart(), and gem5::ArmISA::TlbEntry::updateVaddr().

pan

Bitfield< 23, 20 > gem5::ArmISA::pan

Definition at line 59 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

parange

Bitfield<3, 0> gem5::ArmISA::parange

Definition at line 163 of file misc_types.hh.

parEL1

Bitfield<27> gem5::ArmISA::parEL1

Definition at line 1042 of file misc_types.hh.

partidD

Bitfield<31,16> gem5::ArmISA::partidD

Definition at line 1129 of file misc_types.hh.

partidI

Bitfield<15,0> gem5::ArmISA::partidI

Definition at line 1130 of file misc_types.hh.

partidMax

Bitfield<15,0> gem5::ArmISA::partidMax

Definition at line 1100 of file misc_types.hh.

pcsample

Bitfield<3,0> gem5::ArmISA::pcsample

Definition at line 958 of file misc_types.hh.

pd0

Bitfield<4> gem5::ArmISA::pd0

Definition at line 574 of file misc_types.hh.

pd1

Bitfield<5> gem5::ArmISA::pd1

Definition at line 575 of file misc_types.hh.

pmc

Bitfield<2, 1> gem5::ArmISA::pmc

Definition at line 880 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::isEnabled().

pmgD

gem5::ArmISA::pmgD

Definition at line 1127 of file misc_types.hh.

pmgI

Bitfield<39,32> gem5::ArmISA::pmgI

Definition at line 1128 of file misc_types.hh.

pmgMax

Bitfield<39,32> gem5::ArmISA::pmgMax

Definition at line 1097 of file misc_types.hh.

pmsver

Bitfield<35, 32> gem5::ArmISA::pmsver

Definition at line 108 of file misc_types.hh.

pmuver

Bitfield<11, 8> gem5::ArmISA::pmuver

Definition at line 112 of file misc_types.hh.

PREDREG_FFR

const int gem5::ArmISA::PREDREG_FFR = 16

Definition at line 93 of file vec.hh.

PREDREG_UREG0

const int gem5::ArmISA::PREDREG_UREG0 = 17

Definition at line 94 of file vec.hh.

priority

Bitfield<3, 0> gem5::ArmISA::priority

Definition at line 860 of file misc_types.hh.

Referenced by gem5::prefetch::Queued::alreadyInQueue(), gem5::EventQueue::debugVerify(), gem5::memory::qos::FixedPriorityPolicy::initRequestorName(), gem5::memory::qos::FixedPriorityPolicy::initRequestorObj(), gem5::prefetch::Queued::insert(), gem5::MathExpr::parse(), gem5::MinorCPU::roundRobinPriority(), and gem5::Plic::updateInt().

privSyscallDescs32

SyscallDescTable<EmuLinux::SyscallABI32> gem5::ArmISA::privSyscallDescs32

static

Initial value:

= {
    { 0xf0001, "breakpoint" },
    { 0xf0002, "cacheflush" },
    { 0xf0003, "usr26" },
    { 0xf0004, "usr32" },
    { 0xf0005, "set_tls", setTLSFunc32 },
}

Definition at line 851 of file se_workload.cc.

Referenced by gem5::ArmISA::EmuLinux::syscall().

privSyscallDescs64

SyscallDescTable<EmuLinux::SyscallABI64> gem5::ArmISA::privSyscallDescs64

static

Initial value:

= {
    { 0x1002, "cacheflush" },
    { 0x1005, "set_tls", setTLSFunc64 }
}

Definition at line 860 of file se_workload.cc.

Referenced by gem5::ArmISA::EmuLinux::syscall().

procid

Bitfield<31,8> gem5::ArmISA::procid

Definition at line 703 of file misc_types.hh.

ps

Bitfield< 18, 16 > gem5::ArmISA::ps

Definition at line 598 of file misc_types.hh.

Referenced by gem5::GenericISA::DelaySlotPCState< InstWidth >::equals(), gem5::GenericISA::PCStateWithNext::equals(), gem5::SparcISA::TLB::MakeTsbPtr(), gem5::BasePixelPump::nextLine(), and gem5::ArmISA::TableWalker::processWalkAArch64().

psruser

Bitfield<22> gem5::ArmISA::psruser

Definition at line 125 of file types.hh.

ptw

Bitfield< 8 > gem5::ArmISA::ptw

Definition at line 363 of file misc_types.hh.

pubwl

gem5::ArmISA::pubwl

Definition at line 130 of file types.hh.

punwl

Bitfield<24, 20> gem5::ArmISA::punwl

Definition at line 154 of file types.hh.

q

Bitfield<27> gem5::ArmISA::q

Definition at line 55 of file misc_types.hh.

Referenced by gem5::SDMAEngine::atomic(), gem5::SDMAEngine::atomicData(), gem5::SDMAEngine::atomicDone(), gem5::SDMAEngine::constFill(), gem5::SDMAEngine::constFillDone(), gem5::SDMAEngine::copy(), gem5::SDMAEngine::copyDone(), gem5::SDMAEngine::copyReadData(), gem5::PM4PacketProcessor::decodeHeader(), gem5::SDMAEngine::decodeHeader(), gem5::PM4PacketProcessor::decodeNext(), gem5::SDMAEngine::decodeNext(), gem5::ruby::AbstractController::dequeueMemRespQueue(), gem5::BaseGlobalEvent::deschedule(), gem5::PowerISA::IntArithOp::divide(), gem5::PowerISA::IntArithOp::divide(), gem5::AddrRangeMap< V, max_cache_size >::erase(), gem5::SparcISA::TlbMap::erase(), gem5::memory::qos::MemCtrl::escalate(), gem5::SDMAEngine::fence(), gem5::SDMAEngine::fenceDone(), gem5::PM4PacketProcessor::indirectBuffer(), gem5::SDMAEngine::indirectBuffer(), gem5::PM4PacketProcessor::mapProcessV1(), gem5::PM4PacketProcessor::mapProcessV2(), gem5::PM4PacketProcessor::mapQueues(), gem5::PM4PacketProcessor::newQueue(), gem5::SDMAEngine::SDMAQueue::parent(), gem5::SDMAEngine::pollRegMem(), gem5::SDMAEngine::pollRegMemRead(), gem5::PM4PacketProcessor::process(), gem5::PM4PacketProcessor::processMQD(), gem5::PM4PacketProcessor::processSDMAMQD(), gem5::SDMAEngine::ptePde(), gem5::SDMAEngine::ptePdeDone(), gem5::pybind_init_event(), gem5::PM4PacketProcessor::queryStatus(), gem5::PM4PacketProcessor::queryStatusDone(), recipEstimate(), gem5::PM4PacketProcessor::releaseMem(), gem5::PM4PacketProcessor::releaseMemDone(), gem5::PM4PacketProcessor::runList(), gem5::memory::qos::LrgQueuePolicy::selectPacket(), gem5::PM4PacketProcessor::serialize(), Gem5SystemC::ControlExtension::setQos(), gem5::PM4PacketProcessor::setUconfigReg(), gem5::Event::setWhen(), gem5::SDMAEngine::srbmWrite(), gem5::PM4PacketProcessor::switchBuffer(), gem5::TracingExtension::TracingExtension(), gem5::SDMAEngine::trap(), gem5::PM4PacketProcessor::unmapQueues(), gem5::PM4PacketProcessor::waitRegMem(), gem5::SDMAEngine::write(), gem5::PM4PacketProcessor::writeData(), gem5::PM4PacketProcessor::writeDataDone(), gem5::SDMAEngine::writeDone(), and gem5::SDMAEngine::writeReadData().

qc

Bitfield<27> gem5::ArmISA::qc

Definition at line 536 of file misc_types.hh.

rao2

Bitfield<18> gem5::ArmISA::rao2

Definition at line 448 of file misc_types.hh.

rao3

Bitfield<16> gem5::ArmISA::rao3

Definition at line 451 of file misc_types.hh.

rao4

Bitfield<6, 3> gem5::ArmISA::rao4

Definition at line 470 of file misc_types.hh.

ras

Bitfield<31, 28> gem5::ArmISA::ras

Definition at line 219 of file misc_types.hh.

raz

Bitfield<31, 28> gem5::ArmISA::raz

Definition at line 568 of file misc_types.hh.

Referenced by TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), and TEST_F().

raz_13_4

Bitfield<13,4> gem5::ArmISA::raz_13_4

Definition at line 725 of file misc_types.hh.

raz_28

Bitfield<28> gem5::ArmISA::raz_28

Definition at line 730 of file misc_types.hh.

razwi_8_4

Bitfield<8, 4> gem5::ArmISA::razwi_8_4

Definition at line 839 of file misc_types.hh.

rd

Bitfield<15, 12> gem5::ArmISA::rd

Definition at line 114 of file types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printDataInst().

rdm

Bitfield< 31, 28 > gem5::ArmISA::rdm

Definition at line 86 of file misc_types.hh.

recip_sqrt_estimate

const uint8_t gem5::ArmISA::recip_sqrt_estimate[256]

static

Initial value:

= {
    255, 253, 251, 249, 247, 245, 243, 242, 240, 238, 236, 234, 233, 231, 229, 228,
    226, 224, 223, 221, 219, 218, 216, 215, 213, 212, 210, 209, 207, 206, 204, 203,
    201, 200, 198, 197, 196, 194, 193, 192, 190, 189, 188, 186, 185, 184, 183, 181,
    180, 179, 178, 176, 175, 174, 173, 172, 170, 169, 168, 167, 166, 165, 164, 163,
    162, 160, 159, 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146,
    145, 144, 143, 142, 141, 140, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131,
    131, 130, 129, 128, 127, 126, 126, 125, 124, 123, 122, 121, 121, 120, 119, 118,
    118, 117, 116, 115, 114, 114, 113, 112, 111, 111, 110, 109, 109, 108, 107, 106,
    105, 104, 103, 101, 100,  99,  97,  96,  95,  93,  92,  91,  90,  88,  87,  86,
    85,  84,  82,  81,  80,  79,  78,  77,  76,  75,  74,  72,  71,  70,  69,  68,
    67,  66,  65,  64,  63,  62,  61,  60,  60,  59,  58,  57,  56,  55,  54,  53,
    52,  51,  51,  50,  49,  48,  47,  46,  46,  45,  44,  43,  42,  42,  41,  40,
    39,  38,  38,  37,  36,  35,  35,  34,  33,  33,  32,  31,  30,  30,  29,  28,
    28,  27,  26,  26,  25,  24,  24,  23,  22,  22,  21,  20,  20,  19,  19,  18,
    17,  17,  16,  16,  15,  14,  14,  13,  13,  12,  11,  11,  10,  10,   9,   9,
    8,   8,   7,   6,   6,   5,   5,   4,   4,   3,   3,   2,   2,   1,   1,   0
}

Definition at line 3510 of file fplib.cc.

Referenced by fplibRSqrtEstimate(), fplibRSqrtEstimate(), and fplibRSqrtEstimate().

regList

Bitfield<15, 0> gem5::ArmISA::regList

Definition at line 142 of file types.hh.

res0

gem5::ArmISA::res0

Definition at line 864 of file misc_types.hh.

Referenced by TEST_F().

res0_

Bitfield<13> gem5::ArmISA::res0_

Definition at line 915 of file misc_types.hh.

res0_0

Bitfield< 0 > gem5::ArmISA::res0_0

Definition at line 879 of file misc_types.hh.

res0_1

Bitfield< 5 > gem5::ArmISA::res0_1

Definition at line 877 of file misc_types.hh.

res0_14_12

Bitfield<14, 12> gem5::ArmISA::res0_14_12

Definition at line 854 of file misc_types.hh.

res0_2

Bitfield< 9, 8 > gem5::ArmISA::res0_2

Definition at line 872 of file misc_types.hh.

res0_3

Bitfield< 13 > gem5::ArmISA::res0_3

Definition at line 908 of file misc_types.hh.

res0_30_9

Bitfield<30, 9> gem5::ArmISA::res0_30_9

Definition at line 838 of file misc_types.hh.

res0_4

Bitfield< 24, 16 > gem5::ArmISA::res0_4

Definition at line 905 of file misc_types.hh.

res0_5

Bitfield< 29 > gem5::ArmISA::res0_5

Definition at line 902 of file misc_types.hh.

res0_63_2

gem5::ArmISA::res0_63_2

Definition at line 844 of file misc_types.hh.

res0_63_32

gem5::ArmISA::res0_63_32

Definition at line 836 of file misc_types.hh.

res0_63_4

gem5::ArmISA::res0_63_4

Definition at line 859 of file misc_types.hh.

res1_12_el2

Bitfield<12, 12> gem5::ArmISA::res1_12_el2

Definition at line 820 of file misc_types.hh.

res1_13_el2

Bitfield<13, 13> gem5::ArmISA::res1_13_el2

Definition at line 819 of file misc_types.hh.

res1_7_0_el2

Bitfield<7, 0> gem5::ArmISA::res1_7_0_el2

Definition at line 828 of file misc_types.hh.

res1_8_el2

Bitfield<8> gem5::ArmISA::res1_8_el2

Definition at line 825 of file misc_types.hh.

res1_9_el2

Bitfield<9> gem5::ArmISA::res1_9_el2

Definition at line 824 of file misc_types.hh.

reserved_20_13

Bitfield<20,13> gem5::ArmISA::reserved_20_13

Definition at line 714 of file misc_types.hh.

reserved_22

Bitfield<22> gem5::ArmISA::reserved_22

Definition at line 716 of file misc_types.hh.

reserved_30_26

Bitfield<30,26> gem5::ArmISA::reserved_30_26

Definition at line 719 of file misc_types.hh.

reserved_4_3

Bitfield<4,3> gem5::ArmISA::reserved_4_3

Definition at line 708 of file misc_types.hh.

ReturnAddressReg

auto & gem5::ArmISA::ReturnAddressReg = int_reg::Lr

Definition at line 655 of file int.hh.

Referenced by gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::ArmISA::SkipFunc::returnFromFuncIn(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt(), and gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt().

ReturnValueReg

auto& gem5::ArmISA::ReturnValueReg = int_reg::X0

inlineconstexpr

Definition at line 648 of file int.hh.

Referenced by gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store(), and gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > >::store().

ReturnValueReg1

auto & gem5::ArmISA::ReturnValueReg1 = int_reg::X1

Definition at line 649 of file int.hh.

revidrEL1

Bitfield<28> gem5::ArmISA::revidrEL1

Definition at line 1041 of file misc_types.hh.

revision

Bitfield<23, 16> gem5::ArmISA::revision

Definition at line 852 of file misc_types.hh.

rfr

Bitfield<19> gem5::ArmISA::rfr

Definition at line 370 of file misc_types.hh.

rm

Bitfield<3, 0> gem5::ArmISA::rm

Definition at line 118 of file types.hh.

Referenced by fp16_round_(), fp32_round_(), fp64_round_(), gem5::getFpRound(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::setFpRound(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

rMode

Bitfield<23, 22> gem5::ArmISA::rMode

Definition at line 532 of file misc_types.hh.

Referenced by gem5::ArmISA::FpOp::binaryOp(), prepFpState(), gem5::ArmISA::FpOp::ternaryOp(), gem5::ArmISA::FpOp::unaryOp(), vcvtFpDFpH(), vcvtFpFpH(), and vcvtFpSFpH().

rn

Bitfield<19, 16> gem5::ArmISA::rn

Definition at line 113 of file types.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldMultOp64::VldMultOp64(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VldSingleOp64::VldSingleOp64(), gem5::ArmISA::VstMultOp::VstMultOp(), gem5::ArmISA::VstMultOp64::VstMultOp64(), gem5::ArmISA::VstSingleOp::VstSingleOp(), and gem5::ArmISA::VstSingleOp64::VstSingleOp64().

rndr

gem5::ArmISA::rndr

Definition at line 118 of file misc_types.hh.

rotate

Bitfield<11, 8> gem5::ArmISA::rotate

Definition at line 134 of file types.hh.

Referenced by gem5::ArmISA::PredIntOp::generateDisassembly().

roundingModes

Bitfield<31, 28> gem5::ArmISA::roundingModes

Definition at line 557 of file misc_types.hh.

rr

Bitfield<14> gem5::ArmISA::rr

Definition at line 454 of file misc_types.hh.

rs

Bitfield< 11, 8 > gem5::ArmISA::rs

Definition at line 462 of file misc_types.hh.

Referenced by gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::ruby::GPUCoalescer::completeHitCallback(), gem5::ruby::Sequencer::completeHitCallback(), gem5::Gicv3CPUInterface::generateSGI(), gem5::ruby::RubyPort::MemResponsePort::hitCallback(), gem5::ruby::Sequencer::hitCallback(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::ruby::RubyPort::MemResponsePort::recvAtomic(), gem5::ruby::RubyPort::MemResponsePort::recvFunctional(), gem5::ruby::RubyPort::MemResponsePort::recvTimingReq(), and gem5::statistics::BinaryNode< Op >::size().

rsvd

Bitfield<29, 28> gem5::ArmISA::rsvd

Definition at line 499 of file misc_types.hh.

rt

Bitfield<15, 12> gem5::ArmISA::rt

Definition at line 115 of file types.hh.

Referenced by mcrMrc14TrapToHyp(), mcrMrc15TrapToHyp(), mcrMrcIssBuild(), mcrMrcIssExtract(), mcrrMrrc15TrapToHyp(), mcrrMrrcIssBuild(), gem5::ArmISA::PairMemOp::PairMemOp(), and gem5::ArmISA::HTMCheckpoint::restore().

rw

Bitfield< 10 > gem5::ArmISA::rw

Definition at line 333 of file misc_types.hh.

Referenced by gem5::Pl111::pixelConverter().

rxfull

Bitfield<30> gem5::ArmISA::rxfull

Definition at line 900 of file misc_types.hh.

rxo

Bitfield<27> gem5::ArmISA::rxo

Definition at line 903 of file misc_types.hh.

s

Bitfield< 9 > gem5::ArmISA::s

Definition at line 646 of file misc_types.hh.

Referenced by gem5::IniFile::add(), gem5::AMDGPUDevice::AMDGPUDevice(), gem5::atomic_read(), gem5::atomic_write(), gem5::debug::changeFlag(), gem5::prefetch::AccessMapPatternMatching::checkCandidate(), gem5::AtagCmdline::cmdline(), gem5::BaseRemoteGDB::cmdQueryVar(), gem5::ExecStage::dispStatusToStr(), gem5::ScheduleStage::doDispatchListTransition(), gem5::ScheduleStage::doDispatchListTransition(), gem5::statistics::VectorBase< Derived, Stor >::doInit(), gem5::statistics::VectorDistBase< Derived, Stor >::doInit(), gem5::o3::DynInst::dump(), gem5::ExecStage::dumpDispList(), gem5::eat_end_white(), gem5::eat_lead_white(), gem5::eat_white(), gem5::emptyStrings(), gem5::statistics::VectorDistInfo::enable(), gem5::statistics::VectorInfo::enable(), gem5::ExecStage::exec(), gem5::ExecStage::ExecStageStats::ExecStageStats(), gem5::Float16::Float16(), gem5::o3::FUPool::FUPool(), gem5::VecRegContainer< SIZE >::getString(), gem5::Random::init(), gem5::ARMArchTLB::invalidateAll(), gem5::ConfigCache::invalidateAll(), gem5::IPACache::invalidateAll(), gem5::SMMUTLB::invalidateAll(), gem5::WalkCache::invalidateAll(), gem5::ARMArchTLB::invalidateASID(), gem5::SMMUTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPAA(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSID(), gem5::WalkCache::invalidateVA(), gem5::ARMArchTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::SMMUTLB::invalidateVMID(), gem5::WalkCache::invalidateVMID(), gem5::Logger::log(), gem5::SMMUTLB::lookupAnyVA(), gem5::EmulatedDriver::match(), gem5::ArmISA::TableWalker::memAttrs(), gem5::statistics::Group::mergeStatGroup(), gem5::Float16::operator float(), gem5::ParseParam< BitUnionType< T > >::parse(), gem5::ParseParam< bool >::parse(), gem5::ParseParam< std::string >::parse(), gem5::ParseParam< T, decltype(to_number("", std::declval< T & >()), void())>::parse(), gem5::ParseParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > >::parse(), gem5::ParseParam< VecPredRegContainer< NumBits, Packed > >::parse(), gem5::CacheBlk::print(), gem5::MSHR::TargetList::print(), gem5::PcCountTrackerManager::printAllTargets(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::linux::printk(), gem5::pybind_init_core(), gem5::quote(), gem5::Random::Random(), gem5::ruby::AbstractController::recvTimingResp(), gem5::replace(), gem5::EventQueue::replaceHead(), gem5::ScheduleStage::reserveResources(), gem5::statistics::Group::resetStats(), gem5::SyscallReturn::retry(), gem5::TCPIface::sendCmd(), gem5::memory::PhysicalMemory::serialize(), gem5::ruby::AbstractController::serviceMemoryQueue(), gem5::trace::InstRecord::setMem(), Gem5SystemC::ControlExtension::setSecure(), Gem5SystemC::ControlExtension::setStreamId(), Gem5SystemC::ControlExtension::setSubstreamId(), gem5::ruby::SimpleNetwork::SimpleNetwork(), gem5::split_first(), gem5::split_last(), gem5::startswith(), gem5::startswith(), gem5::startswith(), gem5::BaseRemoteGDB::TrapEvent::stopReason(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::to_bool(), gem5::to_lower(), gem5::PcCountPair::to_string(), gem5::tokenize(), gem5::trace::InstPBTrace::traceMem(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::unserialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< BufBytes >::unserialize(), gem5::WalkCache::WalkCacheStats::WalkCacheStats(), and gem5::memory::PhysicalMemory::~PhysicalMemory().

s1pie

Bitfield<11, 8> gem5::ArmISA::s1pie

Definition at line 206 of file misc_types.hh.

s1poe

Bitfield<19, 16> gem5::ArmISA::s1poe

Definition at line 204 of file misc_types.hh.

s1ptw

Bitfield< 7 > gem5::ArmISA::s1ptw

Definition at line 781 of file misc_types.hh.

Referenced by gem5::ArmISA::AbortFault< T >::annotate().

s2pie

Bitfield<15, 12> gem5::ArmISA::s2pie

Definition at line 205 of file misc_types.hh.

s2poe

Bitfield<23, 20> gem5::ArmISA::s2poe

Definition at line 203 of file misc_types.hh.

sa

Bitfield<3> gem5::ArmISA::sa

Definition at line 475 of file misc_types.hh.

Referenced by gem5::acceptFunc(), gem5::MipsISA::dspExtr(), gem5::MipsISA::dspMulq(), gem5::MipsISA::dspPrece(), gem5::MipsISA::dspPrecrSra(), gem5::MipsISA::dspShll(), gem5::MipsISA::dspShra(), gem5::MipsISA::dspShrl(), gem5::getsocknameFunc(), gem5::installSignalHandler(), gem5::recvfromFunc(), gem5::sendtoFunc(), and gem5::BaseKvmCPU::setupSignalHandler().

sa0

Bitfield<4> gem5::ArmISA::sa0

Definition at line 473 of file misc_types.hh.

sas

Bitfield<23, 22> gem5::ArmISA::sas

Definition at line 772 of file misc_types.hh.

sataRAMLatency

gem5::ArmISA::sataRAMLatency

Definition at line 707 of file misc_types.hh.

sb

Bitfield< 39, 36 > gem5::ArmISA::sb

Definition at line 99 of file misc_types.hh.

Referenced by gem5::prefetch::SBOOE::access().

sc2

Bitfield<19> gem5::ArmISA::sc2

Definition at line 909 of file misc_types.hh.

Referenced by addPACDA(), addPACDB(), addPACIA(), addPACIB(), authDA(), authDB(), authIA(), and authIB().

scd

Bitfield<7> gem5::ArmISA::scd

Definition at line 409 of file misc_types.hh.

sctlrEL1

Bitfield<29> gem5::ArmISA::sctlrEL1

Definition at line 1040 of file misc_types.hh.

sctlrx

Bitfield<7, 4> gem5::ArmISA::sctlrx

Definition at line 207 of file misc_types.hh.

scxtnumEL0

Bitfield<31> gem5::ArmISA::scxtnumEL0

Definition at line 1038 of file misc_types.hh.

scxtnumEL1

Bitfield<30> gem5::ArmISA::scxtnumEL1

Definition at line 1039 of file misc_types.hh.

sd

Bitfield<4> gem5::ArmISA::sd

Definition at line 943 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::activateBreakpoint(), gem5::DebugStep::execute(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), gem5::StackDistProbe::handleRequest(), and gem5::ArmISA::MMU::translateFs().

sdeflt

Bitfield<61> gem5::ArmISA::sdeflt

Definition at line 1123 of file misc_types.hh.

sed

Bitfield<8> gem5::ArmISA::sed

Definition at line 465 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::checkSETENDEnabled().

sel

gem5::ArmISA::sel

Definition at line 735 of file misc_types.hh.

Referenced by gem5::AddrRange::contains(), gem5::VegaISA::Inst_VOP3__V_PERM_B32::permute(), gem5::VegaISA::sdwaInstDstImpl(), gem5::VegaISA::sdwaInstDstImpl_helper(), gem5::VegaISA::sdwaInstSrcImpl(), gem5::VegaISA::sdwaInstSrcImpl_helper(), and gem5::Intel8254Timer::writeControl().

sel2

Bitfield<39, 36> gem5::ArmISA::sel2

Definition at line 217 of file misc_types.hh.

set

Bitfield<12, 11> gem5::ArmISA::set

Definition at line 788 of file misc_types.hh.

Referenced by gem5::NoMaliGpu::_interrupt(), gem5::ruby::CacheMemory::allocate(), gem5::ARMArchTLB::ARMArchTLB(), gem5::minor::BranchData::BranchData(), gem5::minor::BranchData::BranchData(), gem5::minor::Fetch1::changeStream(), gem5::SimpleThread::clearArchRegs(), gem5::ruby::CacheMemory::clearLockedAll(), gem5::o3::Fetch::clearStates(), gem5::o3::Commit::commit(), gem5::o3::Commit::commitInsts(), gem5::ConfigCache::ConfigCache(), gem5::GicV2::copyGicState(), gem5::statistics::AvgStor::dec(), gem5::minor::Decode::DecodeThreadInfo::DecodeThreadInfo(), gem5::GenericISA::DelaySlotPCState< InstWidth >::DelaySlotPCState(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::DelaySlotUPCState(), gem5::VegaISA::GpuTLB::demapPage(), gem5::X86ISA::GpuTLB::demapPage(), gem5::o3::Fetch::doSquash(), gem5::o3::DynInst::DynInst(), gem5::minor::Decode::evaluate(), gem5::minor::Fetch2::evaluate(), gem5::Wavefront::exec(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::o3::Fetch::fetch(), gem5::minor::Fetch2::Fetch2ThreadInfo::Fetch2ThreadInfo(), gem5::BaseTags::findBlockBySetAndWay(), gem5::FALRU::findBlockBySetAndWay(), gem5::ruby::CacheMemory::getAddressAtIdx(), gem5::BaseIndexingPolicy::getEntry(), gem5::ruby::CacheMemory::getReplacementWeight(), gem5::ruby::CacheMemory::htmAbortTransaction(), gem5::ruby::CacheMemory::htmCommitTransaction(), gem5::statistics::AvgStor::inc(), gem5::VegaISA::GpuTLB::insert(), gem5::X86ISA::GpuTLB::insert(), gem5::MemFootprintProbe::insertAddr(), gem5::InstResult::InstResult(), gem5::InstResult::InstResult(), gem5::InstResult::InstResult(), gem5::ARMArchTLB::invalidateAll(), gem5::ConfigCache::invalidateAll(), gem5::IPACache::invalidateAll(), gem5::SMMUTLB::invalidateAll(), gem5::WalkCache::invalidateAll(), gem5::ARMArchTLB::invalidateASID(), gem5::SMMUTLB::invalidateASID(), gem5::WalkCache::invalidateASID(), gem5::IPACache::invalidateIPA(), gem5::IPACache::invalidateIPAA(), gem5::ConfigCache::invalidateSID(), gem5::SMMUTLB::invalidateSID(), gem5::ConfigCache::invalidateSSID(), gem5::SMMUTLB::invalidateSSID(), gem5::ARMArchTLB::invalidateVA(), gem5::SMMUTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::ARMArchTLB::invalidateVAA(), gem5::SMMUTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::ARMArchTLB::invalidateVMID(), gem5::IPACache::invalidateVMID(), gem5::SMMUTLB::invalidateVMID(), gem5::WalkCache::invalidateVMID(), gem5::networking::Ip6Ptr::Ip6Ptr(), gem5::networking::Ip6Ptr::Ip6Ptr(), gem5::IPACache::IPACache(), gem5::networking::IpPtr::IpPtr(), gem5::networking::IpPtr::IpPtr(), gem5::ARMArchTLB::lookup(), gem5::branch_prediction::SimpleIndirectPredictor::lookup(), gem5::ConfigCache::lookup(), gem5::IPACache::lookup(), gem5::SMMUTLB::lookup(), gem5::VegaISA::GpuTLB::lookup(), gem5::WalkCache::lookup(), gem5::X86ISA::GpuTLB::lookup(), gem5::SMMUTLB::lookupAnyVA(), gem5::VegaISA::GpuTLB::lookupIt(), gem5::X86ISA::GpuTLB::lookupIt(), gem5::IntSourcePinBase::lower(), gem5::PowerState::matchPwrState(), gem5::NoMaliGpu::onInterrupt(), gem5::TimeBuffer< T >::wire::operator++(), gem5::TimeBuffer< T >::wire::operator++(), gem5::TimeBuffer< T >::wire::operator+=(), gem5::TimeBuffer< T >::wire::operator--(), gem5::TimeBuffer< T >::wire::operator--(), gem5::TimeBuffer< T >::wire::operator-=(), gem5::InstResult::operator=(), gem5::minor::BranchData::operator=(), gem5::minor::ForwardLineData::operator=(), gem5::networking::Ip6Ptr::operator=(), gem5::networking::Ip6Ptr::operator=(), gem5::networking::IpPtr::operator=(), gem5::networking::IpPtr::operator=(), gem5::networking::TcpPtr::operator=(), gem5::networking::TcpPtr::operator=(), gem5::networking::UdpPtr::operator=(), gem5::networking::UdpPtr::operator=(), gem5::RefCountingPtr< T >::operator=(), gem5::TimeBuffer< T >::wire::operator=(), gem5::TimeBuffer< T >::wire::operator=(), gem5::RiscvISA::PCState::PCState(), gem5::RiscvISA::PCState::PCState(), gem5::X86ISA::PCState::PCState(), gem5::o3::Commit::pcState(), gem5::o3::DynInst::pcState(), gem5::SimpleThread::pcState(), gem5::SimpleThread::pcStateNoRecord(), gem5::ARMArchTLB::pickEntryIdxToReplace(), gem5::ConfigCache::pickEntryIdxToReplace(), gem5::IPACache::pickEntryIdxToReplace(), gem5::SMMUTLB::pickEntryIdxToReplace(), gem5::WalkCache::pickEntryIdxToReplace(), gem5::branch_prediction::ReturnAddrStack::pop(), gem5::branch_prediction::BPredUnit::predict(), gem5::minor::Fetch2::predictBranch(), gem5::BaseSimpleCPU::preExecute(), gem5::minor::Fetch1::processResponse(), gem5::branch_prediction::ReturnAddrStack::AddrStack::push(), gem5::IntSourcePinBase::raise(), gem5::CheckerCPU::recordPCChange(), gem5::branch_prediction::SimpleIndirectPredictor::recordTarget(), gem5::o3::Fetch::resetStage(), gem5::branch_prediction::ReturnAddrStack::AddrStack::restore(), gem5::Flags< T >::set(), gem5::InstResult::set(), gem5::networking::TcpPtr::set(), gem5::networking::TcpPtr::set(), gem5::networking::UdpPtr::set(), gem5::networking::UdpPtr::set(), gem5::Gicv3Redistributor::setClrLPI(), gem5::BaseIndexingPolicy::setEntry(), gem5::PowerDomain::setFollowerPowerStates(), gem5::ruby::NetDest::setNetDest(), gem5::ReplaceableEntry::setPosition(), gem5::SectorBlk::setPosition(), gem5::o3::DynInst::setPredTarg(), gem5::Time::setTick(), gem5::PollQueue::setupAsyncIO(), gem5::GenericISA::SimplePCState< InstWidth >::SimplePCState(), gem5::SMMUTLB::SMMUTLB(), gem5::branch_prediction::BPredUnit::squash(), gem5::o3::Decode::squash(), gem5::o3::Commit::squashAll(), gem5::o3::IEW::squashDueToBranch(), gem5::o3::IEW::squashDueToMemOrder(), gem5::ARMArchTLB::store(), gem5::ConfigCache::store(), gem5::IPACache::store(), gem5::SMMUTLB::store(), gem5::WalkCache::store(), gem5::networking::TcpPtr::TcpPtr(), gem5::networking::TcpPtr::TcpPtr(), TEST(), gem5::Time::Time(), gem5::networking::UdpPtr::UdpPtr(), gem5::networking::UdpPtr::UdpPtr(), gem5::GenericISA::UPCState< InstWidth >::UPCState(), gem5::branch_prediction::SimpleBTB::update(), gem5::Checker< class >::verify(), gem5::minor::Fetch1::wakeupFetch(), and gem5::WalkCache::WalkCache().

sevenAndFour

Bitfield<33> gem5::ArmISA::sevenAndFour

Definition at line 84 of file types.hh.

sevl

Bitfield<3, 0> gem5::ArmISA::sevl

Definition at line 91 of file misc_types.hh.

sf

Bitfield< 7 > gem5::ArmISA::sf

Definition at line 775 of file misc_types.hh.

sField

Bitfield<20> gem5::ArmISA::sField

Definition at line 112 of file types.hh.

sh

Bitfield<8, 7> gem5::ArmISA::sh

Definition at line 745 of file misc_types.hh.

Referenced by gem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >::buildDispatcher(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gPredictions(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gPredictions(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gPredictions(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::gUpdates(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::gUpdates(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::makeThreadHistory(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::makeThreadHistory(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::makeThreadHistory(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::makeThreadHistory(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::RiscvISA::sat_add(), gem5::RiscvISA::sat_sub(), gem5::branch_prediction::MPP_StatisticalCorrector_64KB::scHistoryUpdate(), gem5::branch_prediction::MPP_StatisticalCorrector_8KB::scHistoryUpdate(), gem5::branch_prediction::TAGE_SC_L_64KB_StatisticalCorrector::scHistoryUpdate(), gem5::branch_prediction::TAGE_SC_L_8KB_StatisticalCorrector::scHistoryUpdate(), and gem5::BaseSemihosting::SemiCallBase< Semihosting, Abi32, Abi64 >::wrapImpl().

sh0

Bitfield< 13, 12 > gem5::ArmISA::sh0

Definition at line 62 of file int.hh.

sh1

Bitfield< 29, 28 > gem5::ArmISA::sh1

Definition at line 61 of file int.hh.

sha1

Bitfield< 11, 8 > gem5::ArmISA::sha1

Definition at line 89 of file misc_types.hh.

sha2

Bitfield< 15, 12 > gem5::ArmISA::sha2

Definition at line 88 of file misc_types.hh.

sha3

Bitfield< 35, 32 > gem5::ArmISA::sha3

Definition at line 125 of file misc_types.hh.

shift

Bitfield<6, 5> gem5::ArmISA::shift

Definition at line 117 of file types.hh.

Referenced by gem5::MipsISA::bitrev(), gem5::AMDGPU::convertMXFP(), gem5::divideFromConf(), gem5::X86ISA::X86StaticInst::divideStep(), gem5::findCarry(), gem5::findOverflow(), fp128_normalise(), fp16_normalise(), fp32_normalise(), fp64_normalise(), gem5::MipsISA::getCondCode(), gem5::branch_prediction::MultiperspectivePerceptron::ACYCLIC::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTMODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::GHISTPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::MODPATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::PATH::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCY::getHash(), gem5::branch_prediction::MultiperspectivePerceptron::SGHISTPATH::getHash(), gem5::branch_prediction::StatisticalCorrector::SCThreadHistory::initLocalHistory(), gem5::ps2::keySymToPs2(), lsl128(), lsl16(), lsl32(), lsl64(), lsr128(), lsr16(), lsr32(), lsr64(), gem5::Cycles::operator<<(), gem5::GenericSatCounter< T >::operator<<=(), gem5::Cycles::operator>>(), gem5::GenericSatCounter< T >::operator>>=(), gem5::ArmISA::Crypto::ror(), gem5::PowerISA::IntConcatRotateOp::rotate(), gem5::PowerISA::IntRotateOp::rotate(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::prefetch::IndirectMemory::trackMissIndex1(), gem5::prefetch::IndirectMemory::trackMissIndex2(), and gem5::X86ISA::X86MicroopBase::X86MicroopBase().

shiftSize

Bitfield<11, 7> gem5::ArmISA::shiftSize

Definition at line 116 of file types.hh.

shortVectors

Bitfield<27, 24> gem5::ArmISA::shortVectors

Definition at line 556 of file misc_types.hh.

si

Bitfield<6> gem5::ArmISA::si

Definition at line 941 of file misc_types.hh.

Referenced by gem5::ArmISA::Decoder::decode(), gem5::MipsISA::Decoder::decode(), gem5::RiscvISA::Decoder::decode(), gem5::SparcISA::Decoder::decode(), gem5::trace::InstPBTrace::getInstRecord(), gem5::CheckerCPU::getRegOperand(), gem5::CheckerCPU::getRegOperand(), gem5::minor::ExecContext::getRegOperand(), gem5::minor::ExecContext::getRegOperand(), gem5::SimpleExecContext::getRegOperand(), gem5::SimpleExecContext::getRegOperand(), gem5::MathExprPowerModel::getStatValue(), gem5::CheckerCPU::getWritableRegOperand(), gem5::minor::ExecContext::getWritableRegOperand(), gem5::SimpleExecContext::getWritableRegOperand(), gem5::CheckerCPU::readMiscRegOperand(), gem5::minor::ExecContext::readMiscRegOperand(), gem5::o3::DynInst::readMiscRegOperand(), gem5::SimpleExecContext::readMiscRegOperand(), gem5::CheckerCPU::setMiscRegOperand(), gem5::minor::ExecContext::setMiscRegOperand(), gem5::o3::DynInst::setMiscRegOperand(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::CheckerCPU::setRegOperand(), gem5::CheckerCPU::setRegOperand(), gem5::minor::ExecContext::setRegOperand(), gem5::minor::ExecContext::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::trace::InstPBTrace::traceInst(), and gem5::trace::InstPBTrace::traceMem().

sif

Bitfield<9> gem5::ArmISA::sif

Definition at line 407 of file misc_types.hh.

singlePrecision

Bitfield<7, 4> gem5::ArmISA::singlePrecision

Definition at line 551 of file misc_types.hh.

sl0

Bitfield<7, 6> gem5::ArmISA::sl0

Definition at line 648 of file misc_types.hh.

Referenced by gem5::ArmISA::V8PageTableOps16k::firstS2Level(), gem5::ArmISA::V8PageTableOps4k::firstS2Level(), and gem5::ArmISA::V8PageTableOps64k::firstS2Level().

sm

Bitfield<0, 0> gem5::ArmISA::sm

Definition at line 846 of file misc_types.hh.

sm3

Bitfield<39, 36> gem5::ArmISA::sm3

Definition at line 124 of file misc_types.hh.

sm4

Bitfield< 43, 40 > gem5::ArmISA::sm4

Definition at line 123 of file misc_types.hh.

smd

Bitfield<7> gem5::ArmISA::smd

Definition at line 410 of file misc_types.hh.

sme

gem5::ArmISA::sme

Definition at line 230 of file misc_types.hh.

smen

Bitfield< 25, 24 > gem5::ArmISA::smen

Definition at line 496 of file misc_types.hh.

smEver

Bitfield<59, 56> gem5::ArmISA::smEver

Definition at line 249 of file misc_types.hh.

smps

Bitfield<15, 15> gem5::ArmISA::smps

Definition at line 853 of file misc_types.hh.

snerr

Bitfield<43, 40> gem5::ArmISA::snerr

Definition at line 198 of file misc_types.hh.

snsmem

Bitfield<15, 12> gem5::ArmISA::snsmem

Definition at line 160 of file misc_types.hh.

sp

Bitfield< 3 > gem5::ArmISA::sp

Definition at line 75 of file misc_types.hh.

Referenced by gem5::RiscvProcess::argsInit(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::SparcISA::FillNNormal::invoke(), gem5::SparcISA::SpillNNormal::invoke(), gem5::SparcISA::TrapInstruction::invoke(), gem5::statistics::DistProxy< Stat >::operator=(), gem5::statistics::ScalarProxy< Stat >::operator=(), gem5::statistics::VectorProxy< Stat >::operator=(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), and gem5::ArmISA::ISA::setMiscReg().

span

Bitfield<23> gem5::ArmISA::span

Definition at line 434 of file misc_types.hh.

Referenced by gem5::SMMUTranslationProcess::doReadSTE().

specres

Bitfield< 43, 40 > gem5::ArmISA::specres

Definition at line 98 of file misc_types.hh.

specsei

Bitfield<27, 24> gem5::ArmISA::specsei

Definition at line 169 of file misc_types.hh.

spiddis

Bitfield<16> gem5::ArmISA::spiddis

Definition at line 912 of file misc_types.hh.

spniddis

Bitfield<17> gem5::ArmISA::spniddis

Definition at line 911 of file misc_types.hh.

squareRoot

Bitfield<23, 20> gem5::ArmISA::squareRoot

Definition at line 555 of file misc_types.hh.

srt

Bitfield<20, 16> gem5::ArmISA::srt

Definition at line 774 of file misc_types.hh.

ss

Bitfield< 2 > gem5::ArmISA::ss

Definition at line 60 of file misc_types.hh.

Referenced by gem5::ruby::PendingWriteInst::ackWriteCompletion(), gem5::ruby::UncoalescedTable::checkDeadlock(), gem5::TesterThread::checkDeadlock(), gem5::ruby::GPUCoalescer::coalescePacket(), gem5::ruby::GPUCoalescer::completeHitCallback(), gem5::ruby::Sequencer::completeHitCallback(), gem5::X86ISA::PageFault::describe(), gem5::X86ISA::X86FaultBase::describe(), gem5::RegisterFile::dump(), gem5::ExecStage::dumpDispList(), gem5::ProtocolTester::dumpErrorLog(), gem5::RegisterFileCache::dumpLL(), gem5::dumpSimcall(), TrieTestData::dumpTrie(), gem5::EmulationPageTable::externalize(), gem5::ArmISA::ArmStaticInst::generateDisassembly(), gem5::ArmISA::BranchEret64::generateDisassembly(), gem5::ArmISA::BranchEretA64::generateDisassembly(), gem5::ArmISA::BranchImm64::generateDisassembly(), gem5::ArmISA::BranchImm::generateDisassembly(), gem5::ArmISA::BranchImmCond64::generateDisassembly(), gem5::ArmISA::BranchImmImmReg64::generateDisassembly(), gem5::ArmISA::BranchImmReg64::generateDisassembly(), gem5::ArmISA::BranchReg64::generateDisassembly(), gem5::ArmISA::BranchReg::generateDisassembly(), gem5::ArmISA::BranchRegReg64::generateDisassembly(), gem5::ArmISA::BranchRegReg::generateDisassembly(), gem5::ArmISA::BranchRet64::generateDisassembly(), gem5::ArmISA::BranchRetA64::generateDisassembly(), gem5::ArmISA::DataImmOp::generateDisassembly(), gem5::ArmISA::DataRegOp::generateDisassembly(), gem5::ArmISA::DataRegRegOp::generateDisassembly(), gem5::ArmISA::DataX1Reg2ImmOp::generateDisassembly(), gem5::ArmISA::DataX1RegImmOp::generateDisassembly(), gem5::ArmISA::DataX1RegOp::generateDisassembly(), gem5::ArmISA::DataX2RegImmOp::generateDisassembly(), gem5::ArmISA::DataX2RegOp::generateDisassembly(), gem5::ArmISA::DataX3RegOp::generateDisassembly(), gem5::ArmISA::DataXCondCompImmOp::generateDisassembly(), gem5::ArmISA::DataXCondCompRegOp::generateDisassembly(), gem5::ArmISA::DataXCondSelOp::generateDisassembly(), gem5::ArmISA::DataXERegOp::generateDisassembly(), gem5::ArmISA::DataXImmOnlyOp::generateDisassembly(), gem5::ArmISA::DataXImmOp::generateDisassembly(), gem5::ArmISA::DataXSRegOp::generateDisassembly(), gem5::ArmISA::FpCondCompRegOp::generateDisassembly(), gem5::ArmISA::FpCondSelOp::generateDisassembly(), gem5::ArmISA::FpRegImmOp::generateDisassembly(), gem5::ArmISA::FpRegRegImmOp::generateDisassembly(), gem5::ArmISA::FpRegRegOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegCondOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegImmOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegOp::generateDisassembly(), gem5::ArmISA::FpRegRegRegRegOp::generateDisassembly(), gem5::ArmISA::MemoryAtomicPair64::generateDisassembly(), gem5::ArmISA::MemoryDImm64::generateDisassembly(), gem5::ArmISA::MemoryDImmEx64::generateDisassembly(), gem5::ArmISA::MemoryEx64::generateDisassembly(), gem5::ArmISA::MemoryImm64::generateDisassembly(), gem5::ArmISA::MemoryLiteral64::generateDisassembly(), gem5::ArmISA::MemoryOffset< Base >::generateDisassembly(), gem5::ArmISA::MemoryPostIndex64::generateDisassembly(), gem5::ArmISA::MemoryPostIndex< Base >::generateDisassembly(), gem5::ArmISA::MemoryPreIndex64::generateDisassembly(), gem5::ArmISA::MemoryPreIndex< Base >::generateDisassembly(), gem5::ArmISA::MemoryRaw64::generateDisassembly(), gem5::ArmISA::MemoryReg64::generateDisassembly(), gem5::ArmISA::MicroIntImmOp::generateDisassembly(), gem5::ArmISA::MicroIntImmXOp::generateDisassembly(), gem5::ArmISA::MicroIntMov::generateDisassembly(), gem5::ArmISA::MicroIntOp::generateDisassembly(), gem5::ArmISA::MicroIntRegXOp::generateDisassembly(), gem5::ArmISA::MicroMemOp::generateDisassembly(), gem5::ArmISA::MicroMemPairOp::generateDisassembly(), gem5::ArmISA::MicroSetPCCPSR::generateDisassembly(), gem5::ArmISA::PredImmOp::generateDisassembly(), gem5::ArmISA::PredIntOp::generateDisassembly(), gem5::ArmISA::PredMacroOp::generateDisassembly(), gem5::ArmISA::RfeOp::generateDisassembly(), gem5::ArmISA::SmeAddOp::generateDisassembly(), gem5::ArmISA::SmeAddVlOp::generateDisassembly(), gem5::ArmISA::SmeLd1xSt1xOp::generateDisassembly(), gem5::ArmISA::SmeLdrStrOp::generateDisassembly(), gem5::ArmISA::SmeMovExtractOp::generateDisassembly(), gem5::ArmISA::SmeMovInsertOp::generateDisassembly(), gem5::ArmISA::SmeOPOp::generateDisassembly(), gem5::ArmISA::SmeRdsvlOp::generateDisassembly(), gem5::ArmISA::SmeZeroOp::generateDisassembly(), gem5::ArmISA::SrsOp::generateDisassembly(), gem5::ArmISA::SveAdrOp::generateDisassembly(), gem5::ArmISA::SveBinConstrPredOp::generateDisassembly(), gem5::ArmISA::SveBinDestrPredOp::generateDisassembly(), gem5::ArmISA::SveBinIdxUnpredOp::generateDisassembly(), gem5::ArmISA::SveBinImmIdxUnpredOp::generateDisassembly(), gem5::ArmISA::SveBinImmPredOp::generateDisassembly(), gem5::ArmISA::SveBinImmUnpredConstrOp::generateDisassembly(), gem5::ArmISA::SveBinImmUnpredDestrOp::generateDisassembly(), gem5::ArmISA::SveBinUnpredOp::generateDisassembly(), gem5::ArmISA::SveBinWideImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveClampOp::generateDisassembly(), gem5::ArmISA::SveCmpImmOp::generateDisassembly(), gem5::ArmISA::SveCmpOp::generateDisassembly(), gem5::ArmISA::SveComplexIdxOp::generateDisassembly(), gem5::ArmISA::SveComplexOp::generateDisassembly(), gem5::ArmISA::SveCompTermOp::generateDisassembly(), gem5::ArmISA::SveContigMemSI::generateDisassembly(), gem5::ArmISA::SveContigMemSS::generateDisassembly(), gem5::ArmISA::SveDotProdIdxOp::generateDisassembly(), gem5::ArmISA::SveDotProdOp::generateDisassembly(), gem5::ArmISA::SveElemCountOp::generateDisassembly(), gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::generateDisassembly(), gem5::ArmISA::SveIndexIIOp::generateDisassembly(), gem5::ArmISA::SveIndexIROp::generateDisassembly(), gem5::ArmISA::SveIndexRIOp::generateDisassembly(), gem5::ArmISA::SveIndexRROp::generateDisassembly(), gem5::ArmISA::SveIntCmpImmOp::generateDisassembly(), gem5::ArmISA::SveIntCmpOp::generateDisassembly(), gem5::ArmISA::SveLdStructSI< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveLdStructSS< Element, MicroopLdMemType, MicroopDeIntrlvType >::generateDisassembly(), gem5::ArmISA::SveMemPredFillSpill::generateDisassembly(), gem5::ArmISA::SveMemVecFillSpill::generateDisassembly(), gem5::ArmISA::SveOrdReducOp::generateDisassembly(), gem5::ArmISA::SvePartBrkOp::generateDisassembly(), gem5::ArmISA::SvePartBrkPropOp::generateDisassembly(), gem5::ArmISA::SvePredBinPermOp::generateDisassembly(), gem5::ArmISA::SvePredCountOp::generateDisassembly(), gem5::ArmISA::SvePredCountPredOp::generateDisassembly(), gem5::ArmISA::SvePredLogicalOp::generateDisassembly(), gem5::ArmISA::SvePredTestOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitDstOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitSrcOp::generateDisassembly(), gem5::ArmISA::SvePredUnaryWImplicitSrcPredOp::generateDisassembly(), gem5::ArmISA::SvePselOp::generateDisassembly(), gem5::ArmISA::SvePtrueOp::generateDisassembly(), gem5::ArmISA::SveReducOp::generateDisassembly(), gem5::ArmISA::SveSelectOp::generateDisassembly(), gem5::ArmISA::SveStStructSI< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveStStructSS< Element, MicroopStMemType, MicroopIntrlvType >::generateDisassembly(), gem5::ArmISA::SveTblOp::generateDisassembly(), gem5::ArmISA::SveTerImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveTerPredOp::generateDisassembly(), gem5::ArmISA::SveTerUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnaryPredOp::generateDisassembly(), gem5::ArmISA::SveUnaryPredPredOp::generateDisassembly(), gem5::ArmISA::SveUnarySca2VecUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnaryUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnaryWideImmPredOp::generateDisassembly(), gem5::ArmISA::SveUnaryWideImmUnpredOp::generateDisassembly(), gem5::ArmISA::SveUnpackOp::generateDisassembly(), gem5::ArmISA::SveWhileOp::generateDisassembly(), gem5::ArmISA::SveWImplicitSrcDstOp::generateDisassembly(), gem5::ArmISA::SysDC64::generateDisassembly(), gem5::ArmISAInst::MicroTmeBasic64::generateDisassembly(), gem5::ArmISAInst::TmeImmOp64::generateDisassembly(), gem5::ArmISAInst::TmeRegNone64::generateDisassembly(), gem5::ImmOp64::generateDisassembly(), gem5::ImmOp::generateDisassembly(), gem5::McrrOp::generateDisassembly(), gem5::MiscRegImmOp64::generateDisassembly(), gem5::MiscRegRegImmOp64::generateDisassembly(), gem5::MiscRegRegImmOp::generateDisassembly(), gem5::MrrcOp::generateDisassembly(), gem5::MrsOp::generateDisassembly(), gem5::MsrImmOp::generateDisassembly(), gem5::MsrRegOp::generateDisassembly(), gem5::PowerISA::BranchDispCondOp::generateDisassembly(), gem5::PowerISA::BranchOp::generateDisassembly(), gem5::PowerISA::BranchRegCondOp::generateDisassembly(), gem5::PowerISA::CondLogicOp::generateDisassembly(), gem5::PowerISA::CondMoveOp::generateDisassembly(), gem5::PowerISA::FloatOp::generateDisassembly(), gem5::PowerISA::IntArithOp::generateDisassembly(), gem5::PowerISA::IntCompOp::generateDisassembly(), gem5::PowerISA::IntConcatRotateOp::generateDisassembly(), gem5::PowerISA::IntConcatShiftOp::generateDisassembly(), gem5::PowerISA::IntDispArithOp::generateDisassembly(), gem5::PowerISA::IntImmArithOp::generateDisassembly(), gem5::PowerISA::IntImmCompLogicOp::generateDisassembly(), gem5::PowerISA::IntImmCompOp::generateDisassembly(), gem5::PowerISA::IntImmLogicOp::generateDisassembly(), gem5::PowerISA::IntImmOp::generateDisassembly(), gem5::PowerISA::IntImmTrapOp::generateDisassembly(), gem5::PowerISA::IntLogicOp::generateDisassembly(), gem5::PowerISA::IntOp::generateDisassembly(), gem5::PowerISA::IntRotateOp::generateDisassembly(), gem5::PowerISA::IntShiftOp::generateDisassembly(), gem5::PowerISA::IntTrapOp::generateDisassembly(), gem5::PowerISA::MemDispOp::generateDisassembly(), gem5::PowerISA::MemDispShiftOp::generateDisassembly(), gem5::PowerISA::MemIndexOp::generateDisassembly(), gem5::PowerISA::MiscOp::generateDisassembly(), gem5::PowerISA::PowerStaticInst::generateDisassembly(), gem5::RegImmImmOp64::generateDisassembly(), gem5::RegImmImmOp::generateDisassembly(), gem5::RegImmOp::generateDisassembly(), gem5::RegImmRegOp::generateDisassembly(), gem5::RegImmRegShiftOp::generateDisassembly(), gem5::RegMiscRegImmOp64::generateDisassembly(), gem5::RegMiscRegImmOp::generateDisassembly(), gem5::RegNone::generateDisassembly(), gem5::RegOp64::generateDisassembly(), gem5::RegOp::generateDisassembly(), gem5::RegRegImmImmOp64::generateDisassembly(), gem5::RegRegImmImmOp::generateDisassembly(), gem5::RegRegImmOp::generateDisassembly(), gem5::RegRegOp::generateDisassembly(), gem5::RegRegRegImmOp64::generateDisassembly(), gem5::RegRegRegImmOp::generateDisassembly(), gem5::RegRegRegOp::generateDisassembly(), gem5::RegRegRegRegOp::generateDisassembly(), gem5::SparcISA::SparcStaticInst::generateDisassembly(), gem5::X86ISA::X86MicroopBase::generateDisassembly(), gem5::X86ISA::X86StaticInst::generateDisassembly(), gem5::BaseKvmCPU::getAndFormatOneReg(), gem5::ruby::GPUCoalescer::getDynInst(), gem5::LdsState::getDynInstr(), gem5::ArmISA::ArmStaticInst::getPSTATEFromPSR(), getSymbolError(), gem5::ruby::VIPERCoalescer::invTCCCallback(), gem5::Logger::print(), gem5::TesterThread::printAllOutstandingReqs(), gem5::TesterThread::printOutstandingReqs(), gem5::ruby::GPUCoalescer::printRequestTable(), gem5::ruby::UncoalescedTable::printRequestTable(), gem5::ruby::garnet::NetworkInterface::InputPort::printVnets(), gem5::ruby::garnet::NetworkInterface::OutputPort::printVnets(), gem5::LdsState::process(), gem5::ProtocolTester::ProtocolTester(), gem5::RegisterBank< BankByteOrder >::read(), gem5::ruby::RubyPort::MemResponsePort::recvTimingReq(), gem5::X86ISA::FlatFloatRegClassOps::regName(), gem5::X86ISA::FlatIntRegClassOps::regName(), gem5::ScheduleStage::reserveResources(), gem5::ThermalDomain::setSubSystem(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::branch_prediction::ReturnAddrStack::AddrStack::toString(), gem5::TesterThread::validateAtomicResp(), gem5::TesterThread::validateLoadResp(), gem5::ruby::GPUCoalescer::wakeup(), and gem5::RegisterBank< BankByteOrder >::write().

ssc

Bitfield< 15, 14 > gem5::ArmISA::ssc

Definition at line 875 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), and gem5::ArmISA::SelfDebug::securityStateMatch().

sse

Bitfield<21> gem5::ArmISA::sse

Definition at line 773 of file misc_types.hh.

st

Bitfield< 11 > gem5::ArmISA::st

Definition at line 186 of file misc_types.hh.

Referenced by gem5::OutputDirectory::isFile(), and gem5::EventQueue::name().

StackPointerReg

auto & gem5::ArmISA::StackPointerReg = int_reg::Sp

Definition at line 654 of file int.hh.

Referenced by gem5::PowerProcess::argsInit(), gem5::RiscvProcess::argsInit(), gem5::SparcProcess::argsInit(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::trace::TarmacTracerRecord::TraceRegEntry::updateInt(), and gem5::trace::TarmacTracerRecordV8::TraceRegEntryV8::updateInt().

status

Bitfield<5, 0> gem5::ArmISA::status

Definition at line 507 of file misc_types.hh.

Referenced by gem5::o3::CPU::addThreadToExitingList(), gem5::MipsISA::MipsFaultBase::base(), gem5::fastmodel::ScxEvsCortexA76< Types >::before_end_of_elaboration(), gem5::bindFunc(), gem5::BaseSemihosting::callIsError(), gem5::MipsISA::Interrupts::checkInterrupts(), gem5::RiscvISA::TLB::checkPermissions(), gem5::RiscvISA::ISA::clear(), gem5::FDArray::closeFDEntry(), gem5::MipsISA::ISA::configCP(), gem5::connectFunc(), gem5::RiscvISA::TLB::doTranslate(), gem5::o3::CPU::drainResume(), gem5::scmi::EndBitUnion(), gem5::RiscvISA::VlFFTrimVlMicroOp::execute(), gem5::exitFunc(), gem5::exitGroupFunc(), gem5::exitImpl(), gem5::MipsISA::forkThread(), gem5::MipsISA::Interrupts::getInterrupt(), gem5::RiscvISA::TLB::getMemPriv(), gem5::getsocknameFunc(), gem5::getsockoptFunc(), gem5::fastmodel::GIC::GIC(), gem5::RiscvISA::Interrupts::globalMask(), gem5::RiscvISA::Walker::WalkerState::initState(), gem5::MipsISA::ResetFault::invoke(), gem5::RiscvISA::Reset::invoke(), gem5::RiscvISA::RiscvFault::invoke(), gem5::ioctlFunc(), gem5::listenFunc(), main(), gem5::ruby::Sequencer::makeRequest(), gem5::System::Threads::numRunning(), gem5::MipsISA::TlbRefillFault::offset(), gem5::VirtIOBlock::RequestQueue::onNotifyDescriptor(), gem5::IGbE::RxDescCache::pktComplete(), gem5::fastmodel::PL330::PL330(), gem5::pollFunc(), gem5::Pl050::read(), gem5::RiscvISA::ISA::readMiscReg(), gem5::ps2::PS2Mouse::recv(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), gem5::AMDGPUMemoryManager::GPUMemPort::recvTimingResp(), gem5::sinic::Device::rxKick(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::sendBeginResp(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::sendEndReq(), gem5::IdeController::Channel::serialize(), gem5::Pl050::serialize(), gem5::ps2::PS2Mouse::serialize(), gem5::VirtIODeviceBase::setDeviceStatus(), gem5::MipsISA::MipsFaultBase::setExceptionState(), gem5::setsockoptFunc(), gem5::fastmodel::SignalReceiverInt::SignalReceiverInt(), gem5::socketpairFunc(), gem5::UFSHostDevice::UFSSCSIDevice::statusCheck(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::DrainManager::tryDrain(), gem5::IdeController::Channel::unserialize(), gem5::Pl050::unserialize(), gem5::ps2::PS2Mouse::unserialize(), gem5::MipsISA::updateStatusView(), gem5::MipsISA::updateTCStatusView(), gem5::MinorCPU::wakeup(), gem5::o3::CPU::wakeup(), and gem5::PciVirtIO::write().

stride

Bitfield<21, 20> gem5::ArmISA::stride

Definition at line 531 of file misc_types.hh.

Referenced by gem5::ruby::RubyPrefetcher::accessNonunitFilter(), gem5::ruby::RubyPrefetcher::accessUnitFilter(), gem5::ArmISA::VfpMacroOp::addStride(), gem5::VegaISA::Inst_MUBUF::calcAddr(), gem5::prefetch::AccessMapPatternMatching::calculatePrefetch(), gem5::prefetch::SignaturePath::calculatePrefetch(), gem5::prefetch::AccessMapPatternMatching::checkCandidate(), gem5::prefetch::SignaturePath::PatternEntry::findStride(), gem5::prefetch::SignaturePath::getSignatureEntry(), gem5::prefetch::SignaturePath::PatternEntry::getStrideEntry(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::prefetch::Queued::insert(), gem5::prefetch::Stride::StrideEntry::invalidate(), gem5::ruby::makeNextStrideAddress(), gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr(), gem5::ArmISA::VfpMacroOp::nextIdxs(), gem5::ArmISA::VfpMacroOp::nextIdxs(), gem5::ArmISA::VfpMacroOp::nextIdxs(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::prefetch::SignaturePath::updatePatternTable(), and gem5::ArmISA::TableWalker::walkAddresses().

su

Bitfield<1> gem5::ArmISA::su

Definition at line 946 of file misc_types.hh.

subArchDefined

Bitfield<29, 0> gem5::ArmISA::subArchDefined

Definition at line 546 of file misc_types.hh.

svcEL0

Bitfield<52> gem5::ArmISA::svcEL0

Definition at line 964 of file misc_types.hh.

svcEL1

Bitfield<53> gem5::ArmISA::svcEL1

Definition at line 963 of file misc_types.hh.

sve

Bitfield<35, 32> gem5::ArmISA::sve

Definition at line 218 of file misc_types.hh.

sveLen

Bitfield<59, 56> gem5::ArmISA::sveLen

Definition at line 67 of file types.hh.

sveVer

Bitfield<3, 0> gem5::ArmISA::sveVer

Definition at line 244 of file misc_types.hh.

sw

Bitfield< 10 > gem5::ArmISA::sw

Definition at line 64 of file int.hh.

swio

Bitfield<1> gem5::ArmISA::swio

Definition at line 364 of file misc_types.hh.

syscallDescs32

SyscallDescTable< EmuFreebsd::SyscallABI32 > gem5::ArmISA::syscallDescs32({}) ( {} )

static

Referenced by gem5::ArmISA::EmuFreebsd::syscall().

syscallDescs32High

SyscallTable32 gem5::ArmISA::syscallDescs32High(0x900000)

(

0x900000

)

syscallDescs32Low

SyscallTable32 gem5::ArmISA::syscallDescs32Low(0) ( 0 )

static

Referenced by gem5::ArmISA::EmuLinux::syscall().

syscallDescs64

SyscallDescTable<EmuFreebsd::SyscallABI64> gem5::ArmISA::syscallDescs64

static

Initial value:

= {
    {    1, "exit", exitFunc },
    {    3, "read", readFunc<ArmFreebsd64> },
    {    4, "write", writeFunc<ArmFreebsd64> },
    {   17, "obreak", brkFunc },
    {   54, "ioctl", ioctlFunc<ArmFreebsd64> },
    {   58, "readlink", readlinkFunc<ArmFreebsd64> },
    {  117, "getrusage", getrusageFunc<ArmFreebsd64> },
    {  189, "fstat", fstatFunc<ArmFreebsd64> },
 
    {  202, "sysctl", sysctlFunc },
 
 
 
    {  253, "issetugid", issetugidFunc },
    {  477, "mmap", mmapFunc<ArmFreebsd64> }
}

Definition at line 133 of file se_workload.cc.

Referenced by gem5::ArmISA::EmuFreebsd::syscall().

syscallDescs64High

SyscallTable64 gem5::ArmISA::syscallDescs64High(0x900000)

(

0x900000

)

syscallDescs64Low

SyscallTable64 gem5::ArmISA::syscallDescs64Low(0) ( 0 )

static

Referenced by gem5::ArmISA::EmuLinux::syscall().

SyscallNumReg

auto & gem5::ArmISA::SyscallNumReg = ReturnValueReg

Definition at line 657 of file int.hh.

SyscallPseudoReturnReg

auto & gem5::ArmISA::SyscallPseudoReturnReg = ReturnValueReg

Definition at line 658 of file int.hh.

Referenced by gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store(), and gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuLinux::BaseSyscallABI, ABI > > >::store().

SyscallSuccessReg

auto & gem5::ArmISA::SyscallSuccessReg = ReturnValueReg

Definition at line 659 of file int.hh.

t

Bitfield<5> gem5::ArmISA::t

Definition at line 71 of file misc_types.hh.

Referenced by gem5::RiscvISA::_rvk_emu_aes64ks1i(), gem5::RiscvISA::_rvk_emu_aes64ks2(), addPAC(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::b_transport(), gem5::BaseSemihosting::BaseSemihosting(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::fastmodel::AmbaFromTlmBridge64::bTransport(), gem5::fastmodel::AmbaToTlmBridge64::bTransport(), gem5::branch_prediction::TAGE_SC_L_TAGE::calculateIndicesAndTags(), gem5::IGbE::chkInterrupt(), gem5::SparcISA::TLB::clearUsedBits(), gem5::prefetch::Queued::DeferredPacket::createPkt(), gem5::o3::CPU::drain(), gem5::ProtocolTester::dumpErrorLog(), gem5::HDLcd::PixelPump::dumpSettings(), gem5::Packet::findNextSenderState(), gem5::Serializable::generateCheckpointOut(), gem5::ruby::GPUCoalescer::getFirstResponseToCompletionDelayHist(), gem5::ruby::Sequencer::getFirstResponseToCompletionDelayHist(), gem5::ruby::GPUCoalescer::getForwardRequestToFirstResponseHist(), gem5::ruby::Sequencer::getForwardRequestToFirstResponseHist(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::getHash(), gem5::ruby::Sequencer::getHitMachLatencyHist(), gem5::ruby::Sequencer::getHitTypeLatencyHist(), gem5::ruby::Sequencer::getHitTypeMachLatencyHist(), gem5::ruby::Sequencer::getIncompleteTimes(), gem5::ruby::GPUCoalescer::getInitialToForwardDelayHist(), gem5::ruby::Sequencer::getInitialToForwardDelayHist(), gem5::ruby::GPUCoalescer::getIssueToInitialDelayHist(), gem5::ruby::Sequencer::getIssueToInitialDelayHist(), gem5::ruby::GPUCoalescer::getMissMachLatencyHist(), gem5::ruby::Sequencer::getMissMachLatencyHist(), gem5::ruby::GPUCoalescer::getMissTypeLatencyHist(), gem5::ruby::Sequencer::getMissTypeLatencyHist(), gem5::ruby::GPUCoalescer::getMissTypeMachLatencyHist(), gem5::ruby::Sequencer::getMissTypeMachLatencyHist(), gem5::ruby::GPUCoalescer::getTypeLatencyHist(), gem5::ruby::Sequencer::getTypeLatencyHist(), gem5::branch_prediction::MultiperspectivePerceptron::RECENCYPOS::hash(), gem5::System::Threads::insert(), gem5::TimingSimpleCPU::IprEvent::IprEvent(), gem5::SparcISA::TLB::lookup(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >::EnumClassHash::operator()(), gem5::stl_helpers::hash_impl::hash< std::tuple< T... > >::operator()(), gem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >::operator()(), gem5::CircularQueue< T >::iterator::operator+(), gem5::CircularQueue< T >::iterator::operator++(), gem5::CircularQueue< T >::iterator::operator+=(), gem5::CircularQueue< T >::iterator::operator-(), gem5::CircularQueue< T >::iterator::operator--(), gem5::CircularQueue< T >::iterator::operator-=(), gem5::networking::TcpPtr::operator=(), gem5::networking::UdpPtr::operator=(), gem5::TrafficGen::parseConfig(), gem5::o3::DynInst::popResult(), gem5::SparcISA::PageTableEntry::populate(), gem5::MSHR::TargetList::populateFlags(), gem5::IGbE::postInterrupt(), gem5::MSHR::TargetList::print(), gem5::WriteQueueEntry::TargetList::print(), gem5::MSHR::promoteDeferredTargets(), gem5::MSHR::promoteReadable(), gem5::MSHR::promoteWritable(), gem5::pybind_init_core(), gem5::pybind_init_event(), gem5::System::Threads::quiesce(), gem5::System::Threads::quiesceTick(), gem5::RealViewTemperatureSensor::read(), gem5::SerialLink::SerialLinkResponsePort::recvTimingReq(), gem5::SerialLink::SerialLinkRequestPort::recvTimingResp(), gem5::System::Threads::replace(), gem5::EventQueue::replaceHead(), gem5::MSHR::TargetList::replaceUpgrades(), gem5::RiscvISA::sat_addu(), gem5::RiscvISA::sat_subu(), gem5::TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(), gem5::System::serialize(), gem5::o3::DynInst::setResult(), gem5::StaticInst::simpleAsBytes(), gem5::LinearSystem::solve(), gem5::BaseCPU::suspendContext(), gem5::SimulatorThreads::terminateThreads(), TEST(), TEST(), gem5::Clocked::ticksToCycles(), gem5::timeFunc(), gem5::MSHR::TargetList::trySatisfyFunctional(), gem5::WriteQueueEntry::TargetList::trySatisfyFunctional(), gem5::SerialLink::SerialLinkRequestPort::trySendTiming(), gem5::SerialLink::SerialLinkResponsePort::trySendTiming(), gem5::QARMA::tweakCellInvRot(), gem5::QARMA::tweakCellRot(), gem5::BaseRemoteGDB::TrapEvent::type(), gem5::Globals::unserialize(), gem5::System::unserialize(), gem5::branch_prediction::MPP_TAGE::updatePathAndGlobalHistory(), and gem5::branch_prediction::TAGE_SC_L_TAGE::updatePathAndGlobalHistory().

t0

Bitfield<0> gem5::ArmISA::t0

Definition at line 309 of file misc_types.hh.

Referenced by fp16_sqrt(), fp32_sqrt(), fp64_muladd(), mul64x32(), and gem5::QARMA::PACMult().

t0sz

gem5::ArmISA::t0sz

Definition at line 577 of file misc_types.hh.

t0sz64

Bitfield<5, 0> gem5::ArmISA::t0sz64

Definition at line 647 of file misc_types.hh.

t1

Bitfield<1> gem5::ArmISA::t1

Definition at line 308 of file misc_types.hh.

Referenced by gem5::ArmISA::Crypto::aesMixColumns(), gem5::ThreadContext::compare(), fp16_sqrt(), fp32_sqrt(), fp64_muladd(), gem5::igbreg::txd_op::isTypes(), mul64x32(), gem5::QARMA::PACMult(), gem5::RiscvISA::PMP::pmpDecodeNapot(), gem5::Shader::sampleInstRoundTrip(), and TEST().

t10

Bitfield<10> gem5::ArmISA::t10

Definition at line 299 of file misc_types.hh.

t11

Bitfield<11> gem5::ArmISA::t11

Definition at line 298 of file misc_types.hh.

t12

Bitfield<12> gem5::ArmISA::t12

Definition at line 297 of file misc_types.hh.

t13

Bitfield<13> gem5::ArmISA::t13

Definition at line 296 of file misc_types.hh.

t15

Bitfield<15> gem5::ArmISA::t15

Definition at line 295 of file misc_types.hh.

t1sz

Bitfield< 21, 16 > gem5::ArmISA::t1sz

Definition at line 584 of file misc_types.hh.

t2

Bitfield<2> gem5::ArmISA::t2

Definition at line 307 of file misc_types.hh.

Referenced by gem5::ThreadContext::compare(), gem5::igbreg::txd_op::isTypes(), gem5::QARMA::PACMult(), gem5::Shader::sampleInstRoundTrip(), and TEST().

t2e

Bitfield<6> gem5::ArmISA::t2e

Definition at line 578 of file misc_types.hh.

t3

Bitfield<3> gem5::ArmISA::t3

Definition at line 306 of file misc_types.hh.

Referenced by gem5::QARMA::PACMult(), gem5::Shader::sampleInstRoundTrip(), and TEST().

t4

Bitfield<4> gem5::ArmISA::t4

Definition at line 305 of file misc_types.hh.

Referenced by gem5::Shader::sampleInstRoundTrip().

t5

Bitfield<5> gem5::ArmISA::t5

Definition at line 304 of file misc_types.hh.

Referenced by gem5::Shader::sampleInstRoundTrip().

t6

Bitfield<6> gem5::ArmISA::t6

Definition at line 303 of file misc_types.hh.

t7

Bitfield<7> gem5::ArmISA::t7

Definition at line 302 of file misc_types.hh.

t8

Bitfield<8> gem5::ArmISA::t8

Definition at line 301 of file misc_types.hh.

t9

Bitfield<9> gem5::ArmISA::t9

Definition at line 300 of file misc_types.hh.

tac

Bitfield<21> gem5::ArmISA::tac

Definition at line 343 of file misc_types.hh.

tacr

Bitfield<21> gem5::ArmISA::tacr

Definition at line 344 of file misc_types.hh.

tagRAMLatency

Bitfield<8,6> gem5::ArmISA::tagRAMLatency

Definition at line 710 of file misc_types.hh.

tagRAMSetup

Bitfield<9> gem5::ArmISA::tagRAMSetup

Definition at line 711 of file misc_types.hh.

tagRAMSlice

Bitfield<12> gem5::ArmISA::tagRAMSlice

Definition at line 713 of file misc_types.hh.

tam

Bitfield<30> gem5::ArmISA::tam

Definition at line 813 of file misc_types.hh.

tase

Bitfield<15> gem5::ArmISA::tase

Definition at line 273 of file misc_types.hh.

tbi

Bitfield< 20 > gem5::ArmISA::tbi

Definition at line 599 of file misc_types.hh.

Referenced by addPAC(), auth(), calculateTBI(), computeAddrTop(), gem5::branch_prediction::TAGE_SC_L_TAGE::getUseAltIdx(), and stripPAC().

tbi0

Bitfield< 37 > gem5::ArmISA::tbi0

Definition at line 593 of file misc_types.hh.

tbi1

Bitfield< 38 > gem5::ArmISA::tbi1

Definition at line 594 of file misc_types.hh.

tbid

Bitfield<29> gem5::ArmISA::tbid

Definition at line 622 of file misc_types.hh.

Referenced by computeAddrTop().

tbid0

Bitfield<51> gem5::ArmISA::tbid0

Definition at line 632 of file misc_types.hh.

tbid1

Bitfield<52> gem5::ArmISA::tbid1

Definition at line 633 of file misc_types.hh.

tcp0

Bitfield<0> gem5::ArmISA::tcp0

Definition at line 289 of file misc_types.hh.

tcp1

Bitfield<1> gem5::ArmISA::tcp1

Definition at line 288 of file misc_types.hh.

tcp10

Bitfield<10> gem5::ArmISA::tcp10

Definition at line 277 of file misc_types.hh.

tcp11

Bitfield<11> gem5::ArmISA::tcp11

Definition at line 276 of file misc_types.hh.

tcp12

Bitfield<12> gem5::ArmISA::tcp12

Definition at line 275 of file misc_types.hh.

tcp13

Bitfield<13> gem5::ArmISA::tcp13

Definition at line 274 of file misc_types.hh.

tcp2

Bitfield<2> gem5::ArmISA::tcp2

Definition at line 287 of file misc_types.hh.

tcp3

Bitfield<3> gem5::ArmISA::tcp3

Definition at line 286 of file misc_types.hh.

tcp4

Bitfield<4> gem5::ArmISA::tcp4

Definition at line 285 of file misc_types.hh.

tcp5

Bitfield<5> gem5::ArmISA::tcp5

Definition at line 284 of file misc_types.hh.

tcp6

Bitfield<6> gem5::ArmISA::tcp6

Definition at line 283 of file misc_types.hh.

tcp7

Bitfield<7> gem5::ArmISA::tcp7

Definition at line 282 of file misc_types.hh.

tcp8

Bitfield<8> gem5::ArmISA::tcp8

Definition at line 280 of file misc_types.hh.

tcp9

Bitfield<9> gem5::ArmISA::tcp9

Definition at line 279 of file misc_types.hh.

tcr2En

Bitfield< 14 > gem5::ArmISA::tcr2En

Definition at line 391 of file misc_types.hh.

tcrEL1

Bitfield<32> gem5::ArmISA::tcrEL1

Definition at line 1037 of file misc_types.hh.

tcrx

Bitfield<3, 0> gem5::ArmISA::tcrx

Definition at line 208 of file misc_types.hh.

tda

Bitfield< 21 > gem5::ArmISA::tda

Definition at line 262 of file misc_types.hh.

tdcc

Bitfield<12> gem5::ArmISA::tdcc

Definition at line 917 of file misc_types.hh.

tde

Bitfield<8> gem5::ArmISA::tde

Definition at line 263 of file misc_types.hh.

tdosa

Bitfield<10> gem5::ArmISA::tdosa

Definition at line 261 of file misc_types.hh.

tdra

Bitfield<11> gem5::ArmISA::tdra

Definition at line 260 of file misc_types.hh.

tdz

Bitfield<28> gem5::ArmISA::tdz

Definition at line 336 of file misc_types.hh.

te

Bitfield<30> gem5::ArmISA::te

Definition at line 423 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::MMU::checkPermissions64(), gem5::ArmISA::TableWalker::doL1Descriptor(), gem5::ArmISA::TableWalker::doL2Descriptor(), gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::ArmISA::TLB::flush(), gem5::ArmISA::TLB::flushAll(), gem5::ArmISA::MMU::getResultTe(), gem5::ArmISA::MMU::getTE(), gem5::ArmISA::MMU::getTE(), gem5::ArmISA::TableWalker::insertPartialTableEntry(), gem5::ArmISA::TableWalker::insertTableEntry(), gem5::ArmISA::DTLBIALL::match(), gem5::ArmISA::DTLBIASID::match(), gem5::ArmISA::DTLBIMVA::match(), gem5::ArmISA::ITLBIALL::match(), gem5::ArmISA::ITLBIASID::match(), gem5::ArmISA::ITLBIMVA::match(), gem5::ArmISA::TLBIALL::match(), gem5::ArmISA::TLBIALLEL::match(), gem5::ArmISA::TLBIALLN::match(), gem5::ArmISA::TLBIASID::match(), gem5::ArmISA::TLBIMVA::match(), gem5::ArmISA::TLBIMVAA::match(), gem5::ArmISA::TLBIRMVA::match(), gem5::ArmISA::TLBIRMVAA::match(), gem5::ArmISA::TLBIVMALL::match(), gem5::ArmISA::TableWalker::memAttrs(), gem5::ArmISA::TableWalker::memAttrsAArch64(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::ArmISA::TableWalker::memAttrsWalkAArch64(), gem5::ArmISA::TLB::multiLookup(), gem5::ArmISA::TLB::printTlb(), gem5::ArmISA::MMU::s1PermBits64(), gem5::ArmISA::MMU::s2PermBits64(), gem5::ArmISA::MMU::testAndFinalize(), and gem5::ArmISA::MMU::translateMmuOn().

tea

Bitfield<37> gem5::ArmISA::tea

Definition at line 327 of file misc_types.hh.

teer

Bitfield<15> gem5::ArmISA::teer

Definition at line 401 of file misc_types.hh.

terr

Bitfield<36> gem5::ArmISA::terr

Definition at line 328 of file misc_types.hh.

tfp

Bitfield< 10 > gem5::ArmISA::tfp

Definition at line 278 of file misc_types.hh.

tg0

Bitfield< 15, 14 > gem5::ArmISA::tg0

Definition at line 583 of file misc_types.hh.

tg1

Bitfield< 31, 30 > gem5::ArmISA::tg1

Definition at line 590 of file misc_types.hh.

tge

Bitfield<27> gem5::ArmISA::tge

Definition at line 337 of file misc_types.hh.

tgran16

Bitfield<23, 20> gem5::ArmISA::tgran16

Definition at line 158 of file misc_types.hh.

tgran16_2

Bitfield<35, 32> gem5::ArmISA::tgran16_2

Definition at line 155 of file misc_types.hh.

tgran4

Bitfield<31, 28> gem5::ArmISA::tgran4

Definition at line 156 of file misc_types.hh.

tgran4_2

Bitfield<43, 40> gem5::ArmISA::tgran4_2

Definition at line 153 of file misc_types.hh.

tgran64

Bitfield<27, 24> gem5::ArmISA::tgran64

Definition at line 157 of file misc_types.hh.

tgran64_2

Bitfield<39, 36> gem5::ArmISA::tgran64_2

Definition at line 154 of file misc_types.hh.

thumb

Bitfield<36> gem5::ArmISA::thumb

Definition at line 79 of file types.hh.

Referenced by gem5::ArmISA::BrkPoint::testAddrMatch(), and gem5::ArmISA::BrkPoint::testAddrMissMatch().

ticab

Bitfield<50> gem5::ArmISA::ticab

Definition at line 316 of file misc_types.hh.

tid0

Bitfield<15> gem5::ArmISA::tid0

Definition at line 350 of file misc_types.hh.

tid1

Bitfield<16> gem5::ArmISA::tid1

Definition at line 349 of file misc_types.hh.

tid2

Bitfield<17> gem5::ArmISA::tid2

Definition at line 348 of file misc_types.hh.

tid3

Bitfield<18> gem5::ArmISA::tid3

Definition at line 347 of file misc_types.hh.

tid4

Bitfield<49> gem5::ArmISA::tid4

Definition at line 317 of file misc_types.hh.

tidcp

Bitfield<20> gem5::ArmISA::tidcp

Definition at line 345 of file misc_types.hh.

tidr

Bitfield<58> gem5::ArmISA::tidr

Definition at line 1114 of file misc_types.hh.

tlb

Bitfield<59, 56> gem5::ArmISA::tlb

Definition at line 119 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::checkWalkCache(), gem5::ArmISA::MMU::dflush(), gem5::X86ISA::TLB::evictLRU(), gem5::BaseMMU::flushAll(), gem5::ArmISA::MMU::flushStage1(), gem5::ArmISA::MMU::iflush(), gem5::BaseMMU::init(), gem5::AMDGPUVM::invalidateTLBs(), gem5::ArmISA::MMU::lookup(), gem5::ArmISA::TLB::multiLookup(), gem5::AMDGPUVM::registerTLB(), gem5::RiscvISA::TLB::remove(), gem5::ArmISA::MMU::translateFunctional(), and gem5::ArmISA::MMU::updateMiscReg().

tlbiaside1

Bitfield<44> gem5::ArmISA::tlbiaside1

Definition at line 969 of file misc_types.hh.

tlbiaside1is

Bitfield<30> gem5::ArmISA::tlbiaside1is

Definition at line 983 of file misc_types.hh.

tlbiaside1os

Bitfield<20> gem5::ArmISA::tlbiaside1os

Definition at line 993 of file misc_types.hh.

tlbirvaae1

Bitfield<39> gem5::ArmISA::tlbirvaae1

Definition at line 974 of file misc_types.hh.

tlbirvaae1is

Bitfield<35> gem5::ArmISA::tlbirvaae1is

Definition at line 978 of file misc_types.hh.

tlbirvaae1os

Bitfield<25> gem5::ArmISA::tlbirvaae1os

Definition at line 988 of file misc_types.hh.

tlbirvaale1

Bitfield<41> gem5::ArmISA::tlbirvaale1

Definition at line 972 of file misc_types.hh.

tlbirvaale1is

Bitfield<37> gem5::ArmISA::tlbirvaale1is

Definition at line 976 of file misc_types.hh.

tlbirvaale1os

Bitfield<27> gem5::ArmISA::tlbirvaale1os

Definition at line 986 of file misc_types.hh.

tlbirvae1

Bitfield<38> gem5::ArmISA::tlbirvae1

Definition at line 975 of file misc_types.hh.

tlbirvae1is

Bitfield<34> gem5::ArmISA::tlbirvae1is

Definition at line 979 of file misc_types.hh.

tlbirvae1os

Bitfield<24> gem5::ArmISA::tlbirvae1os

Definition at line 989 of file misc_types.hh.

tlbirvale1

Bitfield<40> gem5::ArmISA::tlbirvale1

Definition at line 973 of file misc_types.hh.

tlbirvale1is

Bitfield<36> gem5::ArmISA::tlbirvale1is

Definition at line 977 of file misc_types.hh.

tlbirvale1os

Bitfield<26> gem5::ArmISA::tlbirvale1os

Definition at line 987 of file misc_types.hh.

tlbivaae1

Bitfield<45> gem5::ArmISA::tlbivaae1

Definition at line 968 of file misc_types.hh.

tlbivaae1is

Bitfield<31> gem5::ArmISA::tlbivaae1is

Definition at line 982 of file misc_types.hh.

tlbivaae1os

Bitfield<21> gem5::ArmISA::tlbivaae1os

Definition at line 992 of file misc_types.hh.

tlbivaale1

Bitfield<47> gem5::ArmISA::tlbivaale1

Definition at line 966 of file misc_types.hh.

tlbivaale1is

Bitfield<33> gem5::ArmISA::tlbivaale1is

Definition at line 980 of file misc_types.hh.

tlbivaale1os

Bitfield<23> gem5::ArmISA::tlbivaale1os

Definition at line 990 of file misc_types.hh.

tlbivae1

Bitfield<43> gem5::ArmISA::tlbivae1

Definition at line 970 of file misc_types.hh.

tlbivae1is

Bitfield<29> gem5::ArmISA::tlbivae1is

Definition at line 984 of file misc_types.hh.

tlbivae1os

Bitfield<19> gem5::ArmISA::tlbivae1os

Definition at line 994 of file misc_types.hh.

tlbivale1

Bitfield<46> gem5::ArmISA::tlbivale1

Definition at line 967 of file misc_types.hh.

tlbivale1is

Bitfield<32> gem5::ArmISA::tlbivale1is

Definition at line 981 of file misc_types.hh.

tlbivale1os

Bitfield<22> gem5::ArmISA::tlbivale1os

Definition at line 991 of file misc_types.hh.

tlbivmalle1

Bitfield<42> gem5::ArmISA::tlbivmalle1

Definition at line 971 of file misc_types.hh.

tlbivmalle1is

Bitfield<28> gem5::ArmISA::tlbivmalle1is

Definition at line 985 of file misc_types.hh.

tlbivmalle1os

Bitfield<18> gem5::ArmISA::tlbivmalle1os

Definition at line 995 of file misc_types.hh.

tlor

Bitfield< 14 > gem5::ArmISA::tlor

Definition at line 329 of file misc_types.hh.

tme

Bitfield<27, 24> gem5::ArmISA::tme

Definition at line 127 of file misc_types.hh.

tocu

Bitfield<52> gem5::ArmISA::tocu

Definition at line 315 of file misc_types.hh.

top6

Bitfield<7, 2> gem5::ArmISA::top6

Definition at line 65 of file pcstate.hh.

topcode10_8

Bitfield<10, 8> gem5::ArmISA::topcode10_8

Definition at line 166 of file types.hh.

topcode10_9

Bitfield<10, 9> gem5::ArmISA::topcode10_9

Definition at line 165 of file types.hh.

topcode11_8

Bitfield<11, 8> gem5::ArmISA::topcode11_8

Definition at line 164 of file types.hh.

topcode11_9

Bitfield<11, 9> gem5::ArmISA::topcode11_9

Definition at line 163 of file types.hh.

topcode12_10

Bitfield<12, 10> gem5::ArmISA::topcode12_10

Definition at line 162 of file types.hh.

topcode12_11

Bitfield<12, 11> gem5::ArmISA::topcode12_11

Definition at line 161 of file types.hh.

topcode13_11

Bitfield<13, 11> gem5::ArmISA::topcode13_11

Definition at line 160 of file types.hh.

topcode15_13

Bitfield<15, 13> gem5::ArmISA::topcode15_13

Definition at line 159 of file types.hh.

topcode3_0

Bitfield<3, 0> gem5::ArmISA::topcode3_0

Definition at line 172 of file types.hh.

topcode7

Bitfield<7> gem5::ArmISA::topcode7

Definition at line 168 of file types.hh.

topcode7_4

Bitfield<7, 4> gem5::ArmISA::topcode7_4

Definition at line 171 of file types.hh.

topcode7_5

Bitfield<7, 5> gem5::ArmISA::topcode7_5

Definition at line 170 of file types.hh.

topcode7_6

Bitfield<7, 6> gem5::ArmISA::topcode7_6

Definition at line 169 of file types.hh.

topcode9_6

Bitfield<9, 6> gem5::ArmISA::topcode9_6

Definition at line 167 of file types.hh.

tpc

Bitfield<23> gem5::ArmISA::tpc

Definition at line 341 of file misc_types.hh.

tpidrEL0

Bitfield<35> gem5::ArmISA::tpidrEL0

Definition at line 1034 of file misc_types.hh.

tpidrEL1

Bitfield<33> gem5::ArmISA::tpidrEL1

Definition at line 1036 of file misc_types.hh.

tpidrroEL0

Bitfield<34> gem5::ArmISA::tpidrroEL0

Definition at line 1035 of file misc_types.hh.

tpm

Bitfield<6> gem5::ArmISA::tpm

Definition at line 265 of file misc_types.hh.

tpmcr

Bitfield<5> gem5::ArmISA::tpmcr

Definition at line 266 of file misc_types.hh.

tpu

Bitfield<24> gem5::ArmISA::tpu

Definition at line 340 of file misc_types.hh.

tr0

gem5::ArmISA::tr0

Definition at line 660 of file misc_types.hh.

tr1

Bitfield<3,2> gem5::ArmISA::tr1

Definition at line 661 of file misc_types.hh.

tr2

Bitfield<5,4> gem5::ArmISA::tr2

Definition at line 662 of file misc_types.hh.

tr3

Bitfield<7,6> gem5::ArmISA::tr3

Definition at line 663 of file misc_types.hh.

tr4

Bitfield<9,8> gem5::ArmISA::tr4

Definition at line 664 of file misc_types.hh.

tr5

Bitfield<11,10> gem5::ArmISA::tr5

Definition at line 665 of file misc_types.hh.

tr6

Bitfield<13,12> gem5::ArmISA::tr6

Definition at line 666 of file misc_types.hh.

tr7

Bitfield<15,14> gem5::ArmISA::tr7

Definition at line 667 of file misc_types.hh.

tracefilt

gem5::ArmISA::tracefilt

Definition at line 106 of file misc_types.hh.

tracever

Bitfield<7, 4> gem5::ArmISA::tracever

Definition at line 113 of file misc_types.hh.

trapLower

Bitfield<62> gem5::ArmISA::trapLower

Definition at line 1122 of file misc_types.hh.

trapMpam0EL1

Bitfield<49> gem5::ArmISA::trapMpam0EL1

Definition at line 1116 of file misc_types.hh.

trapMpam1EL1

Bitfield<48> gem5::ArmISA::trapMpam1EL1

Definition at line 1117 of file misc_types.hh.

tre

Bitfield<28> gem5::ArmISA::tre

Definition at line 425 of file misc_types.hh.

trndr

Bitfield<40> gem5::ArmISA::trndr

Definition at line 392 of file misc_types.hh.

trvm

Bitfield<30> gem5::ArmISA::trvm

Definition at line 334 of file misc_types.hh.

ts

Bitfield<55, 52> gem5::ArmISA::ts

Definition at line 120 of file misc_types.hh.

Referenced by gem5::PosixKvmTimer::arm(), gem5::PosixKvmTimer::calcResolution(), gem5::PosixKvmTimer::disarm(), gem5::floorLog2(), gem5::Time::operator=(), gem5::sleep(), gem5::Time::Time(), and gem5::GPUCommandProcessor::updateHsaEventTs().

tsc

Bitfield<19> gem5::ArmISA::tsc

Definition at line 346 of file misc_types.hh.

tsm

Bitfield<12> gem5::ArmISA::tsm

Definition at line 822 of file misc_types.hh.

tsw

Bitfield<22> gem5::ArmISA::tsw

Definition at line 342 of file misc_types.hh.

tta

Bitfield< 20 > gem5::ArmISA::tta

Definition at line 272 of file misc_types.hh.

tta_e2h

Bitfield<28> gem5::ArmISA::tta_e2h

Definition at line 814 of file misc_types.hh.

ttbr0EL1

Bitfield<36> gem5::ArmISA::ttbr0EL1

Definition at line 1033 of file misc_types.hh.

ttbr1EL1

Bitfield<37> gem5::ArmISA::ttbr1EL1

Definition at line 1032 of file misc_types.hh.

ttee

Bitfield<16> gem5::ArmISA::ttee

Definition at line 294 of file misc_types.hh.

ttl

Bitfield<51, 48> gem5::ArmISA::ttl

Definition at line 182 of file misc_types.hh.

ttlb

Bitfield<25> gem5::ArmISA::ttlb

Definition at line 339 of file misc_types.hh.

ttlbis

Bitfield<54> gem5::ArmISA::ttlbis

Definition at line 314 of file misc_types.hh.

tvm

Bitfield<26> gem5::ArmISA::tvm

Definition at line 338 of file misc_types.hh.

twe

Bitfield< 13 > gem5::ArmISA::twe

Definition at line 351 of file misc_types.hh.

twi

Bitfield< 12 > gem5::ArmISA::twi

Definition at line 352 of file misc_types.hh.

txfull

Bitfield<29> gem5::ArmISA::txfull

Definition at line 901 of file misc_types.hh.

txu

Bitfield<26> gem5::ArmISA::txu

Definition at line 904 of file misc_types.hh.

tz

Bitfield< 8 > gem5::ArmISA::tz

Definition at line 281 of file misc_types.hh.

Referenced by gem5::mkutctime().

u

Bitfield<22> gem5::ArmISA::u

Definition at line 438 of file misc_types.hh.

Referenced by gem5::bitsToFloat32(), gem5::bitsToFloat64(), gem5::floatToBits32(), gem5::floatToBits64(), fp16_cvtf(), fp32_cvtf(), fp64_cvtf(), fplibFixedToFP(), fplibFPToFixed(), fplibFPToFixed(), fplibFPToFixed(), FPToFixed_16(), FPToFixed_32(), FPToFixed_64(), gem5::branch_prediction::MPP_TAGE::handleUReset(), gem5::branch_prediction::TAGE_SC_L_TAGE::handleUReset(), gem5::branch_prediction::TAGEBase::handleUReset(), gem5::ArmISA::MiscRegLUTEntryInitializer::mapsTo(), gem5::SparcISA::SparcStaticInst::passesFpCondition(), gem5::branch_prediction::MPP_TAGE::resetUctr(), gem5::branch_prediction::TAGE_SC_L_TAGE_8KB::resetUctr(), gem5::branch_prediction::TAGEBase::resetUctr(), and BitUnionData::templatedFunction().

uao

Bitfield< 7, 4 > gem5::ArmISA::uao

Definition at line 58 of file misc_types.hh.

Referenced by gem5::ArmISA::ISA::setMiscReg().

uci

Bitfield<26> gem5::ArmISA::uci

Definition at line 428 of file misc_types.hh.

uct

Bitfield<15> gem5::ArmISA::uct

Definition at line 452 of file misc_types.hh.

udccdis

Bitfield<12> gem5::ArmISA::udccdis

Definition at line 916 of file misc_types.hh.

ufc

Bitfield<3> gem5::ArmISA::ufc

Definition at line 520 of file misc_types.hh.

ufe

Bitfield<11> gem5::ArmISA::ufe

Definition at line 526 of file misc_types.hh.

uh0

Bitfield<15, 0> gem5::ArmISA::uh0

Definition at line 60 of file int.hh.

uh1

gem5::ArmISA::uh1

Definition at line 59 of file int.hh.

uma

Bitfield<9> gem5::ArmISA::uma

Definition at line 464 of file misc_types.hh.

unflattenResultMiscReg

int gem5::ArmISA::unflattenResultMiscReg[NUM_MISCREGS]

If the reg is a child reg of a banked set, then the parent is the last banked one in the list.

This is messy, and the wish is to eventually have the bitmap replaced with a better data structure. the preUnflatten function initializes a lookup table to speed up the search for these banked registers.

Definition at line 705 of file misc.cc.

Referenced by preUnflattenMiscReg(), and unflattenMiscReg().

up

Bitfield<23> gem5::ArmISA::up

Definition at line 124 of file types.hh.

Referenced by gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::branch_prediction::LoopPredictor::signedCtrUpdate(), gem5::branch_prediction::LoopPredictor::unsignedCtrUpdate(), and gem5::branch_prediction::TAGEBase::unsignedCtrUpdate().

useImm

Bitfield<25> gem5::ArmISA::useImm

Definition at line 91 of file types.hh.

uw

Bitfield<31, 0> gem5::ArmISA::uw

Definition at line 63 of file int.hh.

Referenced by gem5::ArmISA::MMU::s1PermBits64().

uwxn

Bitfield<20> gem5::ArmISA::uwxn

Definition at line 441 of file misc_types.hh.

v

Bitfield< 28 > gem5::ArmISA::v

Definition at line 54 of file misc_types.hh.

Referenced by gem5::ruby::garnet::RoutingUnit::addRoute(), gem5::trace::TarmacParserRecord::advanceTrace(), gem5::ArmISA::MiscRegLUTEntryInitializer::allPrivileges(), gem5::IniFile::Entry::appendValue(), gem5::ArmISA::MiscRegLUTEntryInitializer::banked(), gem5::ArmISA::MiscRegLUTEntryInitializer::banked64(), gem5::ArmISA::MiscRegLUTEntryInitializer::bankedChild(), gem5::o3::LSQ::cacheBlocked(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::ruby::Topology::createLinks(), gem5::ruby::Topology::extend_shortest_path(), gem5::VecPredRegContainer< NumBits, Packed >::getBits(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::stl_helpers::hash_impl::hash_value(), gem5::htop9(), gem5::htop9(), gem5::ArmISA::MiscRegLUTEntryInitializer::hyp(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::hypWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::implemented(), gem5::branch_prediction::MultiperspectivePerceptron::insert(), gem5::ArmISA::BrkPoint::isEnabled(), gem5::ArmISA::WatchPoint::isEnabled(), gem5::ruby::Topology::makeLink(), gem5::PortProxy::memsetBlob(), gem5::ArmISA::MiscRegLUTEntryInitializer::mon(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::monSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::monWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::mutex(), gem5::ArmISA::MiscRegLUTEntryInitializer::nonSecure(), gem5::statistics::ScalarBase< Derived, Stor >::operator+=(), gem5::statistics::ScalarProxy< Stat >::operator+=(), gem5::statistics::ScalarBase< Derived, Stor >::operator-=(), gem5::statistics::ScalarProxy< Stat >::operator-=(), gem5::statistics::Formula::operator=(), gem5::statistics::ScalarBase< Derived, Stor >::operator=(), gem5::statistics::ScalarProxy< Stat >::operator=(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractSecDisp(), gem5::p9toh(), gem5::p9toh(), gem5::MathExpr::parse(), gem5::ArmISA::MiscRegLUTEntryInitializer::priv(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::privRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecure(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::privSecureWrite(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::ArmISA::MiscRegLUTEntryInitializer::reads(), gem5::DistIface::RecvScheduler::resumeRecvTicks(), gem5::statistics::DistBase< Derived, Stor >::sample(), gem5::statistics::DistProxy< Stat >::sample(), gem5::statistics::SparseHistBase< Derived, Stor >::sample(), gem5::ArmISA::MiscRegLUTEntryInitializer::secure(), gem5::Packet::set(), gem5::Packet::setBE(), gem5::Packet::setLE(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::Packet::setRaw(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::IniFile::Entry::setValue(), gem5::OperandInfo::setVirtToPhysMapping(), gem5::swap_byte(), gem5::swap_byte(), gem5::o3::LSQ::LSQRequest::taskId(), TEST(), gem5::ArmISA::BrkPoint::test(), gem5::ArmISA::WatchPoint::test(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::ArmISA::BrkPoint::testContextMatch(), testPredicate(), RegisterBankTest::TestReg::TestReg(), gem5::ArmISA::BrkPoint::testVMIDMatch(), gem5::tokenize(), gem5::TranslatingPortProxy::tryMemsetBlob(), gem5::ArmISA::MiscRegLUTEntryInitializer::unserialize(), gem5::ArmISA::MiscRegLUTEntryInitializer::unverifiable(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::ArmISA::MiscRegLUTEntryInitializer::user(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userNonSecureWrite(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureRead(), gem5::ArmISA::MiscRegLUTEntryInitializer::userSecureWrite(), gem5::SDMAEngine::SDMAQueue::valid(), gem5::ArmISA::MiscRegLUTEntryInitializer::warnNotFail(), gem5::ArmISA::MiscRegLUTEntryInitializer::writes(), and gem5::ArmISA::ISA::zeroSveVecRegUpperPart().

va

Bitfield<8> gem5::ArmISA::va

Definition at line 356 of file misc_types.hh.

Referenced by gem5::ArmISA::RemoteGDB::acc(), gem5::SparcISA::TLB::demapPage(), gem5::VegaISA::GpuTLB::demapPage(), gem5::X86ISA::GpuTLB::demapPage(), gem5::X86ISA::TLB::demapPage(), gem5::SparcISA::TLB::doMmuRegRead(), gem5::SparcISA::TLB::doMmuRegWrite(), gem5::ArmISA::AbortFault< T >::getFaultVAddr(), getFaultVAddr(), gem5::RiscvISA::getFaultVAddr(), gem5::ArmISA::V7LPageTableOps::index(), gem5::ArmISA::V8PageTableOps16k::index(), gem5::ArmISA::V8PageTableOps4k::index(), gem5::ArmISA::V8PageTableOps64k::index(), gem5::SparcISA::TLB::insert(), gem5::ARMArchTLB::invalidateVA(), gem5::SMMUTLB::invalidateVA(), gem5::WalkCache::invalidateVA(), gem5::ARMArchTLB::invalidateVAA(), gem5::SMMUTLB::invalidateVAA(), gem5::WalkCache::invalidateVAA(), gem5::ARMArchTLB::lookup(), gem5::ArmISA::MMU::lookup(), gem5::SMMUTLB::lookup(), gem5::SparcISA::TLB::lookup(), gem5::VegaISA::GpuTLB::lookup(), gem5::WalkCache::lookup(), gem5::X86ISA::GpuTLB::lookup(), gem5::X86ISA::TLB::lookup(), gem5::VegaISA::GpuTLB::lookupIt(), gem5::X86ISA::GpuTLB::lookupIt(), gem5::ArmISA::TableWalker::LongDescriptor::nextDescAddr(), gem5::ArmISA::TlbEntry::pAddr(), gem5::ArmISA::TableWalker::L1Descriptor::paddr(), gem5::ArmISA::TableWalker::L2Descriptor::paddr(), gem5::ARMArchTLB::pickSetIdx(), gem5::IPACache::pickSetIdx(), gem5::SMMUTLB::pickSetIdx(), gem5::WalkCache::pickSetIdx(), gem5::ArmISA::MMU::translateFunctional(), gem5::SparcISA::TLB::validVirtualAddress(), gem5::SMMUTranslationProcess::walkCacheUpdate(), and gem5::SparcISA::TLB::writeTagAccess().

varange

Bitfield<19, 16> gem5::ArmISA::varange

Definition at line 189 of file misc_types.hh.

vbarEL1

Bitfield<38> gem5::ArmISA::vbarEL1

Definition at line 1031 of file misc_types.hh.

vcma

gem5::ArmISA::vcma

Definition at line 85 of file misc_types.hh.

vecElemClass

RegClass gem5::ArmISA::vecElemClass

inlineconstexpr

Initial value:

=
    RegClass(VecElemClass, VecElemClassName, NumVecRegs * NumVecElemPerVecReg,
            debug::VecRegs).
        ops(vecRegElemClassOps)

Definition at line 105 of file vec.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::get(), gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::X86ISA::ISA::ISA(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point_v< Float > > >::store(), syncVecElemsToRegs(), and syncVecRegsToElems().

vecPredRegClass

RegClass gem5::ArmISA::vecPredRegClass

inlineconstexpr

Initial value:

=
    RegClass(VecPredRegClass, VecPredRegClassName, NumVecPredRegs,
            debug::VecPredRegs).
        ops(vecPredRegClassOps).
        regType<VecPredRegContainer>()

Definition at line 109 of file vec.hh.

Referenced by gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::X86ISA::ISA::ISA(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::Iris::ThreadContext::readVecPredRegFlat(), gem5::ArmISA::HTMCheckpoint::restore(), and gem5::ArmISA::HTMCheckpoint::save().

vecPredRegClassOps

TypedRegClassOps<ArmISA::VecPredRegContainer> gem5::ArmISA::vecPredRegClassOps

inlinestatic

Definition at line 99 of file vec.hh.

VecPredRegSizeBits

unsigned gem5::ArmISA::VecPredRegSizeBits = MaxSveVecLenInBytes

constexpr

Definition at line 500 of file types.hh.

VECREG_UREG0

const int gem5::ArmISA::VECREG_UREG0 = 32

Definition at line 92 of file vec.hh.

Referenced by gem5::ArmISA::SveIndexedMemSV< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemSV(), and gem5::ArmISA::SveIndexedMemVI< RegElemType, MemElemType, MicroopType, FirstFaultWritebackMicroopType >::SveIndexedMemVI().

vecRegClass

RegClass gem5::ArmISA::vecRegClass

inlineconstexpr

Initial value:

=
    RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
        ops(vecRegClassOps).
        regType<VecRegContainer>()

Definition at line 101 of file vec.hh.

Referenced by gem5::ArmISA::ISA::copyRegsFrom(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::guest_abi::Argument< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > >::get(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::X86ISA::ISA::ISA(), gem5::trace::TarmacParserRecord::TarmacParserRecordEvent::process(), gem5::Iris::ThreadContext::readVecRegFlat(), gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::guest_abi::Result< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > >::store(), syncVecElemsToRegs(), syncVecRegsToElems(), gem5::trace::ArmNativeTrace::ThreadState::update(), gem5::ArmV8KvmCPU::updateKvmState(), and gem5::ArmV8KvmCPU::updateThreadContext().

vecRegClassOps

TypedRegClassOps<ArmISA::VecRegContainer> gem5::ArmISA::vecRegClassOps

inlinestatic

Definition at line 98 of file vec.hh.

vecRegElemClassOps

VecElemRegClassOps< RegVal > gem5::ArmISA::vecRegElemClassOps(NumVecElemPerVecReg) ( NumVecElemPerVecReg )

inlinestatic

VecRegSizeBytes

unsigned gem5::ArmISA::VecRegSizeBytes = MaxSveVecLenInBytes

constexpr

Definition at line 499 of file types.hh.

VecSpecialElem

const int gem5::ArmISA::VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg

Definition at line 87 of file vec.hh.

Referenced by gem5::ArmISA::VldMultOp::VldMultOp(), gem5::ArmISA::VldSingleOp::VldSingleOp(), gem5::ArmISA::VstMultOp::VstMultOp(), and gem5::ArmISA::VstSingleOp::VstSingleOp().

vectorcatch

Bitfield<15,12> gem5::ArmISA::vectorcatch

Definition at line 955 of file misc_types.hh.

vf

Bitfield<6> gem5::ArmISA::vf

Definition at line 359 of file misc_types.hh.

vfpExceptionTrapping

Bitfield<15, 12> gem5::ArmISA::vfpExceptionTrapping

Definition at line 553 of file misc_types.hh.

vfpHalfPrecision

Bitfield<27, 24> gem5::ArmISA::vfpHalfPrecision

Definition at line 567 of file misc_types.hh.

vh

Bitfield<11, 8> gem5::ArmISA::vh

Definition at line 173 of file misc_types.hh.

vi

Bitfield<7> gem5::ArmISA::vi

Definition at line 358 of file misc_types.hh.

virtextns

Bitfield<19,16> gem5::ArmISA::virtextns

Definition at line 954 of file misc_types.hh.

vm

Bitfield<0> gem5::ArmISA::vm

Definition at line 365 of file misc_types.hh.

Referenced by gem5::MuxingKvmGic< Types >::drainResume(), gem5::MuxingKvmGic< Types >::MuxingKvmGic(), gem5::ArchTimerKvm::scheduleEvents(), gem5::System::setKvmVM(), gem5::MuxingKvmGic< Types >::startup(), gem5::AMDGPUVM::GARTTranslationGen::translate(), gem5::AMDGPUVM::MMHUBTranslationGen::translate(), gem5::AMDGPUVM::UserTranslationGen::translate(), gem5::ArmISA::MMU::translateFs(), and gem5::ArmISA::MMU::CachedState::updateMiscReg().

vmidbits

Bitfield<7, 4> gem5::ArmISA::vmidbits

Definition at line 174 of file misc_types.hh.

vncr

Bitfield< 13 > gem5::ArmISA::vncr

Definition at line 777 of file misc_types.hh.

vpmrMax

Bitfield<20,18> gem5::ArmISA::vpmrMax

Definition at line 1098 of file misc_types.hh.

vs

Bitfield<19> gem5::ArmISA::vs

Definition at line 654 of file misc_types.hh.

Referenced by gem5::ArmISA::BrkPoint::getVMIDfromReg(), and gem5::ArmISA::BrkPoint::testVMIDMatch().

vse

Bitfield<8> gem5::ArmISA::vse

Definition at line 357 of file misc_types.hh.

width

Bitfield< 4 > gem5::ArmISA::width

Definition at line 72 of file misc_types.hh.

Referenced by gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::findCarry(), gem5::findNegative(), gem5::findOverflow(), gem5::findParity(), gem5::findZero(), gem5::Trie< Key, Value >::insert(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::nb_transport_fw(), gem5::linux::printk(), gem5::ArmISA::ArmStaticInst::satInt(), gem5::ArmISA::ArmStaticInst::saturateOp(), gem5::VncInput::setDirty(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ArmISA::ArmStaticInst::uSatInt(), gem5::ArmISA::ArmStaticInst::uSaturateOp(), vfpFpToFixed(), vfpSFixedToFpD(), vfpSFixedToFpS(), vfpUFixedToFpD(), vfpUFixedToFpS(), and gem5::PngWriter::write().

wnr

Bitfield< 6 > gem5::ArmISA::wnr

Definition at line 511 of file misc_types.hh.

wpaddrmask

Bitfield<7,4> gem5::ArmISA::wpaddrmask

Definition at line 957 of file misc_types.hh.

writeback

Bitfield<21> gem5::ArmISA::writeback

Definition at line 126 of file types.hh.

Referenced by gem5::o3::LSQUnit::completeDataAccess(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ArmISA::PairMemOp::PairMemOp(), gem5::IGbE::TxDescCache::pktComplete(), gem5::IGbE::DescCache< T >::wbComplete(), and gem5::memory::CfiMemory::write().

wrps

Bitfield<23, 20> gem5::ArmISA::wrps

Definition at line 110 of file misc_types.hh.

wt

Bitfield<20> gem5::ArmISA::wt

Definition at line 888 of file misc_types.hh.

wxn

Bitfield<19> gem5::ArmISA::wxn

Definition at line 445 of file misc_types.hh.

Referenced by gem5::ArmISA::MMU::s1PermBits64().

xnx

Bitfield<31, 28> gem5::ArmISA::xnx

Definition at line 168 of file misc_types.hh.

xp

Bitfield<23> gem5::ArmISA::xp

Definition at line 436 of file misc_types.hh.

z

Bitfield< 30 > gem5::ArmISA::z

Definition at line 460 of file misc_types.hh.

Referenced by gem5::ArmISA::HTMCheckpoint::restore(), gem5::ArmISA::HTMCheckpoint::save(), testPredicate(), gem5::branch_prediction::MultiperspectivePerceptron::update(), gem5::branch_prediction::MultiperspectivePerceptronTAGE::updateHistories(), and gem5::ArmISA::TableWalker::walkAddresses().

za

Bitfield<1, 1> gem5::ArmISA::za

Definition at line 845 of file misc_types.hh.

zen

Bitfield< 17, 16 > gem5::ArmISA::zen

Definition at line 491 of file misc_types.hh.