gem5  v21.1.0.2
Classes | Typedefs | Enumerations | Functions | Variables
gem5::ArmISA Namespace Reference

Classes

class  AbortFault
 
class  ArmFault
 
class  ArmFaultVals
 
class  ArmSev
 
class  ArmStaticInst
 
class  BaseISADevice
 Base class for devices that use the MiscReg interfaces. More...
 
class  BigFpMemImmOp
 
class  BigFpMemLitOp
 
class  BigFpMemPostOp
 
class  BigFpMemPreOp
 
class  BigFpMemRegOp
 
class  BranchEret64
 
class  BranchEretA64
 
class  BranchImm
 
class  BranchImm64
 
class  BranchImmCond
 
class  BranchImmCond64
 
class  BranchImmImmReg64
 
class  BranchImmReg
 
class  BranchImmReg64
 
class  BranchReg
 
class  BranchReg64
 
class  BranchRegCond
 
class  BranchRegReg
 
class  BranchRegReg64
 
class  BranchRet64
 
class  BranchRetA64
 
class  BrkPoint
 
class  Crypto
 
class  DataAbort
 
class  DataImmOp
 
class  DataRegOp
 
class  DataRegRegOp
 
class  DataX1Reg2ImmOp
 
class  DataX1RegImmOp
 
class  DataX1RegOp
 
class  DataX2RegImmOp
 
class  DataX2RegOp
 
class  DataX3RegOp
 
class  DataXCondCompImmOp
 
class  DataXCondCompRegOp
 
class  DataXCondSelOp
 
class  DataXERegOp
 
class  DataXImmOnlyOp
 
class  DataXImmOp
 
class  DataXSRegOp
 
class  Decoder
 
class  DTLBIALL
 Data TLB Invalidate All. More...
 
class  DTLBIASID
 Data TLB Invalidate by ASID match. More...
 
class  DTLBIMVA
 Data TLB Invalidate by VA. More...
 
class  DummyISADevice
 Dummy device that prints a warning when it is accessed. More...
 
class  DumpStats
 
class  DumpStats64
 
class  EmuFreebsd
 
class  EmuLinux
 
class  FastInterrupt
 
class  FpCondCompRegOp
 
class  FpCondSelOp
 
class  FpOp
 
class  FpRegImmOp
 
class  FpRegRegImmOp
 
class  FpRegRegOp
 
class  FpRegRegRegCondOp
 
class  FpRegRegRegImmOp
 
class  FpRegRegRegOp
 
class  FpRegRegRegRegOp
 
class  FsFreebsd
 
class  FsLinux
 
class  FsWorkload
 
class  HardwareBreakpoint
 
class  HTMCheckpoint
 
class  HypervisorCall
 
class  HypervisorTrap
 
class  IllegalInstSetStateFault
 Illegal Instruction Set State fault (AArch64 only) More...
 
class  Interrupt
 
class  Interrupts
 
class  ISA
 
class  ITLBIALL
 Instruction TLB Invalidate All. More...
 
class  ITLBIASID
 Instruction TLB Invalidate by ASID match. More...
 
class  ITLBIMVA
 Instruction TLB Invalidate by VA. More...
 
class  MacroMemOp
 Base class for microcoded integer memory instructions. More...
 
class  MacroVFPMemOp
 Base class for microcoded floating point memory instructions. More...
 
class  Memory
 
class  Memory64
 
class  MemoryAtomicPair64
 
class  MemoryDImm
 
class  MemoryDImm64
 
class  MemoryDImmEx64
 
class  MemoryDReg
 
class  MemoryEx64
 
class  MemoryExDImm
 
class  MemoryExImm
 
class  MemoryImm
 
class  MemoryImm64
 
class  MemoryLiteral64
 
class  MemoryOffset
 
class  MemoryPostIndex
 
class  MemoryPostIndex64
 
class  MemoryPreIndex
 
class  MemoryPreIndex64
 
class  MemoryRaw64
 
class  MemoryReg
 
class  MemoryReg64
 
class  MicroIntImmOp
 Microops of the form IntRegA = IntRegB op Imm. More...
 
class  MicroIntImmXOp
 
class  MicroIntMov
 Microops of the form IntRegA = IntRegB. More...
 
class  MicroIntOp
 Microops of the form IntRegA = IntRegB op IntRegC. More...
 
class  MicroIntRegOp
 Microops of the form IntRegA = IntRegB op shifted IntRegC. More...
 
class  MicroIntRegXOp
 
class  MicroMemOp
 Memory microops which use IntReg + Imm addressing. More...
 
class  MicroMemPairOp
 
class  MicroNeonMemOp
 Microops for Neon loads/stores. More...
 
class  MicroNeonMixLaneOp
 
class  MicroNeonMixLaneOp64
 
class  MicroNeonMixOp
 Microops for Neon load/store (de)interleaving. More...
 
class  MicroNeonMixOp64
 Microops for AArch64 NEON load/store (de)interleaving. More...
 
class  MicroOp
 Base class for Memory microops. More...
 
class  MicroOpX
 
class  MicroSetPCCPSR
 Microops of the form PC = IntRegA CPSR = IntRegB. More...
 
class  MightBeMicro
 
class  MightBeMicro64
 
class  MMU
 
class  Mult3
 Base class for multipy instructions using three registers. More...
 
class  Mult4
 Base class for multipy instructions using four registers. More...
 
class  PairMemOp
 Base class for pair load/store instructions. More...
 
class  PCAlignmentFault
 PC alignment fault (AArch64 only) More...
 
class  PMU
 Model of an ARM PMU version 3. More...
 
class  PredImmOp
 Base class for predicated immediate operations. More...
 
class  PredIntOp
 Base class for predicated integer operations. More...
 
class  PredMacroOp
 Base class for predicated macro-operations. More...
 
class  PredMicroop
 Base class for predicated micro-operations. More...
 
class  PredOp
 Base class for predicated integer operations. More...
 
class  PrefetchAbort
 
struct  PTE
 
struct  RegABI32
 
struct  RegABI64
 
class  RemoteGDB
 
class  Reset
 
class  RfeOp
 
class  SecureMonitorCall
 
class  SecureMonitorTrap
 
class  SelfDebug
 
class  SEWorkload
 
class  SkipFunc
 
class  SkipFuncLinux32
 
class  SkipFuncLinux64
 
class  SoftwareBreakpoint
 System error (AArch64 only) More...
 
class  SoftwareStep
 
class  SoftwareStepFault
 
class  SPAlignmentFault
 Stack pointer alignment fault (AArch64 only) More...
 
class  SrsOp
 
class  StackTrace
 
class  Stage2LookUp
 
class  SupervisorCall
 
class  SupervisorTrap
 
class  SveAdrOp
 ADR. More...
 
class  SveBinConstrPredOp
 Binary, constructive, predicated SVE instruction. More...
 
class  SveBinDestrPredOp
 Binary, destructive, predicated (merging) SVE instruction. More...
 
class  SveBinIdxUnpredOp
 Binary, unpredicated SVE instruction. More...
 
class  SveBinImmIdxUnpredOp
 Binary with immediate index, destructive, unpredicated SVE instruction. More...
 
class  SveBinImmPredOp
 Binary with immediate, destructive, predicated (merging) SVE instruction. More...
 
class  SveBinImmUnpredConstrOp
 Binary with immediate, destructive, unpredicated SVE instruction. More...
 
class  SveBinImmUnpredDestrOp
 SVE vector - immediate binary operation. More...
 
class  SveBinUnpredOp
 Binary, unpredicated SVE instruction with indexed operand. More...
 
class  SveBinWideImmUnpredOp
 Binary with wide immediate, destructive, unpredicated SVE instruction. More...
 
class  SveCmpImmOp
 SVE compare-with-immediate instructions, predicated (zeroing). More...
 
class  SveCmpOp
 SVE compare instructions, predicated (zeroing). More...
 
class  SveComplexIdxOp
 SVE Complex Instructions (indexed) More...
 
class  SveComplexOp
 SVE Complex Instructions (vectors) More...
 
class  SveCompTermOp
 Compare and terminate loop SVE instruction. More...
 
class  SveContigMemSI
 
class  SveContigMemSS
 
class  SveDotProdIdxOp
 SVE dot product instruction (indexed) More...
 
class  SveDotProdOp
 SVE dot product instruction (vectors) More...
 
class  SveElemCountOp
 Element count SVE instruction. More...
 
class  SveIndexedMemSV
 
class  SveIndexedMemVI
 
class  SveIndexIIOp
 Index generation instruction, immediate operands. More...
 
class  SveIndexIROp
 
class  SveIndexRIOp
 
class  SveIndexRROp
 
class  SveIntCmpImmOp
 Integer compare with immediate SVE instruction. More...
 
class  SveIntCmpOp
 Integer compare SVE instruction. More...
 
class  SveLdStructSI
 
class  SveLdStructSS
 
class  SveMemPredFillSpill
 
class  SveMemVecFillSpill
 
class  SveOrdReducOp
 SVE ordered reductions. More...
 
class  SvePartBrkOp
 Partition break SVE instruction. More...
 
class  SvePartBrkPropOp
 Partition break with propagation SVE instruction. More...
 
class  SvePredBinPermOp
 Predicate binary permute instruction. More...
 
class  SvePredCountOp
 
class  SvePredCountPredOp
 
class  SvePredLogicalOp
 Predicate logical instruction. More...
 
class  SvePredTestOp
 SVE predicate test. More...
 
class  SvePredUnaryWImplicitDstOp
 SVE unary predicate instructions with implicit destination operand. More...
 
class  SvePredUnaryWImplicitSrcOp
 SVE unary predicate instructions with implicit source operand. More...
 
class  SvePredUnaryWImplicitSrcPredOp
 SVE unary predicate instructions, predicated, with implicit source operand. More...
 
class  SvePtrueOp
 PTRUE, PTRUES. More...
 
class  SveReducOp
 SVE reductions. More...
 
class  SveSelectOp
 Scalar element select SVE instruction. More...
 
class  SveStStructSI
 
class  SveStStructSS
 
class  SveTblOp
 SVE table lookup/permute using vector of element indices (TBL) More...
 
class  SveTerImmUnpredOp
 Ternary with immediate, destructive, unpredicated SVE instruction. More...
 
class  SveTerPredOp
 Ternary, destructive, predicated (merging) SVE instruction. More...
 
class  SveUnaryPredOp
 Unary, constructive, predicated (merging) SVE instruction. More...
 
class  SveUnaryPredPredOp
 SVE unary operation on predicate (predicated) More...
 
class  SveUnarySca2VecUnpredOp
 Unary unpredicated scalar to vector instruction. More...
 
class  SveUnaryUnpredOp
 Unary, constructive, unpredicated SVE instruction. More...
 
class  SveUnaryWideImmPredOp
 Unary with wide immediate, constructive, predicated SVE instruction. More...
 
class  SveUnaryWideImmUnpredOp
 Unary with wide immediate, constructive, unpredicated SVE instruction. More...
 
class  SveUnpackOp
 SVE unpack and widen predicate. More...
 
class  SveWhileOp
 While predicate generation SVE instruction. More...
 
class  SveWImplicitSrcDstOp
 SVE unary predicate instructions with implicit destination operand. More...
 
class  SyscallTable32
 
class  SyscallTable64
 
class  SysDC64
 
class  SystemError
 System error (AArch64 only) More...
 
class  TableWalker
 
class  TLB
 
struct  TlbEntry
 
class  TLBIALL
 TLB Invalidate All. More...
 
class  TLBIALLEL
 Implementaton of AArch64 TLBI ALLE(1,2,3)(IS) instructions. More...
 
class  TLBIALLN
 TLB Invalidate All, Non-Secure. More...
 
class  TLBIASID
 TLB Invalidate by ASID match. More...
 
class  TLBIIPA
 TLB Invalidate by Intermediate Physical Address. More...
 
class  TLBIMVA
 TLB Invalidate by VA. More...
 
class  TLBIMVAA
 TLB Invalidate by VA, All ASID. More...
 
class  TLBIOp
 
class  TLBIVMALL
 Implementaton of AArch64 TLBI VMALLE1(IS)/VMALLS112E1(IS) instructions. More...
 
class  TlbTestInterface
 
class  UndefinedInstruction
 
class  VectorCatch
 
class  VfpMacroOp
 
class  VirtualDataAbort
 
class  VirtualFastInterrupt
 
class  VirtualInterrupt
 
class  VldMultOp
 Base classes for microcoded integer memory instructions. More...
 
class  VldMultOp64
 Base classes for microcoded AArch64 NEON memory instructions. More...
 
class  VldSingleOp
 
class  VldSingleOp64
 
struct  VReg
 128-bit NEON vector register. More...
 
class  VstMultOp
 Base class for microcoded integer memory instructions. More...
 
class  VstMultOp64
 
class  VstSingleOp
 
class  VstSingleOp64
 
class  Watchpoint
 
class  WatchPoint
 

Typedefs

typedef Addr FaultOffset
 
typedef uint64_t XReg
 
typedef int VfpSavedState
 
typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS]
 
using VecElem = uint32_t
 
using VecRegContainer = gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)>
 
using VecPredReg = gem5::VecPredRegT< VecElem, NumVecElemPerVecReg, false, false >
 
using ConstVecPredReg = gem5::VecPredRegT< VecElem, NumVecElemPerVecReg, false, true >
 
using VecPredRegContainer = VecPredReg::Container
 
typedef uint32_t MachInst
 
typedef uint16_t vmid_t
 
typedef int RegContextParam
 
typedef int RegContextVal
 

Enumerations

enum  FPRounding {
  FPRounding_TIEEVEN = 0, FPRounding_POSINF = 1, FPRounding_NEGINF = 2, FPRounding_ZERO = 3,
  FPRounding_TIEAWAY = 4, FPRounding_ODD = 5
}
 
enum  FpDataType { FpDataType::Fp16, FpDataType::Fp32, FpDataType::Fp64 }
 Floating point data types. More...
 
enum  SvePredType { SvePredType::NONE, SvePredType::MERGE, SvePredType::ZERO, SvePredType::SELECT }
 
enum  VfpMicroMode { VfpNotAMicroop, VfpMicroop, VfpFirstMicroop, VfpLastMicroop }
 
enum  FeExceptionBit {
  FeDivByZero = FE_DIVBYZERO, FeInexact = FE_INEXACT, FeInvalid = FE_INVALID, FeOverflow = FE_OVERFLOW,
  FeUnderflow = FE_UNDERFLOW, FeAllExceptions = FE_ALL_EXCEPT
}
 
enum  FeRoundingMode { FeRoundDown = FE_DOWNWARD, FeRoundNearest = FE_TONEAREST, FeRoundZero = FE_TOWARDZERO, FeRoundUpward = FE_UPWARD }
 
enum  VfpRoundingMode {
  VfpRoundNearest = 0, VfpRoundUpward = 1, VfpRoundDown = 2, VfpRoundZero = 3,
  VfpRoundAway = 4
}
 
enum  InterruptTypes {
  INT_RST, INT_ABT, INT_IRQ, INT_FIQ,
  INT_SEV, INT_VIRT_IRQ, INT_VIRT_FIQ, NumInterruptTypes
}
 
enum  LookupLevel {
  L0 = 0, L1, L2, L3,
  MAX_LOOKUP_LEVELS
}
 
enum  ccRegIndex {
  CCREG_NZ, CCREG_C, CCREG_V, CCREG_GE,
  CCREG_FP, CCREG_ZERO, NUM_CCREGS
}
 
enum  ConditionCode {
  COND_EQ = 0, COND_NE, COND_CS, COND_CC,
  COND_MI, COND_PL, COND_VS, COND_VC,
  COND_HI, COND_LS, COND_GE, COND_LT,
  COND_GT, COND_LE, COND_AL, COND_UC
}
 
enum  MiscRegIndex {
  MISCREG_CPSR = 0, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ,
  MISCREG_SPSR_SVC, MISCREG_SPSR_MON, MISCREG_SPSR_ABT, MISCREG_SPSR_HYP,
  MISCREG_SPSR_UND, MISCREG_ELR_HYP, MISCREG_FPSID, MISCREG_FPSCR,
  MISCREG_MVFR1, MISCREG_MVFR0, MISCREG_FPEXC, MISCREG_CPSR_MODE,
  MISCREG_CPSR_Q, MISCREG_FPSCR_EXC, MISCREG_FPSCR_QC, MISCREG_LOCKADDR,
  MISCREG_LOCKFLAG, MISCREG_PRRR_MAIR0, MISCREG_PRRR_MAIR0_NS, MISCREG_PRRR_MAIR0_S,
  MISCREG_NMRR_MAIR1, MISCREG_NMRR_MAIR1_NS, MISCREG_NMRR_MAIR1_S, MISCREG_PMXEVTYPER_PMCCFILTR,
  MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, MISCREG_DBGDIDR, MISCREG_DBGDSCRint,
  MISCREG_DBGDCCINT, MISCREG_DBGDTRTXint, MISCREG_DBGDTRRXint, MISCREG_DBGWFAR,
  MISCREG_DBGVCR, MISCREG_DBGDTRRXext, MISCREG_DBGDSCRext, MISCREG_DBGDTRTXext,
  MISCREG_DBGOSECCR, MISCREG_DBGBVR0, MISCREG_DBGBVR1, MISCREG_DBGBVR2,
  MISCREG_DBGBVR3, MISCREG_DBGBVR4, MISCREG_DBGBVR5, MISCREG_DBGBVR6,
  MISCREG_DBGBVR7, MISCREG_DBGBVR8, MISCREG_DBGBVR9, MISCREG_DBGBVR10,
  MISCREG_DBGBVR11, MISCREG_DBGBVR12, MISCREG_DBGBVR13, MISCREG_DBGBVR14,
  MISCREG_DBGBVR15, MISCREG_DBGBCR0, MISCREG_DBGBCR1, MISCREG_DBGBCR2,
  MISCREG_DBGBCR3, MISCREG_DBGBCR4, MISCREG_DBGBCR5, MISCREG_DBGBCR6,
  MISCREG_DBGBCR7, MISCREG_DBGBCR8, MISCREG_DBGBCR9, MISCREG_DBGBCR10,
  MISCREG_DBGBCR11, MISCREG_DBGBCR12, MISCREG_DBGBCR13, MISCREG_DBGBCR14,
  MISCREG_DBGBCR15, MISCREG_DBGWVR0, MISCREG_DBGWVR1, MISCREG_DBGWVR2,
  MISCREG_DBGWVR3, MISCREG_DBGWVR4, MISCREG_DBGWVR5, MISCREG_DBGWVR6,
  MISCREG_DBGWVR7, MISCREG_DBGWVR8, MISCREG_DBGWVR9, MISCREG_DBGWVR10,
  MISCREG_DBGWVR11, MISCREG_DBGWVR12, MISCREG_DBGWVR13, MISCREG_DBGWVR14,
  MISCREG_DBGWVR15, MISCREG_DBGWCR0, MISCREG_DBGWCR1, MISCREG_DBGWCR2,
  MISCREG_DBGWCR3, MISCREG_DBGWCR4, MISCREG_DBGWCR5, MISCREG_DBGWCR6,
  MISCREG_DBGWCR7, MISCREG_DBGWCR8, MISCREG_DBGWCR9, MISCREG_DBGWCR10,
  MISCREG_DBGWCR11, MISCREG_DBGWCR12, MISCREG_DBGWCR13, MISCREG_DBGWCR14,
  MISCREG_DBGWCR15, MISCREG_DBGDRAR, MISCREG_DBGBXVR0, MISCREG_DBGBXVR1,
  MISCREG_DBGBXVR2, MISCREG_DBGBXVR3, MISCREG_DBGBXVR4, MISCREG_DBGBXVR5,
  MISCREG_DBGBXVR6, MISCREG_DBGBXVR7, MISCREG_DBGBXVR8, MISCREG_DBGBXVR9,
  MISCREG_DBGBXVR10, MISCREG_DBGBXVR11, MISCREG_DBGBXVR12, MISCREG_DBGBXVR13,
  MISCREG_DBGBXVR14, MISCREG_DBGBXVR15, MISCREG_DBGOSLAR, MISCREG_DBGOSLSR,
  MISCREG_DBGOSDLR, MISCREG_DBGPRCR, MISCREG_DBGDSAR, MISCREG_DBGCLAIMSET,
  MISCREG_DBGCLAIMCLR, MISCREG_DBGAUTHSTATUS, MISCREG_DBGDEVID2, MISCREG_DBGDEVID1,
  MISCREG_DBGDEVID0, MISCREG_TEECR, MISCREG_JIDR, MISCREG_TEEHBR,
  MISCREG_JOSCR, MISCREG_JMCR, MISCREG_MIDR, MISCREG_CTR,
  MISCREG_TCMTR, MISCREG_TLBTR, MISCREG_MPIDR, MISCREG_REVIDR,
  MISCREG_ID_PFR0, MISCREG_ID_PFR1, MISCREG_ID_DFR0, MISCREG_ID_AFR0,
  MISCREG_ID_MMFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, MISCREG_ID_MMFR3,
  MISCREG_ID_MMFR4, MISCREG_ID_ISAR0, MISCREG_ID_ISAR1, MISCREG_ID_ISAR2,
  MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, MISCREG_ID_ISAR6,
  MISCREG_CCSIDR, MISCREG_CLIDR, MISCREG_AIDR, MISCREG_CSSELR,
  MISCREG_CSSELR_NS, MISCREG_CSSELR_S, MISCREG_VPIDR, MISCREG_VMPIDR,
  MISCREG_SCTLR, MISCREG_SCTLR_NS, MISCREG_SCTLR_S, MISCREG_ACTLR,
  MISCREG_ACTLR_NS, MISCREG_ACTLR_S, MISCREG_CPACR, MISCREG_SDCR,
  MISCREG_SCR, MISCREG_SDER, MISCREG_NSACR, MISCREG_HSCTLR,
  MISCREG_HACTLR, MISCREG_HCR, MISCREG_HCR2, MISCREG_HDCR,
  MISCREG_HCPTR, MISCREG_HSTR, MISCREG_HACR, MISCREG_TTBR0,
  MISCREG_TTBR0_NS, MISCREG_TTBR0_S, MISCREG_TTBR1, MISCREG_TTBR1_NS,
  MISCREG_TTBR1_S, MISCREG_TTBCR, MISCREG_TTBCR_NS, MISCREG_TTBCR_S,
  MISCREG_HTCR, MISCREG_VTCR, MISCREG_DACR, MISCREG_DACR_NS,
  MISCREG_DACR_S, MISCREG_DFSR, MISCREG_DFSR_NS, MISCREG_DFSR_S,
  MISCREG_IFSR, MISCREG_IFSR_NS, MISCREG_IFSR_S, MISCREG_ADFSR,
  MISCREG_ADFSR_NS, MISCREG_ADFSR_S, MISCREG_AIFSR, MISCREG_AIFSR_NS,
  MISCREG_AIFSR_S, MISCREG_HADFSR, MISCREG_HAIFSR, MISCREG_HSR,
  MISCREG_DFAR, MISCREG_DFAR_NS, MISCREG_DFAR_S, MISCREG_IFAR,
  MISCREG_IFAR_NS, MISCREG_IFAR_S, MISCREG_HDFAR, MISCREG_HIFAR,
  MISCREG_HPFAR, MISCREG_ICIALLUIS, MISCREG_BPIALLIS, MISCREG_PAR,
  MISCREG_PAR_NS, MISCREG_PAR_S, MISCREG_ICIALLU, MISCREG_ICIMVAU,
  MISCREG_CP15ISB, MISCREG_BPIALL, MISCREG_BPIMVA, MISCREG_DCIMVAC,
  MISCREG_DCISW, MISCREG_ATS1CPR, MISCREG_ATS1CPW, MISCREG_ATS1CUR,
  MISCREG_ATS1CUW, MISCREG_ATS12NSOPR, MISCREG_ATS12NSOPW, MISCREG_ATS12NSOUR,
  MISCREG_ATS12NSOUW, MISCREG_DCCMVAC, MISCREG_DCCSW, MISCREG_CP15DSB,
  MISCREG_CP15DMB, MISCREG_DCCMVAU, MISCREG_DCCIMVAC, MISCREG_DCCISW,
  MISCREG_ATS1HR, MISCREG_ATS1HW, MISCREG_TLBIALLIS, MISCREG_TLBIMVAIS,
  MISCREG_TLBIASIDIS, MISCREG_TLBIMVAAIS, MISCREG_TLBIMVALIS, MISCREG_TLBIMVAALIS,
  MISCREG_ITLBIALL, MISCREG_ITLBIMVA, MISCREG_ITLBIASID, MISCREG_DTLBIALL,
  MISCREG_DTLBIMVA, MISCREG_DTLBIASID, MISCREG_TLBIALL, MISCREG_TLBIMVA,
  MISCREG_TLBIASID, MISCREG_TLBIMVAA, MISCREG_TLBIMVAL, MISCREG_TLBIMVAAL,
  MISCREG_TLBIIPAS2IS, MISCREG_TLBIIPAS2LIS, MISCREG_TLBIALLHIS, MISCREG_TLBIMVAHIS,
  MISCREG_TLBIALLNSNHIS, MISCREG_TLBIMVALHIS, MISCREG_TLBIIPAS2, MISCREG_TLBIIPAS2L,
  MISCREG_TLBIALLH, MISCREG_TLBIMVAH, MISCREG_TLBIALLNSNH, MISCREG_TLBIMVALH,
  MISCREG_PMCR, MISCREG_PMCNTENSET, MISCREG_PMCNTENCLR, MISCREG_PMOVSR,
  MISCREG_PMSWINC, MISCREG_PMSELR, MISCREG_PMCEID0, MISCREG_PMCEID1,
  MISCREG_PMCCNTR, MISCREG_PMXEVTYPER, MISCREG_PMCCFILTR, MISCREG_PMXEVCNTR,
  MISCREG_PMUSERENR, MISCREG_PMINTENSET, MISCREG_PMINTENCLR, MISCREG_PMOVSSET,
  MISCREG_L2CTLR, MISCREG_L2ECTLR, MISCREG_PRRR, MISCREG_PRRR_NS,
  MISCREG_PRRR_S, MISCREG_MAIR0, MISCREG_MAIR0_NS, MISCREG_MAIR0_S,
  MISCREG_NMRR, MISCREG_NMRR_NS, MISCREG_NMRR_S, MISCREG_MAIR1,
  MISCREG_MAIR1_NS, MISCREG_MAIR1_S, MISCREG_AMAIR0, MISCREG_AMAIR0_NS,
  MISCREG_AMAIR0_S, MISCREG_AMAIR1, MISCREG_AMAIR1_NS, MISCREG_AMAIR1_S,
  MISCREG_HMAIR0, MISCREG_HMAIR1, MISCREG_HAMAIR0, MISCREG_HAMAIR1,
  MISCREG_VBAR, MISCREG_VBAR_NS, MISCREG_VBAR_S, MISCREG_MVBAR,
  MISCREG_RMR, MISCREG_ISR, MISCREG_HVBAR, MISCREG_FCSEIDR,
  MISCREG_CONTEXTIDR, MISCREG_CONTEXTIDR_NS, MISCREG_CONTEXTIDR_S, MISCREG_TPIDRURW,
  MISCREG_TPIDRURW_NS, MISCREG_TPIDRURW_S, MISCREG_TPIDRURO, MISCREG_TPIDRURO_NS,
  MISCREG_TPIDRURO_S, MISCREG_TPIDRPRW, MISCREG_TPIDRPRW_NS, MISCREG_TPIDRPRW_S,
  MISCREG_HTPIDR, MISCREG_CNTFRQ, MISCREG_CNTPCT, MISCREG_CNTVCT,
  MISCREG_CNTP_CTL, MISCREG_CNTP_CTL_NS, MISCREG_CNTP_CTL_S, MISCREG_CNTP_CVAL,
  MISCREG_CNTP_CVAL_NS, MISCREG_CNTP_CVAL_S, MISCREG_CNTP_TVAL, MISCREG_CNTP_TVAL_NS,
  MISCREG_CNTP_TVAL_S, MISCREG_CNTV_CTL, MISCREG_CNTV_CVAL, MISCREG_CNTV_TVAL,
  MISCREG_CNTKCTL, MISCREG_CNTHCTL, MISCREG_CNTHP_CTL, MISCREG_CNTHP_CVAL,
  MISCREG_CNTHP_TVAL, MISCREG_CNTVOFF, MISCREG_IL1DATA0, MISCREG_IL1DATA1,
  MISCREG_IL1DATA2, MISCREG_IL1DATA3, MISCREG_DL1DATA0, MISCREG_DL1DATA1,
  MISCREG_DL1DATA2, MISCREG_DL1DATA3, MISCREG_DL1DATA4, MISCREG_RAMINDEX,
  MISCREG_L2ACTLR, MISCREG_CBAR, MISCREG_HTTBR, MISCREG_VTTBR,
  MISCREG_CPUMERRSR, MISCREG_L2MERRSR, MISCREG_MDCCINT_EL1, MISCREG_OSDTRRX_EL1,
  MISCREG_MDSCR_EL1, MISCREG_OSDTRTX_EL1, MISCREG_OSECCR_EL1, MISCREG_DBGBVR0_EL1,
  MISCREG_DBGBVR1_EL1, MISCREG_DBGBVR2_EL1, MISCREG_DBGBVR3_EL1, MISCREG_DBGBVR4_EL1,
  MISCREG_DBGBVR5_EL1, MISCREG_DBGBVR6_EL1, MISCREG_DBGBVR7_EL1, MISCREG_DBGBVR8_EL1,
  MISCREG_DBGBVR9_EL1, MISCREG_DBGBVR10_EL1, MISCREG_DBGBVR11_EL1, MISCREG_DBGBVR12_EL1,
  MISCREG_DBGBVR13_EL1, MISCREG_DBGBVR14_EL1, MISCREG_DBGBVR15_EL1, MISCREG_DBGBCR0_EL1,
  MISCREG_DBGBCR1_EL1, MISCREG_DBGBCR2_EL1, MISCREG_DBGBCR3_EL1, MISCREG_DBGBCR4_EL1,
  MISCREG_DBGBCR5_EL1, MISCREG_DBGBCR6_EL1, MISCREG_DBGBCR7_EL1, MISCREG_DBGBCR8_EL1,
  MISCREG_DBGBCR9_EL1, MISCREG_DBGBCR10_EL1, MISCREG_DBGBCR11_EL1, MISCREG_DBGBCR12_EL1,
  MISCREG_DBGBCR13_EL1, MISCREG_DBGBCR14_EL1, MISCREG_DBGBCR15_EL1, MISCREG_DBGWVR0_EL1,
  MISCREG_DBGWVR1_EL1, MISCREG_DBGWVR2_EL1, MISCREG_DBGWVR3_EL1, MISCREG_DBGWVR4_EL1,
  MISCREG_DBGWVR5_EL1, MISCREG_DBGWVR6_EL1, MISCREG_DBGWVR7_EL1, MISCREG_DBGWVR8_EL1,
  MISCREG_DBGWVR9_EL1, MISCREG_DBGWVR10_EL1, MISCREG_DBGWVR11_EL1, MISCREG_DBGWVR12_EL1,
  MISCREG_DBGWVR13_EL1, MISCREG_DBGWVR14_EL1, MISCREG_DBGWVR15_EL1, MISCREG_DBGWCR0_EL1,
  MISCREG_DBGWCR1_EL1, MISCREG_DBGWCR2_EL1, MISCREG_DBGWCR3_EL1, MISCREG_DBGWCR4_EL1,
  MISCREG_DBGWCR5_EL1, MISCREG_DBGWCR6_EL1, MISCREG_DBGWCR7_EL1, MISCREG_DBGWCR8_EL1,
  MISCREG_DBGWCR9_EL1, MISCREG_DBGWCR10_EL1, MISCREG_DBGWCR11_EL1, MISCREG_DBGWCR12_EL1,
  MISCREG_DBGWCR13_EL1, MISCREG_DBGWCR14_EL1, MISCREG_DBGWCR15_EL1, MISCREG_MDCCSR_EL0,
  MISCREG_MDDTR_EL0, MISCREG_MDDTRTX_EL0, MISCREG_MDDTRRX_EL0, MISCREG_DBGVCR32_EL2,
  MISCREG_MDRAR_EL1, MISCREG_OSLAR_EL1, MISCREG_OSLSR_EL1, MISCREG_OSDLR_EL1,
  MISCREG_DBGPRCR_EL1, MISCREG_DBGCLAIMSET_EL1, MISCREG_DBGCLAIMCLR_EL1, MISCREG_DBGAUTHSTATUS_EL1,
  MISCREG_TEECR32_EL1, MISCREG_TEEHBR32_EL1, MISCREG_MIDR_EL1, MISCREG_MPIDR_EL1,
  MISCREG_REVIDR_EL1, MISCREG_ID_PFR0_EL1, MISCREG_ID_PFR1_EL1, MISCREG_ID_DFR0_EL1,
  MISCREG_ID_AFR0_EL1, MISCREG_ID_MMFR0_EL1, MISCREG_ID_MMFR1_EL1, MISCREG_ID_MMFR2_EL1,
  MISCREG_ID_MMFR3_EL1, MISCREG_ID_MMFR4_EL1, MISCREG_ID_ISAR0_EL1, MISCREG_ID_ISAR1_EL1,
  MISCREG_ID_ISAR2_EL1, MISCREG_ID_ISAR3_EL1, MISCREG_ID_ISAR4_EL1, MISCREG_ID_ISAR5_EL1,
  MISCREG_ID_ISAR6_EL1, MISCREG_MVFR0_EL1, MISCREG_MVFR1_EL1, MISCREG_MVFR2_EL1,
  MISCREG_ID_AA64PFR0_EL1, MISCREG_ID_AA64PFR1_EL1, MISCREG_ID_AA64DFR0_EL1, MISCREG_ID_AA64DFR1_EL1,
  MISCREG_ID_AA64AFR0_EL1, MISCREG_ID_AA64AFR1_EL1, MISCREG_ID_AA64ISAR0_EL1, MISCREG_ID_AA64ISAR1_EL1,
  MISCREG_ID_AA64MMFR0_EL1, MISCREG_ID_AA64MMFR1_EL1, MISCREG_CCSIDR_EL1, MISCREG_CLIDR_EL1,
  MISCREG_AIDR_EL1, MISCREG_CSSELR_EL1, MISCREG_CTR_EL0, MISCREG_DCZID_EL0,
  MISCREG_VPIDR_EL2, MISCREG_VMPIDR_EL2, MISCREG_SCTLR_EL1, MISCREG_SCTLR_EL12,
  MISCREG_ACTLR_EL1, MISCREG_CPACR_EL1, MISCREG_CPACR_EL12, MISCREG_SCTLR_EL2,
  MISCREG_ACTLR_EL2, MISCREG_HCR_EL2, MISCREG_MDCR_EL2, MISCREG_CPTR_EL2,
  MISCREG_HSTR_EL2, MISCREG_HACR_EL2, MISCREG_SCTLR_EL3, MISCREG_ACTLR_EL3,
  MISCREG_SCR_EL3, MISCREG_SDER32_EL3, MISCREG_CPTR_EL3, MISCREG_MDCR_EL3,
  MISCREG_TTBR0_EL1, MISCREG_TTBR0_EL12, MISCREG_TTBR1_EL1, MISCREG_TTBR1_EL12,
  MISCREG_TCR_EL1, MISCREG_TCR_EL12, MISCREG_TTBR0_EL2, MISCREG_TCR_EL2,
  MISCREG_VTTBR_EL2, MISCREG_VTCR_EL2, MISCREG_VSTTBR_EL2, MISCREG_VSTCR_EL2,
  MISCREG_TTBR0_EL3, MISCREG_TCR_EL3, MISCREG_DACR32_EL2, MISCREG_SPSR_EL1,
  MISCREG_SPSR_EL12, MISCREG_ELR_EL1, MISCREG_ELR_EL12, MISCREG_SP_EL0,
  MISCREG_SPSEL, MISCREG_CURRENTEL, MISCREG_NZCV, MISCREG_DAIF,
  MISCREG_FPCR, MISCREG_FPSR, MISCREG_DSPSR_EL0, MISCREG_DLR_EL0,
  MISCREG_SPSR_EL2, MISCREG_ELR_EL2, MISCREG_SP_EL1, MISCREG_SPSR_IRQ_AA64,
  MISCREG_SPSR_ABT_AA64, MISCREG_SPSR_UND_AA64, MISCREG_SPSR_FIQ_AA64, MISCREG_SPSR_EL3,
  MISCREG_ELR_EL3, MISCREG_SP_EL2, MISCREG_AFSR0_EL1, MISCREG_AFSR0_EL12,
  MISCREG_AFSR1_EL1, MISCREG_AFSR1_EL12, MISCREG_ESR_EL1, MISCREG_ESR_EL12,
  MISCREG_IFSR32_EL2, MISCREG_AFSR0_EL2, MISCREG_AFSR1_EL2, MISCREG_ESR_EL2,
  MISCREG_FPEXC32_EL2, MISCREG_AFSR0_EL3, MISCREG_AFSR1_EL3, MISCREG_ESR_EL3,
  MISCREG_FAR_EL1, MISCREG_FAR_EL12, MISCREG_FAR_EL2, MISCREG_HPFAR_EL2,
  MISCREG_FAR_EL3, MISCREG_IC_IALLUIS, MISCREG_PAR_EL1, MISCREG_IC_IALLU,
  MISCREG_DC_IVAC_Xt, MISCREG_DC_ISW_Xt, MISCREG_AT_S1E1R_Xt, MISCREG_AT_S1E1W_Xt,
  MISCREG_AT_S1E0R_Xt, MISCREG_AT_S1E0W_Xt, MISCREG_DC_CSW_Xt, MISCREG_DC_CISW_Xt,
  MISCREG_DC_ZVA_Xt, MISCREG_IC_IVAU_Xt, MISCREG_DC_CVAC_Xt, MISCREG_DC_CVAU_Xt,
  MISCREG_DC_CIVAC_Xt, MISCREG_AT_S1E2R_Xt, MISCREG_AT_S1E2W_Xt, MISCREG_AT_S12E1R_Xt,
  MISCREG_AT_S12E1W_Xt, MISCREG_AT_S12E0R_Xt, MISCREG_AT_S12E0W_Xt, MISCREG_AT_S1E3R_Xt,
  MISCREG_AT_S1E3W_Xt, MISCREG_TLBI_VMALLE1IS, MISCREG_TLBI_VAE1IS_Xt, MISCREG_TLBI_ASIDE1IS_Xt,
  MISCREG_TLBI_VAAE1IS_Xt, MISCREG_TLBI_VALE1IS_Xt, MISCREG_TLBI_VAALE1IS_Xt, MISCREG_TLBI_VMALLE1,
  MISCREG_TLBI_VAE1_Xt, MISCREG_TLBI_ASIDE1_Xt, MISCREG_TLBI_VAAE1_Xt, MISCREG_TLBI_VALE1_Xt,
  MISCREG_TLBI_VAALE1_Xt, MISCREG_TLBI_IPAS2E1IS_Xt, MISCREG_TLBI_IPAS2LE1IS_Xt, MISCREG_TLBI_ALLE2IS,
  MISCREG_TLBI_VAE2IS_Xt, MISCREG_TLBI_ALLE1IS, MISCREG_TLBI_VALE2IS_Xt, MISCREG_TLBI_VMALLS12E1IS,
  MISCREG_TLBI_IPAS2E1_Xt, MISCREG_TLBI_IPAS2LE1_Xt, MISCREG_TLBI_ALLE2, MISCREG_TLBI_VAE2_Xt,
  MISCREG_TLBI_ALLE1, MISCREG_TLBI_VALE2_Xt, MISCREG_TLBI_VMALLS12E1, MISCREG_TLBI_ALLE3IS,
  MISCREG_TLBI_VAE3IS_Xt, MISCREG_TLBI_VALE3IS_Xt, MISCREG_TLBI_ALLE3, MISCREG_TLBI_VAE3_Xt,
  MISCREG_TLBI_VALE3_Xt, MISCREG_PMINTENSET_EL1, MISCREG_PMINTENCLR_EL1, MISCREG_PMCR_EL0,
  MISCREG_PMCNTENSET_EL0, MISCREG_PMCNTENCLR_EL0, MISCREG_PMOVSCLR_EL0, MISCREG_PMSWINC_EL0,
  MISCREG_PMSELR_EL0, MISCREG_PMCEID0_EL0, MISCREG_PMCEID1_EL0, MISCREG_PMCCNTR_EL0,
  MISCREG_PMXEVTYPER_EL0, MISCREG_PMCCFILTR_EL0, MISCREG_PMXEVCNTR_EL0, MISCREG_PMUSERENR_EL0,
  MISCREG_PMOVSSET_EL0, MISCREG_MAIR_EL1, MISCREG_MAIR_EL12, MISCREG_AMAIR_EL1,
  MISCREG_AMAIR_EL12, MISCREG_MAIR_EL2, MISCREG_AMAIR_EL2, MISCREG_MAIR_EL3,
  MISCREG_AMAIR_EL3, MISCREG_L2CTLR_EL1, MISCREG_L2ECTLR_EL1, MISCREG_VBAR_EL1,
  MISCREG_VBAR_EL12, MISCREG_RVBAR_EL1, MISCREG_ISR_EL1, MISCREG_VBAR_EL2,
  MISCREG_RVBAR_EL2, MISCREG_VBAR_EL3, MISCREG_RVBAR_EL3, MISCREG_RMR_EL3,
  MISCREG_CONTEXTIDR_EL1, MISCREG_CONTEXTIDR_EL12, MISCREG_TPIDR_EL1, MISCREG_TPIDR_EL0,
  MISCREG_TPIDRRO_EL0, MISCREG_TPIDR_EL2, MISCREG_TPIDR_EL3, MISCREG_CNTFRQ_EL0,
  MISCREG_CNTPCT_EL0, MISCREG_CNTVCT_EL0, MISCREG_CNTP_CTL_EL0, MISCREG_CNTP_CVAL_EL0,
  MISCREG_CNTP_TVAL_EL0, MISCREG_CNTV_CTL_EL0, MISCREG_CNTV_CVAL_EL0, MISCREG_CNTV_TVAL_EL0,
  MISCREG_CNTP_CTL_EL02, MISCREG_CNTP_CVAL_EL02, MISCREG_CNTP_TVAL_EL02, MISCREG_CNTV_CTL_EL02,
  MISCREG_CNTV_CVAL_EL02, MISCREG_CNTV_TVAL_EL02, MISCREG_CNTKCTL_EL1, MISCREG_CNTKCTL_EL12,
  MISCREG_CNTPS_CTL_EL1, MISCREG_CNTPS_CVAL_EL1, MISCREG_CNTPS_TVAL_EL1, MISCREG_CNTHCTL_EL2,
  MISCREG_CNTHP_CTL_EL2, MISCREG_CNTHP_CVAL_EL2, MISCREG_CNTHP_TVAL_EL2, MISCREG_CNTHPS_CTL_EL2,
  MISCREG_CNTHPS_CVAL_EL2, MISCREG_CNTHPS_TVAL_EL2, MISCREG_CNTHV_CTL_EL2, MISCREG_CNTHV_CVAL_EL2,
  MISCREG_CNTHV_TVAL_EL2, MISCREG_CNTHVS_CTL_EL2, MISCREG_CNTHVS_CVAL_EL2, MISCREG_CNTHVS_TVAL_EL2,
  MISCREG_CNTVOFF_EL2, MISCREG_PMEVCNTR0_EL0, MISCREG_PMEVCNTR1_EL0, MISCREG_PMEVCNTR2_EL0,
  MISCREG_PMEVCNTR3_EL0, MISCREG_PMEVCNTR4_EL0, MISCREG_PMEVCNTR5_EL0, MISCREG_PMEVTYPER0_EL0,
  MISCREG_PMEVTYPER1_EL0, MISCREG_PMEVTYPER2_EL0, MISCREG_PMEVTYPER3_EL0, MISCREG_PMEVTYPER4_EL0,
  MISCREG_PMEVTYPER5_EL0, MISCREG_IL1DATA0_EL1, MISCREG_IL1DATA1_EL1, MISCREG_IL1DATA2_EL1,
  MISCREG_IL1DATA3_EL1, MISCREG_DL1DATA0_EL1, MISCREG_DL1DATA1_EL1, MISCREG_DL1DATA2_EL1,
  MISCREG_DL1DATA3_EL1, MISCREG_DL1DATA4_EL1, MISCREG_L2ACTLR_EL1, MISCREG_CPUACTLR_EL1,
  MISCREG_CPUECTLR_EL1, MISCREG_CPUMERRSR_EL1, MISCREG_L2MERRSR_EL1, MISCREG_CBAR_EL1,
  MISCREG_CONTEXTIDR_EL2, MISCREG_TTBR1_EL2, MISCREG_ID_AA64MMFR2_EL1, MISCREG_APDAKeyHi_EL1,
  MISCREG_APDAKeyLo_EL1, MISCREG_APDBKeyHi_EL1, MISCREG_APDBKeyLo_EL1, MISCREG_APGAKeyHi_EL1,
  MISCREG_APGAKeyLo_EL1, MISCREG_APIAKeyHi_EL1, MISCREG_APIAKeyLo_EL1, MISCREG_APIBKeyHi_EL1,
  MISCREG_APIBKeyLo_EL1, MISCREG_ICC_PMR_EL1, MISCREG_ICC_IAR0_EL1, MISCREG_ICC_EOIR0_EL1,
  MISCREG_ICC_HPPIR0_EL1, MISCREG_ICC_BPR0_EL1, MISCREG_ICC_AP0R0_EL1, MISCREG_ICC_AP0R1_EL1,
  MISCREG_ICC_AP0R2_EL1, MISCREG_ICC_AP0R3_EL1, MISCREG_ICC_AP1R0_EL1, MISCREG_ICC_AP1R0_EL1_NS,
  MISCREG_ICC_AP1R0_EL1_S, MISCREG_ICC_AP1R1_EL1, MISCREG_ICC_AP1R1_EL1_NS, MISCREG_ICC_AP1R1_EL1_S,
  MISCREG_ICC_AP1R2_EL1, MISCREG_ICC_AP1R2_EL1_NS, MISCREG_ICC_AP1R2_EL1_S, MISCREG_ICC_AP1R3_EL1,
  MISCREG_ICC_AP1R3_EL1_NS, MISCREG_ICC_AP1R3_EL1_S, MISCREG_ICC_DIR_EL1, MISCREG_ICC_RPR_EL1,
  MISCREG_ICC_SGI1R_EL1, MISCREG_ICC_ASGI1R_EL1, MISCREG_ICC_SGI0R_EL1, MISCREG_ICC_IAR1_EL1,
  MISCREG_ICC_EOIR1_EL1, MISCREG_ICC_HPPIR1_EL1, MISCREG_ICC_BPR1_EL1, MISCREG_ICC_BPR1_EL1_NS,
  MISCREG_ICC_BPR1_EL1_S, MISCREG_ICC_CTLR_EL1, MISCREG_ICC_CTLR_EL1_NS, MISCREG_ICC_CTLR_EL1_S,
  MISCREG_ICC_SRE_EL1, MISCREG_ICC_SRE_EL1_NS, MISCREG_ICC_SRE_EL1_S, MISCREG_ICC_IGRPEN0_EL1,
  MISCREG_ICC_IGRPEN1_EL1, MISCREG_ICC_IGRPEN1_EL1_NS, MISCREG_ICC_IGRPEN1_EL1_S, MISCREG_ICC_SRE_EL2,
  MISCREG_ICC_CTLR_EL3, MISCREG_ICC_SRE_EL3, MISCREG_ICC_IGRPEN1_EL3, MISCREG_ICH_AP0R0_EL2,
  MISCREG_ICH_AP0R1_EL2, MISCREG_ICH_AP0R2_EL2, MISCREG_ICH_AP0R3_EL2, MISCREG_ICH_AP1R0_EL2,
  MISCREG_ICH_AP1R1_EL2, MISCREG_ICH_AP1R2_EL2, MISCREG_ICH_AP1R3_EL2, MISCREG_ICH_HCR_EL2,
  MISCREG_ICH_VTR_EL2, MISCREG_ICH_MISR_EL2, MISCREG_ICH_EISR_EL2, MISCREG_ICH_ELRSR_EL2,
  MISCREG_ICH_VMCR_EL2, MISCREG_ICH_LR0_EL2, MISCREG_ICH_LR1_EL2, MISCREG_ICH_LR2_EL2,
  MISCREG_ICH_LR3_EL2, MISCREG_ICH_LR4_EL2, MISCREG_ICH_LR5_EL2, MISCREG_ICH_LR6_EL2,
  MISCREG_ICH_LR7_EL2, MISCREG_ICH_LR8_EL2, MISCREG_ICH_LR9_EL2, MISCREG_ICH_LR10_EL2,
  MISCREG_ICH_LR11_EL2, MISCREG_ICH_LR12_EL2, MISCREG_ICH_LR13_EL2, MISCREG_ICH_LR14_EL2,
  MISCREG_ICH_LR15_EL2, MISCREG_ICV_PMR_EL1, MISCREG_ICV_IAR0_EL1, MISCREG_ICV_EOIR0_EL1,
  MISCREG_ICV_HPPIR0_EL1, MISCREG_ICV_BPR0_EL1, MISCREG_ICV_AP0R0_EL1, MISCREG_ICV_AP0R1_EL1,
  MISCREG_ICV_AP0R2_EL1, MISCREG_ICV_AP0R3_EL1, MISCREG_ICV_AP1R0_EL1, MISCREG_ICV_AP1R0_EL1_NS,
  MISCREG_ICV_AP1R0_EL1_S, MISCREG_ICV_AP1R1_EL1, MISCREG_ICV_AP1R1_EL1_NS, MISCREG_ICV_AP1R1_EL1_S,
  MISCREG_ICV_AP1R2_EL1, MISCREG_ICV_AP1R2_EL1_NS, MISCREG_ICV_AP1R2_EL1_S, MISCREG_ICV_AP1R3_EL1,
  MISCREG_ICV_AP1R3_EL1_NS, MISCREG_ICV_AP1R3_EL1_S, MISCREG_ICV_DIR_EL1, MISCREG_ICV_RPR_EL1,
  MISCREG_ICV_SGI1R_EL1, MISCREG_ICV_ASGI1R_EL1, MISCREG_ICV_SGI0R_EL1, MISCREG_ICV_IAR1_EL1,
  MISCREG_ICV_EOIR1_EL1, MISCREG_ICV_HPPIR1_EL1, MISCREG_ICV_BPR1_EL1, MISCREG_ICV_BPR1_EL1_NS,
  MISCREG_ICV_BPR1_EL1_S, MISCREG_ICV_CTLR_EL1, MISCREG_ICV_CTLR_EL1_NS, MISCREG_ICV_CTLR_EL1_S,
  MISCREG_ICV_SRE_EL1, MISCREG_ICV_SRE_EL1_NS, MISCREG_ICV_SRE_EL1_S, MISCREG_ICV_IGRPEN0_EL1,
  MISCREG_ICV_IGRPEN1_EL1, MISCREG_ICV_IGRPEN1_EL1_NS, MISCREG_ICV_IGRPEN1_EL1_S, MISCREG_ICC_AP0R0,
  MISCREG_ICC_AP0R1, MISCREG_ICC_AP0R2, MISCREG_ICC_AP0R3, MISCREG_ICC_AP1R0,
  MISCREG_ICC_AP1R0_NS, MISCREG_ICC_AP1R0_S, MISCREG_ICC_AP1R1, MISCREG_ICC_AP1R1_NS,
  MISCREG_ICC_AP1R1_S, MISCREG_ICC_AP1R2, MISCREG_ICC_AP1R2_NS, MISCREG_ICC_AP1R2_S,
  MISCREG_ICC_AP1R3, MISCREG_ICC_AP1R3_NS, MISCREG_ICC_AP1R3_S, MISCREG_ICC_ASGI1R,
  MISCREG_ICC_BPR0, MISCREG_ICC_BPR1, MISCREG_ICC_BPR1_NS, MISCREG_ICC_BPR1_S,
  MISCREG_ICC_CTLR, MISCREG_ICC_CTLR_NS, MISCREG_ICC_CTLR_S, MISCREG_ICC_DIR,
  MISCREG_ICC_EOIR0, MISCREG_ICC_EOIR1, MISCREG_ICC_HPPIR0, MISCREG_ICC_HPPIR1,
  MISCREG_ICC_HSRE, MISCREG_ICC_IAR0, MISCREG_ICC_IAR1, MISCREG_ICC_IGRPEN0,
  MISCREG_ICC_IGRPEN1, MISCREG_ICC_IGRPEN1_NS, MISCREG_ICC_IGRPEN1_S, MISCREG_ICC_MCTLR,
  MISCREG_ICC_MGRPEN1, MISCREG_ICC_MSRE, MISCREG_ICC_PMR, MISCREG_ICC_RPR,
  MISCREG_ICC_SGI0R, MISCREG_ICC_SGI1R, MISCREG_ICC_SRE, MISCREG_ICC_SRE_NS,
  MISCREG_ICC_SRE_S, MISCREG_ICH_AP0R0, MISCREG_ICH_AP0R1, MISCREG_ICH_AP0R2,
  MISCREG_ICH_AP0R3, MISCREG_ICH_AP1R0, MISCREG_ICH_AP1R1, MISCREG_ICH_AP1R2,
  MISCREG_ICH_AP1R3, MISCREG_ICH_HCR, MISCREG_ICH_VTR, MISCREG_ICH_MISR,
  MISCREG_ICH_EISR, MISCREG_ICH_ELRSR, MISCREG_ICH_VMCR, MISCREG_ICH_LR0,
  MISCREG_ICH_LR1, MISCREG_ICH_LR2, MISCREG_ICH_LR3, MISCREG_ICH_LR4,
  MISCREG_ICH_LR5, MISCREG_ICH_LR6, MISCREG_ICH_LR7, MISCREG_ICH_LR8,
  MISCREG_ICH_LR9, MISCREG_ICH_LR10, MISCREG_ICH_LR11, MISCREG_ICH_LR12,
  MISCREG_ICH_LR13, MISCREG_ICH_LR14, MISCREG_ICH_LR15, MISCREG_ICH_LRC0,
  MISCREG_ICH_LRC1, MISCREG_ICH_LRC2, MISCREG_ICH_LRC3, MISCREG_ICH_LRC4,
  MISCREG_ICH_LRC5, MISCREG_ICH_LRC6, MISCREG_ICH_LRC7, MISCREG_ICH_LRC8,
  MISCREG_ICH_LRC9, MISCREG_ICH_LRC10, MISCREG_ICH_LRC11, MISCREG_ICH_LRC12,
  MISCREG_ICH_LRC13, MISCREG_ICH_LRC14, MISCREG_ICH_LRC15, MISCREG_ID_AA64ZFR0_EL1,
  MISCREG_ZCR_EL3, MISCREG_ZCR_EL2, MISCREG_ZCR_EL12, MISCREG_ZCR_EL1,
  NUM_PHYS_MISCREGS, MISCREG_NOP, MISCREG_RAZ, MISCREG_CP14_UNIMPL,
  MISCREG_CP15_UNIMPL, MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL, MISCREG_ERRIDR_EL1,
  MISCREG_ERRSELR_EL1, MISCREG_ERXFR_EL1, MISCREG_ERXCTLR_EL1, MISCREG_ERXSTATUS_EL1,
  MISCREG_ERXADDR_EL1, MISCREG_ERXMISC0_EL1, MISCREG_ERXMISC1_EL1, MISCREG_DISR_EL1,
  MISCREG_VSESR_EL2, MISCREG_VDISR_EL2, MISCREG_PAN, NUM_MISCREGS
}
 
enum  MiscRegInfo {
  MISCREG_IMPLEMENTED, MISCREG_UNVERIFIABLE, MISCREG_WARN_NOT_FAIL, MISCREG_MUTEX,
  MISCREG_BANKED, MISCREG_BANKED64, MISCREG_BANKED_CHILD, MISCREG_USR_NS_RD,
  MISCREG_USR_NS_WR, MISCREG_USR_S_RD, MISCREG_USR_S_WR, MISCREG_PRI_NS_RD,
  MISCREG_PRI_NS_WR, MISCREG_PRI_S_RD, MISCREG_PRI_S_WR, MISCREG_HYP_NS_RD,
  MISCREG_HYP_NS_WR, MISCREG_HYP_S_RD, MISCREG_HYP_S_WR, MISCREG_HYP_E2H_NS_RD,
  MISCREG_HYP_E2H_NS_WR, MISCREG_HYP_E2H_S_RD, MISCREG_HYP_E2H_S_WR, MISCREG_MON_NS0_RD,
  MISCREG_MON_NS0_WR, MISCREG_MON_NS1_RD, MISCREG_MON_NS1_WR, MISCREG_MON_E2H_RD,
  MISCREG_MON_E2H_WR, NUM_MISCREG_INFOS
}
 
enum  ArmExtendType {
  UXTB = 0, UXTH = 1, UXTW = 2, UXTX = 3,
  SXTB = 4, SXTH = 5, SXTW = 6, SXTX = 7
}
 
enum  ConvertType {
  SINGLE_TO_DOUBLE, SINGLE_TO_WORD, SINGLE_TO_LONG, DOUBLE_TO_SINGLE,
  DOUBLE_TO_WORD, DOUBLE_TO_LONG, LONG_TO_SINGLE, LONG_TO_DOUBLE,
  LONG_TO_WORD, LONG_TO_PS, WORD_TO_SINGLE, WORD_TO_DOUBLE,
  WORD_TO_LONG, WORD_TO_PS, PL_TO_SINGLE, PU_TO_SINGLE
}
 
enum  RoundMode { RND_ZERO, RND_DOWN, RND_UP, RND_NEAREST }
 
enum  ExceptionLevel { EL0 = 0, EL1, EL2, EL3 }
 
enum  OperatingMode {
  MODE_EL0T = 0x0, MODE_EL1T = 0x4, MODE_EL1H = 0x5, MODE_EL2T = 0x8,
  MODE_EL2H = 0x9, MODE_EL3T = 0xC, MODE_EL3H = 0xD, MODE_USER = 16,
  MODE_FIQ = 17, MODE_IRQ = 18, MODE_SVC = 19, MODE_MON = 22,
  MODE_ABORT = 23, MODE_HYP = 26, MODE_UNDEFINED = 27, MODE_SYSTEM = 31,
  MODE_MAXMODE = MODE_SYSTEM
}
 
enum  ExceptionClass {
  EC_INVALID = -1, EC_UNKNOWN = 0x0, EC_TRAPPED_WFI_WFE = 0x1, EC_TRAPPED_CP15_MCR_MRC = 0x3,
  EC_TRAPPED_CP15_MCRR_MRRC = 0x4, EC_TRAPPED_CP14_MCR_MRC = 0x5, EC_TRAPPED_CP14_LDC_STC = 0x6, EC_TRAPPED_HCPTR = 0x7,
  EC_TRAPPED_SIMD_FP = 0x7, EC_TRAPPED_CP10_MRC_VMRS = 0x8, EC_TRAPPED_PAC = 0x9, EC_TRAPPED_BXJ = 0xA,
  EC_TRAPPED_CP14_MCRR_MRRC = 0xC, EC_ILLEGAL_INST = 0xE, EC_SVC_TO_HYP = 0x11, EC_SVC = 0x11,
  EC_HVC = 0x12, EC_SMC_TO_HYP = 0x13, EC_SMC = 0x13, EC_SVC_64 = 0x15,
  EC_HVC_64 = 0x16, EC_SMC_64 = 0x17, EC_TRAPPED_MSR_MRS_64 = 0x18, EC_TRAPPED_SVE = 0x19,
  EC_PREFETCH_ABORT_TO_HYP = 0x20, EC_PREFETCH_ABORT_LOWER_EL = 0x20, EC_PREFETCH_ABORT_FROM_HYP = 0x21, EC_PREFETCH_ABORT_CURR_EL = 0x21,
  EC_PC_ALIGNMENT = 0x22, EC_DATA_ABORT_TO_HYP = 0x24, EC_DATA_ABORT_LOWER_EL = 0x24, EC_DATA_ABORT_FROM_HYP = 0x25,
  EC_DATA_ABORT_CURR_EL = 0x25, EC_STACK_PTR_ALIGNMENT = 0x26, EC_FP_EXCEPTION = 0x28, EC_FP_EXCEPTION_64 = 0x2C,
  EC_SERROR = 0x2F, EC_HW_BREAKPOINT = 0x30, EC_HW_BREAKPOINT_LOWER_EL = 0x30, EC_HW_BREAKPOINT_CURR_EL = 0x31,
  EC_SOFTWARE_STEP = 0x32, EC_SOFTWARE_STEP_LOWER_EL = 0x32, EC_SOFTWARE_STEP_CURR_EL = 0x33, EC_WATCHPOINT = 0x34,
  EC_WATCHPOINT_LOWER_EL = 0x34, EC_WATCHPOINT_CURR_EL = 0x35, EC_SOFTWARE_BREAKPOINT = 0x38, EC_VECTOR_CATCH = 0x3A,
  EC_SOFTWARE_BREAKPOINT_64 = 0x3C
}
 
enum  DecoderFault : std::uint8_t { OK = 0x0, UNALIGNED = 0x1, PANIC = 0x3 }
 Instruction decoder fault codes in ExtMachInst. More...
 

Functions

bool getFaultVAddr (Fault fault, Addr &va)
 Returns true if the fault passed as a first argument was triggered by a memory access, false otherwise. More...
 
static SyscallReturn issetugidFunc (SyscallDesc *desc, ThreadContext *tc)
 
static SyscallReturn sysctlFunc (SyscallDesc *desc, ThreadContext *tc, VPtr<> namep, size_t nameLen, VPtr<> oldp, VPtr<> oldlenp, VPtr<> newp, size_t newlen)
 
static uint16_t lsl16 (uint16_t x, uint32_t shift)
 
static uint16_t lsr16 (uint16_t x, uint32_t shift)
 
static uint32_t lsl32 (uint32_t x, uint32_t shift)
 
static uint32_t lsr32 (uint32_t x, uint32_t shift)
 
static uint64_t lsl64 (uint64_t x, uint32_t shift)
 
static uint64_t lsr64 (uint64_t x, uint32_t shift)
 
static void lsl128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
 
static void lsr128 (uint64_t *r0, uint64_t *r1, uint64_t x0, uint64_t x1, uint32_t shift)
 
static void mul62x62 (uint64_t *x0, uint64_t *x1, uint64_t a, uint64_t b)
 
static void mul64x32 (uint64_t *x0, uint64_t *x1, uint64_t a, uint32_t b)
 
static void add128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static void sub128 (uint64_t *x0, uint64_t *x1, uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static int cmp128 (uint64_t a0, uint64_t a1, uint64_t b0, uint64_t b1)
 
static uint16_t fp16_normalise (uint16_t mnt, int *exp)
 
static uint32_t fp32_normalise (uint32_t mnt, int *exp)
 
static uint64_t fp64_normalise (uint64_t mnt, int *exp)
 
static void fp128_normalise (uint64_t *mnt0, uint64_t *mnt1, int *exp)
 
static uint16_t fp16_pack (uint16_t sgn, uint16_t exp, uint16_t mnt)
 
static uint32_t fp32_pack (uint32_t sgn, uint32_t exp, uint32_t mnt)
 
static uint64_t fp64_pack (uint64_t sgn, uint64_t exp, uint64_t mnt)
 
static uint16_t fp16_zero (int sgn)
 
static uint32_t fp32_zero (int sgn)
 
static uint64_t fp64_zero (int sgn)
 
static uint16_t fp16_max_normal (int sgn)
 
static uint32_t fp32_max_normal (int sgn)
 
static uint64_t fp64_max_normal (int sgn)
 
static uint16_t fp16_infinity (int sgn)
 
static uint32_t fp32_infinity (int sgn)
 
static uint64_t fp64_infinity (int sgn)
 
static uint16_t fp16_defaultNaN ()
 
static uint32_t fp32_defaultNaN ()
 
static uint64_t fp64_defaultNaN ()
 
static void fp16_unpack (int *sgn, int *exp, uint16_t *mnt, uint16_t x, int mode, int *flags)
 
static void fp32_unpack (int *sgn, int *exp, uint32_t *mnt, uint32_t x, int mode, int *flags)
 
static void fp64_unpack (int *sgn, int *exp, uint64_t *mnt, uint64_t x, int mode, int *flags)
 
static int fp16_is_NaN (int exp, uint16_t mnt)
 
static int fp32_is_NaN (int exp, uint32_t mnt)
 
static int fp64_is_NaN (int exp, uint64_t mnt)
 
static int fp16_is_signalling_NaN (int exp, uint16_t mnt)
 
static int fp32_is_signalling_NaN (int exp, uint32_t mnt)
 
static int fp64_is_signalling_NaN (int exp, uint64_t mnt)
 
static int fp16_is_quiet_NaN (int exp, uint16_t mnt)
 
static int fp32_is_quiet_NaN (int exp, uint32_t mnt)
 
static int fp64_is_quiet_NaN (int exp, uint64_t mnt)
 
static int fp16_is_infinity (int exp, uint16_t mnt)
 
static int fp32_is_infinity (int exp, uint32_t mnt)
 
static int fp64_is_infinity (int exp, uint64_t mnt)
 
static uint16_t fp16_process_NaN (uint16_t a, int mode, int *flags)
 
static uint32_t fp32_process_NaN (uint32_t a, int mode, int *flags)
 
static uint64_t fp64_process_NaN (uint64_t a, int mode, int *flags)
 
static uint16_t fp16_process_NaNs (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_process_NaNs (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_process_NaNs (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_process_NaNs3 (uint16_t a, uint16_t b, uint16_t c, int mode, int *flags)
 
static uint32_t fp32_process_NaNs3 (uint32_t a, uint32_t b, uint32_t c, int mode, int *flags)
 
static uint64_t fp64_process_NaNs3 (uint64_t a, uint64_t b, uint64_t c, int mode, int *flags)
 
static uint16_t fp16_round_ (int sgn, int exp, uint16_t mnt, int rm, int mode, int *flags)
 
static uint16_t fp16_round (int sgn, int exp, uint16_t mnt, int mode, int *flags)
 
static uint32_t fp32_round_ (int sgn, int exp, uint32_t mnt, int rm, int mode, int *flags)
 
static uint32_t fp32_round (int sgn, int exp, uint32_t mnt, int mode, int *flags)
 
static uint64_t fp64_round_ (int sgn, int exp, uint64_t mnt, int rm, int mode, int *flags)
 
static uint64_t fp64_round (int sgn, int exp, uint64_t mnt, int mode, int *flags)
 
static int fp16_compare_eq (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_ge (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_gt (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp16_compare_un (uint16_t a, uint16_t b, int mode, int *flags)
 
static int fp32_compare_eq (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_ge (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_gt (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp32_compare_un (uint32_t a, uint32_t b, int mode, int *flags)
 
static int fp64_compare_eq (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_ge (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_gt (uint64_t a, uint64_t b, int mode, int *flags)
 
static int fp64_compare_un (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_add (uint16_t a, uint16_t b, int neg, int mode, int *flags)
 
static uint32_t fp32_add (uint32_t a, uint32_t b, int neg, int mode, int *flags)
 
static uint64_t fp64_add (uint64_t a, uint64_t b, int neg, int mode, int *flags)
 
static uint16_t fp16_mul (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_mul (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_mul (uint64_t a, uint64_t b, int mode, int *flags)
 
static uint16_t fp16_muladd (uint16_t a, uint16_t b, uint16_t c, int scale, int mode, int *flags)
 
static uint32_t fp32_muladd (uint32_t a, uint32_t b, uint32_t c, int scale, int mode, int *flags)
 
static uint64_t fp64_muladd (uint64_t a, uint64_t b, uint64_t c, int scale, int mode, int *flags)
 
static uint16_t fp16_div (uint16_t a, uint16_t b, int mode, int *flags)
 
static uint32_t fp32_div (uint32_t a, uint32_t b, int mode, int *flags)
 
static uint64_t fp64_div (uint64_t a, uint64_t b, int mode, int *flags)
 
static void set_fpscr0 (FPSCR &fpscr, int flags)
 
static uint16_t fp16_scale (uint16_t a, int16_t b, int mode, int *flags)
 
static uint32_t fp32_scale (uint32_t a, int32_t b, int mode, int *flags)
 
static uint64_t fp64_scale (uint64_t a, int64_t b, int mode, int *flags)
 
static uint16_t fp16_sqrt (uint16_t a, int mode, int *flags)
 
static uint32_t fp32_sqrt (uint32_t a, int mode, int *flags)
 
static uint64_t fp64_sqrt (uint64_t a, int mode, int *flags)
 
static int modeConv (FPSCR fpscr)
 
static void set_fpscr (FPSCR &fpscr, int flags)
 
template<>
bool fplibCompareEQ (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint16_t a, uint16_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareEQ (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint32_t a, uint32_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareEQ (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGE (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareGT (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
bool fplibCompareUN (uint64_t a, uint64_t b, FPSCR &fpscr)
 
template<>
uint16_t fplibAbs (uint16_t op)
 
template<>
uint32_t fplibAbs (uint32_t op)
 
template<>
uint64_t fplibAbs (uint64_t op)
 
template<>
uint16_t fplibAdd (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibAdd (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibAdd (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
int fplibCompare (uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr)
 
template<>
int fplibCompare (uint32_t op1, uint32_t op2, bool signal_nans, FPSCR &fpscr)
 
template<>
int fplibCompare (uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr)
 
static uint16_t fp16_FPConvertNaN_32 (uint32_t op)
 
static uint16_t fp16_FPConvertNaN_64 (uint64_t op)
 
static uint32_t fp32_FPConvertNaN_16 (uint16_t op)
 
static uint32_t fp32_FPConvertNaN_64 (uint64_t op)
 
static uint64_t fp64_FPConvertNaN_16 (uint16_t op)
 
static uint64_t fp64_FPConvertNaN_32 (uint32_t op)
 
static uint16_t fp16_FPOnePointFive (int sgn)
 
static uint32_t fp32_FPOnePointFive (int sgn)
 
static uint64_t fp64_FPOnePointFive (int sgn)
 
static uint16_t fp16_FPThree (int sgn)
 
static uint32_t fp32_FPThree (int sgn)
 
static uint64_t fp64_FPThree (int sgn)
 
static uint16_t fp16_FPTwo (int sgn)
 
static uint32_t fp32_FPTwo (int sgn)
 
static uint64_t fp64_FPTwo (int sgn)
 
template<>
uint16_t fplibConvert (uint32_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint16_t fplibConvert (uint64_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibConvert (uint16_t op, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint16_t fplibMulAdd (uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMulAdd (uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMulAdd (uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibDiv (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibDiv (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibDiv (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibExpA (uint16_t op)
 
template<>
uint32_t fplibExpA (uint32_t op)
 
template<>
uint64_t fplibExpA (uint64_t op)
 
static uint16_t fp16_repack (int sgn, int exp, uint16_t mnt)
 
static uint32_t fp32_repack (int sgn, int exp, uint32_t mnt)
 
static uint64_t fp64_repack (int sgn, int exp, uint64_t mnt)
 
static void fp16_minmaxnum (uint16_t *op1, uint16_t *op2, int sgn)
 
static void fp32_minmaxnum (uint32_t *op1, uint32_t *op2, int sgn)
 
static void fp64_minmaxnum (uint64_t *op1, uint64_t *op2, int sgn)
 
template<>
uint16_t fplibMax (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMax (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMax (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMaxNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMaxNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMaxNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMin (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMin (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMin (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMinNum (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMinNum (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMinNum (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibMulX (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibMulX (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibMulX (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibNeg (uint16_t op)
 
template<>
uint32_t fplibNeg (uint32_t op)
 
template<>
uint64_t fplibNeg (uint64_t op)
 
template<>
uint16_t fplibRSqrtEstimate (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRSqrtEstimate (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRSqrtEstimate (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRSqrtStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibRSqrtStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibRSqrtStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibRecipEstimate (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRecipEstimate (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRecipEstimate (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRecipStepFused (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibRecipStepFused (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibRecipStepFused (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibRecpX (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibRecpX (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibRecpX (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibRoundInt (uint16_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint32_t fplibRoundInt (uint32_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint64_t fplibRoundInt (uint64_t op, FPRounding rounding, bool exact, FPSCR &fpscr)
 
template<>
uint16_t fplibScale (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibScale (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibScale (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibSqrt (uint16_t op, FPSCR &fpscr)
 
template<>
uint32_t fplibSqrt (uint32_t op, FPSCR &fpscr)
 
template<>
uint64_t fplibSqrt (uint64_t op, FPSCR &fpscr)
 
template<>
uint16_t fplibSub (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibSub (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibSub (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigMulAdd (uint8_t coeff_index, uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigMulAdd (uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigMulAdd (uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigSMul (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigSMul (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigSMul (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
template<>
uint16_t fplibTrigSSel (uint16_t op1, uint16_t op2, FPSCR &fpscr)
 
template<>
uint32_t fplibTrigSSel (uint32_t op1, uint32_t op2, FPSCR &fpscr)
 
template<>
uint64_t fplibTrigSSel (uint64_t op1, uint64_t op2, FPSCR &fpscr)
 
static uint64_t FPToFixed_64 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
static uint32_t FPToFixed_32 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
static uint16_t FPToFixed_16 (int sgn, int exp, uint64_t mnt, bool u, FPRounding rounding, int *flags)
 
template<>
uint16_t fplibFPToFixed (uint16_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibFPToFixed (uint32_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
template<>
uint32_t fplibFPToFixed (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 
uint32_t fplibFPToFixedJS (uint64_t op, FPSCR &fpscr, bool Is64, uint8_t &nz)
 Floating-point JS convert to a signed integer, with rounding to zero. More...
 
static uint16_t fp16_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
static uint32_t fp32_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
static uint64_t fp64_cvtf (uint64_t a, int fbits, int u, int mode, int *flags)
 
template<>
uint16_t fplibFixedToFP (uint64_t op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert from fixed-point. More...
 
template<>
uint16_t fplibInfinity (int sgn)
 Floating-point value for +/- infinity. More...
 
template<>
uint16_t fplibDefaultNaN ()
 Foating-point value for default NaN. More...
 
static FPRounding FPCRRounding (FPSCR &fpscr)
 
template<class T >
fplibAbs (T op)
 Floating-point absolute value. More...
 
template<class T >
fplibAdd (T op1, T op2, FPSCR &fpscr)
 Floating-point add. More...
 
template<class T >
int fplibCompare (T op1, T op2, bool signal_nans, FPSCR &fpscr)
 Floating-point compare (quiet and signaling). More...
 
template<class T >
bool fplibCompareEQ (T op1, T op2, FPSCR &fpscr)
 Floating-point compare equal. More...
 
template<class T >
bool fplibCompareGE (T op1, T op2, FPSCR &fpscr)
 Floating-point compare greater than or equal. More...
 
template<class T >
bool fplibCompareGT (T op1, T op2, FPSCR &fpscr)
 Floating-point compare greater than. More...
 
template<class T >
bool fplibCompareUN (T op1, T op2, FPSCR &fpscr)
 Floating-point compare unordered. More...
 
template<class T1 , class T2 >
T2 fplibConvert (T1 op, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert precision. More...
 
template<class T >
fplibDiv (T op1, T op2, FPSCR &fpscr)
 Floating-point division. More...
 
template<class T >
fplibExpA (T op)
 Floating-point exponential accelerator. More...
 
template<class T >
fplibMax (T op1, T op2, FPSCR &fpscr)
 Floating-point maximum. More...
 
template<class T >
fplibMaxNum (T op1, T op2, FPSCR &fpscr)
 Floating-point maximum number. More...
 
template<class T >
fplibMin (T op1, T op2, FPSCR &fpscr)
 Floating-point minimum. More...
 
template<class T >
fplibMinNum (T op1, T op2, FPSCR &fpscr)
 Floating-point minimum number. More...
 
template<class T >
fplibMul (T op1, T op2, FPSCR &fpscr)
 Floating-point multiply. More...
 
template<class T >
fplibMulAdd (T addend, T op1, T op2, FPSCR &fpscr)
 Floating-point multiply-add. More...
 
template<class T >
fplibMulX (T op1, T op2, FPSCR &fpscr)
 Floating-point multiply extended. More...
 
template<class T >
fplibNeg (T op)
 Floating-point negate. More...
 
template<class T >
fplibRSqrtEstimate (T op, FPSCR &fpscr)
 Floating-point reciprocal square root estimate. More...
 
template<class T >
fplibRSqrtStepFused (T op1, T op2, FPSCR &fpscr)
 Floating-point reciprocal square root step. More...
 
template<class T >
fplibRecipEstimate (T op, FPSCR &fpscr)
 Floating-point reciprocal estimate. More...
 
template<class T >
fplibRecipStepFused (T op1, T op2, FPSCR &fpscr)
 Floating-point reciprocal step. More...
 
template<class T >
fplibRecpX (T op, FPSCR &fpscr)
 Floating-point reciprocal exponent. More...
 
template<class T >
fplibRoundInt (T op, FPRounding rounding, bool exact, FPSCR &fpscr)
 Floating-point convert to integer. More...
 
template<class T >
fplibScale (T op1, T op2, FPSCR &fpscr)
 Floating-point adjust exponent. More...
 
template<class T >
fplibSqrt (T op, FPSCR &fpscr)
 Floating-point square root. More...
 
template<class T >
fplibSub (T op1, T op2, FPSCR &fpscr)
 Floating-point subtract. More...
 
template<class T >
fplibTrigMulAdd (uint8_t coeff_index, T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric multiply-add coefficient. More...
 
template<class T >
fplibTrigSMul (T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric starting value. More...
 
template<class T >
fplibTrigSSel (T op1, T op2, FPSCR &fpscr)
 Floating-point trigonometric select coefficient. More...
 
template<class T1 , class T2 >
T2 fplibFPToFixed (T1 op, int fbits, bool u, FPRounding rounding, FPSCR &fpscr)
 Floating-point convert to fixed-point. More...
 
static unsigned int number_of_ones (int32_t val)
 
void writeVecElem (VReg *dest, XReg src, int index, int eSize)
 Write a single NEON vector element leaving the others untouched. More...
 
XReg readVecElem (VReg src, int index, int eSize)
 Read a single NEON vector element. More...
 
static uint32_t rotate_imm (uint32_t immValue, uint32_t rotateValue)
 
static uint32_t modified_imm (uint8_t ctrlImm, uint8_t dataImm)
 
static uint64_t simd_modified_imm (bool op, uint8_t cmode, uint8_t data, bool &immValid, bool isAarch64=false)
 
static uint64_t vfp_modified_imm (uint8_t data, FpDataType dtype)
 
static FpDataType decode_fp_data_type (uint8_t encoding)
 
static uint8_t getRestoredITBits (ThreadContext *tc, CPSR spsr)
 
static bool illegalExceptionReturn (ThreadContext *tc, CPSR cpsr, CPSR spsr)
 
const char * svePredTypeToStr (SvePredType pt)
 Returns the specifier for the predication type pt as a string. More...
 
std::string sveDisasmPredCountImm (uint8_t imm)
 Returns the symbolic name associated with pattern imm for PTRUE(S) instructions. More...
 
unsigned int sveDecodePredCount (uint8_t imm, unsigned int num_elems)
 Returns the actual number of elements active for PTRUE(S) instructions. More...
 
uint64_t sveExpandFpImmAddSub (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.5 or 1.0 (FADD, FSUB, FSUBR). More...
 
uint64_t sveExpandFpImmMaxMin (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.0 or 1.0 (FMAX, FMAXNM, FMIN, FMINNM). More...
 
uint64_t sveExpandFpImmMul (uint8_t imm, uint8_t size)
 Expand 1-bit floating-point immediate to 0.5 or 2.0 (FMUL). More...
 
VfpSavedState prepFpState (uint32_t rMode)
 
void finishVfp (FPSCR &fpscr, VfpSavedState state, bool flush, FPSCR mask)
 
template<class fpType >
fpType fixDest (bool flush, bool defaultNan, fpType val, fpType op1)
 
template float fixDest< float > (bool flush, bool defaultNan, float val, float op1)
 
template double fixDest< double > (bool flush, bool defaultNan, double val, double op1)
 
template<class fpType >
fpType fixDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
 
template float fixDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
 
template double fixDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
 
template<class fpType >
fpType fixDivDest (bool flush, bool defaultNan, fpType val, fpType op1, fpType op2)
 
template float fixDivDest< float > (bool flush, bool defaultNan, float val, float op1, float op2)
 
template double fixDivDest< double > (bool flush, bool defaultNan, double val, double op1, double op2)
 
float fixFpDFpSDest (FPSCR fpscr, double val)
 
double fixFpSFpDDest (FPSCR fpscr, float val)
 
static uint16_t vcvtFpFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, uint64_t opBits, bool isDouble)
 
uint16_t vcvtFpSFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, float op)
 
uint16_t vcvtFpDFpH (FPSCR &fpscr, bool flush, bool defaultNan, uint32_t rMode, bool ahp, double op)
 
static uint64_t vcvtFpHFp (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op, bool isDouble)
 
double vcvtFpHFpD (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
 
float vcvtFpHFpS (FPSCR &fpscr, bool defaultNan, bool ahp, uint16_t op)
 
float vfpUFixedToFpS (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
 
float vfpSFixedToFpS (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
 
double vfpUFixedToFpD (bool flush, bool defaultNan, uint64_t val, uint8_t width, uint8_t imm)
 
double vfpSFixedToFpD (bool flush, bool defaultNan, int64_t val, uint8_t width, uint8_t imm)
 
static double recipSqrtEstimate (double a)
 
float fprSqrtEstimate (FPSCR &fpscr, float op)
 
uint32_t unsignedRSqrtEstimate (uint32_t op)
 
static double recipEstimate (double a)
 
float fpRecipEstimate (FPSCR &fpscr, float op)
 
uint32_t unsignedRecipEstimate (uint32_t op)
 
FPSCR fpStandardFPSCRValue (const FPSCR &fpscr)
 
template<class T >
static void setVfpMicroFlags (VfpMicroMode mode, T &flags)
 
static float bitsToFp (uint64_t, float)
 
static double bitsToFp (uint64_t, double)
 
static uint32_t fpToBits (float)
 
static uint64_t fpToBits (double)
 
template<class fpType >
static bool flushToZero (fpType &op)
 
template<class fpType >
static bool flushToZero (fpType &op1, fpType &op2)
 
template<class fpType >
static void vfpFlushToZero (FPSCR &fpscr, fpType &op)
 
template<class fpType >
static void vfpFlushToZero (FPSCR &fpscr, fpType &op1, fpType &op2)
 
template<class fpType >
static bool isSnan (fpType val)
 
template<class fpType >
fpType fixDest (FPSCR fpscr, fpType val, fpType op1)
 
template<class fpType >
fpType fixDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
 
template<class fpType >
fpType fixDivDest (FPSCR fpscr, fpType val, fpType op1, fpType op2)
 
static double makeDouble (uint32_t low, uint32_t high)
 
static uint32_t lowFromDouble (double val)
 
static uint32_t highFromDouble (double val)
 
static void setFPExceptions (int exceptions)
 
template<typename T >
uint64_t vfpFpToFixed (T val, bool isSigned, uint8_t width, uint8_t imm, bool useRmode=true, VfpRoundingMode roundMode=VfpRoundZero, bool aarch64=false)
 
template<typename T >
static T fpAdd (T a, T b)
 
template<typename T >
static T fpSub (T a, T b)
 
static float fpAddS (float a, float b)
 
static double fpAddD (double a, double b)
 
static float fpSubS (float a, float b)
 
static double fpSubD (double a, double b)
 
static float fpDivS (float a, float b)
 
static double fpDivD (double a, double b)
 
template<typename T >
static T fpDiv (T a, T b)
 
template<typename T >
static T fpMulX (T a, T b)
 
template<typename T >
static T fpMul (T a, T b)
 
static float fpMulS (float a, float b)
 
static double fpMulD (double a, double b)
 
template<typename T >
static T fpMulAdd (T op1, T op2, T addend)
 
template<typename T >
static T fpRIntX (T a, FPSCR &fpscr)
 
template<typename T >
static T fpMaxNum (T a, T b)
 
template<typename T >
static T fpMax (T a, T b)
 
template<typename T >
static T fpMinNum (T a, T b)
 
template<typename T >
static T fpMin (T a, T b)
 
template<typename T >
static T fpRSqrts (T a, T b)
 
template<typename T >
static T fpRecps (T a, T b)
 
static float fpRSqrtsS (float a, float b)
 
static float fpRecpsS (float a, float b)
 
template<typename T >
static T roundNEven (T a)
 
static void copyVecRegs (ThreadContext *src, ThreadContext *dest)
 
static SyscallReturn unameFunc32 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn unameFunc64 (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
static SyscallReturn setTLSFunc32 (SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
 Target set_tls() handler. More...
 
static SyscallReturn setTLSFunc64 (SyscallDesc *desc, ThreadContext *tc, uint32_t tlsPtr)
 
template<class XC >
void handleLockedSnoop (XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 
template<class XC >
void handleLockedRead (XC *xc, const RequestPtr &req)
 
template<class XC >
void handleLockedSnoopHit (XC *xc)
 
template<class XC >
bool handleLockedWrite (XC *xc, const RequestPtr &req, Addr cacheBlockMask)
 
template<class XC >
void globalClearExclusive (XC *xc)
 
template<typename T >
MMUgetMMUPtr (T *tc)
 
bool upperAndLowerRange (ThreadContext *tc, ExceptionLevel el)
 
bool calculateTBI (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, bool data)
 
int calculateBottomPACBit (ThreadContext *tc, ExceptionLevel el, bool top_bit)
 
Fault trapPACUse (ThreadContext *tc, ExceptionLevel el)
 
uint64_t addPAC (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t k0, bool data)
 
uint64_t auth (ThreadContext *tc, ExceptionLevel el, uint64_t ptr, uint64_t modifier, uint64_t k1, uint64_t K0, bool data, uint8_t errorcode)
 
Fault authDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault authIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACDA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACDB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACGA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACIA (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault addPACIB (ThreadContext *tc, uint64_t X, uint64_t Y, uint64_t *out)
 
Fault stripPAC (ThreadContext *tc, uint64_t A, bool data, uint64_t *out)
 
 BitUnion8 (ITSTATE) Bitfield< 7
 
 BitUnion32 (PackedIntReg) Bitfield< 31
 
 EndBitUnion (PackedIntReg) enum IntRegIndex
 
static IntRegIndex INTREG_USR (unsigned index)
 
static IntRegIndex INTREG_HYP (unsigned index)
 
static IntRegIndex INTREG_SVC (unsigned index)
 
static IntRegIndex INTREG_MON (unsigned index)
 
static IntRegIndex INTREG_ABT (unsigned index)
 
static IntRegIndex INTREG_UND (unsigned index)
 
static IntRegIndex INTREG_IRQ (unsigned index)
 
static IntRegIndex INTREG_FIQ (unsigned index)
 
static int intRegInMode (OperatingMode mode, int reg)
 
static int flattenIntRegModeIndex (int reg)
 
static IntRegIndex makeSP (IntRegIndex reg)
 
static IntRegIndex makeZero (IntRegIndex reg)
 
static bool isSP (IntRegIndex reg)
 
MiscRegIndex decodeCP14Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex decodeCP15Reg (unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 
MiscRegIndex decodeCP15Reg64 (unsigned crm, unsigned opc1)
 
std::tuple< bool, bool > canReadCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to read coprocessor registers. More...
 
std::tuple< bool, bool > canWriteCoprocReg (MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
 Check for permission to write coprocessor registers. More...
 
bool AArch32isUndefinedGenericTimer (MiscRegIndex reg, ThreadContext *tc)
 
int snsBankedIndex (MiscRegIndex reg, ThreadContext *tc)
 
int snsBankedIndex (MiscRegIndex reg, ThreadContext *tc, bool ns)
 
int snsBankedIndex64 (MiscRegIndex reg, ThreadContext *tc)
 
void preUnflattenMiscReg ()
 
int unflattenMiscReg (int reg)
 
bool canReadAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
bool canWriteAArch64SysReg (MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc)
 
MiscRegIndex decodeAArch64SysReg (unsigned op0, unsigned op1, unsigned crn, unsigned crm, unsigned op2)
 
bool aarch64SysRegReadOnly (MiscRegIndex miscReg)
 
 BitUnion32 (CPSR) Bitfield< 31
 
 EndBitUnion (CPSR) BitUnion64(AA64DFR0) Bitfield< 43
 
 EndBitUnion (AA64DFR0) BitUnion64(AA64ISAR0) Bitfield< 63
 
 EndBitUnion (AA64ISAR0) BitUnion64(AA64ISAR1) Bitfield< 43
 
 EndBitUnion (AA64ISAR1) BitUnion64(AA64MMFR0) Bitfield< 63
 
 EndBitUnion (AA64MMFR0) BitUnion64(AA64MMFR1) Bitfield< 31
 
 EndBitUnion (AA64MMFR1) BitUnion64(AA64MMFR2) Bitfield< 63
 
 EndBitUnion (AA64MMFR2) BitUnion64(AA64PFR0) Bitfield< 63
 
 EndBitUnion (AA64PFR0) BitUnion32(HDCR) Bitfield< 11 > tdra
 
 EndBitUnion (HDCR) BitUnion32(HCPTR) Bitfield< 31 > tcpac
 
 EndBitUnion (HCPTR) BitUnion32(HSTR) Bitfield< 17 > tjdbx
 
 EndBitUnion (HSTR) BitUnion64(HCR) Bitfield< 47 > fien
 
 EndBitUnion (HCR) BitUnion32(NSACR) Bitfield< 20 > nstrcdis
 
 EndBitUnion (NSACR) BitUnion32(SCR) Bitfield< 21 > fien
 
 EndBitUnion (SCR) BitUnion32(SCTLR) Bitfield< 31 > enia
 
 EndBitUnion (SCTLR) BitUnion32(CPACR) Bitfield< 1
 
 EndBitUnion (CPACR) BitUnion32(FSR) Bitfield< 3
 
 EndBitUnion (FSR) BitUnion32(FPSCR) Bitfield< 0 > ioc
 
 EndBitUnion (FPSCR) BitUnion32(FPEXC) Bitfield< 31 > ex
 
 EndBitUnion (FPEXC) BitUnion32(MVFR0) Bitfield< 3
 
 EndBitUnion (MVFR0) BitUnion32(MVFR1) Bitfield< 3
 
 EndBitUnion (MVFR1) BitUnion64(TTBCR) Bitfield< 2
 
 EndBitUnion (TTBCR) BitUnion64(TCR) Bitfield< 5
 
 EndBitUnion (TCR) BitUnion32(HTCR) Bitfield< 2
 
 EndBitUnion (HTCR) BitUnion32(VTCR_t) Bitfield< 3
 
 EndBitUnion (VTCR_t) BitUnion32(PRRR) Bitfield< 1
 
 EndBitUnion (PRRR) BitUnion32(NMRR) Bitfield< 1
 
 EndBitUnion (NMRR) BitUnion32(CONTEXTIDR) Bitfield< 7
 
 EndBitUnion (CONTEXTIDR) BitUnion32(L2CTLR) Bitfield< 2
 
 EndBitUnion (L2CTLR) BitUnion32(CTR) Bitfield< 3
 
 EndBitUnion (CTR) BitUnion32(PMSELR) Bitfield< 4
 
 EndBitUnion (PMSELR) BitUnion64(PAR) Bitfield< 63
 
 EndBitUnion (PAR) BitUnion32(ESR) Bitfield< 31
 
 EndBitUnion (ESR) BitUnion32(CPTR) Bitfield< 31 > tcpac
 
 EndBitUnion (CPTR) BitUnion64(ZCR) Bitfield< 3
 
 EndBitUnion (ZCR) BitUnion32(OSL) Bitfield< 64
 
 EndBitUnion (OSL) BitUnion64(DBGBCR) Bitfield< 63
 
 EndBitUnion (DBGBCR) BitUnion64(DBGWCR) Bitfield< 63
 
 EndBitUnion (DBGWCR) BitUnion32(DBGDS32) Bitfield< 31 > tfo
 
 EndBitUnion (DBGDS32) BitUnion32(DBGVCR) Bitfield< 31 > nsf
 
 EndBitUnion (DBGVCR) BitUnion32(DEVID) Bitfield< 31
 
 BitUnion64 (ExtMachInst) Bitfield< 63
 
 SubBitUnion (puswl, 24, 20) Bitfield< 24 > prepost
 
 EndSubBitUnion (puswl) Bitfield< 24
 
 EndBitUnion (ExtMachInst) enum ArmShiftType
 
 BitUnion8 (OperatingMode64) Bitfield< 0 > spX
 
 EndBitUnion (OperatingMode64) static bool inline opModeIs64(OperatingMode mode)
 
static bool opModeIsH (OperatingMode mode)
 
static bool opModeIsT (OperatingMode mode)
 
static ExceptionLevel opModeToEL (OperatingMode mode)
 
static bool unknownMode (OperatingMode mode)
 
static bool unknownMode32 (OperatingMode mode)
 
void sendEvent (ThreadContext *tc)
 Send an event (SEV) to a specific PE if there isn't already a pending event. More...
 
bool isSecure (ThreadContext *tc)
 
bool isSecureBelowEL3 (ThreadContext *tc)
 
ExceptionLevel debugTargetFrom (ThreadContext *tc, bool secure)
 
bool inAArch64 (ThreadContext *tc)
 
bool longDescFormatInUse (ThreadContext *tc)
 
RegVal readMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is either returing the value of MPIDR_EL1 (by calling getMPIDR), or it is issuing a read to VMPIDR_EL2 (as it happens in virtualized systems) More...
 
RegVal getMPIDR (ArmSystem *arm_sys, ThreadContext *tc)
 This helper function is returning the value of MPIDR_EL1. More...
 
static RegVal getAff2 (ArmSystem *arm_sys, ThreadContext *tc)
 
static RegVal getAff1 (ArmSystem *arm_sys, ThreadContext *tc)
 
static RegVal getAff0 (ArmSystem *arm_sys, ThreadContext *tc)
 
RegVal getAffinity (ArmSystem *arm_sys, ThreadContext *tc)
 Retrieves MPIDR_EL1. More...
 
bool HavePACExt (ThreadContext *tc)
 
bool HaveVirtHostExt (ThreadContext *tc)
 
bool HaveLVA (ThreadContext *tc)
 
ExceptionLevel s1TranslationRegime (ThreadContext *tc, ExceptionLevel el)
 
bool HaveSecureEL2Ext (ThreadContext *tc)
 
bool IsSecureEL2Enabled (ThreadContext *tc)
 
bool EL2Enabled (ThreadContext *tc)
 
bool ELIs64 (ThreadContext *tc, ExceptionLevel el)
 
bool ELIs32 (ThreadContext *tc, ExceptionLevel el)
 
bool ELIsInHost (ThreadContext *tc, ExceptionLevel el)
 Returns true if the current exception level el is executing a Host OS or an application of a Host OS (Armv8.1 Virtualization Host Extensions). More...
 
std::pair< bool, bool > ELUsingAArch32K (ThreadContext *tc, ExceptionLevel el)
 This function checks whether selected EL provided as an argument is using the AArch32 ISA. More...
 
bool haveAArch32EL (ThreadContext *tc, ExceptionLevel el)
 
std::pair< bool, bool > ELStateUsingAArch32K (ThreadContext *tc, ExceptionLevel el, bool secure)
 
bool ELStateUsingAArch32 (ThreadContext *tc, ExceptionLevel el, bool secure)
 
bool isBigEndian64 (const ThreadContext *tc)
 
bool badMode32 (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented for AArch32 More...
 
bool badMode (ThreadContext *tc, OperatingMode mode)
 badMode is checking if the execution mode provided as an argument is valid and implemented. More...
 
int computeAddrTop (ThreadContext *tc, bool selbit, bool isInstr, TCR tcr, ExceptionLevel el)
 
Addr purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, TCR tcr, bool isInstr)
 Removes the tag from tagged addresses if that mode is enabled. More...
 
Addr purifyTaggedAddr (Addr addr, ThreadContext *tc, ExceptionLevel el, bool isInstr)
 
Addr truncPage (Addr addr)
 
Addr roundPage (Addr addr)
 
Fault mcrMrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
 
bool mcrMrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
 
bool mcrMrc14TrapToHyp (const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
 
Fault mcrrMrrc15Trap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm)
 
bool mcrrMrrc15TrapToHyp (const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss, ExceptionClass *ec)
 
Fault AArch64AArch32SystemAccessTrap (const MiscRegIndex miscReg, ExtMachInst machInst, ThreadContext *tc, uint32_t imm, ExceptionClass ec)
 
bool isAArch64AArch32SystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
 
bool isGenericTimerCommonEL0HypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
 
bool isGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc, ExceptionClass *ec)
 
bool condGenericTimerPhysHypTrap (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerSystemAccessTrapEL1 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isAArch64AArch32SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerPhysEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerVirtSystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerCommonEL0SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerCommonEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool condGenericTimerPhysEL1SystemAccessTrapEL2 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool isGenericTimerSystemAccessTrapEL3 (const MiscRegIndex miscReg, ThreadContext *tc)
 
bool decodeMrsMsrBankedReg (uint8_t sysM, bool r, bool &isIntReg, int &regIdx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
 
bool isUnpriviledgeAccess (ThreadContext *tc)
 
bool SPAlignmentCheckEnabled (ThreadContext *tc)
 
int decodePhysAddrRange64 (uint8_t pa_enc)
 Returns the n. More...
 
uint8_t encodePhysAddrRange64 (int pa_size)
 Returns the encoding corresponding to the specified n. More...
 
bool testPredicate (uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
 
static bool inUserMode (CPSR cpsr)
 
static bool inPrivilegedMode (CPSR cpsr)
 
static OperatingMode currOpMode (const ThreadContext *tc)
 
static ExceptionLevel currEL (const ThreadContext *tc)
 
ExceptionLevel currEL (CPSR cpsr)
 
static uint8_t itState (CPSR psr)
 
static bool inSecureState (SCR scr, CPSR cpsr)
 
static uint32_t mcrMrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn, uint32_t opc1, uint32_t opc2)
 
static void mcrMrcIssExtract (uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt, uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
 
static uint32_t mcrrMrrcIssBuild (bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2, uint32_t opc1)
 
static uint32_t msrMrs64IssBuild (bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, IntRegIndex rt)
 
static int decodeMrsMsrBankedIntRegIndex (uint8_t sysM, bool r)
 
ByteOrder byteOrder (const ThreadContext *tc)
 
 BitUnion64 (CNTKCTL) Bitfield< 17 > evntis
 
 EndBitUnion (CNTKCTL) BitUnion64(CNTHCTL) Bitfield< 17 > evntis
 
 EndBitUnion (CNTHCTL) BitUnion64(CNTHCTL_E2H) Bitfield< 17 > evntis
 

Variables

const uint32_t HighVecs = 0xFFFF0000
 
static SyscallDescTable< EmuFreebsd::SyscallABI32syscallDescs32 ({})
 
static SyscallDescTable< EmuFreebsd::SyscallABI64syscallDescs64
 
static const uint8_t recip_sqrt_estimate [256]
 
static SyscallTable32 syscallDescs32Low (0)
 
static SyscallTable32 syscallDescs32High (0x900000)
 
static SyscallTable64 syscallDescs64Low (0)
 
static SyscallTable64 syscallDescs64High (0x900000)
 
static SyscallDescTable< EmuLinux::SyscallABI32privSyscallDescs32
 
static SyscallDescTable< EmuLinux::SyscallABI64privSyscallDescs64
 
const Addr PageShift = 12
 
const Addr PageBytes = 1ULL << PageShift
 
const unsigned MaxPhysAddrRange = 52
 
 cond
 
Bitfield< 3, 0 > mask
 
Bitfield< 7, 2 > top6
 
Bitfield< 1, 0 > bottom2
 
const char *const ccRegName [NUM_CCREGS]
 
 uh1
 
Bitfield< 15, 0 > uh0
 
SignedBitfield< 31, 16 > sh1
 
SignedBitfield< 15, 0 > sh0
 
Bitfield< 31, 0 > uw
 
SignedBitfield< 31, 0 > sw
 
const IntRegMap IntReg64Map
 
const IntRegMap IntRegUsrMap
 
const IntRegMap IntRegHypMap
 
const IntRegMap IntRegSvcMap
 
const IntRegMap IntRegMonMap
 
const IntRegMap IntRegAbtMap
 
const IntRegMap IntRegUndMap
 
const IntRegMap IntRegIrqMap
 
const IntRegMap IntRegFiqMap
 
static const unsigned intRegsPerMode = NUM_INTREGS
 
const int ReturnValueReg = 0
 
const int ReturnValueReg1 = 1
 
const int ReturnValueReg2 = 2
 
const int NumArgumentRegs = 4
 
const int NumArgumentRegs64 = 8
 
const int ArgumentReg0 = 0
 
const int ArgumentReg1 = 1
 
const int ArgumentReg2 = 2
 
const int ArgumentReg3 = 3
 
const int FramePointerReg = 11
 
const int StackPointerReg = INTREG_SP
 
const int ReturnAddressReg = INTREG_LR
 
const int PCReg = INTREG_PC
 
const int SyscallNumReg = ReturnValueReg
 
const int SyscallPseudoReturnReg = ReturnValueReg
 
const int SyscallSuccessReg = ReturnValueReg
 
int unflattenResultMiscReg [NUM_MISCREGS]
 If the reg is a child reg of a banked set, then the parent is the last banked one in the list. More...
 
std::bitset< NUM_MISCREG_INFOSmiscRegInfo [NUM_MISCREGS]
 
const char *const miscRegName []
 
static const uint32_t CondCodesMask = 0xF00F0000
 
static const uint32_t CpsrMaskQ = 0x08000000
 
static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0
 
static const uint32_t CpsrMask = ApsrMask | 0x00F003DF
 
static const uint32_t FpCondCodesMask = 0xF0000000
 
static const uint32_t FpscrQcMask = 0x08000000
 
static const uint32_t FpscrAhpMask = 0x04000000
 
static const uint32_t FpscrExcMask = 0x0000009F
 
 nz
 
Bitfield< 29 > c
 
Bitfield< 28 > v
 
Bitfield< 27 > q
 
Bitfield< 26, 25 > it1
 
Bitfield< 24 > j
 
Bitfield< 22 > pan
 
Bitfield< 21 > ss
 
Bitfield< 20 > il
 
Bitfield< 19, 16 > ge
 
Bitfield< 15, 10 > it2
 
Bitfield< 9 > d
 
Bitfield< 9 > e
 
Bitfield< 8 > a
 
Bitfield< 7 > i
 
Bitfield< 6 > f
 
Bitfield< 8, 6 > aif
 
Bitfield< 9, 6 > daif
 
Bitfield< 5 > t
 
Bitfield< 4 > width
 
Bitfield< 3, 2 > el
 
Bitfield< 4, 0 > mode
 
Bitfield< 0 > sp
 
 tracefilt
 
Bitfield< 39, 36 > doublelock
 
Bitfield< 35, 32 > pmsver
 
Bitfield< 31, 28 > ctx_cmps
 
Bitfield< 23, 20 > wrps
 
Bitfield< 15, 12 > brps
 
Bitfield< 11, 8 > pmuver
 
Bitfield< 7, 4 > tracever
 
Bitfield< 3, 0 > debugver
 
 rndr
 
Bitfield< 59, 56 > tlb
 
Bitfield< 55, 52 > ts
 
Bitfield< 51, 48 > fhm
 
Bitfield< 47, 44 > dp
 
Bitfield< 43, 40 > sm4
 
Bitfield< 39, 36 > sm3
 
Bitfield< 35, 32 > sha3
 
Bitfield< 31, 28 > rdm
 
Bitfield< 23, 20 > atomic
 
Bitfield< 19, 16 > crc32
 
Bitfield< 15, 12 > sha2
 
Bitfield< 11, 8 > sha1
 
Bitfield< 3, 0 > aes
 
 specres
 
Bitfield< 39, 36 > sb
 
Bitfield< 35, 32 > frintts
 
Bitfield< 31, 28 > gpi
 
Bitfield< 27, 24 > gpa
 
Bitfield< 23, 20 > lrcpc
 
Bitfield< 19, 16 > fcma
 
Bitfield< 15, 12 > jscvt
 
Bitfield< 11, 8 > api
 
Bitfield< 7, 4 > apa
 
Bitfield< 3, 0 > dpb
 
 ecv
 
Bitfield< 47, 44 > exs
 
Bitfield< 43, 40 > tgran4_2
 
Bitfield< 39, 36 > tgran64_2
 
Bitfield< 35, 32 > tgran16_2
 
Bitfield< 31, 28 > tgran4
 
Bitfield< 27, 24 > tgran64
 
Bitfield< 23, 20 > tgran16
 
Bitfield< 19, 16 > bigendEL0
 
Bitfield< 15, 12 > snsmem
 
Bitfield< 11, 8 > bigend
 
Bitfield< 7, 4 > asidbits
 
Bitfield< 3, 0 > parange
 
 xnx
 
Bitfield< 27, 24 > specsei
 
Bitfield< 19, 16 > lo
 
Bitfield< 15, 12 > hpds
 
Bitfield< 11, 8 > vh
 
Bitfield< 7, 4 > vmidbits
 
Bitfield< 3, 0 > hafdbs
 
 e0pd
 
Bitfield< 59, 56 > evt
 
Bitfield< 55, 52 > bbm
 
Bitfield< 51, 48 > ttl
 
Bitfield< 43, 40 > fwb
 
Bitfield< 39, 36 > ids
 
Bitfield< 35, 32 > at
 
Bitfield< 31, 28 > st
 
Bitfield< 27, 24 > nv
 
Bitfield< 23, 20 > ccidx
 
Bitfield< 19, 16 > varange
 
Bitfield< 15, 12 > iesb
 
Bitfield< 11, 8 > lsm
 
Bitfield< 7, 4 > uao
 
Bitfield< 3, 0 > cnp
 
 csv3
 
Bitfield< 59, 56 > csv2
 
Bitfield< 51, 48 > dit
 
Bitfield< 47, 44 > amu
 
Bitfield< 43, 40 > mpam
 
Bitfield< 39, 36 > sel2
 
Bitfield< 35, 32 > sve
 
Bitfield< 31, 28 > ras
 
Bitfield< 27, 24 > gic
 
Bitfield< 23, 20 > advsimd
 
Bitfield< 19, 16 > fp
 
Bitfield< 15, 12 > el3
 
Bitfield< 11, 8 > el2
 
Bitfield< 7, 4 > el1
 
Bitfield< 3, 0 > el0
 
Bitfield< 10 > tdosa
 
Bitfield< 9 > tda
 
Bitfield< 8 > tde
 
Bitfield< 7 > hpme
 
Bitfield< 6 > tpm
 
Bitfield< 5 > tpmcr
 
Bitfield< 4, 0 > hpmn
 
Bitfield< 20 > tta
 
Bitfield< 15 > tase
 
Bitfield< 13 > tcp13
 
Bitfield< 12 > tcp12
 
Bitfield< 11 > tcp11
 
Bitfield< 10 > tcp10
 
Bitfield< 10 > tfp
 
Bitfield< 9 > tcp9
 
Bitfield< 8 > tcp8
 
Bitfield< 8 > tz
 
Bitfield< 7 > tcp7
 
Bitfield< 6 > tcp6
 
Bitfield< 5 > tcp5
 
Bitfield< 4 > tcp4
 
Bitfield< 3 > tcp3
 
Bitfield< 2 > tcp2
 
Bitfield< 1 > tcp1
 
Bitfield< 0 > tcp0
 
Bitfield< 16 > ttee
 
Bitfield< 15 > t15
 
Bitfield< 13 > t13
 
Bitfield< 12 > t12
 
Bitfield< 11 > t11
 
Bitfield< 10 > t10
 
Bitfield< 9 > t9
 
Bitfield< 8 > t8
 
Bitfield< 7 > t7
 
Bitfield< 6 > t6
 
Bitfield< 5 > t5
 
Bitfield< 4 > t4
 
Bitfield< 3 > t3
 
Bitfield< 2 > t2
 
Bitfield< 1 > t1
 
Bitfield< 0 > t0
 
Bitfield< 45 > nv2
 
Bitfield< 43 > nv1
 
Bitfield< 40 > apk
 
Bitfield< 38 > miocnce
 
Bitfield< 37 > tea
 
Bitfield< 36 > terr
 
Bitfield< 35 > tlor
 
Bitfield< 34 > e2h
 
Bitfield< 33 > id
 
Bitfield< 32 > cd
 
Bitfield< 31 > rw
 
Bitfield< 30 > trvm
 
Bitfield< 29 > hcd
 
Bitfield< 28 > tdz
 
Bitfield< 27 > tge
 
Bitfield< 26 > tvm
 
Bitfield< 25 > ttlb
 
Bitfield< 24 > tpu
 
Bitfield< 23 > tpc
 
Bitfield< 22 > tsw
 
Bitfield< 21 > tac
 
Bitfield< 21 > tacr
 
Bitfield< 20 > tidcp
 
Bitfield< 19 > tsc
 
Bitfield< 18 > tid3
 
Bitfield< 17 > tid2
 
Bitfield< 16 > tid1
 
Bitfield< 15 > tid0
 
Bitfield< 14 > twe
 
Bitfield< 13 > twi
 
Bitfield< 12 > dc
 
Bitfield< 11, 10 > bsu
 
Bitfield< 9 > fb
 
Bitfield< 8 > va
 
Bitfield< 8 > vse
 
Bitfield< 7 > vi
 
Bitfield< 6 > vf
 
Bitfield< 5 > amo
 
Bitfield< 4 > imo
 
Bitfield< 3 > fmo
 
Bitfield< 2 > ptw
 
Bitfield< 1 > swio
 
Bitfield< 0 > vm
 
Bitfield< 19 > rfr
 
Bitfield< 15 > nsasedis
 
Bitfield< 14 > nsd32dis
 
Bitfield< 13 > cp13
 
Bitfield< 12 > cp12
 
Bitfield< 11 > cp11
 
Bitfield< 10 > cp10
 
Bitfield< 9 > cp9
 
Bitfield< 8 > cp8
 
Bitfield< 7 > cp7
 
Bitfield< 6 > cp6
 
Bitfield< 5 > cp5
 
Bitfield< 4 > cp4
 
Bitfield< 3 > cp3
 
Bitfield< 2 > cp2
 
Bitfield< 1 > cp1
 
Bitfield< 0 > cp0
 
Bitfield< 20 > nmea
 
Bitfield< 19 > ease
 
Bitfield< 18 > eel2
 
Bitfield< 15 > teer
 
Bitfield< 9 > sif
 
Bitfield< 8 > hce
 
Bitfield< 7 > scd
 
Bitfield< 7 > smd
 
Bitfield< 6 > nEt
 
Bitfield< 5 > aw
 
Bitfield< 4 > fw
 
Bitfield< 3 > ea
 
Bitfield< 2 > fiq
 
Bitfield< 1 > irq
 
Bitfield< 0 > ns
 
Bitfield< 30 > enib
 
Bitfield< 30 > te
 
Bitfield< 29 > afe
 
Bitfield< 28 > tre
 
Bitfield< 27 > nmfi
 
Bitfield< 27 > enda
 
Bitfield< 26 > uci
 
Bitfield< 25 > ee
 
Bitfield< 24 > e0e
 
Bitfield< 23 > span
 
Bitfield< 23 > xp
 
Bitfield< 22 > u
 
Bitfield< 21 > fi
 
Bitfield< 20 > uwxn
 
Bitfield< 19 > dz
 
Bitfield< 19 > wxn
 
Bitfield< 18 > ntwe
 
Bitfield< 18 > rao2
 
Bitfield< 16 > ntwi
 
Bitfield< 16 > rao3
 
Bitfield< 15 > uct
 
Bitfield< 14 > rr
 
Bitfield< 14 > dze
 
Bitfield< 13 > endb
 
Bitfield< 11 > z
 
Bitfield< 9, 8 > rs
 
Bitfield< 9 > uma
 
Bitfield< 8 > sed
 
Bitfield< 7 > b
 
Bitfield< 7 > itd
 
Bitfield< 6, 3 > rao4
 
Bitfield< 6 > thee
 
Bitfield< 5 > cp15ben
 
Bitfield< 4 > sa0
 
Bitfield< 3 > sa
 
Bitfield< 0 > m
 
Bitfield< 17, 16 > zen
 
Bitfield< 21, 20 > fpen
 
Bitfield< 29, 28 > rsvd
 
Bitfield< 30 > d32dis
 
Bitfield< 31 > asedis
 
 fsLow
 
Bitfield< 5, 0 > status
 
Bitfield< 7, 4 > domain
 
Bitfield< 9 > lpae
 
Bitfield< 10 > fsHigh
 
Bitfield< 11 > wnr
 
Bitfield< 12 > ext
 
Bitfield< 13 > cm
 
Bitfield< 1 > dzc
 
Bitfield< 2 > ofc
 
Bitfield< 3 > ufc
 
Bitfield< 4 > ixc
 
Bitfield< 7 > idc
 
Bitfield< 8 > ioe
 
Bitfield< 10 > ofe
 
Bitfield< 11 > ufe
 
Bitfield< 12 > ixe
 
Bitfield< 15 > ide
 
Bitfield< 18, 16 > len
 
Bitfield< 19 > fz16
 
Bitfield< 21, 20 > stride
 
Bitfield< 23, 22 > rMode
 
Bitfield< 24 > fz
 
Bitfield< 25 > dn
 
Bitfield< 26 > ahp
 
Bitfield< 27 > qc
 
Bitfield< 31 > n
 
Bitfield< 30 > en
 
Bitfield< 29, 0 > subArchDefined
 
 advSimdRegisters
 
Bitfield< 7, 4 > singlePrecision
 
Bitfield< 11, 8 > doublePrecision
 
Bitfield< 15, 12 > vfpExceptionTrapping
 
Bitfield< 19, 16 > divide
 
Bitfield< 23, 20 > squareRoot
 
Bitfield< 27, 24 > shortVectors
 
Bitfield< 31, 28 > roundingModes
 
 flushToZero
 
Bitfield< 7, 4 > defaultNaN
 
Bitfield< 11, 8 > advSimdLoadStore
 
Bitfield< 15, 12 > advSimdInteger
 
Bitfield< 19, 16 > advSimdSinglePrecision
 
Bitfield< 23, 20 > advSimdHalfPrecision
 
Bitfield< 27, 24 > vfpHalfPrecision
 
Bitfield< 31, 28 > raz
 
Bitfield< 4 > pd0
 
Bitfield< 5 > pd1
 
Bitfield< 2, 0 > t0sz
 
Bitfield< 6 > t2e
 
Bitfield< 7 > epd0
 
Bitfield< 9, 8 > irgn0
 
Bitfield< 11, 10 > orgn0
 
Bitfield< 14 > tg0
 
Bitfield< 18, 16 > t1sz
 
Bitfield< 22 > a1
 
Bitfield< 23 > epd1
 
Bitfield< 25, 24 > irgn1
 
Bitfield< 27, 26 > orgn1
 
Bitfield< 30 > tg1
 
Bitfield< 34, 32 > ips
 
Bitfield< 36 > as
 
Bitfield< 37 > tbi0
 
Bitfield< 38 > tbi1
 
Bitfield< 31 > eae
 
Bitfield< 18, 16 > ps
 
Bitfield< 20 > tbi
 
Bitfield< 41 > hpd0
 
Bitfield< 42 > hpd1
 
Bitfield< 24 > hpd
 
Bitfield< 29 > tbid
 
Bitfield< 39 > ha
 
Bitfield< 40 > hd
 
Bitfield< 51 > tbid0
 
Bitfield< 52 > tbid1
 
Bitfield< 4 > s
 
Bitfield< 5, 0 > t0sz64
 
Bitfield< 7, 6 > sl0
 
Bitfield< 19 > vs
 
 tr0
 
Bitfield< 3, 2 > tr1
 
Bitfield< 5, 4 > tr2
 
Bitfield< 7, 6 > tr3
 
Bitfield< 9, 8 > tr4
 
Bitfield< 11, 10 > tr5
 
Bitfield< 13, 12 > tr6
 
Bitfield< 15, 14 > tr7
 
Bitfield< 16 > ds0
 
Bitfield< 17 > ds1
 
Bitfield< 18 > ns0
 
Bitfield< 19 > ns1
 
Bitfield< 24 > nos0
 
Bitfield< 25 > nos1
 
Bitfield< 26 > nos2
 
Bitfield< 27 > nos3
 
Bitfield< 28 > nos4
 
Bitfield< 29 > nos5
 
Bitfield< 30 > nos6
 
Bitfield< 31 > nos7
 
 ir0
 
Bitfield< 3, 2 > ir1
 
Bitfield< 5, 4 > ir2
 
Bitfield< 7, 6 > ir3
 
Bitfield< 9, 8 > ir4
 
Bitfield< 11, 10 > ir5
 
Bitfield< 13, 12 > ir6
 
Bitfield< 15, 14 > ir7
 
Bitfield< 17, 16 > or0
 
Bitfield< 19, 18 > or1
 
Bitfield< 21, 20 > or2
 
Bitfield< 23, 22 > or3
 
Bitfield< 25, 24 > or4
 
Bitfield< 27, 26 > or5
 
Bitfield< 29, 28 > or6
 
Bitfield< 31, 30 > or7
 
 asid
 
Bitfield< 31, 8 > procid
 
 sataRAMLatency
 
Bitfield< 4, 3 > reserved_4_3
 
Bitfield< 5 > dataRAMSetup
 
Bitfield< 8, 6 > tagRAMLatency
 
Bitfield< 9 > tagRAMSetup
 
Bitfield< 11, 10 > dataRAMSlice
 
Bitfield< 12 > tagRAMSlice
 
Bitfield< 20, 13 > reserved_20_13
 
Bitfield< 21 > eccandParityEnable
 
Bitfield< 22 > reserved_22
 
Bitfield< 23 > interptCtrlPresent
 
Bitfield< 25, 24 > numCPUs
 
Bitfield< 30, 26 > reserved_30_26
 
Bitfield< 31 > l2rstDISABLE_monitor
 
 iCacheLineSize
 
Bitfield< 13, 4 > raz_13_4
 
Bitfield< 15, 14 > l1IndexPolicy
 
Bitfield< 19, 16 > dCacheLineSize
 
Bitfield< 23, 20 > erg
 
Bitfield< 27, 24 > cwg
 
Bitfield< 28 > raz_28
 
Bitfield< 31, 29 > format
 
 sel
 
 attr
 
Bitfield< 39, 12 > pa
 
Bitfield< 8, 7 > sh
 
Bitfield< 6, 1 > fst
 
Bitfield< 6 > fs5
 
Bitfield< 5, 1 > fs4_0
 
 ec
 
Bitfield< 15, 0 > imm16
 
Bitfield< 30 > tam
 
Bitfield< 28 > tta_e2h
 
Bitfield< 13, 12 > res1_13_12_el2
 
Bitfield< 9 > res1_9_el2
 
Bitfield< 8 > res1_8_el2
 
Bitfield< 8 > ez
 
Bitfield< 7, 0 > res1_7_0_el2
 
 res0
 
Bitfield< 3 > oslm_3
 
Bitfield< 2 > nTT
 
Bitfield< 1 > oslk
 
Bitfield< 0 > oslm_0
 
 res0_2
 
Bitfield< 23, 20 > bt
 
Bitfield< 19, 16 > lbn
 
Bitfield< 15, 14 > ssc
 
Bitfield< 13 > hmc
 
Bitfield< 12, 9 > res0_1
 
Bitfield< 8, 5 > bas
 
Bitfield< 4, 3 > res0_0
 
Bitfield< 2, 1 > pmc
 
Bitfield< 20 > wt
 
Bitfield< 4, 3 > lsv
 
Bitfield< 2, 1 > pac
 
Bitfield< 30 > rxfull
 
Bitfield< 29 > txfull
 
Bitfield< 28 > res0_5
 
Bitfield< 27 > rxo
 
Bitfield< 26 > txu
 
Bitfield< 25, 24 > res0_4
 
Bitfield< 23, 22 > intdis
 
Bitfield< 20 > res0_3
 
Bitfield< 19 > sc2
 
Bitfield< 17 > spniddis
 
Bitfield< 16 > spiddis
 
Bitfield< 15 > mdbgen
 
Bitfield< 14 > hde
 
Bitfield< 13 > res0_
 
Bitfield< 12 > udccdis
 
Bitfield< 12 > tdcc
 
Bitfield< 6 > err
 
Bitfield< 5, 2 > moe
 
Bitfield< 30 > nsi
 
Bitfield< 28 > nsd
 
Bitfield< 27 > nsp
 
Bitfield< 26 > nss
 
Bitfield< 25 > nsu
 
Bitfield< 15 > mf
 
Bitfield< 14 > mi
 
Bitfield< 12 > md
 
Bitfield< 11 > mp
 
Bitfield< 10 > ms
 
Bitfield< 7 > sf
 
Bitfield< 6 > si
 
Bitfield< 4 > sd
 
Bitfield< 1 > su
 
 cidmask
 
Bitfield< 27, 24 > auxregs
 
Bitfield< 19, 16 > virtextns
 
Bitfield< 15, 12 > vectorcatch
 
Bitfield< 11, 8 > bpaddremask
 
Bitfield< 7, 4 > wpaddrmask
 
Bitfield< 3, 0 > pcsample
 
constexpr unsigned NumVecElemPerNeonVecReg = 4
 
constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords
 
const int NumFloatV7ArchRegs = 64
 
const int NumVecV7ArchRegs = 16
 
const int NumVecV8ArchRegs = 32
 
const int NumVecSpecialRegs = 8
 
const int NumVecIntrlvRegs = 4
 
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs
 
const int NumVecPredRegs = 18
 
const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg
 
const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs
 
const int INTRLVREG1 = INTRLVREG0 + 1
 
const int INTRLVREG2 = INTRLVREG0 + 2
 
const int INTRLVREG3 = INTRLVREG0 + 3
 
const int VECREG_UREG0 = 32
 
const int PREDREG_FFR = 16
 
const int PREDREG_UREG0 = 17
 
 decoderFault
 
Bitfield< 61 > illegalExecution
 
Bitfield< 60 > debugStep
 
Bitfield< 59, 56 > sveLen
 
Bitfield< 55, 48 > itstate
 
Bitfield< 55, 52 > itstateCond
 
Bitfield< 51, 48 > itstateMask
 
Bitfield< 41, 40 > fpscrStride
 
Bitfield< 39, 37 > fpscrLen
 
Bitfield< 36 > thumb
 
Bitfield< 35 > bigThumb
 
Bitfield< 34 > aarch64
 
Bitfield< 33 > sevenAndFour
 
Bitfield< 32 > isMisc
 
uint32_t instBits
 
Bitfield< 27, 25 > encoding
 
Bitfield< 25 > useImm
 
Bitfield< 24, 21 > opcode
 
Bitfield< 24, 20 > mediaOpcode
 
Bitfield< 24 > opcode24
 
Bitfield< 24, 23 > opcode24_23
 
Bitfield< 23, 20 > opcode23_20
 
Bitfield< 23, 21 > opcode23_21
 
Bitfield< 20 > opcode20
 
Bitfield< 22 > opcode22
 
Bitfield< 19, 16 > opcode19_16
 
Bitfield< 19 > opcode19
 
Bitfield< 18 > opcode18
 
Bitfield< 15, 12 > opcode15_12
 
Bitfield< 15 > opcode15
 
Bitfield< 7, 4 > miscOpcode
 
Bitfield< 7, 5 > opc2
 
Bitfield< 7 > opcode7
 
Bitfield< 6 > opcode6
 
Bitfield< 4 > opcode4
 
Bitfield< 31, 28 > condCode
 
Bitfield< 20 > sField
 
Bitfield< 19, 16 > rn
 
Bitfield< 15, 12 > rd
 
Bitfield< 15, 12 > rt
 
Bitfield< 11, 7 > shiftSize
 
Bitfield< 6, 5 > shift
 
Bitfield< 3, 0 > rm
 
Bitfield< 23 > up
 
Bitfield< 22 > psruser
 
Bitfield< 21 > writeback
 
Bitfield< 20 > loadOp
 
 pubwl
 
Bitfield< 7, 0 > imm
 
Bitfield< 11, 8 > rotate
 
Bitfield< 11, 0 > immed11_0
 
Bitfield< 7, 0 > immed7_0
 
Bitfield< 11, 8 > immedHi11_8
 
Bitfield< 3, 0 > immedLo3_0
 
Bitfield< 15, 0 > regList
 
Bitfield< 23, 0 > offset
 
Bitfield< 23, 0 > immed23_0
 
Bitfield< 11, 8 > cpNum
 
Bitfield< 18, 16 > fn
 
Bitfield< 14, 12 > fd
 
Bitfield< 3 > fpRegImm
 
Bitfield< 3, 0 > fm
 
Bitfield< 2, 0 > fpImm
 
Bitfield< 24, 20 > punwl
 
Bitfield< 15, 8 > m5Func
 
Bitfield< 15, 13 > topcode15_13
 
Bitfield< 13, 11 > topcode13_11
 
Bitfield< 12, 11 > topcode12_11
 
Bitfield< 12, 10 > topcode12_10
 
Bitfield< 11, 9 > topcode11_9
 
Bitfield< 11, 8 > topcode11_8
 
Bitfield< 10, 9 > topcode10_9
 
Bitfield< 10, 8 > topcode10_8
 
Bitfield< 9, 6 > topcode9_6
 
Bitfield< 7 > topcode7
 
Bitfield< 7, 6 > topcode7_6
 
Bitfield< 7, 5 > topcode7_5
 
Bitfield< 7, 4 > topcode7_4
 
Bitfield< 3, 0 > topcode3_0
 
Bitfield< 28, 27 > htopcode12_11
 
Bitfield< 26, 25 > htopcode10_9
 
Bitfield< 25 > htopcode9
 
Bitfield< 25, 24 > htopcode9_8
 
Bitfield< 25, 21 > htopcode9_5
 
Bitfield< 25, 20 > htopcode9_4
 
Bitfield< 24 > htopcode8
 
Bitfield< 24, 23 > htopcode8_7
 
Bitfield< 24, 22 > htopcode8_6
 
Bitfield< 24, 21 > htopcode8_5
 
Bitfield< 23 > htopcode7
 
Bitfield< 23, 21 > htopcode7_5
 
Bitfield< 22 > htopcode6
 
Bitfield< 22, 21 > htopcode6_5
 
Bitfield< 21, 20 > htopcode5_4
 
Bitfield< 20 > htopcode4
 
Bitfield< 19, 16 > htrn
 
Bitfield< 20 > hts
 
Bitfield< 15 > ltopcode15
 
Bitfield< 11, 8 > ltopcode11_8
 
Bitfield< 7, 6 > ltopcode7_6
 
Bitfield< 7, 4 > ltopcode7_4
 
Bitfield< 4 > ltopcode4
 
Bitfield< 11, 8 > ltrd
 
Bitfield< 11, 8 > ltcoproc
 
constexpr unsigned MaxSveVecLenInBits = 2048
 
constexpr unsigned MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3
 
constexpr unsigned MaxSveVecLenInWords = MaxSveVecLenInBits >> 5
 
constexpr unsigned MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6
 
constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes
 
constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes
 
Bitfield< 9 > el0pten
 
Bitfield< 8 > el0vten
 
Bitfield< 7, 4 > evnti
 
Bitfield< 3 > evntdir
 
Bitfield< 2 > evnten
 
Bitfield< 1 > el0vcten
 
Bitfield< 0 > el0pcten
 
Bitfield< 16 > el1nvvct
 
Bitfield< 15 > el1nvpct
 
Bitfield< 14 > el1tvct
 
Bitfield< 13 > el1tvt
 
Bitfield< 1 > el1pcen
 
Bitfield< 0 > el1pcten
 
Bitfield< 11 > el1pten
 

Typedef Documentation

◆ ConstVecPredReg

Definition at line 67 of file vec.hh.

◆ FaultOffset

Definition at line 60 of file faults.hh.

◆ IntRegMap

typedef IntRegIndex gem5::ArmISA::IntRegMap[NUM_ARCH_INTREGS]

Definition at line 314 of file int.hh.

◆ MachInst

typedef uint32_t gem5::ArmISA::MachInst

Definition at line 55 of file types.hh.

◆ RegContextParam

Definition at line 227 of file types.hh.

◆ RegContextVal

Definition at line 228 of file types.hh.

◆ VecElem

using gem5::ArmISA::VecElem = typedef uint32_t

Definition at line 60 of file vec.hh.

◆ VecPredReg

Definition at line 65 of file vec.hh.

◆ VecPredRegContainer

Definition at line 68 of file vec.hh.

◆ VecRegContainer

Definition at line 62 of file vec.hh.

◆ VfpSavedState

Definition at line 215 of file vfp.hh.

◆ vmid_t

typedef uint16_t gem5::ArmISA::vmid_t

Definition at line 57 of file types.hh.

◆ XReg

typedef uint64_t gem5::ArmISA::XReg

Definition at line 53 of file neon64_mem.hh.

Enumeration Type Documentation

◆ ArmExtendType

Enumerator
UXTB 
UXTH 
UXTW 
UXTX 
SXTB 
SXTH 
SXTW 
SXTX 

Definition at line 215 of file types.hh.

◆ ccRegIndex

Enumerator
CCREG_NZ 
CCREG_C 
CCREG_V 
CCREG_GE 
CCREG_FP 
CCREG_ZERO 
NUM_CCREGS 

Definition at line 47 of file cc.hh.

◆ ConditionCode

Enumerator
COND_EQ 
COND_NE 
COND_CS 
COND_CC 
COND_MI 
COND_PL 
COND_VS 
COND_VC 
COND_HI 
COND_LS 
COND_GE 
COND_LT 
COND_GT 
COND_LE 
COND_AL 
COND_UC 

Definition at line 67 of file cc.hh.

◆ ConvertType

Enumerator
SINGLE_TO_DOUBLE 
SINGLE_TO_WORD 
SINGLE_TO_LONG 
DOUBLE_TO_SINGLE 
DOUBLE_TO_WORD 
DOUBLE_TO_LONG 
LONG_TO_SINGLE 
LONG_TO_DOUBLE 
LONG_TO_WORD 
LONG_TO_PS 
WORD_TO_SINGLE 
WORD_TO_DOUBLE 
WORD_TO_LONG 
WORD_TO_PS 
PL_TO_SINGLE 
PU_TO_SINGLE 

Definition at line 231 of file types.hh.

◆ DecoderFault

enum gem5::ArmISA::DecoderFault : std::uint8_t

Instruction decoder fault codes in ExtMachInst.

Enumerator
OK 

No fault.

UNALIGNED 

Unaligned instruction fault.

PANIC 

Internal gem5 error.

Definition at line 349 of file types.hh.

◆ ExceptionClass

Enumerator
EC_INVALID 
EC_UNKNOWN 
EC_TRAPPED_WFI_WFE 
EC_TRAPPED_CP15_MCR_MRC 
EC_TRAPPED_CP15_MCRR_MRRC 
EC_TRAPPED_CP14_MCR_MRC 
EC_TRAPPED_CP14_LDC_STC 
EC_TRAPPED_HCPTR 
EC_TRAPPED_SIMD_FP 
EC_TRAPPED_CP10_MRC_VMRS 
EC_TRAPPED_PAC 
EC_TRAPPED_BXJ 
EC_TRAPPED_CP14_MCRR_MRRC 
EC_ILLEGAL_INST 
EC_SVC_TO_HYP 
EC_SVC 
EC_HVC 
EC_SMC_TO_HYP 
EC_SMC 
EC_SVC_64 
EC_HVC_64 
EC_SMC_64 
EC_TRAPPED_MSR_MRS_64 
EC_TRAPPED_SVE 
EC_PREFETCH_ABORT_TO_HYP 
EC_PREFETCH_ABORT_LOWER_EL 
EC_PREFETCH_ABORT_FROM_HYP 
EC_PREFETCH_ABORT_CURR_EL 
EC_PC_ALIGNMENT 
EC_DATA_ABORT_TO_HYP 
EC_DATA_ABORT_LOWER_EL 
EC_DATA_ABORT_FROM_HYP 
EC_DATA_ABORT_CURR_EL 
EC_STACK_PTR_ALIGNMENT 
EC_FP_EXCEPTION 
EC_FP_EXCEPTION_64 
EC_SERROR 
EC_HW_BREAKPOINT 
EC_HW_BREAKPOINT_LOWER_EL 
EC_HW_BREAKPOINT_CURR_EL 
EC_SOFTWARE_STEP 
EC_SOFTWARE_STEP_LOWER_EL 
EC_SOFTWARE_STEP_CURR_EL 
EC_WATCHPOINT 
EC_WATCHPOINT_LOWER_EL 
EC_WATCHPOINT_CURR_EL 
EC_SOFTWARE_BREAKPOINT 
EC_VECTOR_CATCH 
EC_SOFTWARE_BREAKPOINT_64 

Definition at line 293 of file types.hh.

◆ ExceptionLevel

Enumerator
EL0 
EL1 
EL2 
EL3 

Definition at line 264 of file types.hh.

◆ FeExceptionBit

Enumerator
FeDivByZero 
FeInexact 
FeInvalid 
FeOverflow 
FeUnderflow 
FeAllExceptions 

Definition at line 86 of file vfp.hh.

◆ FeRoundingMode

Enumerator
FeRoundDown 
FeRoundNearest 
FeRoundZero 
FeRoundUpward 

Definition at line 96 of file vfp.hh.

◆ FpDataType

Floating point data types.

Enumerator
Fp16 
Fp32 
Fp64 

Definition at line 166 of file pred_inst.hh.

◆ FPRounding

Enumerator
FPRounding_TIEEVEN 
FPRounding_POSINF 
FPRounding_NEGINF 
FPRounding_ZERO 
FPRounding_TIEAWAY 
FPRounding_ODD 

Definition at line 60 of file fplib.hh.

◆ InterruptTypes

Enumerator
INT_RST 
INT_ABT 
INT_IRQ 
INT_FIQ 
INT_SEV 
INT_VIRT_IRQ 
INT_VIRT_FIQ 
NumInterruptTypes 

Definition at line 58 of file interrupts.hh.

◆ LookupLevel

Enumerator
L0 
L1 
L2 
L3 
MAX_LOOKUP_LEVELS 

Definition at line 76 of file pagetable.hh.

◆ MiscRegIndex

Enumerator
MISCREG_CPSR 
MISCREG_SPSR 
MISCREG_SPSR_FIQ 
MISCREG_SPSR_IRQ 
MISCREG_SPSR_SVC 
MISCREG_SPSR_MON 
MISCREG_SPSR_ABT 
MISCREG_SPSR_HYP 
MISCREG_SPSR_UND 
MISCREG_ELR_HYP 
MISCREG_FPSID 
MISCREG_FPSCR 
MISCREG_MVFR1 
MISCREG_MVFR0 
MISCREG_FPEXC 
MISCREG_CPSR_MODE 
MISCREG_CPSR_Q 
MISCREG_FPSCR_EXC 
MISCREG_FPSCR_QC 
MISCREG_LOCKADDR 
MISCREG_LOCKFLAG 
MISCREG_PRRR_MAIR0 
MISCREG_PRRR_MAIR0_NS 
MISCREG_PRRR_MAIR0_S 
MISCREG_NMRR_MAIR1 
MISCREG_NMRR_MAIR1_NS 
MISCREG_NMRR_MAIR1_S 
MISCREG_PMXEVTYPER_PMCCFILTR 
MISCREG_SCTLR_RST 
MISCREG_SEV_MAILBOX 
MISCREG_DBGDIDR 
MISCREG_DBGDSCRint 
MISCREG_DBGDCCINT 
MISCREG_DBGDTRTXint 
MISCREG_DBGDTRRXint 
MISCREG_DBGWFAR 
MISCREG_DBGVCR 
MISCREG_DBGDTRRXext 
MISCREG_DBGDSCRext 
MISCREG_DBGDTRTXext 
MISCREG_DBGOSECCR 
MISCREG_DBGBVR0 
MISCREG_DBGBVR1 
MISCREG_DBGBVR2 
MISCREG_DBGBVR3 
MISCREG_DBGBVR4 
MISCREG_DBGBVR5 
MISCREG_DBGBVR6 
MISCREG_DBGBVR7 
MISCREG_DBGBVR8 
MISCREG_DBGBVR9 
MISCREG_DBGBVR10 
MISCREG_DBGBVR11 
MISCREG_DBGBVR12 
MISCREG_DBGBVR13 
MISCREG_DBGBVR14 
MISCREG_DBGBVR15 
MISCREG_DBGBCR0 
MISCREG_DBGBCR1 
MISCREG_DBGBCR2 
MISCREG_DBGBCR3 
MISCREG_DBGBCR4 
MISCREG_DBGBCR5 
MISCREG_DBGBCR6 
MISCREG_DBGBCR7 
MISCREG_DBGBCR8 
MISCREG_DBGBCR9 
MISCREG_DBGBCR10 
MISCREG_DBGBCR11 
MISCREG_DBGBCR12 
MISCREG_DBGBCR13 
MISCREG_DBGBCR14 
MISCREG_DBGBCR15 
MISCREG_DBGWVR0 
MISCREG_DBGWVR1 
MISCREG_DBGWVR2 
MISCREG_DBGWVR3 
MISCREG_DBGWVR4 
MISCREG_DBGWVR5 
MISCREG_DBGWVR6 
MISCREG_DBGWVR7 
MISCREG_DBGWVR8 
MISCREG_DBGWVR9 
MISCREG_DBGWVR10 
MISCREG_DBGWVR11 
MISCREG_DBGWVR12 
MISCREG_DBGWVR13 
MISCREG_DBGWVR14 
MISCREG_DBGWVR15 
MISCREG_DBGWCR0 
MISCREG_DBGWCR1 
MISCREG_DBGWCR2 
MISCREG_DBGWCR3 
MISCREG_DBGWCR4 
MISCREG_DBGWCR5 
MISCREG_DBGWCR6 
MISCREG_DBGWCR7 
MISCREG_DBGWCR8 
MISCREG_DBGWCR9 
MISCREG_DBGWCR10 
MISCREG_DBGWCR11 
MISCREG_DBGWCR12 
MISCREG_DBGWCR13 
MISCREG_DBGWCR14 
MISCREG_DBGWCR15 
MISCREG_DBGDRAR 
MISCREG_DBGBXVR0 
MISCREG_DBGBXVR1 
MISCREG_DBGBXVR2 
MISCREG_DBGBXVR3 
MISCREG_DBGBXVR4 
MISCREG_DBGBXVR5 
MISCREG_DBGBXVR6 
MISCREG_DBGBXVR7 
MISCREG_DBGBXVR8 
MISCREG_DBGBXVR9 
MISCREG_DBGBXVR10 
MISCREG_DBGBXVR11 
MISCREG_DBGBXVR12 
MISCREG_DBGBXVR13 
MISCREG_DBGBXVR14 
MISCREG_DBGBXVR15 
MISCREG_DBGOSLAR 
MISCREG_DBGOSLSR 
MISCREG_DBGOSDLR 
MISCREG_DBGPRCR 
MISCREG_DBGDSAR 
MISCREG_DBGCLAIMSET 
MISCREG_DBGCLAIMCLR 
MISCREG_DBGAUTHSTATUS 
MISCREG_DBGDEVID2 
MISCREG_DBGDEVID1 
MISCREG_DBGDEVID0 
MISCREG_TEECR 
MISCREG_JIDR 
MISCREG_TEEHBR 
MISCREG_JOSCR 
MISCREG_JMCR 
MISCREG_MIDR 
MISCREG_CTR 
MISCREG_TCMTR 
MISCREG_TLBTR 
MISCREG_MPIDR 
MISCREG_REVIDR 
MISCREG_ID_PFR0 
MISCREG_ID_PFR1 
MISCREG_ID_DFR0 
MISCREG_ID_AFR0 
MISCREG_ID_MMFR0 
MISCREG_ID_MMFR1 
MISCREG_ID_MMFR2 
MISCREG_ID_MMFR3 
MISCREG_ID_MMFR4 
MISCREG_ID_ISAR0 
MISCREG_ID_ISAR1 
MISCREG_ID_ISAR2 
MISCREG_ID_ISAR3 
MISCREG_ID_ISAR4 
MISCREG_ID_ISAR5 
MISCREG_ID_ISAR6 
MISCREG_CCSIDR 
MISCREG_CLIDR 
MISCREG_AIDR 
MISCREG_CSSELR 
MISCREG_CSSELR_NS 
MISCREG_CSSELR_S 
MISCREG_VPIDR 
MISCREG_VMPIDR 
MISCREG_SCTLR 
MISCREG_SCTLR_NS 
MISCREG_SCTLR_S 
MISCREG_ACTLR 
MISCREG_ACTLR_NS 
MISCREG_ACTLR_S 
MISCREG_CPACR 
MISCREG_SDCR 
MISCREG_SCR 
MISCREG_SDER 
MISCREG_NSACR 
MISCREG_HSCTLR 
MISCREG_HACTLR 
MISCREG_HCR 
MISCREG_HCR2 
MISCREG_HDCR 
MISCREG_HCPTR 
MISCREG_HSTR 
MISCREG_HACR 
MISCREG_TTBR0 
MISCREG_TTBR0_NS 
MISCREG_TTBR0_S 
MISCREG_TTBR1 
MISCREG_TTBR1_NS 
MISCREG_TTBR1_S 
MISCREG_TTBCR 
MISCREG_TTBCR_NS 
MISCREG_TTBCR_S 
MISCREG_HTCR 
MISCREG_VTCR 
MISCREG_DACR 
MISCREG_DACR_NS 
MISCREG_DACR_S 
MISCREG_DFSR 
MISCREG_DFSR_NS 
MISCREG_DFSR_S 
MISCREG_IFSR 
MISCREG_IFSR_NS 
MISCREG_IFSR_S 
MISCREG_ADFSR 
MISCREG_ADFSR_NS 
MISCREG_ADFSR_S 
MISCREG_AIFSR 
MISCREG_AIFSR_NS 
MISCREG_AIFSR_S 
MISCREG_HADFSR 
MISCREG_HAIFSR 
MISCREG_HSR 
MISCREG_DFAR 
MISCREG_DFAR_NS 
MISCREG_DFAR_S 
MISCREG_IFAR 
MISCREG_IFAR_NS 
MISCREG_IFAR_S 
MISCREG_HDFAR 
MISCREG_HIFAR 
MISCREG_HPFAR 
MISCREG_ICIALLUIS 
MISCREG_BPIALLIS 
MISCREG_PAR 
MISCREG_PAR_NS 
MISCREG_PAR_S 
MISCREG_ICIALLU 
MISCREG_ICIMVAU 
MISCREG_CP15ISB 
MISCREG_BPIALL 
MISCREG_BPIMVA 
MISCREG_DCIMVAC 
MISCREG_DCISW 
MISCREG_ATS1CPR 
MISCREG_ATS1CPW 
MISCREG_ATS1CUR 
MISCREG_ATS1CUW 
MISCREG_ATS12NSOPR 
MISCREG_ATS12NSOPW 
MISCREG_ATS12NSOUR 
MISCREG_ATS12NSOUW 
MISCREG_DCCMVAC 
MISCREG_DCCSW 
MISCREG_CP15DSB 
MISCREG_CP15DMB 
MISCREG_DCCMVAU 
MISCREG_DCCIMVAC 
MISCREG_DCCISW 
MISCREG_ATS1HR 
MISCREG_ATS1HW 
MISCREG_TLBIALLIS 
MISCREG_TLBIMVAIS 
MISCREG_TLBIASIDIS 
MISCREG_TLBIMVAAIS 
MISCREG_TLBIMVALIS 
MISCREG_TLBIMVAALIS 
MISCREG_ITLBIALL 
MISCREG_ITLBIMVA 
MISCREG_ITLBIASID 
MISCREG_DTLBIALL 
MISCREG_DTLBIMVA 
MISCREG_DTLBIASID 
MISCREG_TLBIALL 
MISCREG_TLBIMVA 
MISCREG_TLBIASID 
MISCREG_TLBIMVAA 
MISCREG_TLBIMVAL 
MISCREG_TLBIMVAAL 
MISCREG_TLBIIPAS2IS 
MISCREG_TLBIIPAS2LIS 
MISCREG_TLBIALLHIS 
MISCREG_TLBIMVAHIS 
MISCREG_TLBIALLNSNHIS 
MISCREG_TLBIMVALHIS 
MISCREG_TLBIIPAS2 
MISCREG_TLBIIPAS2L 
MISCREG_TLBIALLH 
MISCREG_TLBIMVAH 
MISCREG_TLBIALLNSNH 
MISCREG_TLBIMVALH 
MISCREG_PMCR 
MISCREG_PMCNTENSET 
MISCREG_PMCNTENCLR 
MISCREG_PMOVSR 
MISCREG_PMSWINC 
MISCREG_PMSELR 
MISCREG_PMCEID0 
MISCREG_PMCEID1 
MISCREG_PMCCNTR 
MISCREG_PMXEVTYPER 
MISCREG_PMCCFILTR 
MISCREG_PMXEVCNTR 
MISCREG_PMUSERENR 
MISCREG_PMINTENSET 
MISCREG_PMINTENCLR 
MISCREG_PMOVSSET 
MISCREG_L2CTLR 
MISCREG_L2ECTLR 
MISCREG_PRRR 
MISCREG_PRRR_NS 
MISCREG_PRRR_S 
MISCREG_MAIR0 
MISCREG_MAIR0_NS 
MISCREG_MAIR0_S 
MISCREG_NMRR 
MISCREG_NMRR_NS 
MISCREG_NMRR_S 
MISCREG_MAIR1 
MISCREG_MAIR1_NS 
MISCREG_MAIR1_S 
MISCREG_AMAIR0 
MISCREG_AMAIR0_NS 
MISCREG_AMAIR0_S 
MISCREG_AMAIR1 
MISCREG_AMAIR1_NS 
MISCREG_AMAIR1_S 
MISCREG_HMAIR0 
MISCREG_HMAIR1 
MISCREG_HAMAIR0 
MISCREG_HAMAIR1 
MISCREG_VBAR 
MISCREG_VBAR_NS 
MISCREG_VBAR_S 
MISCREG_MVBAR 
MISCREG_RMR 
MISCREG_ISR 
MISCREG_HVBAR 
MISCREG_FCSEIDR 
MISCREG_CONTEXTIDR 
MISCREG_CONTEXTIDR_NS 
MISCREG_CONTEXTIDR_S 
MISCREG_TPIDRURW 
MISCREG_TPIDRURW_NS 
MISCREG_TPIDRURW_S 
MISCREG_TPIDRURO 
MISCREG_TPIDRURO_NS 
MISCREG_TPIDRURO_S 
MISCREG_TPIDRPRW 
MISCREG_TPIDRPRW_NS 
MISCREG_TPIDRPRW_S 
MISCREG_HTPIDR 
MISCREG_CNTFRQ 
MISCREG_CNTPCT 
MISCREG_CNTVCT 
MISCREG_CNTP_CTL 
MISCREG_CNTP_CTL_NS 
MISCREG_CNTP_CTL_S 
MISCREG_CNTP_CVAL 
MISCREG_CNTP_CVAL_NS 
MISCREG_CNTP_CVAL_S 
MISCREG_CNTP_TVAL 
MISCREG_CNTP_TVAL_NS 
MISCREG_CNTP_TVAL_S 
MISCREG_CNTV_CTL 
MISCREG_CNTV_CVAL 
MISCREG_CNTV_TVAL 
MISCREG_CNTKCTL 
MISCREG_CNTHCTL 
MISCREG_CNTHP_CTL 
MISCREG_CNTHP_CVAL 
MISCREG_CNTHP_TVAL 
MISCREG_CNTVOFF 
MISCREG_IL1DATA0 
MISCREG_IL1DATA1 
MISCREG_IL1DATA2 
MISCREG_IL1DATA3 
MISCREG_DL1DATA0 
MISCREG_DL1DATA1 
MISCREG_DL1DATA2 
MISCREG_DL1DATA3 
MISCREG_DL1DATA4 
MISCREG_RAMINDEX 
MISCREG_L2ACTLR 
MISCREG_CBAR 
MISCREG_HTTBR 
MISCREG_VTTBR 
MISCREG_CPUMERRSR 
MISCREG_L2MERRSR 
MISCREG_MDCCINT_EL1 
MISCREG_OSDTRRX_EL1 
MISCREG_MDSCR_EL1 
MISCREG_OSDTRTX_EL1 
MISCREG_OSECCR_EL1 
MISCREG_DBGBVR0_EL1 
MISCREG_DBGBVR1_EL1 
MISCREG_DBGBVR2_EL1 
MISCREG_DBGBVR3_EL1 
MISCREG_DBGBVR4_EL1 
MISCREG_DBGBVR5_EL1 
MISCREG_DBGBVR6_EL1 
MISCREG_DBGBVR7_EL1 
MISCREG_DBGBVR8_EL1 
MISCREG_DBGBVR9_EL1 
MISCREG_DBGBVR10_EL1 
MISCREG_DBGBVR11_EL1 
MISCREG_DBGBVR12_EL1 
MISCREG_DBGBVR13_EL1 
MISCREG_DBGBVR14_EL1 
MISCREG_DBGBVR15_EL1 
MISCREG_DBGBCR0_EL1 
MISCREG_DBGBCR1_EL1 
MISCREG_DBGBCR2_EL1 
MISCREG_DBGBCR3_EL1 
MISCREG_DBGBCR4_EL1 
MISCREG_DBGBCR5_EL1 
MISCREG_DBGBCR6_EL1 
MISCREG_DBGBCR7_EL1 
MISCREG_DBGBCR8_EL1 
MISCREG_DBGBCR9_EL1 
MISCREG_DBGBCR10_EL1 
MISCREG_DBGBCR11_EL1 
MISCREG_DBGBCR12_EL1 
MISCREG_DBGBCR13_EL1 
MISCREG_DBGBCR14_EL1 
MISCREG_DBGBCR15_EL1 
MISCREG_DBGWVR0_EL1 
MISCREG_DBGWVR1_EL1 
MISCREG_DBGWVR2_EL1 
MISCREG_DBGWVR3_EL1 
MISCREG_DBGWVR4_EL1 
MISCREG_DBGWVR5_EL1 
MISCREG_DBGWVR6_EL1 
MISCREG_DBGWVR7_EL1 
MISCREG_DBGWVR8_EL1 
MISCREG_DBGWVR9_EL1 
MISCREG_DBGWVR10_EL1 
MISCREG_DBGWVR11_EL1 
MISCREG_DBGWVR12_EL1 
MISCREG_DBGWVR13_EL1 
MISCREG_DBGWVR14_EL1 
MISCREG_DBGWVR15_EL1 
MISCREG_DBGWCR0_EL1 
MISCREG_DBGWCR1_EL1 
MISCREG_DBGWCR2_EL1 
MISCREG_DBGWCR3_EL1 
MISCREG_DBGWCR4_EL1 
MISCREG_DBGWCR5_EL1 
MISCREG_DBGWCR6_EL1 
MISCREG_DBGWCR7_EL1 
MISCREG_DBGWCR8_EL1 
MISCREG_DBGWCR9_EL1 
MISCREG_DBGWCR10_EL1 
MISCREG_DBGWCR11_EL1 
MISCREG_DBGWCR12_EL1 
MISCREG_DBGWCR13_EL1 
MISCREG_DBGWCR14_EL1 
MISCREG_DBGWCR15_EL1 
MISCREG_MDCCSR_EL0 
MISCREG_MDDTR_EL0 
MISCREG_MDDTRTX_EL0 
MISCREG_MDDTRRX_EL0 
MISCREG_DBGVCR32_EL2 
MISCREG_MDRAR_EL1 
MISCREG_OSLAR_EL1 
MISCREG_OSLSR_EL1 
MISCREG_OSDLR_EL1 
MISCREG_DBGPRCR_EL1 
MISCREG_DBGCLAIMSET_EL1 
MISCREG_DBGCLAIMCLR_EL1 
MISCREG_DBGAUTHSTATUS_EL1 
MISCREG_TEECR32_EL1 
MISCREG_TEEHBR32_EL1 
MISCREG_MIDR_EL1 
MISCREG_MPIDR_EL1 
MISCREG_REVIDR_EL1 
MISCREG_ID_PFR0_EL1 
MISCREG_ID_PFR1_EL1 
MISCREG_ID_DFR0_EL1 
MISCREG_ID_AFR0_EL1 
MISCREG_ID_MMFR0_EL1 
MISCREG_ID_MMFR1_EL1 
MISCREG_ID_MMFR2_EL1 
MISCREG_ID_MMFR3_EL1 
MISCREG_ID_MMFR4_EL1 
MISCREG_ID_ISAR0_EL1 
MISCREG_ID_ISAR1_EL1 
MISCREG_ID_ISAR2_EL1 
MISCREG_ID_ISAR3_EL1 
MISCREG_ID_ISAR4_EL1 
MISCREG_ID_ISAR5_EL1 
MISCREG_ID_ISAR6_EL1 
MISCREG_MVFR0_EL1 
MISCREG_MVFR1_EL1 
MISCREG_MVFR2_EL1 
MISCREG_ID_AA64PFR0_EL1 
MISCREG_ID_AA64PFR1_EL1 
MISCREG_ID_AA64DFR0_EL1 
MISCREG_ID_AA64DFR1_EL1 
MISCREG_ID_AA64AFR0_EL1 
MISCREG_ID_AA64AFR1_EL1 
MISCREG_ID_AA64ISAR0_EL1 
MISCREG_ID_AA64ISAR1_EL1 
MISCREG_ID_AA64MMFR0_EL1 
MISCREG_ID_AA64MMFR1_EL1 
MISCREG_CCSIDR_EL1 
MISCREG_CLIDR_EL1 
MISCREG_AIDR_EL1 
MISCREG_CSSELR_EL1 
MISCREG_CTR_EL0 
MISCREG_DCZID_EL0 
MISCREG_VPIDR_EL2 
MISCREG_VMPIDR_EL2 
MISCREG_SCTLR_EL1 
MISCREG_SCTLR_EL12 
MISCREG_ACTLR_EL1 
MISCREG_CPACR_EL1 
MISCREG_CPACR_EL12 
MISCREG_SCTLR_EL2 
MISCREG_ACTLR_EL2 
MISCREG_HCR_EL2 
MISCREG_MDCR_EL2 
MISCREG_CPTR_EL2 
MISCREG_HSTR_EL2 
MISCREG_HACR_EL2 
MISCREG_SCTLR_EL3 
MISCREG_ACTLR_EL3 
MISCREG_SCR_EL3 
MISCREG_SDER32_EL3 
MISCREG_CPTR_EL3 
MISCREG_MDCR_EL3 
MISCREG_TTBR0_EL1 
MISCREG_TTBR0_EL12 
MISCREG_TTBR1_EL1 
MISCREG_TTBR1_EL12 
MISCREG_TCR_EL1 
MISCREG_TCR_EL12 
MISCREG_TTBR0_EL2 
MISCREG_TCR_EL2 
MISCREG_VTTBR_EL2 
MISCREG_VTCR_EL2 
MISCREG_VSTTBR_EL2 
MISCREG_VSTCR_EL2 
MISCREG_TTBR0_EL3 
MISCREG_TCR_EL3 
MISCREG_DACR32_EL2 
MISCREG_SPSR_EL1 
MISCREG_SPSR_EL12 
MISCREG_ELR_EL1 
MISCREG_ELR_EL12 
MISCREG_SP_EL0 
MISCREG_SPSEL 
MISCREG_CURRENTEL 
MISCREG_NZCV 
MISCREG_DAIF 
MISCREG_FPCR 
MISCREG_FPSR 
MISCREG_DSPSR_EL0 
MISCREG_DLR_EL0 
MISCREG_SPSR_EL2 
MISCREG_ELR_EL2 
MISCREG_SP_EL1 
MISCREG_SPSR_IRQ_AA64 
MISCREG_SPSR_ABT_AA64 
MISCREG_SPSR_UND_AA64 
MISCREG_SPSR_FIQ_AA64 
MISCREG_SPSR_EL3 
MISCREG_ELR_EL3 
MISCREG_SP_EL2 
MISCREG_AFSR0_EL1 
MISCREG_AFSR0_EL12 
MISCREG_AFSR1_EL1 
MISCREG_AFSR1_EL12 
MISCREG_ESR_EL1 
MISCREG_ESR_EL12 
MISCREG_IFSR32_EL2 
MISCREG_AFSR0_EL2 
MISCREG_AFSR1_EL2 
MISCREG_ESR_EL2 
MISCREG_FPEXC32_EL2 
MISCREG_AFSR0_EL3 
MISCREG_AFSR1_EL3 
MISCREG_ESR_EL3 
MISCREG_FAR_EL1 
MISCREG_FAR_EL12 
MISCREG_FAR_EL2 
MISCREG_HPFAR_EL2 
MISCREG_FAR_EL3 
MISCREG_IC_IALLUIS 
MISCREG_PAR_EL1 
MISCREG_IC_IALLU 
MISCREG_DC_IVAC_Xt 
MISCREG_DC_ISW_Xt 
MISCREG_AT_S1E1R_Xt 
MISCREG_AT_S1E1W_Xt 
MISCREG_AT_S1E0R_Xt 
MISCREG_AT_S1E0W_Xt 
MISCREG_DC_CSW_Xt 
MISCREG_DC_CISW_Xt 
MISCREG_DC_ZVA_Xt 
MISCREG_IC_IVAU_Xt 
MISCREG_DC_CVAC_Xt 
MISCREG_DC_CVAU_Xt 
MISCREG_DC_CIVAC_Xt 
MISCREG_AT_S1E2R_Xt 
MISCREG_AT_S1E2W_Xt 
MISCREG_AT_S12E1R_Xt 
MISCREG_AT_S12E1W_Xt 
MISCREG_AT_S12E0R_Xt 
MISCREG_AT_S12E0W_Xt 
MISCREG_AT_S1E3R_Xt 
MISCREG_AT_S1E3W_Xt 
MISCREG_TLBI_VMALLE1IS 
MISCREG_TLBI_VAE1IS_Xt 
MISCREG_TLBI_ASIDE1IS_Xt 
MISCREG_TLBI_VAAE1IS_Xt 
MISCREG_TLBI_VALE1IS_Xt 
MISCREG_TLBI_VAALE1IS_Xt 
MISCREG_TLBI_VMALLE1 
MISCREG_TLBI_VAE1_Xt 
MISCREG_TLBI_ASIDE1_Xt 
MISCREG_TLBI_VAAE1_Xt 
MISCREG_TLBI_VALE1_Xt 
MISCREG_TLBI_VAALE1_Xt 
MISCREG_TLBI_IPAS2E1IS_Xt 
MISCREG_TLBI_IPAS2LE1IS_Xt 
MISCREG_TLBI_ALLE2IS 
MISCREG_TLBI_VAE2IS_Xt 
MISCREG_TLBI_ALLE1IS 
MISCREG_TLBI_VALE2IS_Xt 
MISCREG_TLBI_VMALLS12E1IS 
MISCREG_TLBI_IPAS2E1_Xt 
MISCREG_TLBI_IPAS2LE1_Xt 
MISCREG_TLBI_ALLE2 
MISCREG_TLBI_VAE2_Xt 
MISCREG_TLBI_ALLE1 
MISCREG_TLBI_VALE2_Xt 
MISCREG_TLBI_VMALLS12E1 
MISCREG_TLBI_ALLE3IS 
MISCREG_TLBI_VAE3IS_Xt 
MISCREG_TLBI_VALE3IS_Xt 
MISCREG_TLBI_ALLE3 
MISCREG_TLBI_VAE3_Xt 
MISCREG_TLBI_VALE3_Xt 
MISCREG_PMINTENSET_EL1 
MISCREG_PMINTENCLR_EL1 
MISCREG_PMCR_EL0 
MISCREG_PMCNTENSET_EL0 
MISCREG_PMCNTENCLR_EL0 
MISCREG_PMOVSCLR_EL0 
MISCREG_PMSWINC_EL0 
MISCREG_PMSELR_EL0 
MISCREG_PMCEID0_EL0 
MISCREG_PMCEID1_EL0 
MISCREG_PMCCNTR_EL0 
MISCREG_PMXEVTYPER_EL0 
MISCREG_PMCCFILTR_EL0 
MISCREG_PMXEVCNTR_EL0 
MISCREG_PMUSERENR_EL0 
MISCREG_PMOVSSET_EL0 
MISCREG_MAIR_EL1 
MISCREG_MAIR_EL12 
MISCREG_AMAIR_EL1 
MISCREG_AMAIR_EL12 
MISCREG_MAIR_EL2 
MISCREG_AMAIR_EL2 
MISCREG_MAIR_EL3 
MISCREG_AMAIR_EL3 
MISCREG_L2CTLR_EL1 
MISCREG_L2ECTLR_EL1 
MISCREG_VBAR_EL1 
MISCREG_VBAR_EL12 
MISCREG_RVBAR_EL1 
MISCREG_ISR_EL1 
MISCREG_VBAR_EL2 
MISCREG_RVBAR_EL2 
MISCREG_VBAR_EL3 
MISCREG_RVBAR_EL3 
MISCREG_RMR_EL3 
MISCREG_CONTEXTIDR_EL1 
MISCREG_CONTEXTIDR_EL12 
MISCREG_TPIDR_EL1 
MISCREG_TPIDR_EL0 
MISCREG_TPIDRRO_EL0 
MISCREG_TPIDR_EL2 
MISCREG_TPIDR_EL3 
MISCREG_CNTFRQ_EL0 
MISCREG_CNTPCT_EL0 
MISCREG_CNTVCT_EL0 
MISCREG_CNTP_CTL_EL0 
MISCREG_CNTP_CVAL_EL0 
MISCREG_CNTP_TVAL_EL0 
MISCREG_CNTV_CTL_EL0 
MISCREG_CNTV_CVAL_EL0 
MISCREG_CNTV_TVAL_EL0 
MISCREG_CNTP_CTL_EL02 
MISCREG_CNTP_CVAL_EL02 
MISCREG_CNTP_TVAL_EL02 
MISCREG_CNTV_CTL_EL02 
MISCREG_CNTV_CVAL_EL02 
MISCREG_CNTV_TVAL_EL02 
MISCREG_CNTKCTL_EL1 
MISCREG_CNTKCTL_EL12 
MISCREG_CNTPS_CTL_EL1 
MISCREG_CNTPS_CVAL_EL1 
MISCREG_CNTPS_TVAL_EL1 
MISCREG_CNTHCTL_EL2 
MISCREG_CNTHP_CTL_EL2 
MISCREG_CNTHP_CVAL_EL2 
MISCREG_CNTHP_TVAL_EL2 
MISCREG_CNTHPS_CTL_EL2 
MISCREG_CNTHPS_CVAL_EL2 
MISCREG_CNTHPS_TVAL_EL2 
MISCREG_CNTHV_CTL_EL2 
MISCREG_CNTHV_CVAL_EL2 
MISCREG_CNTHV_TVAL_EL2 
MISCREG_CNTHVS_CTL_EL2 
MISCREG_CNTHVS_CVAL_EL2 
MISCREG_CNTHVS_TVAL_EL2 
MISCREG_CNTVOFF_EL2 
MISCREG_PMEVCNTR0_EL0 
MISCREG_PMEVCNTR1_EL0 
MISCREG_PMEVCNTR2_EL0 
MISCREG_PMEVCNTR3_EL0 
MISCREG_PMEVCNTR4_EL0 
MISCREG_PMEVCNTR5_EL0 
MISCREG_PMEVTYPER0_EL0 
MISCREG_PMEVTYPER1_EL0 
MISCREG_PMEVTYPER2_EL0 
MISCREG_PMEVTYPER3_EL0 
MISCREG_PMEVTYPER4_EL0 
MISCREG_PMEVTYPER5_EL0 
MISCREG_IL1DATA0_EL1 
MISCREG_IL1DATA1_EL1 
MISCREG_IL1DATA2_EL1 
MISCREG_IL1DATA3_EL1 
MISCREG_DL1DATA0_EL1 
MISCREG_DL1DATA1_EL1 
MISCREG_DL1DATA2_EL1 
MISCREG_DL1DATA3_EL1 
MISCREG_DL1DATA4_EL1 
MISCREG_L2ACTLR_EL1 
MISCREG_CPUACTLR_EL1 
MISCREG_CPUECTLR_EL1 
MISCREG_CPUMERRSR_EL1 
MISCREG_L2MERRSR_EL1 
MISCREG_CBAR_EL1 
MISCREG_CONTEXTIDR_EL2 
MISCREG_TTBR1_EL2 
MISCREG_ID_AA64MMFR2_EL1 
MISCREG_APDAKeyHi_EL1 
MISCREG_APDAKeyLo_EL1 
MISCREG_APDBKeyHi_EL1 
MISCREG_APDBKeyLo_EL1 
MISCREG_APGAKeyHi_EL1 
MISCREG_APGAKeyLo_EL1 
MISCREG_APIAKeyHi_EL1 
MISCREG_APIAKeyLo_EL1 
MISCREG_APIBKeyHi_EL1 
MISCREG_APIBKeyLo_EL1 
MISCREG_ICC_PMR_EL1 
MISCREG_ICC_IAR0_EL1 
MISCREG_ICC_EOIR0_EL1 
MISCREG_ICC_HPPIR0_EL1 
MISCREG_ICC_BPR0_EL1 
MISCREG_ICC_AP0R0_EL1 
MISCREG_ICC_AP0R1_EL1 
MISCREG_ICC_AP0R2_EL1 
MISCREG_ICC_AP0R3_EL1 
MISCREG_ICC_AP1R0_EL1 
MISCREG_ICC_AP1R0_EL1_NS 
MISCREG_ICC_AP1R0_EL1_S 
MISCREG_ICC_AP1R1_EL1 
MISCREG_ICC_AP1R1_EL1_NS 
MISCREG_ICC_AP1R1_EL1_S 
MISCREG_ICC_AP1R2_EL1 
MISCREG_ICC_AP1R2_EL1_NS 
MISCREG_ICC_AP1R2_EL1_S 
MISCREG_ICC_AP1R3_EL1 
MISCREG_ICC_AP1R3_EL1_NS 
MISCREG_ICC_AP1R3_EL1_S 
MISCREG_ICC_DIR_EL1 
MISCREG_ICC_RPR_EL1 
MISCREG_ICC_SGI1R_EL1 
MISCREG_ICC_ASGI1R_EL1 
MISCREG_ICC_SGI0R_EL1 
MISCREG_ICC_IAR1_EL1 
MISCREG_ICC_EOIR1_EL1 
MISCREG_ICC_HPPIR1_EL1 
MISCREG_ICC_BPR1_EL1 
MISCREG_ICC_BPR1_EL1_NS 
MISCREG_ICC_BPR1_EL1_S 
MISCREG_ICC_CTLR_EL1 
MISCREG_ICC_CTLR_EL1_NS 
MISCREG_ICC_CTLR_EL1_S 
MISCREG_ICC_SRE_EL1 
MISCREG_ICC_SRE_EL1_NS 
MISCREG_ICC_SRE_EL1_S 
MISCREG_ICC_IGRPEN0_EL1 
MISCREG_ICC_IGRPEN1_EL1 
MISCREG_ICC_IGRPEN1_EL1_NS 
MISCREG_ICC_IGRPEN1_EL1_S 
MISCREG_ICC_SRE_EL2 
MISCREG_ICC_CTLR_EL3 
MISCREG_ICC_SRE_EL3 
MISCREG_ICC_IGRPEN1_EL3 
MISCREG_ICH_AP0R0_EL2 
MISCREG_ICH_AP0R1_EL2 
MISCREG_ICH_AP0R2_EL2 
MISCREG_ICH_AP0R3_EL2 
MISCREG_ICH_AP1R0_EL2