gem5  v22.1.0.0
decoder.cc
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40 
41 #include "arch/arm/decoder.hh"
42 
43 #include "arch/arm/isa.hh"
44 #include "arch/arm/utility.hh"
45 #include "base/cast.hh"
46 #include "base/trace.hh"
47 #include "debug/Decoder.hh"
48 #include "sim/full_system.hh"
49 
50 namespace gem5
51 {
52 
53 namespace ArmISA
54 {
55 
57 
58 Decoder::Decoder(const ArmDecoderParams &params)
59  : InstDecoder(params, &data),
60  dvmEnabled(params.dvm_enabled),
61  data(0), fpscrLen(0), fpscrStride(0),
62  decoderFlavor(safe_cast<ISA *>(params.isa)->decoderFlavor())
63 {
64  reset();
65 
66  // Initialize SVE vector length
67  sveLen = (safe_cast<ISA *>(params.isa)->
68  getCurSveVecLenInBitsAtReset() >> 7) - 1;
69 
70  if (dvmEnabled) {
71  warn_once(
72  "DVM Ops instructions are micro-architecturally "
73  "modelled as loads. This will tamper the effective "
74  "number of loads stat\n");
75  }
76 }
77 
78 void
80 {
82  bigThumb = false;
83  offset = 0;
84  emi = 0;
85  foundIt = false;
86 }
87 
88 void
90 {
91  // emi is typically ready, with some caveats below...
92  instDone = true;
93 
94  if (!emi.thumb) {
95  emi.instBits = data;
96  if (!emi.aarch64) {
97  emi.sevenAndFour = bits(data, 7) && bits(data, 4);
98  emi.isMisc = (bits(data, 24, 23) == 0x2 &&
99  bits(data, 20) == 0);
100  }
101  consumeBytes(4);
102  DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi);
103  } else {
104  uint16_t word = (data >> (offset * 8));
105  if (bigThumb) {
106  // A 32 bit thumb inst is half collected.
107  emi.instBits = emi.instBits | word;
108  bigThumb = false;
109  consumeBytes(2);
110  DPRINTF(Decoder, "Second half of 32 bit Thumb: %#x.\n",
111  emi.instBits);
112  } else {
113  uint16_t highBits = word & 0xF800;
114  if (highBits == 0xE800 || highBits == 0xF000 ||
115  highBits == 0xF800) {
116  // The start of a 32 bit thumb inst.
117  emi.bigThumb = 1;
118  if (offset == 0) {
119  // We've got the whole thing.
120  emi.instBits = (data >> 16) | (data << 16);
121  DPRINTF(Decoder, "All of 32 bit Thumb: %#x.\n",
122  emi.instBits);
123  consumeBytes(4);
124  } else {
125  // We only have the first half word.
127  "First half of 32 bit Thumb.\n");
128  emi.instBits = (uint32_t)word << 16;
129  bigThumb = true;
130  consumeBytes(2);
131  // emi not ready yet.
132  instDone = false;
133  }
134  } else {
135  // A 16 bit thumb inst.
136  consumeBytes(2);
137  emi.instBits = word;
138  // Set the condition code field artificially.
139  emi.condCode = COND_UC;
140  DPRINTF(Decoder, "16 bit Thumb: %#x.\n",
141  emi.instBits);
142  if (bits(word, 15, 8) == 0xbf &&
143  bits(word, 3, 0) != 0x0) {
144  foundIt = true;
145  itBits = bits(word, 7, 0);
147  "IT detected, cond = %#x, mask = %#x\n",
148  itBits.cond, itBits.mask);
149  }
150  }
151  }
152  }
153 }
154 
155 void
157 {
158  offset += numBytes;
159  assert(offset <= sizeof(data) || emi.decoderFault);
160  if (offset == sizeof(data))
161  outOfBytes = true;
162 }
163 
164 void
165 Decoder::moreBytes(const PCStateBase &_pc, Addr fetchPC)
166 {
167  auto &pc = _pc.as<PCState>();
168  data = letoh(data);
169  offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
170  emi.thumb = pc.thumb();
171  emi.aarch64 = pc.aarch64();
172  emi.fpscrLen = fpscrLen;
173  emi.fpscrStride = fpscrStride;
174  emi.sveLen = sveLen;
175 
176  const Addr alignment(pc.thumb() ? 0x1 : 0x3);
177  emi.decoderFault = static_cast<uint8_t>(
178  pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK);
179 
180  outOfBytes = false;
181  process();
182 }
183 
186 {
187  if (!instDone)
188  return NULL;
189 
190  auto &pc = _pc.as<PCState>();
191 
192  const int inst_size((!emi.thumb || emi.bigThumb) ? 4 : 2);
193  ExtMachInst this_emi(emi);
194 
195  pc.npc(pc.pc() + inst_size);
196  if (foundIt)
197  pc.nextItstate(itBits);
198  this_emi.itstate = pc.itstate();
199  this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
200  this_emi.debugStep = pc.debugStep() ? 1 : 0;
201  pc.size(inst_size);
202 
203  emi = 0;
204  instDone = false;
205  foundIt = false;
206 
207  return decode(this_emi, pc.instAddr());
208 }
209 
210 } // namespace ArmISA
211 } // namespace gem5
#define DPRINTF(x,...)
Definition: trace.hh:186
const char data[]
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:91
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:156
void reset() override
Reset the decoders internal state.
Definition: decoder.cc:79
Decoder(const ArmDecoderParams &params)
Definition: decoder.cc:58
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:130
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:86
ExtMachInst emi
Definition: decoder.hh:72
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:89
void moreBytes(const PCStateBase &pc, Addr fetchPC) override
Feed data to the decoder.
Definition: decoder.cc:165
const bool dvmEnabled
True if the decoder should emit DVM Ops (treated as Loads)
Definition: decoder.hh:68
virtual void reset()
Definition: decoder.hh:63
Target & as()
Definition: pcstate.hh:72
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
const Params & params() const
Definition: sim_object.hh:176
#define warn_once(...)
Definition: logging.hh:250
@ UNALIGNED
Unaligned instruction fault.
Definition: types.hh:359
@ OK
No fault.
Definition: types.hh:358
Bitfield< 41, 40 > fpscrStride
Definition: types.hh:75
Bitfield< 39, 37 > fpscrLen
Definition: types.hh:76
@ COND_UC
Definition: cc.hh:108
Bitfield< 4 > pc
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
T letoh(T value)
Definition: byteswap.hh:173
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
T safe_cast(U ptr)
Definition: cast.hh:62
unsigned int word
Definition: scfx_mant.hh:64

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