gem5  v21.1.0.2
decoder.cc
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2012-2014,2018 ARM Limited
3  * All rights reserved
4  *
5  * The license below extends only to copyright in the software and shall
6  * not be construed as granting a license to any other intellectual
7  * property including but not limited to intellectual property relating
8  * to a hardware implementation of the functionality of the software
9  * licensed hereunder. You may use the software subject to the license
10  * terms below provided that you ensure that this notice is replicated
11  * unmodified and in its entirety in all distributions of the software,
12  * modified or unmodified, in source code or in binary form.
13  *
14  * Copyright (c) 2012 Google
15  * All rights reserved.
16  *
17  * Redistribution and use in source and binary forms, with or without
18  * modification, are permitted provided that the following conditions are
19  * met: redistributions of source code must retain the above copyright
20  * notice, this list of conditions and the following disclaimer;
21  * redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the distribution;
24  * neither the name of the copyright holders nor the names of its
25  * contributors may be used to endorse or promote products derived from
26  * this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include "arch/arm/decoder.hh"
42 
43 #include "arch/arm/isa.hh"
44 #include "arch/arm/utility.hh"
45 #include "base/trace.hh"
46 #include "debug/Decoder.hh"
47 #include "sim/full_system.hh"
48 
49 namespace gem5
50 {
51 
52 namespace ArmISA
53 {
54 
56 
58  : InstDecoder(&data), data(0), fpscrLen(0), fpscrStride(0),
59  decoderFlavor(isa->decoderFlavor())
60 {
61  reset();
62 
63  // Initialize SVE vector length
64  sveLen = (isa->getCurSveVecLenInBitsAtReset() >> 7) - 1;
65 }
66 
67 void
69 {
70  bigThumb = false;
71  offset = 0;
72  emi = 0;
73  instDone = false;
74  outOfBytes = true;
75  foundIt = false;
76 }
77 
78 void
80 {
81  // emi is typically ready, with some caveats below...
82  instDone = true;
83 
84  if (!emi.thumb) {
85  emi.instBits = data;
86  if (!emi.aarch64) {
87  emi.sevenAndFour = bits(data, 7) && bits(data, 4);
88  emi.isMisc = (bits(data, 24, 23) == 0x2 &&
89  bits(data, 20) == 0);
90  }
91  consumeBytes(4);
92  DPRINTF(Decoder, "Arm inst: %#x.\n", (uint64_t)emi);
93  } else {
94  uint16_t word = (data >> (offset * 8));
95  if (bigThumb) {
96  // A 32 bit thumb inst is half collected.
97  emi.instBits = emi.instBits | word;
98  bigThumb = false;
99  consumeBytes(2);
100  DPRINTF(Decoder, "Second half of 32 bit Thumb: %#x.\n",
101  emi.instBits);
102  } else {
103  uint16_t highBits = word & 0xF800;
104  if (highBits == 0xE800 || highBits == 0xF000 ||
105  highBits == 0xF800) {
106  // The start of a 32 bit thumb inst.
107  emi.bigThumb = 1;
108  if (offset == 0) {
109  // We've got the whole thing.
110  emi.instBits = (data >> 16) | (data << 16);
111  DPRINTF(Decoder, "All of 32 bit Thumb: %#x.\n",
112  emi.instBits);
113  consumeBytes(4);
114  } else {
115  // We only have the first half word.
117  "First half of 32 bit Thumb.\n");
118  emi.instBits = (uint32_t)word << 16;
119  bigThumb = true;
120  consumeBytes(2);
121  // emi not ready yet.
122  instDone = false;
123  }
124  } else {
125  // A 16 bit thumb inst.
126  consumeBytes(2);
127  emi.instBits = word;
128  // Set the condition code field artificially.
129  emi.condCode = COND_UC;
130  DPRINTF(Decoder, "16 bit Thumb: %#x.\n",
131  emi.instBits);
132  if (bits(word, 15, 8) == 0xbf &&
133  bits(word, 3, 0) != 0x0) {
134  foundIt = true;
135  itBits = bits(word, 7, 0);
137  "IT detected, cond = %#x, mask = %#x\n",
138  itBits.cond, itBits.mask);
139  }
140  }
141  }
142  }
143 }
144 
145 void
147 {
148  offset += numBytes;
149  assert(offset <= sizeof(data) || emi.decoderFault);
150  if (offset == sizeof(data))
151  outOfBytes = true;
152 }
153 
154 void
156 {
157  data = letoh(data);
158  offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
159  emi.thumb = pc.thumb();
160  emi.aarch64 = pc.aarch64();
161  emi.fpscrLen = fpscrLen;
162  emi.fpscrStride = fpscrStride;
163  emi.sveLen = sveLen;
164 
165  const Addr alignment(pc.thumb() ? 0x1 : 0x3);
166  emi.decoderFault = static_cast<uint8_t>(
167  pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK);
168 
169  outOfBytes = false;
170  process();
171 }
172 
175 {
176  if (!instDone)
177  return NULL;
178 
179  const int inst_size((!emi.thumb || emi.bigThumb) ? 4 : 2);
180  ExtMachInst this_emi(emi);
181 
182  pc.npc(pc.pc() + inst_size);
183  if (foundIt)
184  pc.nextItstate(itBits);
185  this_emi.itstate = pc.itstate();
186  this_emi.illegalExecution = pc.illegalExec() ? 1 : 0;
187  this_emi.debugStep = pc.debugStep() ? 1 : 0;
188  pc.size(inst_size);
189 
190  emi = 0;
191  instDone = false;
192  foundIt = false;
193 
194  return decode(this_emi, pc.instAddr());
195 }
196 
197 } // namespace ArmISA
198 } // namespace gem5
gem5::ArmISA::fpscrLen
Bitfield< 39, 37 > fpscrLen
Definition: types.hh:76
gem5::ArmISA::fpscrStride
Bitfield< 41, 40 > fpscrStride
Definition: types.hh:75
gem5::ArmISA::Decoder::data
uint32_t data
Definition: decoder.hh:67
gem5::ArmISA::UNALIGNED
@ UNALIGNED
Unaligned instruction fault.
Definition: types.hh:352
sc_dt::word
unsigned int word
Definition: scfx_mant.hh:96
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::ArmISA::ISA
Definition: isa.hh:68
gem5::ArmISA::Decoder::offset
int offset
Definition: decoder.hh:71
gem5::ArmISA::Decoder::fpscrLen
int fpscrLen
Definition: decoder.hh:75
gem5::GenericISA::BasicDecodeCache
Definition: decode_cache.hh:43
gem5::ArmISA::Decoder::foundIt
bool foundIt
Definition: decoder.hh:72
gem5::ArmISA::ISA::getCurSveVecLenInBitsAtReset
unsigned getCurSveVecLenInBitsAtReset() const
Definition: isa.hh:856
gem5::ArmISA::Decoder::defaultCache
static GenericISA::BasicDecodeCache< Decoder, ExtMachInst > defaultCache
A cache of decoded instruction objects.
Definition: decoder.hh:87
gem5::PowerISA::PCState
Definition: pcstate.hh:42
gem5::RefCountingPtr< StaticInst >
gem5::letoh
T letoh(T value)
Definition: byteswap.hh:173
gem5::ArmISA::Decoder::moreBytes
void moreBytes(const PCState &pc, Addr fetchPC)
Feed data to the decoder.
Definition: decoder.cc:155
gem5::ArmISA::Decoder::instDone
bool instDone
Definition: decoder.hh:69
gem5::InstDecoder
Definition: decoder.hh:39
DPRINTF
#define DPRINTF(x,...)
Definition: trace.hh:186
gem5::ArmISA::Decoder::sveLen
int sveLen
SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN bitfields.
Definition: decoder.hh:82
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::ArmISA::COND_UC
@ COND_UC
Definition: cc.hh:84
isa.hh
gem5::ArmISA::Decoder::consumeBytes
void consumeBytes(int numBytes)
Consume bytes by moving the offset into the data word and sanity check the results.
Definition: decoder.cc:146
gem5::ArmISA::Decoder::fpscrStride
int fpscrStride
Definition: decoder.hh:76
gem5::ArmISA::Decoder
Definition: decoder.hh:62
gem5::ArmISA::Decoder::emi
ExtMachInst emi
Definition: decoder.hh:66
gem5::bits
constexpr T bits(T val, unsigned first, unsigned last)
Extract the bitfield from position 'first' to 'last' (inclusive) from 'val' and right justify it.
Definition: bitfield.hh:76
gem5::ArmISA::Decoder::process
void process()
Pre-decode an instruction from the current state of the decoder.
Definition: decoder.cc:79
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
utility.hh
full_system.hh
gem5::X86ISA::ExtMachInst
Definition: types.hh:206
gem5::ArmISA::Decoder::bigThumb
bool bigThumb
Definition: decoder.hh:68
gem5::ArmISA::OK
@ OK
No fault.
Definition: types.hh:351
gem5::MipsISA::pc
Bitfield< 4 > pc
Definition: pra_constants.hh:243
trace.hh
gem5::ArmISA::Decoder::reset
void reset()
Reset the decoders internal state.
Definition: decoder.cc:68
gem5::ArmISA::Decoder::outOfBytes
bool outOfBytes
Definition: decoder.hh:70
gem5::ArmISA::Decoder::Decoder
Decoder(ISA *isa=nullptr)
Definition: decoder.cc:57
gem5::ArmISA::Decoder::decode
StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
Decode a pre-decoded machine instruction.
Definition: decoder.hh:126
decoder.hh
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ArmISA::Decoder::itBits
ITSTATE itBits
Definition: decoder.hh:73

Generated on Tue Sep 21 2021 12:23:59 for gem5 by doxygen 1.8.17