gem5  v21.1.0.2
Classes | Variables
gem5::copy_engine_reg Namespace Reference

Classes

struct  ChanRegs
 
struct  DmaDesc
 
struct  Reg
 
struct  Regs
 

Variables

const uint32_t GEN_CHANCOUNT = 0x00
 
const uint32_t GEN_XFERCAP = 0x01
 
const uint32_t GEN_INTRCTRL = 0x03
 
const uint32_t GEN_ATTNSTATUS = 0x04
 
const uint32_t CHAN_CONTROL = 0x00
 
const uint32_t CHAN_STATUS = 0x04
 
const uint32_t CHAN_CHAINADDR = 0x0C
 
const uint32_t CHAN_CHAINADDR_LOW = 0x0C
 
const uint32_t CHAN_CHAINADDR_HIGH = 0x10
 
const uint32_t CHAN_COMMAND = 0x14
 
const uint32_t CHAN_CMPLNADDR = 0x18
 
const uint32_t CHAN_CMPLNADDR_LOW = 0x18
 
const uint32_t CHAN_CMPLNADDR_HIGH = 0x1C
 
const uint32_t CHAN_ERROR = 0x28
 
const uint32_t DESC_CTRL_INT_GEN = 0x00000001
 
const uint32_t DESC_CTRL_SRC_SN = 0x00000002
 
const uint32_t DESC_CTRL_DST_SN = 0x00000004
 
const uint32_t DESC_CTRL_CP_STS = 0x00000008
 
const uint32_t DESC_CTRL_FRAME = 0x00000010
 
const uint32_t DESC_CTRL_NULL = 0x00000020
 

Variable Documentation

◆ CHAN_CHAINADDR

const uint32_t gem5::copy_engine_reg::CHAN_CHAINADDR = 0x0C

◆ CHAN_CHAINADDR_HIGH

const uint32_t gem5::copy_engine_reg::CHAN_CHAINADDR_HIGH = 0x10

◆ CHAN_CHAINADDR_LOW

const uint32_t gem5::copy_engine_reg::CHAN_CHAINADDR_LOW = 0x0C

Definition at line 54 of file copy_engine_defs.hh.

◆ CHAN_CMPLNADDR

const uint32_t gem5::copy_engine_reg::CHAN_CMPLNADDR = 0x18

◆ CHAN_CMPLNADDR_HIGH

const uint32_t gem5::copy_engine_reg::CHAN_CMPLNADDR_HIGH = 0x1C

◆ CHAN_CMPLNADDR_LOW

const uint32_t gem5::copy_engine_reg::CHAN_CMPLNADDR_LOW = 0x18

Definition at line 58 of file copy_engine_defs.hh.

◆ CHAN_COMMAND

const uint32_t gem5::copy_engine_reg::CHAN_COMMAND = 0x14

◆ CHAN_CONTROL

const uint32_t gem5::copy_engine_reg::CHAN_CONTROL = 0x00

◆ CHAN_ERROR

const uint32_t gem5::copy_engine_reg::CHAN_ERROR = 0x28

◆ CHAN_STATUS

const uint32_t gem5::copy_engine_reg::CHAN_STATUS = 0x04

◆ DESC_CTRL_CP_STS

const uint32_t gem5::copy_engine_reg::DESC_CTRL_CP_STS = 0x00000008

◆ DESC_CTRL_DST_SN

const uint32_t gem5::copy_engine_reg::DESC_CTRL_DST_SN = 0x00000004

Definition at line 65 of file copy_engine_defs.hh.

◆ DESC_CTRL_FRAME

const uint32_t gem5::copy_engine_reg::DESC_CTRL_FRAME = 0x00000010

Definition at line 67 of file copy_engine_defs.hh.

◆ DESC_CTRL_INT_GEN

const uint32_t gem5::copy_engine_reg::DESC_CTRL_INT_GEN = 0x00000001

Definition at line 63 of file copy_engine_defs.hh.

◆ DESC_CTRL_NULL

const uint32_t gem5::copy_engine_reg::DESC_CTRL_NULL = 0x00000020

◆ DESC_CTRL_SRC_SN

const uint32_t gem5::copy_engine_reg::DESC_CTRL_SRC_SN = 0x00000002

Definition at line 64 of file copy_engine_defs.hh.

◆ GEN_ATTNSTATUS

const uint32_t gem5::copy_engine_reg::GEN_ATTNSTATUS = 0x04

Definition at line 47 of file copy_engine_defs.hh.

Referenced by gem5::CopyEngine::read(), and gem5::CopyEngine::write().

◆ GEN_CHANCOUNT

const uint32_t gem5::copy_engine_reg::GEN_CHANCOUNT = 0x00

Definition at line 44 of file copy_engine_defs.hh.

Referenced by gem5::CopyEngine::read(), and gem5::CopyEngine::write().

◆ GEN_INTRCTRL

const uint32_t gem5::copy_engine_reg::GEN_INTRCTRL = 0x03

Definition at line 46 of file copy_engine_defs.hh.

Referenced by gem5::CopyEngine::read(), and gem5::CopyEngine::write().

◆ GEN_XFERCAP

const uint32_t gem5::copy_engine_reg::GEN_XFERCAP = 0x01

Definition at line 45 of file copy_engine_defs.hh.

Referenced by gem5::CopyEngine::read(), and gem5::CopyEngine::write().


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