gem5  v21.1.0.2
copy_engine_defs.hh
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28 
29 /* @file
30  * Register and structure descriptions for Intel's I/O AT DMA Engine
31  */
32 #include "base/bitfield.hh"
33 #include "base/compiler.hh"
34 #include "sim/serialize.hh"
35 
36 namespace gem5
37 {
38 
39 GEM5_DEPRECATED_NAMESPACE(CopyEngineReg, copy_engine_reg);
40 namespace copy_engine_reg
41 {
42 
43 // General Channel independant registers, 128 bytes starting at 0x00
44 const uint32_t GEN_CHANCOUNT = 0x00;
45 const uint32_t GEN_XFERCAP = 0x01;
46 const uint32_t GEN_INTRCTRL = 0x03;
47 const uint32_t GEN_ATTNSTATUS = 0x04;
48 
49 
50 // Channel specific registers, each block is 128 bytes, starting at 0x80
51 const uint32_t CHAN_CONTROL = 0x00;
52 const uint32_t CHAN_STATUS = 0x04;
53 const uint32_t CHAN_CHAINADDR = 0x0C;
54 const uint32_t CHAN_CHAINADDR_LOW = 0x0C;
55 const uint32_t CHAN_CHAINADDR_HIGH = 0x10;
56 const uint32_t CHAN_COMMAND = 0x14;
57 const uint32_t CHAN_CMPLNADDR = 0x18;
58 const uint32_t CHAN_CMPLNADDR_LOW = 0x18;
59 const uint32_t CHAN_CMPLNADDR_HIGH = 0x1C;
60 const uint32_t CHAN_ERROR = 0x28;
61 
62 
63 const uint32_t DESC_CTRL_INT_GEN = 0x00000001;
64 const uint32_t DESC_CTRL_SRC_SN = 0x00000002;
65 const uint32_t DESC_CTRL_DST_SN = 0x00000004;
66 const uint32_t DESC_CTRL_CP_STS = 0x00000008;
67 const uint32_t DESC_CTRL_FRAME = 0x00000010;
68 const uint32_t DESC_CTRL_NULL = 0x00000020;
69 
70 struct DmaDesc
71 {
72  uint32_t len;
73  uint32_t command;
77  uint64_t reserved1;
78  uint64_t reserved2;
79  uint64_t user1;
80  uint64_t user2;
81 };
82 
83 #define ADD_FIELD8(NAME, OFFSET, BITS) \
84  inline uint8_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
85  inline void NAME(uint8_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
86 
87 #define ADD_FIELD16(NAME, OFFSET, BITS) \
88  inline uint16_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
89  inline void NAME(uint16_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
90 
91 #define ADD_FIELD32(NAME, OFFSET, BITS) \
92  inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
93  inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
94 
95 #define ADD_FIELD64(NAME, OFFSET, BITS) \
96  inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
97  inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); }
98 
99 template<class T>
100 struct Reg
101 {
102  T _data;
103  T operator()() { return _data; }
104  const Reg<T> &operator=(T d) { _data = d; return *this;}
105  bool operator==(T d) { return d == _data; }
106  void operator()(T d) { _data = d; }
107  Reg() { _data = 0; }
108  void serialize(CheckpointOut &cp) const
109  {
111  }
113  {
115  }
116 };
117 
118 
119 struct Regs : public Serializable
120 {
121  uint8_t chanCount;
122  uint8_t xferCap;
123 
124  struct INTRCTRL : public Reg<uint8_t>
125  {
126  // 0x03
127  using Reg<uint8_t>::operator =;
128  ADD_FIELD8(master_int_enable,0,1);
129  ADD_FIELD8(interrupt_status,1,1);
130  ADD_FIELD8(interrupt,2,1);
131  };
133 
134  uint32_t attnStatus; // Read clears
135 
136  void serialize(CheckpointOut &cp) const override
137  {
140  paramOut(cp, "intrctrl", intrctrl._data);
142  }
143 
144  void unserialize(CheckpointIn &cp) override
145  {
148  paramIn(cp, "intrctrl", intrctrl._data);
150  }
151 
152 };
153 
154 struct ChanRegs : public Serializable
155 {
156  struct CHANCTRL : public Reg<uint16_t>
157  {
158  // channelX + 0x00
159  using Reg<uint16_t>::operator =;
160  ADD_FIELD16(interrupt_disable,0,1);
161  ADD_FIELD16(error_completion_enable, 2,1);
162  ADD_FIELD16(any_error_abort_enable,3,1);
163  ADD_FIELD16(error_int_enable,4,1);
164  ADD_FIELD16(desc_addr_snoop_control,5,1);
165  ADD_FIELD16(in_use, 8,1);
166  };
168 
169  struct CHANSTS : public Reg<uint64_t>
170  {
171  // channelX + 0x04
172  ADD_FIELD64(dma_transfer_status, 0, 3);
173  ADD_FIELD64(unaffiliated_error, 3, 1);
174  ADD_FIELD64(soft_error, 4, 1);
175  ADD_FIELD64(compl_desc_addr, 6, 58);
176  };
178 
179  uint64_t descChainAddr;
180 
181  struct CHANCMD : public Reg<uint8_t>
182  {
183  // channelX + 0x14
184  ADD_FIELD8(start_dma,0,1);
185  ADD_FIELD8(append_dma,1,1);
186  ADD_FIELD8(suspend_dma,2,1);
187  ADD_FIELD8(abort_dma,3,1);
188  ADD_FIELD8(resume_dma,4,1);
189  ADD_FIELD8(reset_dma,5,1);
190  };
192 
193  uint64_t completionAddr;
194 
195  struct CHANERR : public Reg<uint32_t>
196  {
197  // channel X + 0x28
198  ADD_FIELD32(source_addr_error,0,1);
199  ADD_FIELD32(dest_addr_error,1,1);
200  ADD_FIELD32(ndesc_addr_error,2,1);
201  ADD_FIELD32(desc_error,3,1);
202  ADD_FIELD32(chain_addr_error,4,1);
203  ADD_FIELD32(chain_cmd_error,5,1);
204  ADD_FIELD32(chipset_parity_error,6,1);
205  ADD_FIELD32(dma_parity_error,7,1);
206  ADD_FIELD32(read_data_error,8,1);
207  ADD_FIELD32(write_data_error,9,1);
208  ADD_FIELD32(desc_control_error,10,1);
209  ADD_FIELD32(desc_len_error,11,1);
210  ADD_FIELD32(completion_addr_error,12,1);
211  ADD_FIELD32(interrupt_config_error,13,1);
212  ADD_FIELD32(soft_error,14,1);
213  ADD_FIELD32(unaffiliated_error,15,1);
214  };
216 
217  void serialize(CheckpointOut &cp) const override
218  {
219  paramOut(cp, "ctrl", ctrl._data);
220  paramOut(cp, "status", status._data);
222  paramOut(cp, "command", command._data);
224  paramOut(cp, "error", error._data);
225  }
226 
227  void unserialize(CheckpointIn &cp) override
228  {
229  paramIn(cp, "ctrl", ctrl._data);
230  paramIn(cp, "status", status._data);
232  paramIn(cp, "command", command._data);
234  paramIn(cp, "error", error._data);
235  }
236 
237 
238 };
239 
240 } // namespace copy_engine_reg
241 } // namespace gem5
gem5::copy_engine_reg::ChanRegs::CHANCMD::ADD_FIELD8
ADD_FIELD8(start_dma, 0, 1)
gem5::copy_engine_reg::Reg::serialize
void serialize(CheckpointOut &cp) const
Definition: copy_engine_defs.hh:108
gem5::copy_engine_reg::Regs::attnStatus
uint32_t attnStatus
Definition: copy_engine_defs.hh:134
gem5::copy_engine_reg::DmaDesc::dest
Addr dest
Definition: copy_engine_defs.hh:75
serialize.hh
UNSERIALIZE_SCALAR
#define UNSERIALIZE_SCALAR(scalar)
Definition: serialize.hh:575
gem5::copy_engine_reg::DESC_CTRL_SRC_SN
const uint32_t DESC_CTRL_SRC_SN
Definition: copy_engine_defs.hh:64
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::copy_engine_reg::CHAN_CMPLNADDR_HIGH
const uint32_t CHAN_CMPLNADDR_HIGH
Definition: copy_engine_defs.hh:59
gem5::copy_engine_reg::Reg::unserialize
void unserialize(CheckpointIn &cp)
Definition: copy_engine_defs.hh:112
gem5::copy_engine_reg::Regs::INTRCTRL
Definition: copy_engine_defs.hh:124
gem5::copy_engine_reg::DmaDesc::reserved1
uint64_t reserved1
Definition: copy_engine_defs.hh:77
gem5::copy_engine_reg::ChanRegs::CHANCTRL
Definition: copy_engine_defs.hh:156
gem5::copy_engine_reg::DESC_CTRL_DST_SN
const uint32_t DESC_CTRL_DST_SN
Definition: copy_engine_defs.hh:65
gem5::copy_engine_reg::CHAN_CMPLNADDR
const uint32_t CHAN_CMPLNADDR
Definition: copy_engine_defs.hh:57
gem5::copy_engine_reg::Reg
Definition: copy_engine_defs.hh:100
gem5::copy_engine_reg::Regs
Definition: copy_engine_defs.hh:119
gem5::copy_engine_reg::Regs::intrctrl
INTRCTRL intrctrl
Definition: copy_engine_defs.hh:132
gem5::copy_engine_reg::DmaDesc
Definition: copy_engine_defs.hh:70
gem5::copy_engine_reg::CHAN_ERROR
const uint32_t CHAN_ERROR
Definition: copy_engine_defs.hh:60
gem5::copy_engine_reg::Reg::operator==
bool operator==(T d)
Definition: copy_engine_defs.hh:105
gem5::copy_engine_reg::DmaDesc::len
uint32_t len
Definition: copy_engine_defs.hh:72
gem5::copy_engine_reg::ChanRegs::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: copy_engine_defs.hh:217
gem5::copy_engine_reg::CHAN_STATUS
const uint32_t CHAN_STATUS
Definition: copy_engine_defs.hh:52
gem5::copy_engine_reg::DESC_CTRL_NULL
const uint32_t DESC_CTRL_NULL
Definition: copy_engine_defs.hh:68
gem5::Serializable
Basic support for object serialization.
Definition: serialize.hh:169
gem5::copy_engine_reg::ChanRegs::CHANCMD
Definition: copy_engine_defs.hh:181
gem5::copy_engine_reg::Regs::xferCap
uint8_t xferCap
Definition: copy_engine_defs.hh:122
bitfield.hh
gem5::copy_engine_reg::GEN_XFERCAP
const uint32_t GEN_XFERCAP
Definition: copy_engine_defs.hh:45
gem5::ArmISA::d
Bitfield< 9 > d
Definition: misc_types.hh:63
gem5::copy_engine_reg::CHAN_CMPLNADDR_LOW
const uint32_t CHAN_CMPLNADDR_LOW
Definition: copy_engine_defs.hh:58
gem5::copy_engine_reg::ChanRegs::CHANSTS::ADD_FIELD64
ADD_FIELD64(dma_transfer_status, 0, 3)
gem5::copy_engine_reg::ChanRegs::completionAddr
uint64_t completionAddr
Definition: copy_engine_defs.hh:193
gem5::copy_engine_reg::CHAN_COMMAND
const uint32_t CHAN_COMMAND
Definition: copy_engine_defs.hh:56
gem5::copy_engine_reg::ChanRegs::CHANSTS
Definition: copy_engine_defs.hh:169
gem5::copy_engine_reg::ChanRegs
Definition: copy_engine_defs.hh:154
compiler.hh
gem5::copy_engine_reg::DmaDesc::user1
uint64_t user1
Definition: copy_engine_defs.hh:79
gem5::copy_engine_reg::ChanRegs::descChainAddr
uint64_t descChainAddr
Definition: copy_engine_defs.hh:179
gem5::copy_engine_reg::ChanRegs::status
CHANSTS status
Definition: copy_engine_defs.hh:177
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
gem5::copy_engine_reg::ChanRegs::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: copy_engine_defs.hh:227
gem5::GEM5_DEPRECATED_NAMESPACE
GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi)
SERIALIZE_SCALAR
#define SERIALIZE_SCALAR(scalar)
Definition: serialize.hh:568
gem5::copy_engine_reg::DmaDesc::user2
uint64_t user2
Definition: copy_engine_defs.hh:80
gem5::copy_engine_reg::DmaDesc::reserved2
uint64_t reserved2
Definition: copy_engine_defs.hh:78
gem5::copy_engine_reg::CHAN_CHAINADDR_HIGH
const uint32_t CHAN_CHAINADDR_HIGH
Definition: copy_engine_defs.hh:55
gem5::igbreg::Regs::Reg
Definition: i8254xGBe_defs.hh:316
gem5::copy_engine_reg::ChanRegs::error
CHANERR error
Definition: copy_engine_defs.hh:215
gem5::copy_engine_reg::ChanRegs::CHANERR
Definition: copy_engine_defs.hh:195
gem5::copy_engine_reg::Reg::operator()
void operator()(T d)
Definition: copy_engine_defs.hh:106
gem5::copy_engine_reg::DESC_CTRL_CP_STS
const uint32_t DESC_CTRL_CP_STS
Definition: copy_engine_defs.hh:66
gem5::copy_engine_reg::Reg::_data
T _data
Definition: copy_engine_defs.hh:102
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
gem5::copy_engine_reg::DmaDesc::src
Addr src
Definition: copy_engine_defs.hh:74
gem5::copy_engine_reg::GEN_ATTNSTATUS
const uint32_t GEN_ATTNSTATUS
Definition: copy_engine_defs.hh:47
gem5::copy_engine_reg::DESC_CTRL_FRAME
const uint32_t DESC_CTRL_FRAME
Definition: copy_engine_defs.hh:67
gem5::copy_engine_reg::ChanRegs::ctrl
CHANCTRL ctrl
Definition: copy_engine_defs.hh:167
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::copy_engine_reg::DmaDesc::next
Addr next
Definition: copy_engine_defs.hh:76
gem5::copy_engine_reg::Regs::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition: copy_engine_defs.hh:136
gem5::copy_engine_reg::DESC_CTRL_INT_GEN
const uint32_t DESC_CTRL_INT_GEN
Definition: copy_engine_defs.hh:63
gem5::copy_engine_reg::Regs::INTRCTRL::ADD_FIELD8
ADD_FIELD8(master_int_enable, 0, 1)
gem5::copy_engine_reg::ChanRegs::CHANERR::ADD_FIELD32
ADD_FIELD32(source_addr_error, 0, 1)
gem5::copy_engine_reg::Reg::Reg
Reg()
Definition: copy_engine_defs.hh:107
gem5::copy_engine_reg::Regs::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition: copy_engine_defs.hh:144
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::copy_engine_reg::DmaDesc::command
uint32_t command
Definition: copy_engine_defs.hh:73
gem5::copy_engine_reg::Reg::operator()
T operator()()
Definition: copy_engine_defs.hh:103
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::copy_engine_reg::CHAN_CHAINADDR
const uint32_t CHAN_CHAINADDR
Definition: copy_engine_defs.hh:53
gem5::copy_engine_reg::Regs::chanCount
uint8_t chanCount
Definition: copy_engine_defs.hh:121
gem5::copy_engine_reg::ChanRegs::command
CHANCMD command
Definition: copy_engine_defs.hh:191
gem5::copy_engine_reg::GEN_CHANCOUNT
const uint32_t GEN_CHANCOUNT
Definition: copy_engine_defs.hh:44
gem5::copy_engine_reg::CHAN_CHAINADDR_LOW
const uint32_t CHAN_CHAINADDR_LOW
Definition: copy_engine_defs.hh:54
gem5::copy_engine_reg::Reg::operator=
const Reg< T > & operator=(T d)
Definition: copy_engine_defs.hh:104
gem5::copy_engine_reg::CHAN_CONTROL
const uint32_t CHAN_CONTROL
Definition: copy_engine_defs.hh:51
gem5::copy_engine_reg::ChanRegs::CHANCTRL::ADD_FIELD16
ADD_FIELD16(interrupt_disable, 0, 1)
gem5::copy_engine_reg::GEN_INTRCTRL
const uint32_t GEN_INTRCTRL
Definition: copy_engine_defs.hh:46

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