gem5 v24.0.0.0
Loading...
Searching...
No Matches
thread_state.hh
Go to the documentation of this file.
1/*
2 * Copyright (c) 2012, 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 */
40
41#ifndef __CPU_O3_THREAD_STATE_HH__
42#define __CPU_O3_THREAD_STATE_HH__
43
44#include <memory>
45
46#include "cpu/thread_context.hh"
47#include "cpu/thread_state.hh"
48
49namespace gem5
50{
51
52class Process;
53
54namespace o3
55{
56
57class CPU;
58
67{
68 public:
75
76 /* This variable controls if writes to a thread context should cause a all
77 * dynamic/speculative state to be thrown away. Nominally this is the
78 * desired behavior because the external thread context write has updated
79 * some state that could be used by an inflight instruction, however there
80 * are some cases like in a fault/trap handler where this behavior would
81 * lead to successive restarts and forward progress couldn't be made. This
82 * variable controls if the squashing will occur.
83 */
84 bool noSquashFromTC = false;
85
89 bool trapPending = false;
90
92 std::unique_ptr<BaseHTMCheckpoint> htmCheckpoint;
93
94 ThreadState(CPU *_cpu, int _thread_num, Process *_process);
95
96 void serialize(CheckpointOut &cp) const override;
97 void unserialize(CheckpointIn &cp) override;
98
101
104};
105
106} // namespace o3
107} // namespace gem5
108
109#endif // __CPU_O3_THREAD_STATE_HH__
Queue of events sorted in time order.
Definition eventq.hh:616
ThreadContext is the external interface to all thread state for anything outside of the CPU.
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition cpu.hh:94
Class that has various thread state, such as the status, the current instruction being processed,...
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
ThreadState(CPU *_cpu, int _thread_num, Process *_process)
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
gem5::ThreadContext * tc
Pointer to the ThreadContext of this thread.
void unserialize(CheckpointIn &cp) override
Unserialize an object.
void serialize(CheckpointOut &cp) const override
Serialize an object.
EventQueue comInstEventQueue
An instruction-based event queue.
gem5::ThreadContext * getTC()
Returns a pointer to the TC of this thread.
PCEventQueue pcEventQueue
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition binary32.hh:36
std::ostream CheckpointOut
Definition serialize.hh:66
Struct for holding general thread state that is needed across CPU models.

Generated on Tue Jun 18 2024 16:24:02 for gem5 by doxygen 1.11.0