gem5
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cpu
o3
thread_state.hh
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/*
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* Copyright (c) 2012, 2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_THREAD_STATE_HH__
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#define __CPU_O3_THREAD_STATE_HH__
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#include <memory>
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#include "
cpu/thread_context.hh
"
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#include "
cpu/thread_state.hh
"
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namespace
gem5
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{
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class
Process;
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namespace
o3
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{
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class
CPU;
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class
ThreadState
:
public
gem5::ThreadState
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{
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public
:
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PCEventQueue
pcEventQueue
;
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EventQueue
comInstEventQueue
;
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/* This variable controls if writes to a thread context should cause a all
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* dynamic/speculative state to be thrown away. Nominally this is the
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* desired behavior because the external thread context write has updated
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* some state that could be used by an inflight instruction, however there
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* are some cases like in a fault/trap handler where this behavior would
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* lead to successive restarts and forward progress couldn't be made. This
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* variable controls if the squashing will occur.
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*/
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bool
noSquashFromTC
=
false
;
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bool
trapPending
=
false
;
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std::unique_ptr<BaseHTMCheckpoint>
htmCheckpoint
;
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ThreadState
(
CPU
*_cpu,
int
_thread_num,
Process
*_process);
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void
serialize
(
CheckpointOut
&cp)
const override
;
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void
unserialize
(
CheckpointIn
&cp)
override
;
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gem5::ThreadContext
*
tc
=
nullptr
;
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gem5::ThreadContext
*
getTC
() {
return
tc
; }
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};
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}
// namespace o3
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}
// namespace gem5
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#endif
// __CPU_O3_THREAD_STATE_HH__
gem5::CheckpointIn
Definition
serialize.hh:69
gem5::EventQueue
Queue of events sorted in time order.
Definition
eventq.hh:616
gem5::PCEventQueue
Definition
pc_event.hh:75
gem5::Process
Definition
process.hh:68
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition
guest_abi.test.cc:41
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition
cpu.hh:94
gem5::o3::ThreadState
Class that has various thread state, such as the status, the current instruction being processed,...
Definition
thread_state.hh:67
gem5::o3::ThreadState::trapPending
bool trapPending
Whether or not the thread is currently waiting on a trap, and thus able to be externally updated with...
Definition
thread_state.hh:89
gem5::o3::ThreadState::ThreadState
ThreadState(CPU *_cpu, int _thread_num, Process *_process)
Definition
thread_state.cc:51
gem5::o3::ThreadState::htmCheckpoint
std::unique_ptr< BaseHTMCheckpoint > htmCheckpoint
Pointer to the hardware transactional memory checkpoint.
Definition
thread_state.hh:92
gem5::o3::ThreadState::tc
gem5::ThreadContext * tc
Pointer to the ThreadContext of this thread.
Definition
thread_state.hh:100
gem5::o3::ThreadState::noSquashFromTC
bool noSquashFromTC
Definition
thread_state.hh:84
gem5::o3::ThreadState::unserialize
void unserialize(CheckpointIn &cp) override
Unserialize an object.
Definition
thread_state.cc:66
gem5::o3::ThreadState::serialize
void serialize(CheckpointOut &cp) const override
Serialize an object.
Definition
thread_state.cc:57
gem5::o3::ThreadState::comInstEventQueue
EventQueue comInstEventQueue
An instruction-based event queue.
Definition
thread_state.hh:74
gem5::o3::ThreadState::getTC
gem5::ThreadContext * getTC()
Returns a pointer to the TC of this thread.
Definition
thread_state.hh:103
gem5::o3::ThreadState::pcEventQueue
PCEventQueue pcEventQueue
Definition
thread_state.hh:69
thread_context.hh
gem5
Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
Definition
binary32.hh:36
gem5::CheckpointOut
std::ostream CheckpointOut
Definition
serialize.hh:66
gem5::ThreadState
Struct for holding general thread state that is needed across CPU models.
Definition
thread_state.hh:48
thread_state.hh
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