gem5  v21.2.1.1
Classes | Public Types | Public Member Functions | Public Attributes | Protected Attributes | Private Member Functions | Private Attributes | Friends | List of all members
gem5::o3::CPU Class Reference

O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages. More...

#include <cpu.hh>

Inheritance diagram for gem5::o3::CPU:

Classes

struct  CPUStats
 

Public Types

enum  Status {
  Running, Idle, Halted, Blocked,
  SwitchedOut
}
 
enum  StageIdx {
  FetchIdx, DecodeIdx, RenameIdx, IEWIdx,
  CommitIdx, NumStages
}
 Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated. More...
 
typedef std::list< DynInstPtr >::iterator ListIt
 
using LSQRequest = LSQ::LSQRequest
 

Public Member Functions

 CPU (const O3CPUParams &params)
 Constructs a CPU with the given parameters. More...
 
void regProbePoints () override
 Register probe points. More...
 
void demapPage (Addr vaddr, uint64_t asn)
 
void tick ()
 Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should deschedule itself. More...
 
void init () override
 Initialize the CPU. More...
 
void startup () override
 
int numActiveThreads ()
 Returns the Number of Active Threads in the CPU. More...
 
void activateThread (ThreadID tid)
 Add Thread to Active Threads List. More...
 
void deactivateThread (ThreadID tid)
 Remove Thread from Active Threads List. More...
 
void insertThread (ThreadID tid)
 Setup CPU to insert a thread's context. More...
 
void removeThread (ThreadID tid)
 Remove all of a thread's context from CPU. More...
 
Counter totalInsts () const override
 Count the Total Instructions Committed in the CPU. More...
 
Counter totalOps () const override
 Count the Total Ops (including micro ops) committed in the CPU. More...
 
void activateContext (ThreadID tid) override
 Add Thread to Active Threads List. More...
 
void suspendContext (ThreadID tid) override
 Remove Thread from Active Threads List. More...
 
void haltContext (ThreadID tid) override
 Remove Thread from Active Threads List && Remove Thread Context from CPU. More...
 
void updateThreadPriority ()
 Update The Order In Which We Process Threads. More...
 
bool isDraining () const
 Is the CPU draining? More...
 
void serializeThread (CheckpointOut &cp, ThreadID tid) const override
 
void unserializeThread (CheckpointIn &cp, ThreadID tid) override
 
void addThreadToExitingList (ThreadID tid)
 Insert tid to the list of threads trying to exit. More...
 
bool isThreadExiting (ThreadID tid) const
 Is the thread trying to exit? More...
 
void scheduleThreadExitEvent (ThreadID tid)
 If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread. More...
 
void exitThreads ()
 Terminate all threads that are ready to exit. More...
 
DrainState drain () override
 Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses. More...
 
void drainResume () override
 Resumes execution after a drain. More...
 
void commitDrained (ThreadID tid)
 Commit has reached a safe point to drain a thread. More...
 
void switchOut () override
 Switches out this CPU. More...
 
void takeOverFrom (BaseCPU *oldCPU) override
 Takes over from another CPU. More...
 
void verifyMemoryMode () const override
 
InstSeqNum getAndIncrementInstSeq ()
 Get the current instruction sequence number, and increment it. More...
 
void trap (const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
 Traps to handle given fault. More...
 
Fault getInterrupts ()
 Returns the Fault for any valid interrupt. More...
 
void processInterrupts (const Fault &interrupt)
 Processes any an interrupt fault. More...
 
void halt ()
 Halts the CPU. More...
 
RegVal readMiscRegNoEffect (int misc_reg, ThreadID tid) const
 Register accessors. More...
 
RegVal readMiscReg (int misc_reg, ThreadID tid)
 Reads a misc. More...
 
void setMiscRegNoEffect (int misc_reg, RegVal val, ThreadID tid)
 Sets a miscellaneous register. More...
 
void setMiscReg (int misc_reg, RegVal val, ThreadID tid)
 Sets a misc. More...
 
RegVal readIntReg (PhysRegIdPtr phys_reg)
 
RegVal readFloatReg (PhysRegIdPtr phys_reg)
 
const TheISA::VecRegContainer & readVecReg (PhysRegIdPtr reg_idx) const
 
TheISA::VecRegContainer & getWritableVecReg (PhysRegIdPtr reg_idx)
 Read physical vector register for modification. More...
 
RegVal readVecElem (PhysRegIdPtr reg_idx) const
 
const TheISA::VecPredRegContainer & readVecPredReg (PhysRegIdPtr reg_idx) const
 
TheISA::VecPredRegContainer & getWritableVecPredReg (PhysRegIdPtr reg_idx)
 
RegVal readCCReg (PhysRegIdPtr phys_reg)
 
void setIntReg (PhysRegIdPtr phys_reg, RegVal val)
 
void setFloatReg (PhysRegIdPtr phys_reg, RegVal val)
 
void setVecReg (PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)
 
void setVecElem (PhysRegIdPtr reg_idx, RegVal val)
 
void setVecPredReg (PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)
 
void setCCReg (PhysRegIdPtr phys_reg, RegVal val)
 
RegVal readArchIntReg (int reg_idx, ThreadID tid)
 
RegVal readArchFloatReg (int reg_idx, ThreadID tid)
 
const TheISA::VecRegContainer & readArchVecReg (int reg_idx, ThreadID tid) const
 
TheISA::VecRegContainer & getWritableArchVecReg (int reg_idx, ThreadID tid)
 Read architectural vector register for modification. More...
 
RegVal readArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const
 
const TheISA::VecPredRegContainer & readArchVecPredReg (int reg_idx, ThreadID tid) const
 
TheISA::VecPredRegContainer & getWritableArchVecPredReg (int reg_idx, ThreadID tid)
 
RegVal readArchCCReg (int reg_idx, ThreadID tid)
 
void setArchIntReg (int reg_idx, RegVal val, ThreadID tid)
 Architectural register accessors. More...
 
void setArchFloatReg (int reg_idx, RegVal val, ThreadID tid)
 
void setArchVecPredReg (int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)
 
void setArchVecReg (int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)
 
void setArchVecElem (const RegIndex &reg_idx, const ElemIndex &ldx, RegVal val, ThreadID tid)
 
void setArchCCReg (int reg_idx, RegVal val, ThreadID tid)
 
void pcState (const PCStateBase &new_pc_state, ThreadID tid)
 Sets the commit PC state of a specific thread. More...
 
const PCStateBasepcState (ThreadID tid)
 Reads the commit PC state of a specific thread. More...
 
void squashFromTC (ThreadID tid)
 Initiates a squash of all in-flight instructions for a given thread. More...
 
ListIt addInst (const DynInstPtr &inst)
 Function to add instruction onto the head of the list of the instructions. More...
 
void instDone (ThreadID tid, const DynInstPtr &inst)
 Function to tell the CPU that an instruction has completed. More...
 
void removeFrontInst (const DynInstPtr &inst)
 Remove an instruction from the front end of the list. More...
 
void removeInstsNotInROB (ThreadID tid)
 Remove all instructions that are not currently in the ROB. More...
 
void removeInstsUntil (const InstSeqNum &seq_num, ThreadID tid)
 Remove all instructions younger than the given sequence number. More...
 
void squashInstIt (const ListIt &instIt, ThreadID tid)
 Removes the instruction pointed to by the iterator. More...
 
void cleanUpRemovedInsts ()
 Cleans up all instructions on the remove list. More...
 
void dumpInsts ()
 Debug function to print all instructions on the list. More...
 
void activityThisCycle ()
 Records that there was time buffer activity this cycle. More...
 
void activateStage (const StageIdx idx)
 Changes a stage's status to active within the activity recorder. More...
 
void deactivateStage (const StageIdx idx)
 Changes a stage's status to inactive within the activity recorder. More...
 
void wakeCPU ()
 Wakes the CPU, rescheduling the CPU if it's not already active. More...
 
virtual void wakeup (ThreadID tid) override
 
ThreadID getFreeTid ()
 Gets a free thread id. More...
 
gem5::ThreadContexttcBase (ThreadID tid)
 Returns a pointer to a thread context. More...
 
Fault pushRequest (const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
 CPU pushRequest function, forwards request to LSQ. More...
 
PortgetInstPort () override
 Used by the fetch unit to get a hold of the instruction port. More...
 
PortgetDataPort () override
 Get the dcache port (used to find block size for translations). More...
 
void htmSendAbortSignal (ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
 

Public Attributes

BaseMMUmmu
 
Status _status
 Overall CPU status. More...
 
ProbePointArg< PacketPtr > * ppInstAccessComplete
 
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
 
int instcount
 Count of total number of dynamic instructions in flight. More...
 
std::list< DynInstPtrinstList
 List of all the instructions in flight. More...
 
std::queue< ListItremoveList
 List of all the instructions that will be removed at the end of this cycle. More...
 
bool removeInstsThisCycle
 Records if instructions need to be removed this cycle due to being retired or squashed. More...
 
TimeBuffer< TimeStructtimeBuffer
 The main time buffer to do backwards communication. More...
 
TimeBuffer< FetchStructfetchQueue
 The fetch stage's instruction queue. More...
 
TimeBuffer< DecodeStructdecodeQueue
 The decode stage's instruction queue. More...
 
TimeBuffer< RenameStructrenameQueue
 The rename stage's instruction queue. More...
 
TimeBuffer< IEWStructiewQueue
 The IEW stage's instruction queue. More...
 
InstSeqNum globalSeqNum
 The global sequence number counter. More...
 
gem5::Checker< DynInstPtr > * checker
 Pointer to the checker, which can dynamically verify instruction results at run time. More...
 
Systemsystem
 Pointer to the system. More...
 
std::vector< ThreadState * > thread
 Pointers to all of the threads in the CPU. More...
 
std::list< int > cpuWaitList
 Threads Scheduled to Enter CPU. More...
 
Cycles lastRunningCycle
 The cycle that the CPU was last running, used for statistics. More...
 
Tick lastActivatedCycle
 The cycle that the CPU was last activated by a new thread. More...
 
std::map< ThreadID, unsigned > threadMap
 Mapping for system thread id to cpu id. More...
 
std::vector< ThreadIDtids
 Available thread ids in the cpu. More...
 
gem5::o3::CPU::CPUStats cpuStats
 

Protected Attributes

Fetch fetch
 The fetch stage. More...
 
Decode decode
 The decode stage. More...
 
Rename rename
 The dispatch stage. More...
 
IEW iew
 The issue/execute/writeback stages. More...
 
Commit commit
 The commit stage. More...
 
PhysRegFile regFile
 The register file. More...
 
UnifiedFreeList freeList
 The free list. More...
 
UnifiedRenameMap renameMap [MaxThreads]
 The rename map. More...
 
UnifiedRenameMap commitRenameMap [MaxThreads]
 The commit rename map. More...
 
ROB rob
 The re-order buffer. More...
 
std::list< ThreadIDactiveThreads
 Active Threads List. More...
 
std::unordered_map< ThreadID, bool > exitingThreads
 This is a list of threads that are trying to exit. More...
 
Scoreboard scoreboard
 Integer Register Scoreboard. More...
 
std::vector< TheISA::ISA * > isa
 

Private Member Functions

void scheduleTickEvent (Cycles delay)
 Schedule tick event, regardless of its current state. More...
 
void unscheduleTickEvent ()
 Unschedule tick event, regardless of its current state. More...
 
bool tryDrain ()
 Check if the pipeline has drained and signal drain done. More...
 
void drainSanityCheck () const
 Perform sanity checks after a drain. More...
 
bool isCpuDrained () const
 Check if a system is in a drained state. More...
 

Private Attributes

EventFunctionWrapper tickEvent
 The tick event used for scheduling CPU ticks. More...
 
EventFunctionWrapper threadExitEvent
 The exit event used for terminating all ready-to-exit threads. More...
 
ActivityRecorder activityRec
 The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself. More...
 

Friends

class ThreadContext
 

Detailed Description

O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buffers between stages.

The tick() function for the CPU is defined here.

Definition at line 94 of file cpu.hh.

Member Typedef Documentation

◆ ListIt

Definition at line 97 of file cpu.hh.

◆ LSQRequest

Definition at line 112 of file cpu.hh.

Member Enumeration Documentation

◆ StageIdx

Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(), they can specify which stage is being activated/deactivated.

Enumerator
FetchIdx 
DecodeIdx 
RenameIdx 
IEWIdx 
CommitIdx 
NumStages 

Definition at line 505 of file cpu.hh.

◆ Status

Enumerator
Running 
Idle 
Halted 
Blocked 
SwitchedOut 

Definition at line 102 of file cpu.hh.

Constructor & Destructor Documentation

◆ CPU()

gem5::o3::CPU::CPU ( const O3CPUParams &  params)

Constructs a CPU with the given parameters.

Definition at line 73 of file cpu.cc.

References tick().

Member Function Documentation

◆ activateContext()

void gem5::o3::CPU::activateContext ( ThreadID  tid)
override

◆ activateStage()

void gem5::o3::CPU::activateStage ( const StageIdx  idx)
inline

◆ activateThread()

void gem5::o3::CPU::activateThread ( ThreadID  tid)

Add Thread to Active Threads List.

Definition at line 576 of file cpu.cc.

References activeThreads, and DPRINTF.

Referenced by activateContext(), and drainResume().

◆ activityThisCycle()

void gem5::o3::CPU::activityThisCycle ( )
inline

◆ addInst()

CPU::ListIt gem5::o3::CPU::addInst ( const DynInstPtr inst)

Function to add instruction onto the head of the list of the instructions.

Used when new instructions are fetched.

Definition at line 1330 of file cpu.cc.

References instList.

Referenced by gem5::o3::Fetch::buildInst().

◆ addThreadToExitingList()

void gem5::o3::CPU::addThreadToExitingList ( ThreadID  tid)

Insert tid to the list of threads trying to exit.

Definition at line 1575 of file cpu.cc.

References DPRINTF, exitingThreads, gem5::ThreadContext::Halted, gem5::ArmISA::status, and tcBase().

Referenced by gem5::o3::ThreadContext::halt().

◆ cleanUpRemovedInsts()

void gem5::o3::CPU::cleanUpRemovedInsts ( )

Cleans up all instructions on the remove list.

Definition at line 1462 of file cpu.cc.

References DPRINTF, instList, removeInstsThisCycle, and removeList.

Referenced by tick().

◆ commitDrained()

void gem5::o3::CPU::commitDrained ( ThreadID  tid)

Commit has reached a safe point to drain a thread.

Commit calls this method to inform the pipeline that it has reached a point where it is not executed microcode and is about to squash uncommitted instructions to fully drain the pipeline.

Definition at line 988 of file cpu.cc.

References gem5::o3::Fetch::drainStall(), and fetch.

Referenced by gem5::o3::Commit::commitInsts().

◆ deactivateStage()

void gem5::o3::CPU::deactivateStage ( const StageIdx  idx)
inline

◆ deactivateThread()

void gem5::o3::CPU::deactivateThread ( ThreadID  tid)

Remove Thread from Active Threads List.

Definition at line 592 of file cpu.cc.

References activeThreads, commit, gem5::o3::Commit::deactivateThread(), gem5::o3::Fetch::deactivateThread(), DPRINTF, gem5::o3::Commit::executingHtmTransaction(), and fetch.

Referenced by haltContext(), and suspendContext().

◆ demapPage()

void gem5::o3::CPU::demapPage ( Addr  vaddr,
uint64_t  asn 
)
inline

Definition at line 181 of file cpu.hh.

References gem5::BaseMMU::demapPage(), mmu, and gem5::MipsISA::vaddr.

Referenced by gem5::o3::DynInst::demapPage().

◆ drain()

DrainState gem5::o3::CPU::drain ( )
override

◆ drainResume()

void gem5::o3::CPU::drainResume ( )
override

◆ drainSanityCheck()

void gem5::o3::CPU::drainSanityCheck ( ) const
private

Perform sanity checks after a drain.

This method is called from drain() when it has determined that the CPU is fully drained when gem5 is compiled with the NDEBUG macro undefined. The intention of this method is to do more extensive tests than the isDrained() method to weed out any draining bugs.

Definition at line 940 of file cpu.cc.

References commit, decode, gem5::o3::Decode::drainSanityCheck(), gem5::o3::IEW::drainSanityCheck(), gem5::o3::Rename::drainSanityCheck(), gem5::o3::Commit::drainSanityCheck(), gem5::o3::Fetch::drainSanityCheck(), fetch, iew, isCpuDrained(), and rename.

Referenced by drain().

◆ dumpInsts()

void gem5::o3::CPU::dumpInsts ( )

Debug function to print all instructions on the list.

Definition at line 1486 of file cpu.cc.

References gem5::cprintf(), and instList.

Referenced by gem5::o3::DynInst::DynInst().

◆ exitThreads()

void gem5::o3::CPU::exitThreads ( )

Terminate all threads that are ready to exit.

Definition at line 1620 of file cpu.cc.

References DPRINTF, exitingThreads, haltContext(), gem5::ThreadContext::Halted, gem5::ThreadContext::setStatus(), and tcBase().

◆ getAndIncrementInstSeq()

InstSeqNum gem5::o3::CPU::getAndIncrementInstSeq ( )
inline

Get the current instruction sequence number, and increment it.

Definition at line 282 of file cpu.hh.

References globalSeqNum.

Referenced by gem5::o3::Fetch::buildInst().

◆ getDataPort()

Port& gem5::o3::CPU::getDataPort ( )
inlineoverride

Get the dcache port (used to find block size for translations).

Definition at line 622 of file cpu.hh.

References gem5::o3::LSQ::getDataPort(), iew, and gem5::o3::IEW::ldstQueue.

◆ getFreeTid()

ThreadID gem5::o3::CPU::getFreeTid ( )

Gets a free thread id.

Use if thread ids change across system.

Definition at line 1546 of file cpu.cc.

References gem5::InvalidThreadID, and tids.

◆ getInstPort()

Port& gem5::o3::CPU::getInstPort ( )
inlineoverride

Used by the fetch unit to get a hold of the instruction port.

Definition at line 615 of file cpu.hh.

References fetch, and gem5::o3::Fetch::getInstPort().

Referenced by gem5::o3::Fetch::takeOverFrom().

◆ getInterrupts()

Fault gem5::o3::CPU::getInterrupts ( )

Returns the Fault for any valid interrupt.

Definition at line 821 of file cpu.cc.

Referenced by gem5::o3::Commit::handleInterrupt(), and gem5::o3::Commit::propagateInterrupt().

◆ getWritableArchVecPredReg()

TheISA::VecPredRegContainer & gem5::o3::CPU::getWritableArchVecPredReg ( int  reg_idx,
ThreadID  tid 
)

◆ getWritableArchVecReg()

TheISA::VecRegContainer & gem5::o3::CPU::getWritableArchVecReg ( int  reg_idx,
ThreadID  tid 
)

Read architectural vector register for modification.

Definition at line 1215 of file cpu.cc.

References commitRenameMap, gem5::o3::PhysRegFile::getWritableVecReg(), gem5::o3::UnifiedRenameMap::lookup(), regFile, and gem5::VecRegClass.

Referenced by gem5::o3::ThreadContext::getWritableVecRegFlat().

◆ getWritableVecPredReg()

TheISA::VecPredRegContainer & gem5::o3::CPU::getWritableVecPredReg ( PhysRegIdPtr  reg_idx)

◆ getWritableVecReg()

TheISA::VecRegContainer & gem5::o3::CPU::getWritableVecReg ( PhysRegIdPtr  reg_idx)

Read physical vector register for modification.

Definition at line 1111 of file cpu.cc.

References cpuStats, gem5::o3::PhysRegFile::getWritableVecReg(), regFile, and gem5::o3::CPU::CPUStats::vecRegfileWrites.

Referenced by gem5::o3::DynInst::getWritableVecRegOperand().

◆ halt()

void gem5::o3::CPU::halt ( )
inline

Halts the CPU.

Definition at line 294 of file cpu.hh.

References panic.

◆ haltContext()

void gem5::o3::CPU::haltContext ( ThreadID  tid)
override

Remove Thread from Active Threads List && Remove Thread Context from CPU.

Definition at line 698 of file cpu.cc.

References _status, activeThreads, deactivateThread(), DPRINTF, Idle, lastRunningCycle, removeThread(), gem5::Event::scheduled(), tickEvent, and unscheduleTickEvent().

Referenced by exitThreads().

◆ htmSendAbortSignal()

void gem5::o3::CPU::htmSendAbortSignal ( ThreadID  tid,
uint64_t  htm_uid,
HtmFailureFaultCause  cause 
)
override

◆ init()

void gem5::o3::CPU::init ( )
override

Initialize the CPU.

Definition at line 546 of file cpu.cc.

References commit, gem5::statistics::init, gem5::o3::Commit::setThreads(), and thread.

◆ insertThread()

void gem5::o3::CPU::insertThread ( ThreadID  tid)

◆ instDone()

void gem5::o3::CPU::instDone ( ThreadID  tid,
const DynInstPtr inst 
)

Function to tell the CPU that an instruction has completed.

Definition at line 1338 of file cpu.cc.

References gem5::o3::CPU::CPUStats::committedInsts, gem5::o3::CPU::CPUStats::committedOps, cpuStats, and thread.

Referenced by gem5::o3::Commit::updateComInstStats().

◆ isCpuDrained()

bool gem5::o3::CPU::isCpuDrained ( ) const
private

◆ isDraining()

bool gem5::o3::CPU::isDraining ( ) const
inline

Is the CPU draining?

Definition at line 236 of file cpu.hh.

References gem5::Draining.

Referenced by gem5::o3::Fetch::checkStall(), gem5::o3::Fetch::drainStall(), and gem5::o3::ThreadContext::suspend().

◆ isThreadExiting()

bool gem5::o3::CPU::isThreadExiting ( ThreadID  tid) const

Is the thread trying to exit?

Definition at line 1594 of file cpu.cc.

References exitingThreads.

Referenced by gem5::o3::Commit::commit(), and gem5::o3::ROB::doSquash().

◆ numActiveThreads()

int gem5::o3::CPU::numActiveThreads ( )
inline

Returns the Number of Active Threads in the CPU.

Definition at line 198 of file cpu.hh.

References activeThreads.

◆ pcState() [1/2]

void gem5::o3::CPU::pcState ( const PCStateBase new_pc_state,
ThreadID  tid 
)

◆ pcState() [2/2]

const PCStateBase & gem5::o3::CPU::pcState ( ThreadID  tid)

Reads the commit PC state of a specific thread.

Definition at line 1311 of file cpu.cc.

References commit, and gem5::o3::Commit::pcState().

◆ processInterrupts()

void gem5::o3::CPU::processInterrupts ( const Fault interrupt)

Processes any an interrupt fault.

Definition at line 828 of file cpu.cc.

References DPRINTF, gem5::NoFault, and trap().

Referenced by gem5::o3::Commit::handleInterrupt().

◆ pushRequest()

Fault gem5::o3::CPU::pushRequest ( const DynInstPtr inst,
bool  isLoad,
uint8_t *  data,
unsigned int  size,
Addr  addr,
Request::Flags  flags,
uint64_t *  res,
AtomicOpFunctorPtr  amo_op = nullptr,
const std::vector< bool > &  byte_enable = std::vector<bool>() 
)
inline

◆ readArchCCReg()

RegVal gem5::o3::CPU::readArchCCReg ( int  reg_idx,
ThreadID  tid 
)

◆ readArchFloatReg()

RegVal gem5::o3::CPU::readArchFloatReg ( int  reg_idx,
ThreadID  tid 
)

◆ readArchIntReg()

RegVal gem5::o3::CPU::readArchIntReg ( int  reg_idx,
ThreadID  tid 
)

◆ readArchVecElem()

RegVal gem5::o3::CPU::readArchVecElem ( const RegIndex reg_idx,
const ElemIndex ldx,
ThreadID  tid 
) const

◆ readArchVecPredReg()

const TheISA::VecPredRegContainer & gem5::o3::CPU::readArchVecPredReg ( int  reg_idx,
ThreadID  tid 
) const

◆ readArchVecReg()

const TheISA::VecRegContainer & gem5::o3::CPU::readArchVecReg ( int  reg_idx,
ThreadID  tid 
) const

◆ readCCReg()

RegVal gem5::o3::CPU::readCCReg ( PhysRegIdPtr  phys_reg)

◆ readFloatReg()

RegVal gem5::o3::CPU::readFloatReg ( PhysRegIdPtr  phys_reg)

◆ readIntReg()

RegVal gem5::o3::CPU::readIntReg ( PhysRegIdPtr  phys_reg)

◆ readMiscReg()

RegVal gem5::o3::CPU::readMiscReg ( int  misc_reg,
ThreadID  tid 
)

Reads a misc.

register, including any side effects the read might have as defined by the architecture.

Definition at line 1070 of file cpu.cc.

References cpuStats, isa, and gem5::o3::CPU::CPUStats::miscRegfileReads.

Referenced by gem5::o3::ThreadContext::readMiscReg(), gem5::o3::DynInst::readMiscReg(), and gem5::o3::DynInst::readMiscRegOperand().

◆ readMiscRegNoEffect()

RegVal gem5::o3::CPU::readMiscRegNoEffect ( int  misc_reg,
ThreadID  tid 
) const

Register accessors.

Index refers to the physical register index. Reads a miscellaneous register.

Definition at line 1064 of file cpu.cc.

References isa.

Referenced by gem5::o3::ThreadContext::readMiscRegNoEffect().

◆ readVecElem()

RegVal gem5::o3::CPU::readVecElem ( PhysRegIdPtr  reg_idx) const

◆ readVecPredReg()

const TheISA::VecPredRegContainer & gem5::o3::CPU::readVecPredReg ( PhysRegIdPtr  reg_idx) const

◆ readVecReg()

const TheISA::VecRegContainer & gem5::o3::CPU::readVecReg ( PhysRegIdPtr  reg_idx) const

◆ regProbePoints()

void gem5::o3::CPU::regProbePoints ( )
override

◆ removeFrontInst()

void gem5::o3::CPU::removeFrontInst ( const DynInstPtr inst)

Remove an instruction from the front end of the list.

There's no restriction on location of the instruction.

Definition at line 1357 of file cpu.cc.

References DPRINTF, removeInstsThisCycle, and removeList.

Referenced by gem5::o3::ROB::retireHead().

◆ removeInstsNotInROB()

void gem5::o3::CPU::removeInstsNotInROB ( ThreadID  tid)

Remove all instructions that are not currently in the ROB.

There's also an option to not squash delay slot instructions.

Definition at line 1370 of file cpu.cc.

References DPRINTF, instList, gem5::o3::ROB::isEmpty(), gem5::o3::ROB::readTailInst(), removeInstsThisCycle, rob, and squashInstIt().

Referenced by gem5::o3::Fetch::squash().

◆ removeInstsUntil()

void gem5::o3::CPU::removeInstsUntil ( const InstSeqNum seq_num,
ThreadID  tid 
)

Remove all instructions younger than the given sequence number.

Definition at line 1414 of file cpu.cc.

References DPRINTF, instList, removeInstsThisCycle, and squashInstIt().

Referenced by gem5::o3::Decode::squash(), and gem5::o3::Fetch::squashFromDecode().

◆ removeThread()

void gem5::o3::CPU::removeThread ( ThreadID  tid)

◆ scheduleThreadExitEvent()

void gem5::o3::CPU::scheduleThreadExitEvent ( ThreadID  tid)

If a thread is trying to exit and its corresponding trap event has been completed, schedule an event to terminate the thread.

Definition at line 1600 of file cpu.cc.

References exitingThreads, gem5::Event::scheduled(), and threadExitEvent.

Referenced by gem5::o3::Commit::commit().

◆ scheduleTickEvent()

void gem5::o3::CPU::scheduleTickEvent ( Cycles  delay)
inlineprivate

Schedule tick event, regardless of its current state.

Definition at line 127 of file cpu.hh.

References gem5::Event::scheduled(), gem5::Event::squashed(), and tickEvent.

Referenced by activateContext().

◆ serializeThread()

void gem5::o3::CPU::serializeThread ( CheckpointOut cp,
ThreadID  tid 
) const
override

Definition at line 851 of file cpu.cc.

References thread.

◆ setArchCCReg()

void gem5::o3::CPU::setArchCCReg ( int  reg_idx,
RegVal  val,
ThreadID  tid 
)

◆ setArchFloatReg()

void gem5::o3::CPU::setArchFloatReg ( int  reg_idx,
RegVal  val,
ThreadID  tid 
)

◆ setArchIntReg()

void gem5::o3::CPU::setArchIntReg ( int  reg_idx,
RegVal  val,
ThreadID  tid 
)

Architectural register accessors.

Looks up in the commit rename table to obtain the true physical index of the architected register first, then accesses that physical register.

Definition at line 1257 of file cpu.cc.

References commitRenameMap, gem5::IntRegClass, gem5::o3::UnifiedRenameMap::lookup(), regFile, gem5::o3::PhysRegFile::setIntReg(), and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setIntRegFlat().

◆ setArchVecElem()

void gem5::o3::CPU::setArchVecElem ( const RegIndex reg_idx,
const ElemIndex ldx,
RegVal  val,
ThreadID  tid 
)

◆ setArchVecPredReg()

void gem5::o3::CPU::setArchVecPredReg ( int  reg_idx,
const TheISA::VecPredRegContainer &  val,
ThreadID  tid 
)

◆ setArchVecReg()

void gem5::o3::CPU::setArchVecReg ( int  reg_idx,
const TheISA::VecRegContainer &  val,
ThreadID  tid 
)

◆ setCCReg()

void gem5::o3::CPU::setCCReg ( PhysRegIdPtr  phys_reg,
RegVal  val 
)

◆ setFloatReg()

void gem5::o3::CPU::setFloatReg ( PhysRegIdPtr  phys_reg,
RegVal  val 
)

◆ setIntReg()

void gem5::o3::CPU::setIntReg ( PhysRegIdPtr  phys_reg,
RegVal  val 
)

◆ setMiscReg()

void gem5::o3::CPU::setMiscReg ( int  misc_reg,
RegVal  val,
ThreadID  tid 
)

Sets a misc.

register, including any side effects the write might have as defined by the architecture.

Definition at line 1083 of file cpu.cc.

References cpuStats, isa, gem5::o3::CPU::CPUStats::miscRegfileWrites, and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setMiscReg(), and gem5::o3::DynInst::updateMiscRegs().

◆ setMiscRegNoEffect()

void gem5::o3::CPU::setMiscRegNoEffect ( int  misc_reg,
RegVal  val,
ThreadID  tid 
)

Sets a miscellaneous register.

Definition at line 1077 of file cpu.cc.

References isa, and gem5::X86ISA::val.

Referenced by gem5::o3::ThreadContext::setMiscRegNoEffect().

◆ setVecElem()

void gem5::o3::CPU::setVecElem ( PhysRegIdPtr  reg_idx,
RegVal  val 
)

◆ setVecPredReg()

void gem5::o3::CPU::setVecPredReg ( PhysRegIdPtr  reg_idx,
const TheISA::VecPredRegContainer &  val 
)

◆ setVecReg()

void gem5::o3::CPU::setVecReg ( PhysRegIdPtr  reg_idx,
const TheISA::VecRegContainer &  val 
)

◆ squashFromTC()

void gem5::o3::CPU::squashFromTC ( ThreadID  tid)

Initiates a squash of all in-flight instructions for a given thread.

The source of the squash is an external update of state through the TC.

Definition at line 1323 of file cpu.cc.

References commit, gem5::o3::Commit::generateTCEvent(), and thread.

Referenced by gem5::o3::ThreadContext::conditionalSquash().

◆ squashInstIt()

void gem5::o3::CPU::squashInstIt ( const ListIt instIt,
ThreadID  tid 
)

Removes the instruction pointed to by the iterator.

Definition at line 1442 of file cpu.cc.

References DPRINTF, and removeList.

Referenced by removeInstsNotInROB(), and removeInstsUntil().

◆ startup()

void gem5::o3::CPU::startup ( )
override

◆ suspendContext()

void gem5::o3::CPU::suspendContext ( ThreadID  tid)
override

Remove Thread from Active Threads List.

Definition at line 678 of file cpu.cc.

References _status, activeThreads, deactivateThread(), DPRINTF, Idle, lastRunningCycle, and unscheduleTickEvent().

Referenced by gem5::o3::ThreadContext::suspend().

◆ switchOut()

void gem5::o3::CPU::switchOut ( )
override

Switches out this CPU.

Definition at line 1020 of file cpu.cc.

References _status, activityRec, checker, DPRINTF, gem5::ActivityRecorder::reset(), and SwitchedOut.

◆ takeOverFrom()

void gem5::o3::CPU::takeOverFrom ( BaseCPU *  oldCPU)
override

◆ tcBase()

gem5::ThreadContext* gem5::o3::CPU::tcBase ( ThreadID  tid)
inline

◆ tick()

void gem5::o3::CPU::tick ( )

◆ totalInsts()

Counter gem5::o3::CPU::totalInsts ( ) const
override

Count the Total Instructions Committed in the CPU.

Definition at line 616 of file cpu.cc.

References gem5::ArmISA::i, thread, and gem5::statistics::total.

◆ totalOps()

Counter gem5::o3::CPU::totalOps ( ) const
override

Count the Total Ops (including micro ops) committed in the CPU.

Definition at line 628 of file cpu.cc.

References gem5::ArmISA::i, thread, and gem5::statistics::total.

◆ trap()

void gem5::o3::CPU::trap ( const Fault fault,
ThreadID  tid,
const StaticInstPtr inst 
)

Traps to handle given fault.

Definition at line 844 of file cpu.cc.

Referenced by gem5::o3::Commit::commitHead(), processInterrupts(), and gem5::o3::DynInst::trap().

◆ tryDrain()

bool gem5::o3::CPU::tryDrain ( )
private

Check if the pipeline has drained and signal drain done.

This method checks if a drain has been requested and if the CPU has drained successfully (i.e., there are no instructions in the pipeline). If the CPU has drained, it deschedules the tick event and signals the drain manager.

Returns
False if a drain hasn't been requested or the CPU hasn't drained, true otherwise.

Definition at line 925 of file cpu.cc.

References DPRINTF, gem5::Draining, isCpuDrained(), gem5::Event::scheduled(), and tickEvent.

Referenced by tick().

◆ unscheduleTickEvent()

void gem5::o3::CPU::unscheduleTickEvent ( )
inlineprivate

Unschedule tick event, regardless of its current state.

Definition at line 137 of file cpu.hh.

References gem5::Event::scheduled(), gem5::Event::squash(), and tickEvent.

Referenced by haltContext(), and suspendContext().

◆ unserializeThread()

void gem5::o3::CPU::unserializeThread ( CheckpointIn cp,
ThreadID  tid 
)
override

Definition at line 857 of file cpu.cc.

References thread.

◆ updateThreadPriority()

void gem5::o3::CPU::updateThreadPriority ( )

Update The Order In Which We Process Threads.

Definition at line 1559 of file cpu.cc.

References activeThreads.

Referenced by tick().

◆ verifyMemoryMode()

void gem5::o3::CPU::verifyMemoryMode ( ) const
override

Definition at line 1055 of file cpu.cc.

References fatal, gem5::System::isTimingMode(), and system.

Referenced by drainResume().

◆ wakeCPU()

void gem5::o3::CPU::wakeCPU ( )

◆ wakeup()

void gem5::o3::CPU::wakeup ( ThreadID  tid)
overridevirtual

Friends And Related Function Documentation

◆ ThreadContext

friend class ThreadContext
friend

Definition at line 99 of file cpu.hh.

Member Data Documentation

◆ _status

Status gem5::o3::CPU::_status

Overall CPU status.

Definition at line 115 of file cpu.hh.

Referenced by activateContext(), drainResume(), haltContext(), suspendContext(), switchOut(), takeOverFrom(), and tick().

◆ activeThreads

std::list<ThreadID> gem5::o3::CPU::activeThreads
protected

Active Threads List.

Definition at line 486 of file cpu.hh.

Referenced by activateThread(), deactivateThread(), haltContext(), numActiveThreads(), suspendContext(), and updateThreadPriority().

◆ activityRec

ActivityRecorder gem5::o3::CPU::activityRec
private

The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and deschedule itself.

Definition at line 535 of file cpu.hh.

Referenced by activateContext(), activateStage(), activityThisCycle(), deactivateStage(), drain(), switchOut(), tick(), and wakeCPU().

◆ checker

gem5::Checker<DynInstPtr>* gem5::o3::CPU::checker

Pointer to the checker, which can dynamically verify instruction results at run time.

This can be set to NULL if it is not being used.

Definition at line 578 of file cpu.hh.

Referenced by gem5::o3::Commit::commitHead(), gem5::o3::Commit::commitInsts(), gem5::o3::DynInst::completeAcc(), gem5::o3::LSQUnit::completeStore(), gem5::o3::Commit::handleInterrupt(), gem5::o3::LSQ::pushRequest(), gem5::o3::IEW::startupStage(), gem5::o3::LSQUnit::storePostSend(), and switchOut().

◆ commit

Commit gem5::o3::CPU::commit
protected

◆ commitRenameMap

UnifiedRenameMap gem5::o3::CPU::commitRenameMap[MaxThreads]
protected

◆ cpuStats

gem5::o3::CPU::CPUStats gem5::o3::CPU::cpuStats

◆ cpuWaitList

std::list<int> gem5::o3::CPU::cpuWaitList

Threads Scheduled to Enter CPU.

Definition at line 587 of file cpu.hh.

◆ decode

Decode gem5::o3::CPU::decode
protected

The decode stage.

Definition at line 459 of file cpu.hh.

Referenced by drainSanityCheck(), isCpuDrained(), removeThread(), startup(), takeOverFrom(), and tick().

◆ decodeQueue

TimeBuffer<DecodeStruct> gem5::o3::CPU::decodeQueue

The decode stage's instruction queue.

Definition at line 522 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ exitingThreads

std::unordered_map<ThreadID, bool> gem5::o3::CPU::exitingThreads
protected

This is a list of threads that are trying to exit.

Each thread id is mapped to a boolean value denoting whether the thread is ready to exit.

Definition at line 493 of file cpu.hh.

Referenced by addThreadToExitingList(), exitThreads(), isThreadExiting(), and scheduleThreadExitEvent().

◆ fetch

Fetch gem5::o3::CPU::fetch
protected

◆ fetchQueue

TimeBuffer<FetchStruct> gem5::o3::CPU::fetchQueue

The fetch stage's instruction queue.

Definition at line 519 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ freeList

UnifiedFreeList gem5::o3::CPU::freeList
protected

The free list.

Definition at line 474 of file cpu.hh.

Referenced by insertThread().

◆ globalSeqNum

InstSeqNum gem5::o3::CPU::globalSeqNum

The global sequence number counter.

Definition at line 572 of file cpu.hh.

Referenced by getAndIncrementInstSeq(), and takeOverFrom().

◆ iew

IEW gem5::o3::CPU::iew
protected

The issue/execute/writeback stages.

Definition at line 465 of file cpu.hh.

Referenced by drainSanityCheck(), getDataPort(), htmSendAbortSignal(), isCpuDrained(), pushRequest(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ iewQueue

TimeBuffer<IEWStruct> gem5::o3::CPU::iewQueue

The IEW stage's instruction queue.

Definition at line 528 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ instcount

int gem5::o3::CPU::instcount

Count of total number of dynamic instructions in flight.

Definition at line 431 of file cpu.hh.

Referenced by gem5::o3::DynInst::DynInst(), and gem5::o3::DynInst::~DynInst().

◆ instList

std::list<DynInstPtr> gem5::o3::CPU::instList

List of all the instructions in flight.

Definition at line 435 of file cpu.hh.

Referenced by addInst(), cleanUpRemovedInsts(), dumpInsts(), gem5::o3::Commit::handleInterrupt(), isCpuDrained(), removeInstsNotInROB(), and removeInstsUntil().

◆ isa

std::vector<TheISA::ISA *> gem5::o3::CPU::isa
protected

◆ lastActivatedCycle

Tick gem5::o3::CPU::lastActivatedCycle

The cycle that the CPU was last activated by a new thread.

Definition at line 593 of file cpu.hh.

Referenced by activateContext().

◆ lastRunningCycle

Cycles gem5::o3::CPU::lastRunningCycle

The cycle that the CPU was last running, used for statistics.

Definition at line 590 of file cpu.hh.

Referenced by activateContext(), haltContext(), suspendContext(), takeOverFrom(), tick(), and wakeCPU().

◆ mmu

BaseMMU* gem5::o3::CPU::mmu

◆ ppDataAccessComplete

ProbePointArg<std::pair<DynInstPtr, PacketPtr> >* gem5::o3::CPU::ppDataAccessComplete

Definition at line 175 of file cpu.hh.

Referenced by gem5::o3::LSQUnit::completeDataAccess(), and regProbePoints().

◆ ppInstAccessComplete

ProbePointArg<PacketPtr>* gem5::o3::CPU::ppInstAccessComplete

Definition at line 174 of file cpu.hh.

Referenced by gem5::o3::Fetch::processCacheCompletion(), and regProbePoints().

◆ regFile

PhysRegFile gem5::o3::CPU::regFile
protected

◆ removeInstsThisCycle

bool gem5::o3::CPU::removeInstsThisCycle

Records if instructions need to be removed this cycle due to being retired or squashed.

Definition at line 452 of file cpu.hh.

Referenced by cleanUpRemovedInsts(), removeFrontInst(), removeInstsNotInROB(), removeInstsUntil(), and tick().

◆ removeList

std::queue<ListIt> gem5::o3::CPU::removeList

List of all the instructions that will be removed at the end of this cycle.

Definition at line 440 of file cpu.hh.

Referenced by cleanUpRemovedInsts(), isCpuDrained(), removeFrontInst(), and squashInstIt().

◆ rename

Rename gem5::o3::CPU::rename
protected

The dispatch stage.

Definition at line 462 of file cpu.hh.

Referenced by drainSanityCheck(), isCpuDrained(), regProbePoints(), removeThread(), startup(), takeOverFrom(), and tick().

◆ renameMap

UnifiedRenameMap gem5::o3::CPU::renameMap[MaxThreads]
protected

The rename map.

Definition at line 477 of file cpu.hh.

Referenced by insertThread().

◆ renameQueue

TimeBuffer<RenameStruct> gem5::o3::CPU::renameQueue

The rename stage's instruction queue.

Definition at line 525 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().

◆ rob

ROB gem5::o3::CPU::rob
protected

The re-order buffer.

Definition at line 483 of file cpu.hh.

Referenced by removeInstsNotInROB().

◆ scoreboard

Scoreboard gem5::o3::CPU::scoreboard
protected

Integer Register Scoreboard.

Definition at line 496 of file cpu.hh.

Referenced by insertThread().

◆ system

System* gem5::o3::CPU::system

Pointer to the system.

Definition at line 581 of file cpu.hh.

Referenced by gem5::o3::Fetch::finishTranslation(), gem5::o3::ThreadContext::getSystemPtr(), insertThread(), and verifyMemoryMode().

◆ thread

std::vector<ThreadState *> gem5::o3::CPU::thread

◆ threadExitEvent

EventFunctionWrapper gem5::o3::CPU::threadExitEvent
private

The exit event used for terminating all ready-to-exit threads.

Definition at line 123 of file cpu.hh.

Referenced by scheduleThreadExitEvent().

◆ threadMap

std::map<ThreadID, unsigned> gem5::o3::CPU::threadMap

Mapping for system thread id to cpu id.

Definition at line 596 of file cpu.hh.

◆ tickEvent

EventFunctionWrapper gem5::o3::CPU::tickEvent
private

The tick event used for scheduling CPU ticks.

Definition at line 120 of file cpu.hh.

Referenced by drain(), drainResume(), haltContext(), scheduleTickEvent(), takeOverFrom(), tick(), tryDrain(), unscheduleTickEvent(), and wakeCPU().

◆ tids

std::vector<ThreadID> gem5::o3::CPU::tids

Available thread ids in the cpu.

Definition at line 599 of file cpu.hh.

Referenced by getFreeTid().

◆ timeBuffer

TimeBuffer<TimeStruct> gem5::o3::CPU::timeBuffer

The main time buffer to do backwards communication.

Definition at line 516 of file cpu.hh.

Referenced by drain(), removeThread(), and tick().


The documentation for this class was generated from the following files:

Generated on Wed May 4 2022 12:15:46 for gem5 by doxygen 1.8.17