gem5  v21.1.0.2
cpu.hh
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42 
43 #ifndef __CPU_O3_CPU_HH__
44 #define __CPU_O3_CPU_HH__
45 
46 #include <iostream>
47 #include <list>
48 #include <queue>
49 #include <set>
50 #include <vector>
51 
52 #include "arch/generic/types.hh"
53 #include "arch/pcstate.hh"
54 #include "base/statistics.hh"
55 #include "config/the_isa.hh"
56 #include "cpu/o3/comm.hh"
57 #include "cpu/o3/commit.hh"
58 #include "cpu/o3/decode.hh"
59 #include "cpu/o3/dyn_inst_ptr.hh"
60 #include "cpu/o3/fetch.hh"
61 #include "cpu/o3/free_list.hh"
62 #include "cpu/o3/iew.hh"
63 #include "cpu/o3/limits.hh"
64 #include "cpu/o3/rename.hh"
65 #include "cpu/o3/rob.hh"
66 #include "cpu/o3/scoreboard.hh"
67 #include "cpu/o3/thread_state.hh"
68 #include "cpu/activity.hh"
69 #include "cpu/base.hh"
70 #include "cpu/simple_thread.hh"
71 #include "cpu/timebuf.hh"
72 #include "params/O3CPU.hh"
73 #include "sim/process.hh"
74 
75 namespace gem5
76 {
77 
78 template <class>
79 class Checker;
80 class ThreadContext;
81 
82 class Checkpoint;
83 class Process;
84 
85 namespace o3
86 {
87 
88 class ThreadContext;
89 
95 class CPU : public BaseCPU
96 {
97  public:
99 
100  friend class ThreadContext;
101 
102  public:
103  enum Status
104  {
110  };
111 
114 
117 
118  private:
119 
122 
125 
128  {
129  if (tickEvent.squashed())
130  reschedule(tickEvent, clockEdge(delay));
131  else if (!tickEvent.scheduled())
132  schedule(tickEvent, clockEdge(delay));
133  }
134 
137  {
138  if (tickEvent.scheduled())
139  tickEvent.squash();
140  }
141 
153  bool tryDrain();
154 
164  void drainSanityCheck() const;
165 
167  bool isCpuDrained() const;
168 
169  public:
171  CPU(const O3CPUParams &params);
172 
175 
177  void regProbePoints() override;
178 
179  void
180  demapPage(Addr vaddr, uint64_t asn)
181  {
182  mmu->demapPage(vaddr, asn);
183  }
184 
188  void tick();
189 
191  void init() override;
192 
193  void startup() override;
194 
197  { return activeThreads.size(); }
198 
200  void activateThread(ThreadID tid);
201 
203  void deactivateThread(ThreadID tid);
204 
206  void insertThread(ThreadID tid);
207 
209  void removeThread(ThreadID tid);
210 
212  Counter totalInsts() const override;
213 
215  Counter totalOps() const override;
216 
218  void activateContext(ThreadID tid) override;
219 
221  void suspendContext(ThreadID tid) override;
222 
226  void haltContext(ThreadID tid) override;
227 
229  void updateThreadPriority();
230 
232  bool isDraining() const { return drainState() == DrainState::Draining; }
233 
234  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
235  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
236 
239 
241  bool isThreadExiting(ThreadID tid) const;
242 
248 
250  void exitThreads();
251 
252  public:
255  DrainState drain() override;
256 
258  void drainResume() override;
259 
267  void commitDrained(ThreadID tid);
268 
270  void switchOut() override;
271 
273  void takeOverFrom(BaseCPU *oldCPU) override;
274 
275  void verifyMemoryMode() const override;
276 
279  { return globalSeqNum++; }
280 
282  void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
283 
288  void setVectorsAsReady(ThreadID tid);
289 
296  void switchRenameMode(ThreadID tid, UnifiedFreeList* freelist);
297 
300 
302  void processInterrupts(const Fault &interrupt);
303 
305  void halt() { panic("Halt not implemented!\n"); }
306 
310  RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
311 
315  RegVal readMiscReg(int misc_reg, ThreadID tid);
316 
318  void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
319 
323  void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
324 
325  RegVal readIntReg(PhysRegIdPtr phys_reg);
326 
327  RegVal readFloatReg(PhysRegIdPtr phys_reg);
328 
329  const TheISA::VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
330 
335 
337  enums::VecRegRenameMode vecRenameMode() const { return vecMode; }
338 
340  void vecRenameMode(enums::VecRegRenameMode vec_mode)
341  { vecMode = vec_mode; }
342 
343  const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
344 
346  readVecPredReg(PhysRegIdPtr reg_idx) const;
347 
349 
350  RegVal readCCReg(PhysRegIdPtr phys_reg);
351 
352  void setIntReg(PhysRegIdPtr phys_reg, RegVal val);
353 
354  void setFloatReg(PhysRegIdPtr phys_reg, RegVal val);
355 
356  void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer& val);
357 
358  void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem& val);
359 
360  void setVecPredReg(PhysRegIdPtr reg_idx,
362 
363  void setCCReg(PhysRegIdPtr phys_reg, RegVal val);
364 
365  RegVal readArchIntReg(int reg_idx, ThreadID tid);
366 
367  RegVal readArchFloatReg(int reg_idx, ThreadID tid);
368 
370  readArchVecReg(int reg_idx, ThreadID tid) const;
373 
374  const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
375  const ElemIndex& ldx, ThreadID tid) const;
376 
378  int reg_idx, ThreadID tid) const;
379 
381  getWritableArchVecPredReg(int reg_idx, ThreadID tid);
382 
383  RegVal readArchCCReg(int reg_idx, ThreadID tid);
384 
390  void setArchIntReg(int reg_idx, RegVal val, ThreadID tid);
391 
392  void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid);
393 
394  void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer& val,
395  ThreadID tid);
396 
397  void setArchVecReg(int reg_idx, const TheISA::VecRegContainer& val,
398  ThreadID tid);
399 
400  void setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx,
401  const TheISA::VecElem& val, ThreadID tid);
402 
403  void setArchCCReg(int reg_idx, RegVal val, ThreadID tid);
404 
406  void pcState(const TheISA::PCState &newPCState, ThreadID tid);
407 
410 
412  Addr instAddr(ThreadID tid);
413 
415  MicroPC microPC(ThreadID tid);
416 
419 
424  void squashFromTC(ThreadID tid);
425 
429  ListIt addInst(const DynInstPtr &inst);
430 
432  void instDone(ThreadID tid, const DynInstPtr &inst);
433 
437  void removeFrontInst(const DynInstPtr &inst);
438 
441  void removeInstsNotInROB(ThreadID tid);
442 
444  void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
445 
447  void squashInstIt(const ListIt &instIt, ThreadID tid);
448 
450  void cleanUpRemovedInsts();
451 
453  void dumpInsts();
454 
455  public:
456 #ifndef NDEBUG
457 
459 #endif
460 
463 
467  std::queue<ListIt> removeList;
468 
469 #ifdef DEBUG
470 
473  std::set<InstSeqNum> snList;
474 #endif
475 
480 
481  protected:
484 
487 
490 
493 
496 
498  enums::VecRegRenameMode vecMode;
499 
502 
505 
508 
511 
514 
517 
523  std::unordered_map<ThreadID, bool> exitingThreads;
524 
527 
529 
530  public:
535  enum StageIdx
536  {
543  };
544 
547 
550 
553 
556 
559 
560  private:
566 
567  public:
570 
572  void activateStage(const StageIdx idx)
573  { activityRec.activateStage(idx); }
574 
576  void deactivateStage(const StageIdx idx)
577  { activityRec.deactivateStage(idx); }
578 
580  void wakeCPU();
581 
582  virtual void wakeup(ThreadID tid) override;
583 
586 
587  public:
591  {
592  return thread[tid]->getTC();
593  }
594 
596  InstSeqNum globalSeqNum;//[MaxThreads];
597 
603 
606 
609 
612 
615 
618 
620  std::map<ThreadID, unsigned> threadMap;
621 
624 
626  Fault pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
627  unsigned int size, Addr addr, Request::Flags flags,
628  uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
629  const std::vector<bool>& byte_enable =
631 
632  {
633  return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
634  flags, res, std::move(amo_op), byte_enable);
635  }
636 
638  Fault read(LSQRequest* req, int load_idx)
639  {
640  return iew.ldstQueue.read(req, load_idx);
641  }
642 
644  Fault write(LSQRequest* req, uint8_t *data, int store_idx)
645  {
646  return iew.ldstQueue.write(req, data, store_idx);
647  }
648 
650  Port &
651  getInstPort() override
652  {
653  return fetch.getInstPort();
654  }
655 
657  Port &
658  getDataPort() override
659  {
660  return iew.ldstQueue.getDataPort();
661  }
662 
663  struct CPUStats : public statistics::Group
664  {
665  CPUStats(CPU *cpu);
666 
687 
688  //number of integer register file accesses
691  //number of float register file accesses
694  //number of vector register file accesses
697  //number of predicate register file accesses
700  //number of CC register file accesses
703  //number of misc
706  } cpuStats;
707 
708  public:
709  // hardware transactional memory
710  void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
711  HtmFailureFaultCause cause);
712 };
713 
714 } // namespace o3
715 } // namespace gem5
716 
717 #endif // __CPU_O3_CPU_HH__
gem5::o3::CPU::vecMode
enums::VecRegRenameMode vecMode
The rename mode of the vector registers.
Definition: cpu.hh:498
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1927
gem5::o3::CPU::setArchIntReg
void setArchIntReg(int reg_idx, RegVal val, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1318
gem5::o3::CPU::DecodeIdx
@ DecodeIdx
Definition: cpu.hh:538
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1656
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1568
gem5::o3::CPU::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
CPU pushRequest function, forwards request to LSQ.
Definition: cpu.hh:626
gem5::o3::CPU::ppDataAccessComplete
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
Definition: cpu.hh:174
gem5::o3::CPU::readVecElem
const TheISA::VecElem & readVecElem(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1176
gem5::o3::CPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: cpu.cc:1009
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:231
gem5::o3::CPU::tids
std::vector< ThreadID > tids
Available thread ids in the cpu.
Definition: cpu.hh:623
gem5::o3::CPU::setArchVecElem
void setArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, const TheISA::VecElem &val, ThreadID tid)
Definition: cpu.cc:1347
gem5::o3::CPU::CPUStats::miscRegfileWrites
statistics::Scalar miscRegfileWrites
Definition: cpu.hh:705
gem5::o3::CPU::threadMap
std::map< ThreadID, unsigned > threadMap
Mapping for system thread id to cpu id.
Definition: cpu.hh:620
gem5::o3::CPU::removeList
std::queue< ListIt > removeList
List of all the instructions that will be removed at the end of this cycle.
Definition: cpu.hh:467
gem5::o3::CPU::setVecElem
void setVecElem(PhysRegIdPtr reg_idx, const TheISA::VecElem &val)
Definition: cpu.cc:1225
gem5::o3::CPU::CPUStats::fpRegfileWrites
statistics::Scalar fpRegfileWrites
Definition: cpu.hh:693
commit.hh
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::readCCReg
RegVal readCCReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1197
gem5::o3::CPU::removeInstsThisCycle
bool removeInstsThisCycle
Records if instructions need to be removed this cycle due to being retired or squashed.
Definition: cpu.hh:479
gem5::o3::CPU::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: cpu.hh:98
gem5::o3::CPU::cpuStats
gem5::o3::CPU::CPUStats cpuStats
gem5::o3::CPU::globalSeqNum
InstSeqNum globalSeqNum
The global sequence number counter.
Definition: cpu.hh:596
gem5::o3::CPU::removeInstsUntil
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
Definition: cpu.cc:1496
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:112
gem5::ArmISA::VecPredRegContainer
VecPredReg::Container VecPredRegContainer
Definition: vec.hh:68
gem5::o3::CPU::CPU
CPU(const O3CPUParams &params)
Constructs a CPU with the given parameters.
Definition: cpu.cc:73
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::CPU::regFile
PhysRegFile regFile
The register file.
Definition: cpu.hh:501
gem5::Drainable::drainState
DrainState drainState() const
Return the current drain state of an object.
Definition: drain.hh:324
gem5::o3::Fetch::getInstPort
RequestPort & getInstPort()
Definition: fetch.hh:361
rename.hh
gem5::o3::CPU::decode
Decode decode
The decode stage.
Definition: cpu.hh:486
gem5::o3::CPU::CPUStats::ccRegfileWrites
statistics::Scalar ccRegfileWrites
Definition: cpu.hh:702
gem5::o3::LSQ::read
Fault read(LSQRequest *req, int load_idx)
Executes a read operation, using the load specified at the load index.
Definition: lsq.cc:1424
gem5::o3::CPU::activeThreads
std::list< ThreadID > activeThreads
Active Threads List.
Definition: cpu.hh:516
gem5::o3::CPU::freeList
UnifiedFreeList freeList
The free list.
Definition: cpu.hh:504
gem5::o3::CPU::processInterrupts
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
Definition: cpu.cc:886
gem5::o3::CPU::RenameIdx
@ RenameIdx
Definition: cpu.hh:539
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::o3::CPU::readArchFloatReg
RegVal readArchFloatReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1257
gem5::o3::CPU::CPUStats::quiesceCycles
statistics::Scalar quiesceCycles
Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for ...
Definition: cpu.hh:673
gem5::o3::CPU::getInterrupts
Fault getInterrupts()
Returns the Fault for any valid interrupt.
Definition: cpu.cc:879
gem5::o3::CPU::squashInstIt
void squashInstIt(const ListIt &instIt, ThreadID tid)
Removes the instruction pointed to by the iterator.
Definition: cpu.cc:1524
gem5::o3::CPU::readArchCCReg
RegVal readArchCCReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1308
gem5::o3::CPU::CPUStats::miscRegfileReads
statistics::Scalar miscRegfileReads
Definition: cpu.hh:704
gem5::o3::CPU::CPUStats::intRegfileReads
statistics::Scalar intRegfileReads
Definition: cpu.hh:689
gem5::o3::CPU::_status
Status _status
Overall CPU status.
Definition: cpu.hh:116
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:775
gem5::o3::CPU::timeBuffer
TimeBuffer< TimeStruct > timeBuffer
The main time buffer to do backwards communication.
Definition: cpu.hh:546
gem5::o3::CPU::getAndIncrementInstSeq
InstSeqNum getAndIncrementInstSeq()
Get the current instruction sequence number, and increment it.
Definition: cpu.hh:278
gem5::o3::CPU::cpuWaitList
std::list< int > cpuWaitList
Threads Scheduled to Enter CPU.
Definition: cpu.hh:611
gem5::o3::CPU::removeThread
void removeThread(ThreadID tid)
Remove all of a thread's context from CPU.
Definition: cpu.cc:785
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:122
gem5::o3::Scoreboard
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:53
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause)
Definition: cpu.cc:1724
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2003
gem5::o3::CPU::setVecReg
void setVecReg(PhysRegIdPtr reg_idx, const TheISA::VecRegContainer &val)
Definition: cpu.cc:1218
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2536
gem5::EventManager::schedule
void schedule(Event &event, Tick when)
Definition: eventq.hh:1019
std::vector< TheISA::ISA * >
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1141
gem5::o3::CPU::CPUStats::totalIpc
statistics::Formula totalIpc
Stat for the total IPC.
Definition: cpu.hh:686
gem5::o3::CPU::getWritableVecPredReg
TheISA::VecPredRegContainer & getWritableVecPredReg(PhysRegIdPtr reg_idx)
Definition: cpu.cc:1190
gem5::o3::CPU::renameMap
UnifiedRenameMap renameMap[MaxThreads]
The rename map.
Definition: cpu.hh:507
gem5::o3::Fetch
Fetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:79
gem5::o3::CPU::instList
std::list< DynInstPtr > instList
List of all the instructions in flight.
Definition: cpu.hh:462
gem5::o3::CPU::NumStages
@ NumStages
Definition: cpu.hh:542
gem5::o3::CPU::vecRenameMode
void vecRenameMode(enums::VecRegRenameMode vec_mode)
Sets the current vector renaming mode.
Definition: cpu.hh:340
gem5::o3::CPU::getDataPort
Port & getDataPort() override
Get the dcache port (used to find block size for translations).
Definition: cpu.hh:658
gem5::o3::CPU::verifyMemoryMode
void verifyMemoryMode() const override
Verify that the system is in a memory mode supported by the CPU.
Definition: cpu.cc:1113
gem5::o3::CPU::deactivateThread
void deactivateThread(ThreadID tid)
Remove Thread from Active Threads List.
Definition: cpu.cc:608
gem5::o3::CPU::CPUStats::intRegfileWrites
statistics::Scalar intRegfileWrites
Definition: cpu.hh:690
iew.hh
gem5::o3::CPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Unserialize one thread.
Definition: cpu.cc:915
gem5::o3::CPU::readFloatReg
RegVal readFloatReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1155
gem5::o3::CPU::CPUStats::cpi
statistics::Formula cpi
Stat for the CPI per thread.
Definition: cpu.hh:680
gem5::o3::CPU::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: cpu.cc:998
gem5::o3::CPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Serialize a single thread.
Definition: cpu.cc:909
gem5::o3::CPU::cleanUpRemovedInsts
void cleanUpRemovedInsts()
Cleans up all instructions on the remove list.
Definition: cpu.cc:1544
rob.hh
gem5::o3::CPU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: cpu.hh:180
gem5::o3::CPU::iewQueue
TimeBuffer< IEWStruct > iewQueue
The IEW stage's instruction queue.
Definition: cpu.hh:558
gem5::o3::CPU::ppInstAccessComplete
ProbePointArg< PacketPtr > * ppInstAccessComplete
Definition: cpu.hh:173
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:50
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:602
gem5::o3::CPU::unscheduleTickEvent
void unscheduleTickEvent()
Unschedule tick event, regardless of its current state.
Definition: cpu.hh:136
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::CPU::totalInsts
Counter totalInsts() const override
Count the Total Instructions Committed in the CPU.
Definition: cpu.cc:632
gem5::o3::CPU::deactivateStage
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
Definition: cpu.hh:576
timebuf.hh
gem5::o3::ThreadContext
Derived ThreadContext class for use with the O3CPU.
Definition: thread_context.hh:68
gem5::o3::CPU::CPUStats::committedInsts
statistics::Vector committedInsts
Stat for the number of committed instructions per thread.
Definition: cpu.hh:675
gem5::o3::CPU::CPUStats::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles the CPU spends descheduled.
Definition: cpu.hh:670
gem5::o3::CPU::numActiveThreads
int numActiveThreads()
Returns the Number of Active Threads in the CPU.
Definition: cpu.hh:196
gem5::o3::CPU::setArchFloatReg
void setArchFloatReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1328
gem5::o3::CPU::decodeQueue
TimeBuffer< DecodeStruct > decodeQueue
The decode stage's instruction queue.
Definition: cpu.hh:552
gem5::o3::CPU::Blocked
@ Blocked
Definition: cpu.hh:108
gem5::MicroPC
uint16_t MicroPC
Definition: types.hh:149
gem5::o3::CPU::CPUStats::totalCpi
statistics::Formula totalCpi
Stat for the total CPI.
Definition: cpu.hh:682
gem5::o3::CPU::setArchCCReg
void setArchCCReg(int reg_idx, RegVal val, ThreadID tid)
Definition: cpu.cc:1365
comm.hh
gem5::Flags< FlagsType >
gem5::o3::CPU::getWritableVecReg
TheISA::VecRegContainer & getWritableVecReg(PhysRegIdPtr reg_idx)
Read physical vector register for modification.
Definition: cpu.cc:1169
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::o3::CPU::setArchVecReg
void setArchVecReg(int reg_idx, const TheISA::VecRegContainer &val, ThreadID tid)
Definition: cpu.cc:1338
gem5::o3::CPU::IEWIdx
@ IEWIdx
Definition: cpu.hh:540
gem5::o3::CPU::readArchVecPredReg
const TheISA::VecPredRegContainer & readArchVecPredReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1292
gem5::System
Definition: system.hh:77
gem5::o3::CPU::tryDrain
bool tryDrain()
Check if the pipeline has drained and signal drain done.
Definition: cpu.cc:983
gem5::o3::CPU::Status
Status
Definition: cpu.hh:103
gem5::o3::CPU::wakeup
virtual void wakeup(ThreadID tid) override
Definition: cpu.cc:1615
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:95
gem5::o3::LSQ::write
Fault write(LSQRequest *req, uint8_t *data, int store_idx)
Executes a store operation, using the store specified at the store index.
Definition: lsq.cc:1432
gem5::o3::CPU::insertThread
void insertThread(ThreadID tid)
Setup CPU to insert a thread's context.
Definition: cpu.cc:736
gem5::o3::CPU::getInstPort
Port & getInstPort() override
Used by the fetch unit to get a hold of the instruction port.
Definition: cpu.hh:651
gem5::o3::CPU::setCCReg
void setCCReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1240
gem5::o3::Commit
Commit handles single threaded and SMT commit.
Definition: commit.hh:91
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:93
gem5::o3::CPU::CPUStats::vecPredRegfileReads
statistics::Scalar vecPredRegfileReads
Definition: cpu.hh:698
gem5::o3::CPU::setIntReg
void setIntReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1204
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:255
gem5::o3::CPU::scheduleTickEvent
void scheduleTickEvent(Cycles delay)
Schedule tick event, regardless of its current state.
Definition: cpu.hh:127
gem5::o3::CPU::totalOps
Counter totalOps() const override
Count the Total Ops (including micro ops) committed in the CPU.
Definition: cpu.cc:644
gem5::SimObject::params
const Params & params() const
Definition: sim_object.hh:176
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:694
gem5::o3::CPU::StageIdx
StageIdx
Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(),...
Definition: cpu.hh:535
gem5::o3::CPU::readArchVecElem
const TheISA::VecElem & readArchVecElem(const RegIndex &reg_idx, const ElemIndex &ldx, ThreadID tid) const
Definition: cpu.cc:1283
gem5::o3::CPU::setVectorsAsReady
void setVectorsAsReady(ThreadID tid)
Mark vector fields in scoreboard as ready right after switching vector mode, since software may read ...
Definition: cpu.cc:837
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:483
gem5::o3::CPU::halt
void halt()
Halts the CPU.
Definition: cpu.hh:305
gem5::o3::CPU::scheduleThreadExitEvent
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
Definition: cpu.cc:1681
gem5::MipsISA::PCState
GenericISA::DelaySlotPCState< 4 > PCState
Definition: pcstate.hh:40
gem5::o3::CPU::CommitIdx
@ CommitIdx
Definition: cpu.hh:541
statistics.hh
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:66
gem5::o3::CPU::vecRenameMode
enums::VecRegRenameMode vecRenameMode() const
Returns current vector renaming mode.
Definition: cpu.hh:337
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::CPU::FetchIdx
@ FetchIdx
Definition: cpu.hh:537
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1405
gem5::o3::CPU::CPUStats::vecPredRegfileWrites
statistics::Scalar vecPredRegfileWrites
Definition: cpu.hh:699
gem5::o3::CPU::readIntReg
RegVal readIntReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1148
gem5::o3::CPU::activateStage
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Definition: cpu.hh:572
process.hh
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1122
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:590
gem5::o3::CPU::activateThread
void activateThread(ThreadID tid)
Add Thread to Active Threads List.
Definition: cpu.cc:592
activity.hh
gem5::o3::CPU::thread
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Definition: cpu.hh:608
gem5::o3::CPU::setArchVecPredReg
void setArchVecPredReg(int reg_idx, const TheISA::VecPredRegContainer &val, ThreadID tid)
Definition: cpu.cc:1356
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:58
thread_state.hh
gem5::o3::CPU::CPUStats::ccRegfileReads
statistics::Scalar ccRegfileReads
Definition: cpu.hh:701
gem5::o3::CPU::CPUStats::timesIdled
statistics::Scalar timesIdled
Stat for total number of times the CPU is descheduled.
Definition: cpu.hh:668
gem5::o3::CPU::drain
DrainState drain() override
Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.
Definition: cpu.cc:921
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1594
gem5::BaseCPU
Definition: base.hh:107
gem5::EventManager::reschedule
void reschedule(Event &event, Tick when, bool always=false)
Definition: eventq.hh:1037
gem5::o3::CPU::readVecReg
const TheISA::VecRegContainer & readVecReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1162
gem5::o3::CPU::tickEvent
EventFunctionWrapper tickEvent
The tick event used for scheduling CPU ticks.
Definition: cpu.hh:121
gem5::o3::CPU::switchOut
void switchOut() override
Switches out this CPU.
Definition: cpu.cc:1078
gem5::ArmISA::VecRegContainer
gem5::VecRegContainer< NumVecElemPerVecReg *sizeof(VecElem)> VecRegContainer
Definition: vec.hh:62
gem5::o3::CPU::Idle
@ Idle
Definition: cpu.hh:106
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1135
gem5::o3::CPU::renameQueue
TimeBuffer< RenameStruct > renameQueue
The rename stage's instruction queue.
Definition: cpu.hh:555
fetch.hh
gem5::o3::CPU::rob
ROB rob
The re-order buffer.
Definition: cpu.hh:513
gem5::o3::CPU::CPUStats
Definition: cpu.hh:663
gem5::o3::CPU::Running
@ Running
Definition: cpu.hh:105
gem5::o3::CPU::CPUStats::vecRegfileWrites
statistics::Scalar vecRegfileWrites
Definition: cpu.hh:696
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
dyn_inst_ptr.hh
gem5::o3::CPU::CPUStats::vecRegfileReads
statistics::Scalar vecRegfileReads
Definition: cpu.hh:695
gem5::o3::CPU::CPUStats::committedOps
statistics::Vector committedOps
Stat for the number of committed ops (including micro ops) per thread.
Definition: cpu.hh:678
gem5::ElemIndex
uint16_t ElemIndex
Logical vector register elem index type.
Definition: types.hh:179
gem5::o3::CPU::instAddr
Addr instAddr(ThreadID tid)
Reads the commit PC of a specific thread.
Definition: cpu.cc:1387
gem5::Clocked::clockEdge
Tick clockEdge(Cycles cycles=Cycles(0)) const
Determine the tick when a cycle begins, by default the current one, but the argument also enables the...
Definition: clocked_object.hh:177
gem5::o3::CPU::getWritableArchVecReg
TheISA::VecRegContainer & getWritableArchVecReg(int reg_idx, ThreadID tid)
Read architectural vector register for modification.
Definition: cpu.cc:1275
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::o3::CPU::setFloatReg
void setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1211
gem5::o3::CPU::setVecPredReg
void setVecPredReg(PhysRegIdPtr reg_idx, const TheISA::VecPredRegContainer &val)
Definition: cpu.cc:1232
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::o3::CPU::regProbePoints
void regProbePoints() override
Register probe points.
Definition: cpu.cc:358
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:605
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::o3::CPU::instcount
int instcount
Count of total number of dynamic instructions in flight.
Definition: cpu.hh:458
types.hh
gem5::o3::CPU::lastRunningCycle
Cycles lastRunningCycle
The cycle that the CPU was last running, used for statistics.
Definition: cpu.hh:614
gem5::o3::CPU::updateThreadPriority
void updateThreadPriority()
Update The Order In Which We Process Threads.
Definition: cpu.cc:1640
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::CPU::getWritableArchVecPredReg
TheISA::VecPredRegContainer & getWritableArchVecPredReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1300
gem5::o3::Rename
Rename handles both single threaded and SMT rename.
Definition: rename.hh:78
gem5::o3::CPU::CPUStats::ipc
statistics::Formula ipc
Stat for the IPC per thread.
Definition: cpu.hh:684
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:569
gem5::o3::CPU::write
Fault write(LSQRequest *req, uint8_t *data, int store_idx)
CPU write function, forwards write to LSQ.
Definition: cpu.hh:644
gem5::o3::CPU::rename
Rename rename
The dispatch stage.
Definition: cpu.hh:489
gem5::o3::CPU::fetchQueue
TimeBuffer< FetchStruct > fetchQueue
The fetch stage's instruction queue.
Definition: cpu.hh:549
simple_thread.hh
gem5::ActivityRecorder::activateStage
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:91
gem5::o3::CPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU) override
Takes over from another CPU.
Definition: cpu.cc:1092
gem5::o3::CPU::iew
IEW iew
The issue/execute/writeback stages.
Definition: cpu.hh:492
gem5::o3::CPU::removeInstsNotInROB
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
Definition: cpu.cc:1452
gem5::o3::CPU::exitThreads
void exitThreads()
Terminate all threads that are ready to exit.
Definition: cpu.cc:1701
gem5::o3::CPU::lastActivatedCycle
Tick lastActivatedCycle
The cycle that the CPU was last activated by a new thread.
Definition: cpu.hh:617
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::o3::CPU::commitDrained
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
Definition: cpu.cc:1046
gem5::ArmISA::VecElem
uint32_t VecElem
Definition: vec.hh:60
gem5::o3::Decode
Decode class handles both single threaded and SMT decode.
Definition: decode.hh:69
gem5::o3::CPU::switchRenameMode
void switchRenameMode(ThreadID tid, UnifiedFreeList *freelist)
Check if a change in renaming is needed for vector registers.
Definition: cpu.cc:860
gem5::o3::CPU::microPC
MicroPC microPC(ThreadID tid)
Reads the commit micro PC of a specific thread.
Definition: cpu.cc:1399
gem5::o3::CPU::commitRenameMap
UnifiedRenameMap commitRenameMap[MaxThreads]
The commit rename map.
Definition: cpu.hh:510
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:902
gem5::Event::squashed
bool squashed() const
Check whether the event is squashed.
Definition: eventq.hh:479
gem5::o3::CPU::drainResume
void drainResume() override
Resumes execution after a drain.
Definition: cpu.cc:1049
gem5::o3::CPU::getFreeTid
ThreadID getFreeTid()
Gets a free thread id.
Definition: cpu.cc:1627
gem5::o3::CPU::addInst
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
Definition: cpu.cc:1412
gem5::o3::CPU::isThreadExiting
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
Definition: cpu.cc:1675
gem5::o3::CPU::threadExitEvent
EventFunctionWrapper threadExitEvent
The exit event used for terminating all ready-to-exit threads.
Definition: cpu.hh:124
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::ActivityRecorder
ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not.
Definition: activity.hh:53
gem5::o3::CPU::isDraining
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:232
free_list.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1128
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:198
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::o3::CPU::SwitchedOut
@ SwitchedOut
Definition: cpu.hh:109
gem5::o3::CPU::CPUStats::fpRegfileReads
statistics::Scalar fpRegfileReads
Definition: cpu.hh:692
gem5::o3::CPU::exitingThreads
std::unordered_map< ThreadID, bool > exitingThreads
This is a list of threads that are trying to exit.
Definition: cpu.hh:523
gem5::o3::CPU::readArchIntReg
RegVal readArchIntReg(int reg_idx, ThreadID tid)
Definition: cpu.cc:1247
gem5::o3::LSQ::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable)
Definition: lsq.cc:774
gem5::Event::squash
void squash()
Squash the current event.
Definition: eventq.hh:472
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:1010
decode.hh
gem5::o3::CPU::scoreboard
Scoreboard scoreboard
Integer Register Scoreboard.
Definition: cpu.hh:526
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
gem5::RegIndex
uint16_t RegIndex
Definition: types.hh:176
gem5::o3::CPU::commit
Commit commit
The commit stage.
Definition: cpu.hh:495
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::CPU::haltContext
void haltContext(ThreadID tid) override
Remove Thread from Active Threads List && Remove Thread Context from CPU.
Definition: cpu.cc:714
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::CPU::activityRec
ActivityRecorder activityRec
The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and...
Definition: cpu.hh:565
gem5::o3::CPU::pcState
void pcState(const TheISA::PCState &newPCState, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1381
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: decoder.cc:40
gem5::ActivityRecorder::deactivateStage
void deactivateStage(const int idx)
Deactivates a stage.
Definition: activity.cc:108
gem5::o3::CPU::readVecPredReg
const TheISA::VecPredRegContainer & readVecPredReg(PhysRegIdPtr reg_idx) const
Definition: cpu.cc:1183
limits.hh
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:656
gem5::o3::CPU::nextInstAddr
Addr nextInstAddr(ThreadID tid)
Reads the next PC of a specific thread.
Definition: cpu.cc:1393
gem5::o3::CPU::tick
void tick()
Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should d...
Definition: cpu.cc:502
gem5::o3::ROB
ROB class.
Definition: rob.hh:72
gem5::Checker
Templated Checker class.
Definition: cpu.hh:565
gem5::o3::CPU::startup
void startup() override
startup() is the final initialization call before simulation.
Definition: cpu.cc:580
scoreboard.hh
gem5::o3::CPU::CPUStats::CPUStats
CPUStats(CPU *cpu)
Definition: cpu.cc:374
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:528
gem5::o3::CPU::read
Fault read(LSQRequest *req, int load_idx)
CPU read function, forwards read to LSQ.
Definition: cpu.hh:638
gem5::o3::CPU::Halted
@ Halted
Definition: cpu.hh:107
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::o3::CPU::instDone
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
Definition: cpu.cc:1420
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:242
gem5::o3::CPU::init
void init() override
Initialize the CPU.
Definition: cpu.cc:560
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:177
gem5::o3::UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:174
gem5::o3::CPU::removeFrontInst
void removeFrontInst(const DynInstPtr &inst)
Remove an instruction from the front end of the list.
Definition: cpu.cc:1439
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84
gem5::o3::CPU::readArchVecReg
const TheISA::VecRegContainer & readArchVecReg(int reg_idx, ThreadID tid) const
Definition: cpu.cc:1267

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