gem5  v22.0.0.1
cpu.hh
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42 
43 #ifndef __CPU_O3_CPU_HH__
44 #define __CPU_O3_CPU_HH__
45 
46 #include <iostream>
47 #include <list>
48 #include <queue>
49 #include <set>
50 #include <vector>
51 
52 #include "arch/generic/pcstate.hh"
53 #include "base/statistics.hh"
54 #include "config/the_isa.hh"
55 #include "cpu/o3/comm.hh"
56 #include "cpu/o3/commit.hh"
57 #include "cpu/o3/decode.hh"
58 #include "cpu/o3/dyn_inst_ptr.hh"
59 #include "cpu/o3/fetch.hh"
60 #include "cpu/o3/free_list.hh"
61 #include "cpu/o3/iew.hh"
62 #include "cpu/o3/limits.hh"
63 #include "cpu/o3/rename.hh"
64 #include "cpu/o3/rob.hh"
65 #include "cpu/o3/scoreboard.hh"
66 #include "cpu/o3/thread_state.hh"
67 #include "cpu/activity.hh"
68 #include "cpu/base.hh"
69 #include "cpu/simple_thread.hh"
70 #include "cpu/timebuf.hh"
71 #include "params/BaseO3CPU.hh"
72 #include "sim/process.hh"
73 
74 namespace gem5
75 {
76 
77 template <class>
78 class Checker;
79 class ThreadContext;
80 
81 class Checkpoint;
82 class Process;
83 
84 namespace o3
85 {
86 
87 class ThreadContext;
88 
94 class CPU : public BaseCPU
95 {
96  public:
98 
99  friend class ThreadContext;
100 
101  public:
102  enum Status
103  {
109  };
110 
113 
116 
117  private:
118 
121 
124 
126  void
128  {
129  if (tickEvent.squashed())
130  reschedule(tickEvent, clockEdge(delay));
131  else if (!tickEvent.scheduled())
132  schedule(tickEvent, clockEdge(delay));
133  }
134 
136  void
138  {
139  if (tickEvent.scheduled())
140  tickEvent.squash();
141  }
142 
154  bool tryDrain();
155 
165  void drainSanityCheck() const;
166 
168  bool isCpuDrained() const;
169 
170  public:
172  CPU(const BaseO3CPUParams &params);
173 
176 
178  void regProbePoints() override;
179 
180  void
181  demapPage(Addr vaddr, uint64_t asn)
182  {
183  mmu->demapPage(vaddr, asn);
184  }
185 
189  void tick();
190 
192  void init() override;
193 
194  void startup() override;
195 
197  int
199  {
200  return activeThreads.size();
201  }
202 
204  void activateThread(ThreadID tid);
205 
207  void deactivateThread(ThreadID tid);
208 
210  void insertThread(ThreadID tid);
211 
213  void removeThread(ThreadID tid);
214 
216  Counter totalInsts() const override;
217 
219  Counter totalOps() const override;
220 
222  void activateContext(ThreadID tid) override;
223 
225  void suspendContext(ThreadID tid) override;
226 
230  void haltContext(ThreadID tid) override;
231 
233  void updateThreadPriority();
234 
236  bool isDraining() const { return drainState() == DrainState::Draining; }
237 
238  void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
239  void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
240 
243 
245  bool isThreadExiting(ThreadID tid) const;
246 
252 
254  void exitThreads();
255 
256  public:
259  DrainState drain() override;
260 
262  void drainResume() override;
263 
271  void commitDrained(ThreadID tid);
272 
274  void switchOut() override;
275 
277  void takeOverFrom(BaseCPU *oldCPU) override;
278 
279  void verifyMemoryMode() const override;
280 
283 
285  void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst);
286 
289 
291  void processInterrupts(const Fault &interrupt);
292 
294  void halt() { panic("Halt not implemented!\n"); }
295 
299  RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
300 
304  RegVal readMiscReg(int misc_reg, ThreadID tid);
305 
307  void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
308 
312  void setMiscReg(int misc_reg, RegVal val, ThreadID tid);
313 
314  RegVal getReg(PhysRegIdPtr phys_reg);
315  void getReg(PhysRegIdPtr phys_reg, void *val);
316  void *getWritableReg(PhysRegIdPtr phys_reg);
317 
318  void setReg(PhysRegIdPtr phys_reg, RegVal val);
319  void setReg(PhysRegIdPtr phys_reg, const void *val);
320 
327  RegVal getArchReg(const RegId &reg, ThreadID tid);
328  void getArchReg(const RegId &reg, void *val, ThreadID tid);
329  void *getWritableArchReg(const RegId &reg, ThreadID tid);
330 
331  void setArchReg(const RegId &reg, RegVal val, ThreadID tid);
332  void setArchReg(const RegId &reg, const void *val, ThreadID tid);
333 
335  void pcState(const PCStateBase &new_pc_state, ThreadID tid);
336 
338  const PCStateBase &pcState(ThreadID tid);
339 
344  void squashFromTC(ThreadID tid);
345 
349  ListIt addInst(const DynInstPtr &inst);
350 
352  void instDone(ThreadID tid, const DynInstPtr &inst);
353 
357  void removeFrontInst(const DynInstPtr &inst);
358 
361  void removeInstsNotInROB(ThreadID tid);
362 
364  void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
365 
367  void squashInstIt(const ListIt &instIt, ThreadID tid);
368 
370  void cleanUpRemovedInsts();
371 
373  void dumpInsts();
374 
375  public:
376 #ifndef NDEBUG
377 
379 #endif
380 
383 
387  std::queue<ListIt> removeList;
388 
389 #ifdef DEBUG
390 
393  std::set<InstSeqNum> snList;
394 #endif
395 
400 
401  protected:
404 
407 
410 
413 
416 
419 
422 
425 
428 
431 
434 
440  std::unordered_map<ThreadID, bool> exitingThreads;
441 
444 
446 
447  public:
452  enum StageIdx
453  {
460  };
461 
464 
467 
470 
473 
476 
477  private:
483 
484  public:
487 
489  void
491  {
493  }
494 
496  void
498  {
500  }
501 
503  void wakeCPU();
504 
505  virtual void wakeup(ThreadID tid) override;
506 
509 
510  public:
514  {
515  return thread[tid]->getTC();
516  }
517 
519  InstSeqNum globalSeqNum;//[MaxThreads];
520 
526 
529 
532 
535 
538 
541 
543  std::map<ThreadID, unsigned> threadMap;
544 
547 
549  Fault
550  pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
551  unsigned int size, Addr addr, Request::Flags flags,
552  uint64_t *res, AtomicOpFunctorPtr amo_op = nullptr,
553  const std::vector<bool>& byte_enable=std::vector<bool>())
554 
555  {
556  return iew.ldstQueue.pushRequest(inst, isLoad, data, size, addr,
557  flags, res, std::move(amo_op), byte_enable);
558  }
559 
561  Port &
562  getInstPort() override
563  {
564  return fetch.getInstPort();
565  }
566 
568  Port &
569  getDataPort() override
570  {
571  return iew.ldstQueue.getDataPort();
572  }
573 
574  struct CPUStats : public statistics::Group
575  {
576  CPUStats(CPU *cpu);
577 
598 
599  //number of integer register file accesses
602  //number of float register file accesses
605  //number of vector register file accesses
608  //number of predicate register file accesses
611  //number of CC register file accesses
614  //number of misc
617  } cpuStats;
618 
619  public:
620  // hardware transactional memory
621  void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid,
622  HtmFailureFaultCause cause) override;
623 };
624 
625 } // namespace o3
626 } // namespace gem5
627 
628 #endif // __CPU_O3_CPU_HH__
gem5::statistics::Scalar
This is a simple scalar statistic, like a counter.
Definition: statistics.hh:1930
gem5::o3::CPU::DecodeIdx
@ DecodeIdx
Definition: cpu.hh:455
gem5::o3::CPU::addThreadToExitingList
void addThreadToExitingList(ThreadID tid)
Insert tid to the list of threads trying to exit.
Definition: cpu.cc:1459
gem5::o3::CPU::dumpInsts
void dumpInsts()
Debug function to print all instructions on the list.
Definition: cpu.cc:1370
gem5::o3::CPU::getWritableArchReg
void * getWritableArchReg(const RegId &reg, ThreadID tid)
Definition: cpu.cc:1174
gem5::o3::CPU::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op=nullptr, const std::vector< bool > &byte_enable=std::vector< bool >())
CPU pushRequest function, forwards request to LSQ.
Definition: cpu.hh:550
gem5::o3::CPU::ppDataAccessComplete
ProbePointArg< std::pair< DynInstPtr, PacketPtr > > * ppDataAccessComplete
Definition: cpu.hh:175
gem5::o3::CPU::isCpuDrained
bool isCpuDrained() const
Check if a system is in a drained state.
Definition: cpu.cc:901
gem5::o3::LSQ::LSQRequest
Memory operation metadata.
Definition: lsq.hh:189
gem5::o3::CPU::tids
std::vector< ThreadID > tids
Available thread ids in the cpu.
Definition: cpu.hh:546
gem5::o3::CPU::CPUStats::miscRegfileWrites
statistics::Scalar miscRegfileWrites
Definition: cpu.hh:616
gem5::o3::CPU::threadMap
std::map< ThreadID, unsigned > threadMap
Mapping for system thread id to cpu id.
Definition: cpu.hh:543
gem5::o3::CPU::removeList
std::queue< ListIt > removeList
List of all the instructions that will be removed at the end of this cycle.
Definition: cpu.hh:387
gem5::o3::CPU::getReg
RegVal getReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1040
gem5::o3::CPU::CPUStats::fpRegfileWrites
statistics::Scalar fpRegfileWrites
Definition: cpu.hh:604
commit.hh
gem5::RegVal
uint64_t RegVal
Definition: types.hh:173
gem5::o3::CPU::removeInstsThisCycle
bool removeInstsThisCycle
Records if instructions need to be removed this cycle due to being retired or squashed.
Definition: cpu.hh:399
gem5::o3::CPU::ListIt
std::list< DynInstPtr >::iterator ListIt
Definition: cpu.hh:97
gem5::o3::CPU::cpuStats
gem5::o3::CPU::CPUStats cpuStats
gem5::o3::CPU::globalSeqNum
InstSeqNum globalSeqNum
The global sequence number counter.
Definition: cpu.hh:519
gem5::o3::CPU::removeInstsUntil
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
Remove all instructions younger than the given sequence number.
Definition: cpu.cc:1298
gem5::o3::CPU::mmu
BaseMMU * mmu
Definition: cpu.hh:111
data
const char data[]
Definition: circlebuf.test.cc:48
gem5::HtmFailureFaultCause
HtmFailureFaultCause
Definition: htm.hh:47
gem5::o3::CPU::regFile
PhysRegFile regFile
The register file.
Definition: cpu.hh:418
gem5::o3::Fetch::getInstPort
RequestPort & getInstPort()
Definition: fetch.hh:361
rename.hh
gem5::o3::CPU::decode
Decode decode
The decode stage.
Definition: cpu.hh:406
gem5::o3::CPU::CPUStats::ccRegfileWrites
statistics::Scalar ccRegfileWrites
Definition: cpu.hh:613
gem5::o3::CPU::activeThreads
std::list< ThreadID > activeThreads
Active Threads List.
Definition: cpu.hh:433
gem5::o3::CPU::freeList
UnifiedFreeList freeList
The free list.
Definition: cpu.hh:421
gem5::o3::CPU::processInterrupts
void processInterrupts(const Fault &interrupt)
Processes any an interrupt fault.
Definition: cpu.cc:778
gem5::o3::CPU::RenameIdx
@ RenameIdx
Definition: cpu.hh:456
gem5::CheckpointIn
Definition: serialize.hh:68
gem5::o3::CPU::CPUStats::quiesceCycles
statistics::Scalar quiesceCycles
Stat for total number of cycles the CPU spends descheduled due to a quiesce operation or waiting for ...
Definition: cpu.hh:584
gem5::o3::CPU::getInterrupts
Fault getInterrupts()
Returns the Fault for any valid interrupt.
Definition: cpu.cc:771
gem5::o3::CPU::squashInstIt
void squashInstIt(const ListIt &instIt, ThreadID tid)
Removes the instruction pointed to by the iterator.
Definition: cpu.cc:1326
gem5::o3::CPU::htmSendAbortSignal
void htmSendAbortSignal(ThreadID tid, uint64_t htm_uid, HtmFailureFaultCause cause) override
Definition: cpu.cc:1527
gem5::o3::CPU::setReg
void setReg(PhysRegIdPtr phys_reg, RegVal val)
Definition: cpu.cc:1108
gem5::o3::CPU::CPUStats::miscRegfileReads
statistics::Scalar miscRegfileReads
Definition: cpu.hh:615
gem5::o3::CPU::CPUStats::intRegfileReads
statistics::Scalar intRegfileReads
Definition: cpu.hh:600
gem5::o3::CPU::_status
Status _status
Overall CPU status.
Definition: cpu.hh:115
gem5::X86ISA::val
Bitfield< 63 > val
Definition: misc.hh:769
gem5::o3::CPU::timeBuffer
TimeBuffer< TimeStruct > timeBuffer
The main time buffer to do backwards communication.
Definition: cpu.hh:463
gem5::o3::CPU::getAndIncrementInstSeq
InstSeqNum getAndIncrementInstSeq()
Get the current instruction sequence number, and increment it.
Definition: cpu.hh:282
gem5::o3::CPU::cpuWaitList
std::list< int > cpuWaitList
Threads Scheduled to Enter CPU.
Definition: cpu.hh:534
gem5::o3::CPU::removeThread
void removeThread(ThreadID tid)
Remove all of a thread's context from CPU.
Definition: cpu.cc:719
gem5::o3::UnifiedFreeList
FreeList class that simply holds the list of free integer and floating point registers.
Definition: free_list.hh:124
gem5::o3::Scoreboard
Implements a simple scoreboard to track which registers are ready.
Definition: scoreboard.hh:54
gem5::statistics::Vector
A vector of scalar stats.
Definition: statistics.hh:2006
gem5::statistics::Formula
A formula for statistics that is calculated when printed.
Definition: statistics.hh:2539
std::vector< TheISA::ISA * >
gem5::o3::CPU::setMiscReg
void setMiscReg(int misc_reg, RegVal val, ThreadID tid)
Sets a misc.
Definition: cpu.cc:1033
gem5::o3::CPU::CPUStats::totalIpc
statistics::Formula totalIpc
Stat for the total IPC.
Definition: cpu.hh:597
gem5::o3::CPU::renameMap
UnifiedRenameMap renameMap[MaxThreads]
The rename map.
Definition: cpu.hh:424
gem5::o3::Fetch
Fetch class handles both single threaded and SMT fetch.
Definition: fetch.hh:79
gem5::o3::CPU::instList
std::list< DynInstPtr > instList
List of all the instructions in flight.
Definition: cpu.hh:382
gem5::o3::CPU::NumStages
@ NumStages
Definition: cpu.hh:459
gem5::o3::CPU::getDataPort
Port & getDataPort() override
Get the dcache port (used to find block size for translations).
Definition: cpu.hh:569
gem5::o3::CPU::verifyMemoryMode
void verifyMemoryMode() const override
Definition: cpu.cc:1005
gem5::o3::CPU::deactivateThread
void deactivateThread(ThreadID tid)
Remove Thread from Active Threads List.
Definition: cpu.cc:553
gem5::o3::CPU::CPUStats::intRegfileWrites
statistics::Scalar intRegfileWrites
Definition: cpu.hh:601
iew.hh
gem5::o3::CPU::unserializeThread
void unserializeThread(CheckpointIn &cp, ThreadID tid) override
Definition: cpu.cc:807
gem5::o3::CPU::CPUStats::cpi
statistics::Formula cpi
Stat for the CPI per thread.
Definition: cpu.hh:591
gem5::o3::CPU::drainSanityCheck
void drainSanityCheck() const
Perform sanity checks after a drain.
Definition: cpu.cc:890
gem5::o3::CPU::serializeThread
void serializeThread(CheckpointOut &cp, ThreadID tid) const override
Definition: cpu.cc:801
gem5::o3::CPU::cleanUpRemovedInsts
void cleanUpRemovedInsts()
Cleans up all instructions on the remove list.
Definition: cpu.cc:1346
rob.hh
gem5::o3::CPU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: cpu.hh:181
gem5::o3::CPU::iewQueue
TimeBuffer< IEWStruct > iewQueue
The IEW stage's instruction queue.
Definition: cpu.hh:475
gem5::o3::CPU::ppInstAccessComplete
ProbePointArg< PacketPtr > * ppInstAccessComplete
Definition: cpu.hh:174
gem5::RefCountingPtr< StaticInst >
gem5::BaseMMU
Definition: mmu.hh:53
gem5::TimeBuffer
Definition: timebuf.hh:40
gem5::o3::CPU::checker
gem5::Checker< DynInstPtr > * checker
Pointer to the checker, which can dynamically verify instruction results at run time.
Definition: cpu.hh:525
gem5::o3::CPU::unscheduleTickEvent
void unscheduleTickEvent()
Unschedule tick event, regardless of its current state.
Definition: cpu.hh:137
gem5::Cycles
Cycles is a wrapper class for representing cycle counts, i.e.
Definition: types.hh:78
gem5::o3::CPU::totalInsts
Counter totalInsts() const override
Count the Total Instructions Committed in the CPU.
Definition: cpu.cc:577
gem5::o3::CPU::deactivateStage
void deactivateStage(const StageIdx idx)
Changes a stage's status to inactive within the activity recorder.
Definition: cpu.hh:497
timebuf.hh
gem5::o3::ThreadContext
Derived ThreadContext class for use with the O3CPU.
Definition: thread_context.hh:68
gem5::o3::CPU::CPUStats::committedInsts
statistics::Vector committedInsts
Stat for the number of committed instructions per thread.
Definition: cpu.hh:586
gem5::o3::CPU::CPUStats::idleCycles
statistics::Scalar idleCycles
Stat for total number of cycles the CPU spends descheduled.
Definition: cpu.hh:581
gem5::o3::CPU::numActiveThreads
int numActiveThreads()
Returns the Number of Active Threads in the CPU.
Definition: cpu.hh:198
gem5::o3::CPU::decodeQueue
TimeBuffer< DecodeStruct > decodeQueue
The decode stage's instruction queue.
Definition: cpu.hh:469
gem5::o3::CPU::Blocked
@ Blocked
Definition: cpu.hh:107
gem5::o3::CPU::CPUStats::totalCpi
statistics::Formula totalCpi
Stat for the total CPI.
Definition: cpu.hh:593
comm.hh
gem5::Flags< FlagsType >
gem5::DrainState
DrainState
Object drain/handover states.
Definition: drain.hh:74
gem5::o3::CPU::IEWIdx
@ IEWIdx
Definition: cpu.hh:457
gem5::System
Definition: system.hh:75
gem5::o3::CPU::tryDrain
bool tryDrain()
Check if the pipeline has drained and signal drain done.
Definition: cpu.cc:875
gem5::o3::CPU::Status
Status
Definition: cpu.hh:102
gem5::o3::CPU::wakeup
virtual void wakeup(ThreadID tid) override
Definition: cpu.cc:1418
gem5::o3::CPU
O3CPU class, has each of the stages (fetch through commit) within it, as well as all of the time buff...
Definition: cpu.hh:94
gem5::o3::CPU::insertThread
void insertThread(ThreadID tid)
Setup CPU to insert a thread's context.
Definition: cpu.cc:681
gem5::o3::CPU::getInstPort
Port & getInstPort() override
Used by the fetch unit to get a hold of the instruction port.
Definition: cpu.hh:562
gem5::o3::Commit
Commit handles single threaded and SMT commit.
Definition: commit.hh:91
gem5::ThreadContext
ThreadContext is the external interface to all thread state for anything outside of the CPU.
Definition: thread_context.hh:94
gem5::o3::CPU::CPUStats::vecPredRegfileReads
statistics::Scalar vecPredRegfileReads
Definition: cpu.hh:609
gem5::Fault
std::shared_ptr< FaultBase > Fault
Definition: types.hh:248
gem5::o3::CPU::scheduleTickEvent
void scheduleTickEvent(Cycles delay)
Schedule tick event, regardless of its current state.
Definition: cpu.hh:127
gem5::o3::CPU::totalOps
Counter totalOps() const override
Count the Total Ops (including micro ops) committed in the CPU.
Definition: cpu.cc:589
gem5::o3::CPU::suspendContext
void suspendContext(ThreadID tid) override
Remove Thread from Active Threads List.
Definition: cpu.cc:639
gem5::o3::CPU::StageIdx
StageIdx
Enum to give each stage a specific index, so when calling activateStage() or deactivateStage(),...
Definition: cpu.hh:452
gem5::o3::CPU::fetch
Fetch fetch
The fetch stage.
Definition: cpu.hh:403
gem5::o3::CPU::halt
void halt()
Halts the CPU.
Definition: cpu.hh:294
gem5::o3::CPU::scheduleThreadExitEvent
void scheduleThreadExitEvent(ThreadID tid)
If a thread is trying to exit and its corresponding trap event has been completed,...
Definition: cpu.cc:1484
gem5::o3::CPU::CommitIdx
@ CommitIdx
Definition: cpu.hh:458
statistics.hh
gem5::o3::PhysRegFile
Simple physical register file class.
Definition: regfile.hh:67
gem5::Tick
uint64_t Tick
Tick count type.
Definition: types.hh:58
gem5::o3::CPU::pcState
void pcState(const PCStateBase &new_pc_state, ThreadID tid)
Sets the commit PC state of a specific thread.
Definition: cpu.cc:1201
gem5::o3::IEW
IEW handles both single threaded and SMT IEW (issue/execute/writeback).
Definition: iew.hh:87
gem5::o3::CPU::FetchIdx
@ FetchIdx
Definition: cpu.hh:454
gem5::o3::CPU::squashFromTC
void squashFromTC(ThreadID tid)
Initiates a squash of all in-flight instructions for a given thread.
Definition: cpu.cc:1207
gem5::o3::CPU::CPUStats::vecPredRegfileWrites
statistics::Scalar vecPredRegfileWrites
Definition: cpu.hh:610
gem5::o3::CPU::activateStage
void activateStage(const StageIdx idx)
Changes a stage's status to active within the activity recorder.
Definition: cpu.hh:490
process.hh
gem5::o3::CPU::readMiscRegNoEffect
RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const
Register accessors.
Definition: cpu.cc:1014
gem5::o3::CPU::tcBase
gem5::ThreadContext * tcBase(ThreadID tid)
Returns a pointer to a thread context.
Definition: cpu.hh:513
gem5::o3::CPU::activateThread
void activateThread(ThreadID tid)
Add Thread to Active Threads List.
Definition: cpu.cc:537
activity.hh
gem5::o3::CPU::thread
std::vector< ThreadState * > thread
Pointers to all of the threads in the CPU.
Definition: cpu.hh:531
gem5::o3::CPU::getWritableReg
void * getWritableReg(PhysRegIdPtr phys_reg)
Definition: cpu.cc:1092
gem5::BaseMMU::demapPage
void demapPage(Addr vaddr, uint64_t asn)
Definition: mmu.cc:97
thread_state.hh
gem5::o3::CPU::CPUStats::ccRegfileReads
statistics::Scalar ccRegfileReads
Definition: cpu.hh:612
gem5::o3::CPU::CPUStats::timesIdled
statistics::Scalar timesIdled
Stat for total number of times the CPU is descheduled.
Definition: cpu.hh:579
gem5::o3::CPU::drain
DrainState drain() override
Starts draining the CPU's pipeline of all instructions in order to stop all memory accesses.
Definition: cpu.cc:813
gem5::o3::CPU::wakeCPU
void wakeCPU()
Wakes the CPU, rescheduling the CPU if it's not already active.
Definition: cpu.cc:1397
gem5::o3::CPU::tickEvent
EventFunctionWrapper tickEvent
The tick event used for scheduling CPU ticks.
Definition: cpu.hh:120
gem5::o3::CPU::switchOut
void switchOut() override
Switches out this CPU.
Definition: cpu.cc:970
flags
uint8_t flags
Definition: helpers.cc:66
gem5::o3::CPU::CPU
CPU(const BaseO3CPUParams &params)
Constructs a CPU with the given parameters.
Definition: cpu.cc:73
gem5::o3::CPU::Idle
@ Idle
Definition: cpu.hh:105
gem5::o3::CPU::setMiscRegNoEffect
void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
Sets a miscellaneous register.
Definition: cpu.cc:1027
gem5::o3::CPU::renameQueue
TimeBuffer< RenameStruct > renameQueue
The rename stage's instruction queue.
Definition: cpu.hh:472
fetch.hh
gem5::o3::CPU::rob
ROB rob
The re-order buffer.
Definition: cpu.hh:430
gem5::o3::CPU::CPUStats
Definition: cpu.hh:574
gem5::o3::CPU::Running
@ Running
Definition: cpu.hh:104
gem5::o3::CPU::CPUStats::vecRegfileWrites
statistics::Scalar vecRegfileWrites
Definition: cpu.hh:607
gem5::Addr
uint64_t Addr
Address type This will probably be moved somewhere else in the near future.
Definition: types.hh:147
dyn_inst_ptr.hh
gem5::o3::CPU::CPUStats::vecRegfileReads
statistics::Scalar vecRegfileReads
Definition: cpu.hh:606
gem5::o3::CPU::CPUStats::committedOps
statistics::Vector committedOps
Stat for the number of committed ops (including micro ops) per thread.
Definition: cpu.hh:589
gem5::ActivityRecorder::activity
void activity()
Records that there is activity this cycle.
Definition: activity.cc:55
gem5::ProbePointArg
ProbePointArg generates a point for the class of Arg.
Definition: thermal_domain.hh:54
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::o3::CPU::regProbePoints
void regProbePoints() override
Register probe points.
Definition: cpu.cc:305
gem5::o3::CPU::system
System * system
Pointer to the system.
Definition: cpu.hh:528
gem5::EventFunctionWrapper
Definition: eventq.hh:1115
gem5::o3::CPU::instcount
int instcount
Count of total number of dynamic instructions in flight.
Definition: cpu.hh:378
pcstate.hh
gem5::o3::CPU::lastRunningCycle
Cycles lastRunningCycle
The cycle that the CPU was last running, used for statistics.
Definition: cpu.hh:537
gem5::o3::CPU::updateThreadPriority
void updateThreadPriority()
Update The Order In Which We Process Threads.
Definition: cpu.cc:1443
gem5::o3::MaxThreads
static constexpr int MaxThreads
Definition: limits.hh:38
gem5::o3::Rename
Rename handles both single threaded and SMT rename.
Definition: rename.hh:78
gem5::o3::CPU::CPUStats::ipc
statistics::Formula ipc
Stat for the IPC per thread.
Definition: cpu.hh:595
gem5::o3::CPU::activityThisCycle
void activityThisCycle()
Records that there was time buffer activity this cycle.
Definition: cpu.hh:486
gem5::o3::CPU::rename
Rename rename
The dispatch stage.
Definition: cpu.hh:409
gem5::o3::CPU::fetchQueue
TimeBuffer< FetchStruct > fetchQueue
The fetch stage's instruction queue.
Definition: cpu.hh:466
simple_thread.hh
gem5::ActivityRecorder::activateStage
void activateStage(const int idx)
Marks a stage as active.
Definition: activity.cc:91
gem5::o3::CPU::takeOverFrom
void takeOverFrom(BaseCPU *oldCPU) override
Takes over from another CPU.
Definition: cpu.cc:984
gem5::o3::CPU::iew
IEW iew
The issue/execute/writeback stages.
Definition: cpu.hh:412
gem5::o3::CPU::removeInstsNotInROB
void removeInstsNotInROB(ThreadID tid)
Remove all instructions that are not currently in the ROB.
Definition: cpu.cc:1254
gem5::o3::CPU::exitThreads
void exitThreads()
Terminate all threads that are ready to exit.
Definition: cpu.cc:1504
gem5::o3::CPU::lastActivatedCycle
Tick lastActivatedCycle
The cycle that the CPU was last activated by a new thread.
Definition: cpu.hh:540
base.hh
gem5::Port
Ports are used to interface objects to each other.
Definition: port.hh:61
gem5::o3::CPU::commitDrained
void commitDrained(ThreadID tid)
Commit has reached a safe point to drain a thread.
Definition: cpu.cc:938
gem5::o3::Decode
Decode class handles both single threaded and SMT decode.
Definition: decode.hh:69
gem5::o3::CPU::commitRenameMap
UnifiedRenameMap commitRenameMap[MaxThreads]
The commit rename map.
Definition: cpu.hh:427
gem5::o3::CPU::trap
void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst)
Traps to handle given fault.
Definition: cpu.cc:794
gem5::Event::squashed
bool squashed() const
Check whether the event is squashed.
Definition: eventq.hh:479
gem5::o3::CPU::drainResume
void drainResume() override
Resumes execution after a drain.
Definition: cpu.cc:941
gem5::o3::CPU::getFreeTid
ThreadID getFreeTid()
Gets a free thread id.
Definition: cpu.cc:1430
gem5::o3::CPU::addInst
ListIt addInst(const DynInstPtr &inst)
Function to add instruction onto the head of the list of the instructions.
Definition: cpu.cc:1214
gem5::o3::CPU::setArchReg
void setArchReg(const RegId &reg, RegVal val, ThreadID tid)
Definition: cpu.cc:1181
gem5::o3::CPU::isThreadExiting
bool isThreadExiting(ThreadID tid) const
Is the thread trying to exit?
Definition: cpu.cc:1478
gem5::o3::CPU::threadExitEvent
EventFunctionWrapper threadExitEvent
The exit event used for terminating all ready-to-exit threads.
Definition: cpu.hh:123
gem5::statistics::Counter
double Counter
All counters are of 64-bit values.
Definition: types.hh:47
gem5::ActivityRecorder
ActivityRecorder helper class that informs the CPU if it can switch over to being idle or not.
Definition: activity.hh:53
gem5::o3::CPU::isDraining
bool isDraining() const
Is the CPU draining?
Definition: cpu.hh:236
free_list.hh
gem5::statistics::Group
Statistics container.
Definition: group.hh:93
gem5::o3::CPU::readMiscReg
RegVal readMiscReg(int misc_reg, ThreadID tid)
Reads a misc.
Definition: cpu.cc:1020
gem5::InstSeqNum
uint64_t InstSeqNum
Definition: inst_seq.hh:40
gem5::PhysRegId
Physical register ID.
Definition: reg_class.hh:245
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::o3::CPU::SwitchedOut
@ SwitchedOut
Definition: cpu.hh:108
gem5::o3::CPU::CPUStats::fpRegfileReads
statistics::Scalar fpRegfileReads
Definition: cpu.hh:603
gem5::o3::CPU::exitingThreads
std::unordered_map< ThreadID, bool > exitingThreads
This is a list of threads that are trying to exit.
Definition: cpu.hh:440
gem5::o3::LSQ::pushRequest
Fault pushRequest(const DynInstPtr &inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector< bool > &byte_enable)
Definition: lsq.cc:783
gem5::Event::squash
void squash()
Squash the current event.
Definition: eventq.hh:472
gem5::o3::LSQ::getDataPort
RequestPort & getDataPort()
Definition: lsq.hh:892
decode.hh
gem5::o3::CPU::scoreboard
Scoreboard scoreboard
Integer Register Scoreboard.
Definition: cpu.hh:443
gem5::MipsISA::vaddr
vaddr
Definition: pra_constants.hh:278
gem5::PCStateBase
Definition: pcstate.hh:57
gem5::o3::IEW::ldstQueue
LSQ ldstQueue
Load / store queue.
Definition: iew.hh:358
gem5::o3::CPU::commit
Commit commit
The commit stage.
Definition: cpu.hh:415
std::list
STL list class.
Definition: stl.hh:51
gem5::o3::CPU::haltContext
void haltContext(ThreadID tid) override
Remove Thread from Active Threads List && Remove Thread Context from CPU.
Definition: cpu.cc:659
gem5::AtomicOpFunctorPtr
std::unique_ptr< AtomicOpFunctor > AtomicOpFunctorPtr
Definition: amo.hh:242
gem5::o3::CPU::activityRec
ActivityRecorder activityRec
The activity recorder; used to tell if the CPU has any activity remaining or if it can go to idle and...
Definition: cpu.hh:482
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::ActivityRecorder::deactivateStage
void deactivateStage(const int idx)
Deactivates a stage.
Definition: activity.cc:108
limits.hh
gem5::o3::CPU::activateContext
void activateContext(ThreadID tid) override
Add Thread to Active Threads List.
Definition: cpu.cc:601
gem5::o3::CPU::tick
void tick()
Ticks CPU, calling tick() on each stage, and checking the overall activity to see if the CPU should d...
Definition: cpu.cc:449
gem5::o3::CPU::getArchReg
RegVal getArchReg(const RegId &reg, ThreadID tid)
Architectural register accessors.
Definition: cpu.cc:1160
gem5::o3::ROB
ROB class.
Definition: rob.hh:72
gem5::Checker
Templated Checker class.
Definition: cpu.hh:445
gem5::o3::CPU::startup
void startup() override
Definition: cpu.cc:525
scoreboard.hh
gem5::o3::CPU::CPUStats::CPUStats
CPUStats(CPU *cpu)
Definition: cpu.cc:321
gem5::o3::CPU::isa
std::vector< TheISA::ISA * > isa
Definition: cpu.hh:445
gem5::o3::CPU::Halted
@ Halted
Definition: cpu.hh:106
gem5::DrainState::Draining
@ Draining
Draining buffers pending serialization/handover.
gem5::o3::CPU::instDone
void instDone(ThreadID tid, const DynInstPtr &inst)
Function to tell the CPU that an instruction has completed.
Definition: cpu.cc:1222
gem5::Event::scheduled
bool scheduled() const
Determine if the current event is scheduled.
Definition: eventq.hh:465
gem5::ThreadID
int16_t ThreadID
Thread index/ID type.
Definition: types.hh:235
gem5::o3::CPU::init
void init() override
Initialize the CPU.
Definition: cpu.cc:507
gem5::RegId
Register ID: describe an architectural register with its class and index.
Definition: reg_class.hh:126
panic
#define panic(...)
This implements a cprintf based panic() function.
Definition: logging.hh:178
gem5::o3::UnifiedRenameMap
Unified register rename map for all classes of registers.
Definition: rename_map.hh:168
gem5::o3::CPU::removeFrontInst
void removeFrontInst(const DynInstPtr &inst)
Remove an instruction from the front end of the list.
Definition: cpu.cc:1241
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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