gem5  v21.1.0.2
reset_stim.h
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20 /*****************************************************************************
21 
22  reset_stim.h --
23 
24  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
25 
26  *****************************************************************************/
27 
28 /*****************************************************************************
29 
30  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
31  changes you are making here.
32 
33  Name, Affiliation, Date:
34  Description of Modification:
35 
36  *****************************************************************************/
37 
38 #include "define.h"
39 
40 /******************************************************************************/
41 /*************************** reset_stim Function **********************/
42 /******************************************************************************/
43 bool_vector8 mem [LIMIT + 1]; // Stimulus input memory
44 
45 SC_MODULE( RESET_STIM )
46 {
47  SC_HAS_PROCESS( RESET_STIM );
48 
49  sc_in_clk clk;
50 
51  /*** Input and Output Ports ***/
52  sc_signal<bool>& ready;
53  sc_signal<bool>& reset;
54  sc_signal<int>& addr;
55 
56  /*** Constructor ***/
57  RESET_STIM ( sc_module_name NAME,
58  sc_clock& TICK_N,
59  sc_signal<bool>& READY,
60  sc_signal<bool>& RESET,
61  sc_signal<int>& ADDR )
62 
63  :
64  ready (READY),
65  reset (RESET),
66  addr (ADDR)
67 
68  {
69  clk (TICK_N);
70  SC_CTHREAD( entry, clk.neg() );
71  }
72 
73  /*** Call to Process Functionality ***/
74  void entry();
75 
76 };
77 
78 void
79 RESET_STIM::entry()
80 {
81 
82 // LOAD MEMORY WITH DATA AT TIME ZERO
83 
84  ifstream stimulus ("add_chain/add_chain.dat");
85  char buffer[WIDTH+1];
86 
87  for(int i=1; i < LIMIT+1; i++) {
88  stimulus >> buffer;
89  mem[i] = buffer;
90  }
91 
92  stimulus.close();
93 
94 // INITIALIZE reset AND addr, THEN REMOVE RESET AFTER 2 CLOCK CYCLES
95 
96  reset.write(0); // reset = 0
97  addr.write(1); // addr = 1
98  wait(2);
99 
100  reset.write(1); // reset = 1
101  wait();
102 
103 // WAIT FOR LAST MEMORY ADDRESS, THEN 3 CLOCKS, THEN STOP SIMULATION
104 
105  // do { wait(); } while (addr == LIMIT);
106  do { wait(); } while (!(addr == LIMIT));
107  wait(LATENCY);
108  do { wait(); } while (ready != 1);
109  sc_stop();
110  halt();
111 }
LIMIT
#define LIMIT
Definition: define.h:40
gem5::ArmISA::i
Bitfield< 7 > i
Definition: misc_types.hh:66
sc_core::sc_stop
void sc_stop()
Definition: sc_main.cc:103
LATENCY
#define LATENCY
Definition: define.h:42
gem5::statistics::reset
void reset()
Definition: statistics.cc:304
gem5::MipsISA::halt
Bitfield< 26 > halt
Definition: dt_constants.hh:47
sc_core::sc_in_clk
sc_in< bool > sc_in_clk
Definition: sc_clock.hh:116
WIDTH
#define WIDTH
Definition: define.h:41
define.h
mem
bool_vector8 mem[LIMIT+1]
Definition: reset_stim.h:43
sc_core::wait
void wait()
Definition: sc_module.cc:653
SC_MODULE
SC_MODULE(RESET_STIM)
Definition: reset_stim.h:45
SC_HAS_PROCESS
#define SC_HAS_PROCESS(name)
Definition: sc_module.hh:298
bool_vector8
sc_bv< 8 > bool_vector8
Definition: common.h:45
SC_CTHREAD
#define SC_CTHREAD(name, clk)
Definition: sc_module.hh:320
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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