gem5  v22.0.0.2
types.hh
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37 
38 #ifndef __ARCH_X86_TYPES_HH__
39 #define __ARCH_X86_TYPES_HH__
40 
41 #include <cstdint>
42 #include <functional>
43 #include <iostream>
44 
45 #include "arch/x86/pcstate.hh"
46 #include "base/bitunion.hh"
47 #include "base/cprintf.hh"
48 
49 namespace gem5
50 {
51 
52 namespace X86ISA
53 {
54 
55 //This really determines how many bytes are passed to the decoder.
56 typedef uint64_t MachInst;
57 
59 {
71  Rep,
76 };
77 
78 BitUnion8(LegacyPrefixVector)
79  Bitfield<7, 4> decodeVal;
80  Bitfield<7> repne;
81  Bitfield<6> rep;
82  Bitfield<5> lock;
83  Bitfield<4> op;
84  Bitfield<3> addr;
85  //There can be only one segment override, so they share the
86  //first 3 bits in the legacyPrefixes bitfield.
87  Bitfield<2,0> seg;
88 EndBitUnion(LegacyPrefixVector)
89 
90 BitUnion8(ModRM)
91  Bitfield<7,6> mod;
92  Bitfield<5,3> reg;
93  Bitfield<2,0> rm;
94 EndBitUnion(ModRM)
95 
96 BitUnion8(Sib)
97  Bitfield<7,6> scale;
98  Bitfield<5,3> index;
99  Bitfield<2,0> base;
100 EndBitUnion(Sib)
101 
102 BitUnion8(Rex)
103  //This bit doesn't mean anything according to the ISA, but in
104  //this implementation, it being set means an REX prefix was present.
105  Bitfield<6> present;
106  Bitfield<3> w;
107  Bitfield<2> r;
108  Bitfield<1> x;
109  Bitfield<0> b;
110 EndBitUnion(Rex)
111 
112 BitUnion8(Vex2Of3)
113  // Inverted bits from the REX prefix.
114  Bitfield<7> r;
115  Bitfield<6> x;
116  Bitfield<5> b;
117  // Selector for what would be two or three byte opcode types.
118  Bitfield<4, 0> m;
119 EndBitUnion(Vex2Of3)
120 
121 BitUnion8(Vex3Of3)
122  // Bit from the REX prefix.
123  Bitfield<7> w;
124  // Inverted extra register index.
125  Bitfield<6, 3> v;
126  // Vector length specifier.
127  Bitfield<2> l;
128  // Implied 66, F2, or F3 opcode prefix.
129  Bitfield<1, 0> p;
130 EndBitUnion(Vex3Of3)
131 
132 BitUnion8(Vex2Of2)
133  // Inverted bit from the REX prefix.
134  Bitfield<7> r;
135  // Inverted extra register index.
136  Bitfield<6, 3> v;
137  // Vector length specifier
138  Bitfield<2> l;
139  // Implied 66, F2, or F3 opcode prefix.
140  Bitfield<1, 0> p;
141 EndBitUnion(Vex2Of2)
142 
143 BitUnion8(VexInfo)
144  // Extra register index.
145  Bitfield<6, 3> v;
146  // Vector length specifier.
147  Bitfield<2> l;
148  // Whether the VEX prefix was used.
149  Bitfield<0> present;
150 EndBitUnion(VexInfo)
151 
152 enum OpcodeType
153 {
154  BadOpcode,
155  OneByteOpcode,
156  TwoByteOpcode,
157  ThreeByte0F38Opcode,
158  ThreeByte0F3AOpcode,
159 };
160 
161 static inline const char *
163 {
164  switch (type) {
165  case BadOpcode:
166  return "bad";
167  case OneByteOpcode:
168  return "one byte";
169  case TwoByteOpcode:
170  return "two byte";
171  case ThreeByte0F38Opcode:
172  return "three byte 0f38";
173  case ThreeByte0F3AOpcode:
174  return "three byte 0f3a";
175  default:
176  return "unrecognized!";
177  }
178 }
179 
180 BitUnion8(Opcode)
181  Bitfield<7,3> top5;
182  Bitfield<2,0> bottom3;
183 EndBitUnion(Opcode)
184 
186  Bitfield<3> mode;
187  Bitfield<2,0> submode;
189 
190 BitUnion8(OperatingModeAndCPL)
191  Bitfield<5,4> cpl;
192  Bitfield<3> mode;
193  Bitfield<2,0> submode;
194 EndBitUnion(OperatingModeAndCPL)
195 
196 enum X86Mode
197 {
198  LongMode,
199  LegacyMode
200 };
201 
203 {
209 };
210 
211 //The intermediate structure used by the x86 decoder.
213 {
214  void reset() { memset(static_cast<void *>(this), 0, sizeof(*this)); }
215 
216  //Prefixes
217  LegacyPrefixVector legacy;
218  Rex rex;
219  VexInfo vex;
220 
221  //This holds all of the bytes of the opcode
222  struct
223  {
224  OpcodeType type;
225  //The main opcode byte. The highest addressed byte in the opcode.
226  Opcode op;
227  } opcode;
228  //Modifier bytes
229  ModRM modRM;
230  Sib sib;
231  //Immediate fields
232  uint64_t immediate;
233  uint64_t displacement;
234 
235  //The effective operand size.
236  uint8_t opSize;
237  //The effective address size.
238  uint8_t addrSize;
239  //The effective stack size.
240  uint8_t stackSize;
241  //The size of the displacement
242  uint8_t dispSize;
243 
244  //Mode information
245  OperatingModeAndCPL mode;
246 };
247 
248 inline static std::ostream &
249 operator << (std::ostream &os, const ExtMachInst &emi)
250 {
251  ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
252  "vex/xop = %#x,\n\t"
253  "op = {\n\t\ttype = %s,\n\t\top = %#x,\n\t\t},\n\t"
254  "modRM = %#x,\n\tsib = %#x,\n\t"
255  "immediate = %#x,\n\tdisplacement = %#x\n\t"
256  "dispSize = %d}\n",
257  (uint8_t)emi.legacy, (uint8_t)emi.rex,
258  (uint8_t)emi.vex,
259  opcodeTypeToStr(emi.opcode.type), (uint8_t)emi.opcode.op,
260  (uint8_t)emi.modRM, (uint8_t)emi.sib,
261  emi.immediate, emi.displacement, emi.dispSize);
262  return os;
263 }
264 
265 inline static bool
266 operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
267 {
268  if (emi1.legacy != emi2.legacy)
269  return false;
270  if (emi1.rex != emi2.rex)
271  return false;
272  if (emi1.vex != emi2.vex)
273  return false;
274  if (emi1.opcode.type != emi2.opcode.type)
275  return false;
276  if (emi1.opcode.op != emi2.opcode.op)
277  return false;
278  if (emi1.modRM != emi2.modRM)
279  return false;
280  if (emi1.sib != emi2.sib)
281  return false;
282  if (emi1.immediate != emi2.immediate)
283  return false;
284  if (emi1.displacement != emi2.displacement)
285  return false;
286  if (emi1.mode != emi2.mode)
287  return false;
288  if (emi1.opSize != emi2.opSize)
289  return false;
290  if (emi1.addrSize != emi2.addrSize)
291  return false;
292  if (emi1.stackSize != emi2.stackSize)
293  return false;
294  if (emi1.dispSize != emi2.dispSize)
295  return false;
296  return true;
297 }
298 
299 } // namespace X86ISA
300 
301 // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR
302 // and UNSERIALIZE_SCALAR.
303 template <>
304 void paramOut(CheckpointOut &cp, const std::string &name,
305  const X86ISA::ExtMachInst &machInst);
306 template <>
307 void paramIn(CheckpointIn &cp, const std::string &name,
308  X86ISA::ExtMachInst &machInst);
309 
310 } // namespace gem5
311 
312 namespace std
313 {
314 
315 template<>
317 {
318  size_t
320  {
321  return (((uint64_t)emi.legacy << 48) |
322  ((uint64_t)emi.rex << 40) |
323  ((uint64_t)emi.vex << 32) |
324  ((uint64_t)emi.modRM << 24) |
325  ((uint64_t)emi.sib << 16) |
326  ((uint64_t)emi.opcode.type << 8) |
327  ((uint64_t)emi.opcode.op)) ^
328  emi.immediate ^ emi.displacement ^
329  emi.mode ^
330  emi.opSize ^ emi.addrSize ^
331  emi.stackSize ^ emi.dispSize;
332  };
333 };
334 
335 } // namespace std
336 
337 #endif // __ARCH_X86_TYPES_HH__
gem5::X86ISA::Repne
@ Repne
Definition: types.hh:72
gem5::X86ISA::FSOverride
@ FSOverride
Definition: types.hh:65
pcstate.hh
gem5::X86ISA::ExtMachInst::op
Opcode op
Definition: types.hh:226
gem5::X86ISA::Rep
@ Rep
Definition: types.hh:71
std::hash< gem5::X86ISA::ExtMachInst >::operator()
size_t operator()(const gem5::X86ISA::ExtMachInst &emi) const
Definition: types.hh:319
gem5::X86ISA::x
Bitfield< 1 > x
Definition: types.hh:108
gem5::X86ISA::rm
Bitfield< 2, 0 > rm
Definition: types.hh:93
gem5::X86ISA::cpl
Bitfield< 5, 4 > cpl
Definition: misc.hh:580
gem5::X86ISA::ESOverride
@ ESOverride
Definition: types.hh:61
gem5::X86ISA::Vex2Prefix
@ Vex2Prefix
Definition: types.hh:73
gem5::X86ISA::mode
Bitfield< 3 > mode
Definition: types.hh:192
gem5::SparcISA::ExtMachInst
uint64_t ExtMachInst
Definition: types.hh:42
gem5::X86ISA::CSOverride
@ CSOverride
Definition: types.hh:62
gem5::X86ISA::rep
Bitfield< 6 > rep
Definition: types.hh:81
gem5::X86ISA::ExtMachInst::modRM
ModRM modRM
Definition: types.hh:229
gem5::X86ISA::scale
scale
Definition: types.hh:97
gem5::X86ISA::MachInst
uint64_t MachInst
Definition: types.hh:56
gem5::X86ISA::SSOverride
@ SSOverride
Definition: types.hh:63
gem5::X86ISA::mod
mod
Definition: types.hh:91
gem5::X86ISA::ExtMachInst::opSize
uint8_t opSize
Definition: types.hh:236
gem5::X86ISA::NoOverride
@ NoOverride
Definition: types.hh:60
gem5::X86ISA::v
Bitfield< 6, 3 > v
Definition: types.hh:125
gem5::X86ISA::decodeVal
decodeVal
Definition: types.hh:79
gem5::X86ISA::XopPrefix
@ XopPrefix
Definition: types.hh:75
gem5::X86ISA::b
Bitfield< 54 > b
Definition: misc.hh:919
gem5::X86ISA::lock
Bitfield< 5 > lock
Definition: types.hh:82
gem5::X86ISA::AddressSizeOverride
@ AddressSizeOverride
Definition: types.hh:69
gem5::X86ISA::l
Bitfield< 53 > l
Definition: misc.hh:920
gem5::X86ISA::ExtMachInst::stackSize
uint8_t stackSize
Definition: types.hh:240
gem5::X86ISA::GSOverride
@ GSOverride
Definition: types.hh:66
gem5::X86ISA::base
Bitfield< 51, 12 > base
Definition: pagetable.hh:141
gem5::X86ISA::Virtual8086Mode
@ Virtual8086Mode
Definition: types.hh:207
gem5::X86ISA::SixtyFourBitMode
@ SixtyFourBitMode
Definition: types.hh:204
gem5::X86ISA::ExtMachInst::mode
OperatingModeAndCPL mode
Definition: types.hh:245
gem5::X86ISA::OperandSizeOverride
@ OperandSizeOverride
Definition: types.hh:68
gem5::X86ISA::top5
top5
Definition: types.hh:181
gem5::ccprintf
void ccprintf(cp::Print &print)
Definition: cprintf.hh:130
gem5::X86ISA::X86SubMode
X86SubMode
Definition: types.hh:202
gem5::X86ISA::ExtMachInst::reset
void reset()
Definition: types.hh:214
gem5::X86ISA::ExtMachInst::rex
Rex rex
Definition: types.hh:218
gem5::X86ISA::present
Bitfield< 7 > present
Definition: misc.hh:992
gem5::X86ISA::ExtMachInst::type
OpcodeType type
Definition: types.hh:224
gem5::X86ISA::r
Bitfield< 41 > r
Definition: misc.hh:934
gem5::X86ISA::DSOverride
@ DSOverride
Definition: types.hh:64
gem5::X86ISA::ExtMachInst::legacy
LegacyPrefixVector legacy
Definition: types.hh:217
gem5::X86ISA::ProtectedMode
@ ProtectedMode
Definition: types.hh:206
gem5::X86ISA::Prefixes
Prefixes
Definition: types.hh:58
gem5::X86ISA::BitUnion8
BitUnion8(LegacyPrefixVector) Bitfield< 7
gem5::X86ISA::ExtMachInst::vex
VexInfo vex
Definition: types.hh:219
gem5::X86ISA::operator==
static bool operator==(const ExtMachInst &emi1, const ExtMachInst &emi2)
Definition: types.hh:266
gem5::X86ISA::m
Bitfield< 4, 0 > m
Definition: types.hh:118
gem5::X86ISA::ExtMachInst::addrSize
uint8_t addrSize
Definition: types.hh:238
bitunion.hh
gem5::X86ISA::type
type
Definition: misc.hh:727
gem5::X86ISA::submode
Bitfield< 3, 1 > submode
Definition: misc.hh:579
cprintf.hh
gem5::X86ISA::w
Bitfield< 1 > w
Definition: pagetable.hh:150
gem5::X86ISA::RexPrefix
@ RexPrefix
Definition: types.hh:67
name
const std::string & name()
Definition: trace.cc:49
gem5::X86ISA::ExtMachInst::dispSize
uint8_t dispSize
Definition: types.hh:242
gem5::X86ISA::ExtMachInst::sib
Sib sib
Definition: types.hh:230
gem5::X86ISA::reg
Bitfield< 5, 3 > reg
Definition: types.hh:92
gem5::X86ISA::CompatabilityMode
@ CompatabilityMode
Definition: types.hh:205
gem5::X86ISA::ExtMachInst
Definition: types.hh:212
gem5::X86ISA::ExtMachInst::displacement
uint64_t displacement
Definition: types.hh:233
gem5::X86ISA::bottom3
Bitfield< 2, 0 > bottom3
Definition: types.hh:182
gem5::X86ISA::ExtMachInst::immediate
uint64_t immediate
Definition: types.hh:232
gem5::X86ISA::Vex3Prefix
@ Vex3Prefix
Definition: types.hh:74
gem5::paramOut
void paramOut(CheckpointOut &cp, const std::string &name, ExtMachInst const &machInst)
Definition: types.cc:40
std
Overload hash function for BasicBlockRange type.
Definition: misc.hh:2388
gem5::X86ISA::os
Bitfield< 17 > os
Definition: misc.hh:803
gem5::X86ISA::index
Bitfield< 5, 3 > index
Definition: types.hh:98
gem5::X86ISA::operator<<
static std::ostream & operator<<(std::ostream &os, const ExtMachInst &emi)
Definition: types.hh:249
gem5::paramIn
void paramIn(CheckpointIn &cp, const std::string &name, ExtMachInst &machInst)
Definition: types.cc:72
gem5::X86ISA::seg
Bitfield< 2, 0 > seg
Definition: types.hh:87
gem5::X86ISA::opcodeTypeToStr
static const char * opcodeTypeToStr(OpcodeType type)
Definition: types.hh:162
gem5::X86ISA::RealMode
@ RealMode
Definition: types.hh:208
gem5::X86ISA::ExtMachInst::opcode
struct gem5::X86ISA::ExtMachInst::@28 opcode
gem5::X86ISA::p
Bitfield< 0 > p
Definition: pagetable.hh:151
gem5::CheckpointOut
std::ostream CheckpointOut
Definition: serialize.hh:66
gem5::X86ISA::Lock
@ Lock
Definition: types.hh:70
gem5
Reference material can be found at the JEDEC website: UFS standard http://www.jedec....
Definition: gpu_translation_state.hh:37
gem5::X86ISA::repne
Bitfield< 7 > repne
Definition: types.hh:80
gem5::X86ISA::EndBitUnion
EndBitUnion(TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
gem5::X86ISA::op
Bitfield< 4 > op
Definition: types.hh:83
gem5::ArmISA::OperatingMode
OperatingMode
Definition: types.hh:279
gem5::X86ISA::addr
Bitfield< 3 > addr
Definition: types.hh:84

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