gem5  v21.1.0.2
Namespaces | Classes | Typedefs | Enumerations | Functions | Variables
gem5::X86ISA Namespace Reference

This is exposed globally, independent of the ISA. More...

Namespaces

 ACPI
 
 auxv
 
 condition_tests
 
 delivery_mode
 
 intelmp
 
 smbios
 

Classes

struct  AddrOp
 
class  AlignmentCheck
 
class  BoundRange
 
class  Breakpoint
 
class  Cmos
 
struct  CpuidResult
 
struct  CrOp
 
struct  CrRegIndex
 
struct  CtrlRegIndex
 
struct  DataHiOp
 
struct  DataLowOp
 
struct  DataOp
 
struct  DbgOp
 
struct  DbgRegIndex
 
class  DebugException
 
class  Decoder
 
struct  DestOp
 
class  DeviceNotAvailable
 
class  DivideError
 
class  DoubleFault
 
class  E820Entry
 
class  E820Table
 
struct  EmulEnv
 
class  EmuLinux
 
class  ExternalInterrupt
 
struct  ExtMachInst
 
struct  FaultOp
 
struct  FloatOp
 
struct  FoldedOp
 
class  FpOp
 
struct  FpRegIndex
 
class  FsLinux
 
class  FsWorkload
 
class  GeneralProtection
 
struct  GpRegIndex
 Classes for register indices passed to instruction constructors. More...
 
class  GpuTLB
 
class  I386Process
 
class  I8042
 
class  I82094AA
 
class  I8237
 
class  I8254
 
class  I8259
 
struct  Imm64Op
 
struct  Imm8Op
 
class  InitInterrupt
 
class  InstOperands
 
class  Interrupts
 
struct  IntOp
 
class  IntRequestPort
 
class  IntResponsePort
 
class  InvalidOpcode
 
class  InvalidTSS
 
class  ISA
 
class  LdStFpOp
 Base class for load ops using one FP register. More...
 
class  LdStOp
 Base class for load ops using one integer register. More...
 
class  LdStSplitOp
 Base class for load and store ops using two registers, we will call them split ops for this reason. More...
 
class  LongModePTE
 
class  MachineCheck
 
class  MacroopBase
 
class  MediaOpBase
 
class  MemNoDataOp
 Base class for the tia microop which has no destination register. More...
 
class  MemOp
 Base class for memory ops. More...
 
class  MicroCondBase
 
class  MicroDebug
 
class  MicroHalt
 
struct  MiscOp
 
class  MMU
 
class  NonMaskableInterrupt
 
class  OverflowTrap
 
class  PageFault
 
class  PCState
 
class  RegOpBase
 
class  RemoteGDB
 
class  SecurityException
 
class  SegDescriptorLimit
 
class  SegmentNotPresent
 
struct  SegOp
 
struct  SegRegIndex
 
class  SIMDFloatingPointFault
 
class  SoftwareInterrupt
 
class  Speaker
 
struct  Src1Op
 
struct  Src2Op
 
class  StackFault
 
class  StackTrace
 
class  StartupInterrupt
 
class  SystemManagementInterrupt
 
class  TLB
 
struct  TlbEntry
 
class  UnimpInstFault
 
struct  UpcOp
 
class  Walker
 
class  X86_64Process
 
class  X86Abort
 
class  X86Fault
 
class  X86FaultBase
 
class  X86Interrupt
 
class  X86MicroopBase
 
class  X86Process
 
class  X86StaticInst
 Base class for all X86 static instructions. More...
 
class  X86Trap
 
class  X87FpExceptionPending
 

Typedefs

using FoldedDestOp = FoldedOp< DestOp >
 
using DbgDestOp = DbgOp< DestOp >
 
using CrDestOp = CrOp< DestOp >
 
using SegDestOp = SegOp< DestOp >
 
using MiscDestOp = MiscOp< DestOp >
 
using FloatDestOp = FloatOp< DestOp >
 
using IntDestOp = IntOp< DestOp >
 
using FoldedSrc1Op = FoldedOp< Src1Op >
 
using DbgSrc1Op = DbgOp< Src1Op >
 
using CrSrc1Op = CrOp< Src1Op >
 
using SegSrc1Op = SegOp< Src1Op >
 
using MiscSrc1Op = MiscOp< Src1Op >
 
using FloatSrc1Op = FloatOp< Src1Op >
 
using IntSrc1Op = IntOp< Src1Op >
 
using FoldedSrc2Op = FoldedOp< Src2Op >
 
using FloatSrc2Op = FloatOp< Src2Op >
 
using IntSrc2Op = IntOp< Src2Op >
 
using FoldedDataOp = FoldedOp< DataOp >
 
using FloatDataOp = FloatOp< DataOp >
 
using FoldedDataHiOp = FoldedOp< DataHiOp >
 
using FoldedDataLowOp = FoldedOp< DataLowOp >
 
template<typename ... Operands>
using RegOpT = InstOperands< RegOpBase, Operands... >
 
typedef MsrMap::value_type MsrVal
 
typedef std::unordered_map< Addr, MiscRegIndexMsrMap
 
typedef uint64_t MachInst
 
using VecElem = ::gem5::DummyVecElem
 
using VecRegContainer = ::gem5::DummyVecRegContainer
 
using VecPredRegContainer = ::gem5::DummyVecPredRegContainer
 

Enumerations

enum  StandardCpuidFunction {
  VendorAndLargestStdFunc, FamilyModelStepping, CacheAndTLB, SerialNumber,
  CacheParams, MonitorMwait, ThermalPowerMgmt, ExtendedFeatures,
  NumStandardCpuidFuncs
}
 
enum  ExtendedCpuidFunctions {
  VendorAndLargestExtFunc, FamilyModelSteppingBrandFeatures, NameString1, NameString2,
  NameString3, L1CacheAndTLB, L2L3CacheAndL2TLB, APMInfo,
  LongModeAddressSize, NumExtendedCpuidFuncs
}
 
enum  SizeType {
  NoImm, NI = NoImm, ByteImm, BY = ByteImm,
  WordImm, WO = WordImm, DWordImm, DW = DWordImm,
  QWordImm, QW = QWordImm, OWordImm, OW = OWordImm,
  VWordImm, VW = VWordImm, ZWordImm, ZW = ZWordImm,
  Enter, EN = Enter, Pointer, PO = Pointer
}
 
enum  MediaFlag { MediaMultHiOp = 1, MediaSignedOp = 64, MediaScalarOp = 128 }
 
enum  FlagBit { CPL0FlagBit = 1, AddrSizeFlagBit = 2, StoreCheck = 4 }
 
enum  ApicRegIndex {
  APIC_ID, APIC_VERSION, APIC_TASK_PRIORITY, APIC_ARBITRATION_PRIORITY,
  APIC_PROCESSOR_PRIORITY, APIC_EOI, APIC_LOGICAL_DESTINATION, APIC_DESTINATION_FORMAT,
  APIC_SPURIOUS_INTERRUPT_VECTOR, APIC_IN_SERVICE_BASE, APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16, APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16,
  APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16, APIC_INTERRUPT_COMMAND_LOW, APIC_INTERRUPT_COMMAND_HIGH, APIC_LVT_TIMER,
  APIC_LVT_THERMAL_SENSOR, APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, APIC_LVT_LINT0, APIC_LVT_LINT1,
  APIC_LVT_ERROR, APIC_INITIAL_COUNT, APIC_CURRENT_COUNT, APIC_DIVIDE_CONFIGURATION,
  APIC_INTERNAL_STATE, NUM_APIC_REGS
}
 
enum  CCRegIndex {
  CCREG_ZAPS, CCREG_CFOF, CCREG_DF, CCREG_ECF,
  CCREG_EZF, NUM_CCREGS
}
 
enum  FloatRegIndex {
  FLOATREG_MMX_BASE, FLOATREG_FPR_BASE = FLOATREG_MMX_BASE, FLOATREG_MMX0 = FLOATREG_MMX_BASE, FLOATREG_MMX1,
  FLOATREG_MMX2, FLOATREG_MMX3, FLOATREG_MMX4, FLOATREG_MMX5,
  FLOATREG_MMX6, FLOATREG_MMX7, FLOATREG_FPR0 = FLOATREG_FPR_BASE, FLOATREG_FPR1,
  FLOATREG_FPR2, FLOATREG_FPR3, FLOATREG_FPR4, FLOATREG_FPR5,
  FLOATREG_FPR6, FLOATREG_FPR7, FLOATREG_XMM_BASE = FLOATREG_MMX_BASE + NumMMXRegs, FLOATREG_XMM0_LOW = FLOATREG_XMM_BASE,
  FLOATREG_XMM0_HIGH, FLOATREG_XMM1_LOW, FLOATREG_XMM1_HIGH, FLOATREG_XMM2_LOW,
  FLOATREG_XMM2_HIGH, FLOATREG_XMM3_LOW, FLOATREG_XMM3_HIGH, FLOATREG_XMM4_LOW,
  FLOATREG_XMM4_HIGH, FLOATREG_XMM5_LOW, FLOATREG_XMM5_HIGH, FLOATREG_XMM6_LOW,
  FLOATREG_XMM6_HIGH, FLOATREG_XMM7_LOW, FLOATREG_XMM7_HIGH, FLOATREG_XMM8_LOW,
  FLOATREG_XMM8_HIGH, FLOATREG_XMM9_LOW, FLOATREG_XMM9_HIGH, FLOATREG_XMM10_LOW,
  FLOATREG_XMM10_HIGH, FLOATREG_XMM11_LOW, FLOATREG_XMM11_HIGH, FLOATREG_XMM12_LOW,
  FLOATREG_XMM12_HIGH, FLOATREG_XMM13_LOW, FLOATREG_XMM13_HIGH, FLOATREG_XMM14_LOW,
  FLOATREG_XMM14_HIGH, FLOATREG_XMM15_LOW, FLOATREG_XMM15_HIGH, FLOATREG_MICROFP_BASE = FLOATREG_XMM_BASE + 2 * NumXMMRegs,
  FLOATREG_MICROFP0 = FLOATREG_MICROFP_BASE, FLOATREG_MICROFP1, FLOATREG_MICROFP2, FLOATREG_MICROFP3,
  FLOATREG_MICROFP4, FLOATREG_MICROFP5, FLOATREG_MICROFP6, FLOATREG_MICROFP7,
  NUM_FLOATREGS = FLOATREG_MICROFP_BASE + NumMicroFpRegs
}
 
enum  CondFlagBit {
  CFBit = 1 << 0, PFBit = 1 << 2, ECFBit = 1 << 3, AFBit = 1 << 4,
  EZFBit = 1 << 5, ZFBit = 1 << 6, SFBit = 1 << 7, DFBit = 1 << 10,
  OFBit = 1 << 11
}
 
enum  RFLAGBit {
  TFBit = 1 << 8, IFBit = 1 << 9, NTBit = 1 << 14, RFBit = 1 << 16,
  VMBit = 1 << 17, ACBit = 1 << 18, VIFBit = 1 << 19, VIPBit = 1 << 20,
  IDBit = 1 << 21
}
 
enum  X87StatusBit {
  IEBit = 1 << 0, DEBit = 1 << 1, ZEBit = 1 << 2, OEBit = 1 << 3,
  UEBit = 1 << 4, PEBit = 1 << 5, StackFaultBit = 1 << 6, ErrSummaryBit = 1 << 7,
  CC0Bit = 1 << 8, CC1Bit = 1 << 9, CC2Bit = 1 << 10, CC3Bit = 1 << 14,
  BusyBit = 1 << 15
}
 
enum  MiscRegIndex {
  MISCREG_CR_BASE, MISCREG_CR0 = MISCREG_CR_BASE, MISCREG_CR1, MISCREG_CR2,
  MISCREG_CR3, MISCREG_CR4, MISCREG_CR5, MISCREG_CR6,
  MISCREG_CR7, MISCREG_CR8, MISCREG_CR9, MISCREG_CR10,
  MISCREG_CR11, MISCREG_CR12, MISCREG_CR13, MISCREG_CR14,
  MISCREG_CR15, MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, MISCREG_DR0 = MISCREG_DR_BASE, MISCREG_DR1,
  MISCREG_DR2, MISCREG_DR3, MISCREG_DR4, MISCREG_DR5,
  MISCREG_DR6, MISCREG_DR7, MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, MISCREG_M5_REG,
  MISCREG_TSC, MISCREG_MTRRCAP, MISCREG_SYSENTER_CS, MISCREG_SYSENTER_ESP,
  MISCREG_SYSENTER_EIP, MISCREG_MCG_CAP, MISCREG_MCG_STATUS, MISCREG_MCG_CTL,
  MISCREG_DEBUG_CTL_MSR, MISCREG_LAST_BRANCH_FROM_IP, MISCREG_LAST_BRANCH_TO_IP, MISCREG_LAST_EXCEPTION_FROM_IP,
  MISCREG_LAST_EXCEPTION_TO_IP, MISCREG_MTRR_PHYS_BASE_BASE, MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, MISCREG_MTRR_PHYS_BASE_1,
  MISCREG_MTRR_PHYS_BASE_2, MISCREG_MTRR_PHYS_BASE_3, MISCREG_MTRR_PHYS_BASE_4, MISCREG_MTRR_PHYS_BASE_5,
  MISCREG_MTRR_PHYS_BASE_6, MISCREG_MTRR_PHYS_BASE_7, MISCREG_MTRR_PHYS_BASE_END, MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
  MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, MISCREG_MTRR_PHYS_MASK_1, MISCREG_MTRR_PHYS_MASK_2, MISCREG_MTRR_PHYS_MASK_3,
  MISCREG_MTRR_PHYS_MASK_4, MISCREG_MTRR_PHYS_MASK_5, MISCREG_MTRR_PHYS_MASK_6, MISCREG_MTRR_PHYS_MASK_7,
  MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, MISCREG_MTRR_FIX_16K_80000, MISCREG_MTRR_FIX_16K_A0000,
  MISCREG_MTRR_FIX_4K_C0000, MISCREG_MTRR_FIX_4K_C8000, MISCREG_MTRR_FIX_4K_D0000, MISCREG_MTRR_FIX_4K_D8000,
  MISCREG_MTRR_FIX_4K_E0000, MISCREG_MTRR_FIX_4K_E8000, MISCREG_MTRR_FIX_4K_F0000, MISCREG_MTRR_FIX_4K_F8000,
  MISCREG_PAT, MISCREG_DEF_TYPE, MISCREG_MC_CTL_BASE, MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
  MISCREG_MC1_CTL, MISCREG_MC2_CTL, MISCREG_MC3_CTL, MISCREG_MC4_CTL,
  MISCREG_MC5_CTL, MISCREG_MC6_CTL, MISCREG_MC7_CTL, MISCREG_MC_CTL_END,
  MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, MISCREG_MC1_STATUS, MISCREG_MC2_STATUS,
  MISCREG_MC3_STATUS, MISCREG_MC4_STATUS, MISCREG_MC5_STATUS, MISCREG_MC6_STATUS,
  MISCREG_MC7_STATUS, MISCREG_MC_STATUS_END, MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
  MISCREG_MC1_ADDR, MISCREG_MC2_ADDR, MISCREG_MC3_ADDR, MISCREG_MC4_ADDR,
  MISCREG_MC5_ADDR, MISCREG_MC6_ADDR, MISCREG_MC7_ADDR, MISCREG_MC_ADDR_END,
  MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, MISCREG_MC1_MISC, MISCREG_MC2_MISC,
  MISCREG_MC3_MISC, MISCREG_MC4_MISC, MISCREG_MC5_MISC, MISCREG_MC6_MISC,
  MISCREG_MC7_MISC, MISCREG_MC_MISC_END, MISCREG_EFER = MISCREG_MC_MISC_END, MISCREG_STAR,
  MISCREG_LSTAR, MISCREG_CSTAR, MISCREG_SF_MASK, MISCREG_KERNEL_GS_BASE,
  MISCREG_TSC_AUX, MISCREG_PERF_EVT_SEL_BASE, MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, MISCREG_PERF_EVT_SEL1,
  MISCREG_PERF_EVT_SEL2, MISCREG_PERF_EVT_SEL3, MISCREG_PERF_EVT_SEL_END, MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
  MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, MISCREG_PERF_EVT_CTR1, MISCREG_PERF_EVT_CTR2, MISCREG_PERF_EVT_CTR3,
  MISCREG_PERF_EVT_CTR_END, MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, MISCREG_IORR_BASE_BASE, MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
  MISCREG_IORR_BASE1, MISCREG_IORR_BASE_END, MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
  MISCREG_IORR_MASK1, MISCREG_IORR_MASK_END, MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, MISCREG_TOP_MEM2,
  MISCREG_VM_CR, MISCREG_IGNNE, MISCREG_SMM_CTL, MISCREG_VM_HSAVE_PA,
  MISCREG_SEG_SEL_BASE, MISCREG_ES = MISCREG_SEG_SEL_BASE, MISCREG_CS, MISCREG_SS,
  MISCREG_DS, MISCREG_FS, MISCREG_GS, MISCREG_HS,
  MISCREG_TSL, MISCREG_TSG, MISCREG_LS, MISCREG_MS,
  MISCREG_TR, MISCREG_IDTR, MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
  MISCREG_CS_BASE, MISCREG_SS_BASE, MISCREG_DS_BASE, MISCREG_FS_BASE,
  MISCREG_GS_BASE, MISCREG_HS_BASE, MISCREG_TSL_BASE, MISCREG_TSG_BASE,
  MISCREG_LS_BASE, MISCREG_MS_BASE, MISCREG_TR_BASE, MISCREG_IDTR_BASE,
  MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, MISCREG_CS_EFF_BASE, MISCREG_SS_EFF_BASE,
  MISCREG_DS_EFF_BASE, MISCREG_FS_EFF_BASE, MISCREG_GS_EFF_BASE, MISCREG_HS_EFF_BASE,
  MISCREG_TSL_EFF_BASE, MISCREG_TSG_EFF_BASE, MISCREG_LS_EFF_BASE, MISCREG_MS_EFF_BASE,
  MISCREG_TR_EFF_BASE, MISCREG_IDTR_EFF_BASE, MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
  MISCREG_CS_LIMIT, MISCREG_SS_LIMIT, MISCREG_DS_LIMIT, MISCREG_FS_LIMIT,
  MISCREG_GS_LIMIT, MISCREG_HS_LIMIT, MISCREG_TSL_LIMIT, MISCREG_TSG_LIMIT,
  MISCREG_LS_LIMIT, MISCREG_MS_LIMIT, MISCREG_TR_LIMIT, MISCREG_IDTR_LIMIT,
  MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, MISCREG_CS_ATTR, MISCREG_SS_ATTR,
  MISCREG_DS_ATTR, MISCREG_FS_ATTR, MISCREG_GS_ATTR, MISCREG_HS_ATTR,
  MISCREG_TSL_ATTR, MISCREG_TSG_ATTR, MISCREG_LS_ATTR, MISCREG_MS_ATTR,
  MISCREG_TR_ATTR, MISCREG_IDTR_ATTR, MISCREG_X87_TOP, MISCREG_MXCSR,
  MISCREG_FCW, MISCREG_FSW, MISCREG_FTW, MISCREG_FTAG,
  MISCREG_FISEG, MISCREG_FIOFF, MISCREG_FOSEG, MISCREG_FOOFF,
  MISCREG_FOP, MISCREG_APIC_BASE, MISCREG_PCI_CONFIG_ADDRESS, NUM_MISCREGS
}
 
enum  SegmentRegIndex {
  SEGMENT_REG_ES, SEGMENT_REG_CS, SEGMENT_REG_SS, SEGMENT_REG_DS,
  SEGMENT_REG_FS, SEGMENT_REG_GS, SEGMENT_REG_HS, SEGMENT_REG_TSL,
  SEGMENT_REG_TSG, SEGMENT_REG_LS, SEGMENT_REG_MS, SYS_SEGMENT_REG_TR,
  SYS_SEGMENT_REG_IDTR, NUM_SEGMENTREGS
}
 
enum  Prefixes {
  NoOverride, ESOverride, CSOverride, SSOverride,
  DSOverride, FSOverride, GSOverride, RexPrefix,
  OperandSizeOverride, AddressSizeOverride, Lock, Rep,
  Repne, Vex2Prefix, Vex3Prefix, XopPrefix
}
 
enum  X86SubMode {
  SixtyFourBitMode, CompatabilityMode, ProtectedMode, Virtual8086Mode,
  RealMode
}
 

Functions

 GEM5_DEPRECATED_NAMESPACE (IntelMP, intelmp)
 
 GEM5_DEPRECATED_NAMESPACE (SMBios, smbios)
 
uint64_t stringToRegister (const char *str)
 
bool doCpuid (ThreadContext *tc, uint32_t function, uint32_t index, CpuidResult &result)
 
void installSegDesc (ThreadContext *tc, SegmentRegIndex seg, SegDescriptor desc, bool longmode)
 
 GEM5_DEPRECATED_NAMESPACE (ConditionTests, condition_tests)
 
ApicRegIndex decodeAddr (Addr paddr)
 
 BitUnion32 (TriggerIntMessage) Bitfield< 7
 
 EndBitUnion (TriggerIntMessage) GEM5_DEPRECATED_NAMESPACE(DeliveryMode
 
static PacketPtr buildIntTriggerPacket (int id, TriggerIntMessage message)
 
static void copyMiscRegs (ThreadContext *src, ThreadContext *dest)
 
SyscallReturn unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
 Target uname() handler. More...
 
SyscallReturn archPrctlFunc (SyscallDesc *desc, ThreadContext *tc, int code, uint64_t addr)
 
SyscallReturn setThreadArea32Func (SyscallDesc *desc, ThreadContext *tc, VPtr< UserDesc32 > userDesc)
 
 BitUnion32 (UserDescFlags) Bitfield< 0 > seg_32bit
 
 EndBitUnion (UserDescFlags) struct UserDesc32
 
static Fault initiateMemRead (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, unsigned dataSize, Request::Flags flags)
 Initiate a read from memory in timing mode. More...
 
static void getMem (PacketPtr pkt, uint64_t &mem, unsigned dataSize, Trace::InstRecord *traceData)
 
template<typename T , size_t N>
static void getPackedMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize)
 
template<size_t N>
static void getMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize, Trace::InstRecord *traceData)
 
static Fault readMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem, unsigned dataSize, Request::Flags flags)
 
template<typename T , size_t N>
static Fault readPackedMemAtomic (ExecContext *xc, Addr addr, std::array< uint64_t, N > &mem, unsigned flags)
 
template<size_t N>
static Fault readMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, Addr addr, std::array< uint64_t, N > &mem, unsigned dataSize, unsigned flags)
 
template<typename T , size_t N>
static Fault writePackedMem (ExecContext *xc, std::array< uint64_t, N > &mem, Addr addr, unsigned flags, uint64_t *res)
 
static Fault writeMemTiming (ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)
 
template<size_t N>
static Fault writeMemTiming (ExecContext *xc, Trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
 
static Fault writeMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)
 
template<size_t N>
static Fault writeMemAtomic (ExecContext *xc, Trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
 
 BitUnion64 (VAddr) Bitfield< 20
 
 EndBitUnion (VAddr) BitUnion64(PageTableEntry) Bitfield< 63 > nx
 
 EndBitUnion (PageTableEntry) template< int first
 
static ApicRegIndex APIC_IN_SERVICE (int index)
 
static ApicRegIndex APIC_TRIGGER_MODE (int index)
 
static ApicRegIndex APIC_INTERRUPT_REQUEST (int index)
 
 BitUnion32 (InterruptCommandRegLow) Bitfield< 7
 
 EndBitUnion (InterruptCommandRegLow) BitUnion32(InterruptCommandRegHigh) Bitfield< 31
 
static FloatRegIndex FLOATREG_MMX (int index)
 
static FloatRegIndex FLOATREG_FPR (int index)
 
static FloatRegIndex FLOATREG_XMM_LOW (int index)
 
static FloatRegIndex FLOATREG_XMM_HIGH (int index)
 
static FloatRegIndex FLOATREG_MICROFP (int index)
 
static FloatRegIndex FLOATREG_STACK (int index, int top)
 
 BitUnion64 (X86IntReg) Bitfield< 63
 
 EndBitUnion (X86IntReg) enum IntRegIndex
 
static IntRegIndex INTREG_MICRO (int index)
 
static IntRegIndex INTREG_FOLDED (int index, int foldBit)
 
static bool isValidMiscReg (int index)
 
static MiscRegIndex MISCREG_CR (int index)
 
static MiscRegIndex MISCREG_DR (int index)
 
static MiscRegIndex MISCREG_MTRR_PHYS_BASE (int index)
 
static MiscRegIndex MISCREG_MTRR_PHYS_MASK (int index)
 
static MiscRegIndex MISCREG_MC_CTL (int index)
 
static MiscRegIndex MISCREG_MC_STATUS (int index)
 
static MiscRegIndex MISCREG_MC_ADDR (int index)
 
static MiscRegIndex MISCREG_MC_MISC (int index)
 
static MiscRegIndex MISCREG_PERF_EVT_SEL (int index)
 
static MiscRegIndex MISCREG_PERF_EVT_CTR (int index)
 
static MiscRegIndex MISCREG_IORR_BASE (int index)
 
static MiscRegIndex MISCREG_IORR_MASK (int index)
 
static MiscRegIndex MISCREG_SEG_SEL (int index)
 
static MiscRegIndex MISCREG_SEG_BASE (int index)
 
static MiscRegIndex MISCREG_SEG_EFF_BASE (int index)
 
static MiscRegIndex MISCREG_SEG_LIMIT (int index)
 
static MiscRegIndex MISCREG_SEG_ATTR (int index)
 
 BitUnion64 (CCFlagBits) Bitfield< 11 > of
 A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode. More...
 
 EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id
 RFLAGS. More...
 
 EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode
 
 EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg
 Control registers. More...
 
 EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31
 
 EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51
 
 EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave
 
 EndBitUnion (CR4) BitUnion64(CR8) Bitfield< 3
 
 EndBitUnion (CR8) BitUnion64(DR6) Bitfield< 0 > b0
 
 EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0
 
 EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield< 7
 
 EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15
 SYSENTER configuration registers. More...
 
 EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31
 
 EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31
 
 EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield< 7
 Global machine check registers. More...
 
 EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv
 
 EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr
 
 EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield< 7
 
 EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid
 
 EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield< 7
 
 EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15
 Machine check. More...
 
 EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce
 
 EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31
 
 EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31
 
 EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield< 7
 
 EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde
 
 EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr
 
 EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v
 
 EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51
 
 EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd
 
 EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne
 
 EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss
 
 EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63
 Segment Selector. More...
 
 EndBitUnion (SegSelector) class SegDescriptorBase
 Segment Descriptors. More...
 
 BitUnion64 (SegDescriptor) Bitfield< 63
 
 SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData
 
 EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
 TSS Descriptor (long mode - 128 bits) the lower 64 bits. More...
 
 EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield< 1
 
 EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63
 
 EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63
 Long Mode Gate Descriptor. More...
 
 EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31
 
 EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51
 Descriptor-Table Registers. More...
 
const MsrMap msrMap (msrMapData, msrMapData+msrMapSize)
 
bool msrAddrToIndex (MiscRegIndex &regNum, Addr addr)
 Find and return the misc reg corresponding to an MSR address. More...
 
 BitUnion8 (LegacyPrefixVector) Bitfield< 7
 
 EndBitUnion (LegacyPrefixVector) BitUnion8(ModRM) Bitfield< 7
 
 EndBitUnion (ModRM) BitUnion8(Sib) Bitfield< 7
 
 EndBitUnion (Sib) BitUnion8(Rex) Bitfield< 6 > present
 
 EndBitUnion (Rex) BitUnion8(Vex2Of3) Bitfield< 7 > r
 
 EndBitUnion (Vex2Of3) BitUnion8(Vex3Of3) Bitfield< 7 > w
 
 EndBitUnion (Vex3Of3) BitUnion8(Vex2Of2) Bitfield< 7 > r
 
 EndBitUnion (Vex2Of2) BitUnion8(VexInfo) Bitfield< 6
 
 EndBitUnion (VexInfo) enum OpcodeType
 
static const char * opcodeTypeToStr (OpcodeType type)
 
 BitUnion8 (Opcode) Bitfield< 7
 
 EndBitUnion (Opcode) BitUnion8(OperatingMode) Bitfield< 3 > mode
 
 EndBitUnion (OperatingMode) enum X86Mode
 
static std::ostream & operator<< (std::ostream &os, const ExtMachInst &emi)
 
static bool operator== (const ExtMachInst &emi1, const ExtMachInst &emi2)
 
uint64_t getRFlags (ThreadContext *tc)
 Reconstruct the rflags register from the internal gem5 register state. More...
 
void setRFlags (ThreadContext *tc, uint64_t val)
 Set update the rflags register and internal gem5 state. More...
 
uint8_t convX87TagsToXTags (uint16_t ftw)
 Convert an x87 tag word to abridged tag format. More...
 
uint16_t convX87XTagsToTags (uint8_t ftwx)
 Convert an x87 xtag word to normal tags format. More...
 
uint16_t genX87Tags (uint16_t ftw, uint8_t top, int8_t spm)
 Generate and updated x87 tag register after a push/pop operation. More...
 
double loadFloat80 (const void *mem)
 Load an 80-bit float from memory and convert it to double. More...
 
void storeFloat80 (void *mem, double value)
 Convert and store a double as an 80-bit float. More...
 
static Addr x86IOAddress (const uint32_t port)
 
static Addr x86PciConfigAddress (const uint32_t addr)
 
static Addr x86LocalAPICAddress (const uint8_t id, const uint16_t addr)
 
static Addr x86InterruptAddress (const uint8_t id, const uint16_t addr)
 
template<class T >
PacketPtr buildIntPacket (Addr addr, T payload)
 

Variables

static const int nameStringSize = 48
 
static const char nameString [nameStringSize] = "Fake M5 x86_64 CPU"
 
const uint8_t CS = CSOverride
 
const uint8_t DS = DSOverride
 
const uint8_t ES = ESOverride
 
const uint8_t FS = FSOverride
 
const uint8_t GS = GSOverride
 
const uint8_t SS = SSOverride
 
const uint8_t OO = OperandSizeOverride
 
const uint8_t AO = AddressSizeOverride
 
const uint8_t LO = Lock
 
const uint8_t RE = Rep
 
const uint8_t RN = Repne
 
const uint8_t RX = RexPrefix
 
const uint8_t V2 = Vex2Prefix
 
const uint8_t V3 = Vex3Prefix
 
const StaticInstPtr badMicroop
 
 destination
 
Bitfield< 15, 8 > vector
 
Bitfield< 18, 16 > deliveryMode
 
Bitfield< 19 > destMode
 
Bitfield< 20 > level
 
Bitfield< 21 > trigger
 
 delivery_mode
 
static const Addr TriggerIntOffset = 0
 
const GEM5_VAR_USED Request::FlagsType SegmentFlagMask = mask(4)
 
const int FlagShift = 4
 
Bitfield< 2, 1 > contents
 
Bitfield< 3 > read_exec_only
 
Bitfield< 4 > limit_in_pages
 
Bitfield< 5 > seg_not_present
 
Bitfield< 6 > useable
 
const Addr PageShift = 12
 
const Addr PageBytes = 1ULL << PageShift
 
 longl1
 
Bitfield< 29, 21 > longl2
 
Bitfield< 38, 30 > longl3
 
Bitfield< 47, 39 > longl4
 
Bitfield< 20, 12 > pael1
 
Bitfield< 29, 21 > pael2
 
Bitfield< 31, 30 > pael3
 
Bitfield< 21, 12 > norml1
 
Bitfield< 31, 22 > norml2
 
Bitfield< 51, 12 > base
 
Bitfield< 11, 9 > avl
 
Bitfield< 8 > g
 
Bitfield< 7 > ps
 
Bitfield< 6 > d
 
Bitfield< 5 > a
 
Bitfield< 4 > pcd
 
Bitfield< 3 > pwt
 
Bitfield< 2 > u
 
Bitfield< 1 > w
 
Bitfield< 0 > p
 
Bitfield< 12 > deliveryStatus
 
Bitfield< 19, 18 > destShorthand
 
const int NumFloatRegs
 
 R
 
SignedBitfield< 63, 0 > SR
 
Bitfield< 31, 0 > E
 
SignedBitfield< 31, 0 > SE
 
Bitfield< 15, 0 > X
 
SignedBitfield< 15, 0 > SX
 
Bitfield< 15, 8 > H
 
SignedBitfield< 15, 8 > SH
 
Bitfield< 7, 0 > L
 
SignedBitfield< 7, 0 > SL
 
static const IntRegIndex IntFoldBit = (IntRegIndex)(1 << 6)
 
const int NumIntRegs = NUM_INTREGS
 
const uint32_t cfofMask = CFBit | OFBit
 
const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit
 
Bitfield< 7 > sf
 
Bitfield< 6 > zf
 
Bitfield< 5 > ezf
 
Bitfield< 4 > af
 
Bitfield< 3 > ecf
 
Bitfield< 2 > pf
 
Bitfield< 0 > cf
 
Bitfield< 20 > vip
 
Bitfield< 19 > vif
 
Bitfield< 18 > ac
 
Bitfield< 17 > vm
 
Bitfield< 16 > rf
 
Bitfield< 14 > nt
 
Bitfield< 13, 12 > iopl
 
Bitfield< 11 > of
 
Bitfield< 10 > df
 
Bitfield< 9 > intf
 
Bitfield< 8 > tf
 
Bitfield< 3, 1 > submode
 
Bitfield< 5, 4 > cpl
 
Bitfield< 6 > paging
 
Bitfield< 7 > prot
 
Bitfield< 9, 8 > defOp
 
Bitfield< 11, 10 > altOp
 
Bitfield< 13, 12 > defAddr
 
Bitfield< 15, 14 > altAddr
 
Bitfield< 17, 16 > stack
 
Bitfield< 30 > cd
 
Bitfield< 29 > nw
 
Bitfield< 18 > am
 
Bitfield< 16 > wp
 
Bitfield< 5 > ne
 
Bitfield< 4 > et
 
Bitfield< 3 > ts
 
Bitfield< 2 > em
 
Bitfield< 1 > mp
 
Bitfield< 0 > pe
 
 legacy
 
 longPdtb
 
Bitfield< 31, 12 > pdtb
 
Bitfield< 31, 5 > paePdtb
 
Bitfield< 16 > fsgsbase
 
Bitfield< 10 > osxmmexcpt
 
Bitfield< 9 > osfxsr
 
Bitfield< 8 > pce
 
Bitfield< 7 > pge
 
Bitfield< 6 > mce
 
Bitfield< 5 > pae
 
Bitfield< 4 > pse
 
Bitfield< 3 > de
 
Bitfield< 2 > tsd
 
Bitfield< 1 > pvi
 
Bitfield< 0 > vme
 
 tpr
 
Bitfield< 1 > b1
 
Bitfield< 2 > b2
 
Bitfield< 3 > b3
 
Bitfield< 13 > bd
 
Bitfield< 14 > bs
 
Bitfield< 15 > bt
 
Bitfield< 1 > g0
 
Bitfield< 2 > l1
 
Bitfield< 3 > g1
 
Bitfield< 4 > l2
 
Bitfield< 5 > g2
 
Bitfield< 6 > l3
 
Bitfield< 7 > g3
 
Bitfield< 8 > le
 
Bitfield< 9 > ge
 
Bitfield< 13 > gd
 
Bitfield< 17, 16 > rw0
 
Bitfield< 19, 18 > len0
 
Bitfield< 21, 20 > rw1
 
Bitfield< 23, 22 > len1
 
Bitfield< 25, 24 > rw2
 
Bitfield< 27, 26 > len2
 
Bitfield< 29, 28 > rw3
 
Bitfield< 31, 30 > len3
 
 vcnt
 
Bitfield< 8 > fix
 
Bitfield< 10 > wc
 
 targetCS
 
 targetESP
 
 targetEIP
 
 count
 
Bitfield< 8 > MCGCP
 
Bitfield< 1 > eipv
 
Bitfield< 2 > mcip
 
Bitfield< 1 > btf
 
Bitfield< 2 > pb0
 
Bitfield< 3 > pb1
 
Bitfield< 4 > pb2
 
Bitfield< 5 > pb3
 
 type
 
Bitfield< 51, 12 > physbase
 
Bitfield< 51, 12 > physmask
 
Bitfield< 10 > fe
 
Bitfield< 11 > e
 
 mcaErrorCode
 
Bitfield< 31, 16 > modelSpecificCode
 
Bitfield< 56, 32 > otherInfo
 
Bitfield< 57 > pcc
 
Bitfield< 58 > addrv
 
Bitfield< 59 > miscv
 
Bitfield< 60 > en
 
Bitfield< 61 > uc
 
Bitfield< 62 > over
 
Bitfield< 63 > val
 
Bitfield< 8 > lme
 
Bitfield< 10 > lma
 
Bitfield< 11 > nxe
 
Bitfield< 12 > svme
 
Bitfield< 14 > ffxsr
 
 targetEip
 
Bitfield< 47, 32 > syscallCsAndSs
 
Bitfield< 63, 48 > sysretCsAndSs
 
 mask
 
 eventMask
 
Bitfield< 15, 8 > unitMask
 
Bitfield< 16 > usr
 
Bitfield< 17 > os
 
Bitfield< 19 > pc
 
Bitfield< 20 > intEn
 
Bitfield< 23 > inv
 
Bitfield< 31, 24 > counterMask
 
Bitfield< 19 > mfdm
 
Bitfield< 20 > mvdm
 
Bitfield< 21 > tom2
 
Bitfield< 4 > rd
 
 physAddr
 
Bitfield< 1 > rInit
 
Bitfield< 2 > disA20M
 
Bitfield< 1 > enter
 
Bitfield< 2 > smiCycle
 
Bitfield< 3 > exit
 
Bitfield< 4 > rsmCycle
 
 esi
 
Bitfield< 15, 3 > si
 
Bitfield< 2 > ti
 
Bitfield< 1, 0 > rpl
 
 baseHigh
 
Bitfield< 39, 16 > baseLow
 
Bitfield< 54 > b
 
Bitfield< 53 > l
 
Bitfield< 51, 48 > limitHigh
 
Bitfield< 15, 0 > limitLow
 
BitfieldType< SegDescriptorLimitlimit
 
Bitfield< 46, 45 > dpl
 
Bitfield< 44 > s
 
Bitfield< 42 > c
 
Bitfield< 41 > r
 
Bitfield< 2 > unusable
 
Bitfield< 3 > defaultSize
 
Bitfield< 4 > longMode
 
Bitfield< 6 > granularity
 
Bitfield< 7 > present
 
Bitfield< 12 > writable
 
Bitfield< 13 > readable
 
Bitfield< 14 > expandDown
 
Bitfield< 15 > system
 
 offsetHigh
 
Bitfield< 15, 0 > offsetLow
 
Bitfield< 31, 16 > selector
 
Bitfield< 35, 32 > IST
 
 offset
 
Bitfield< 11 > enable
 
Bitfield< 8 > bsp
 
const MsrMap::value_type msrMapData []
 
static const unsigned msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])
 
const MsrMap msrMap
 Map between MSR addresses and their corresponding misc registers. More...
 
const Addr syscallCodeVirtAddr = 0xffff800000000000
 
const Addr GDTVirtAddr = 0xffff800000001000
 
const Addr IDTVirtAddr = 0xffff800000002000
 
const Addr TSSVirtAddr = 0xffff800000003000
 
const Addr TSSPhysAddr = 0x63000
 
const Addr ISTVirtAddr = 0xffff800000004000
 
const Addr PFHandlerVirtAddr = 0xffff800000005000
 
const Addr MMIORegionVirtAddr = 0xffffc90000000000
 
const Addr MMIORegionPhysAddr = 0xffff0000
 
 decodeVal
 
Bitfield< 7 > repne
 
Bitfield< 6 > rep
 
Bitfield< 5 > lock
 
Bitfield< 4 > op
 
Bitfield< 3 > addr
 
Bitfield< 2, 0 > seg
 
 mod
 
Bitfield< 5, 3 > reg
 
Bitfield< 2, 0 > rm
 
 scale
 
Bitfield< 5, 3 > index
 
Bitfield< 1 > x
 
Bitfield< 4, 0 > m
 
Bitfield< 6, 3 > v
 
 top5
 
Bitfield< 2, 0 > bottom3
 
constexpr unsigned NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
 
const int NumMicroIntRegs = 16
 
const int NumMMXRegs = 8
 
const int NumXMMRegs = 16
 
const int NumMicroFpRegs = 8
 
const int NumCRegs = 16
 
const int NumDRegs = 8
 
const int NumSegments = 6
 
const int NumSysSegments = 4
 
const Addr IntAddrPrefixMask = 0xffffffff00000000ULL
 
const Addr IntAddrPrefixCPUID = 0x100000000ULL
 
const Addr IntAddrPrefixMSR = 0x200000000ULL
 
const Addr IntAddrPrefixIO = 0x300000000ULL
 
const Addr PhysAddrPrefixIO = 0x8000000000000000ULL
 
const Addr PhysAddrPrefixPciConfig = 0xC000000000000000ULL
 
const Addr PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL
 
const Addr PhysAddrPrefixInterrupts = 0xA000000000000000ULL
 
const Addr PhysAddrAPICRangeSize = 1 << 12
 

Detailed Description

This is exposed globally, independent of the ISA.

Typedef Documentation

◆ CrDestOp

Definition at line 220 of file microop_args.hh.

◆ CrSrc1Op

Definition at line 228 of file microop_args.hh.

◆ DbgDestOp

Definition at line 219 of file microop_args.hh.

◆ DbgSrc1Op

Definition at line 227 of file microop_args.hh.

◆ FloatDataOp

Definition at line 239 of file microop_args.hh.

◆ FloatDestOp

Definition at line 223 of file microop_args.hh.

◆ FloatSrc1Op

Definition at line 231 of file microop_args.hh.

◆ FloatSrc2Op

Definition at line 235 of file microop_args.hh.

◆ FoldedDataHiOp

Definition at line 240 of file microop_args.hh.

◆ FoldedDataLowOp

Definition at line 241 of file microop_args.hh.

◆ FoldedDataOp

Definition at line 238 of file microop_args.hh.

◆ FoldedDestOp

Definition at line 218 of file microop_args.hh.

◆ FoldedSrc1Op

Definition at line 226 of file microop_args.hh.

◆ FoldedSrc2Op

Definition at line 234 of file microop_args.hh.

◆ IntDestOp

Definition at line 224 of file microop_args.hh.

◆ IntSrc1Op

Definition at line 232 of file microop_args.hh.

◆ IntSrc2Op

Definition at line 236 of file microop_args.hh.

◆ MachInst

typedef uint64_t gem5::X86ISA::MachInst

Definition at line 56 of file types.hh.

◆ MiscDestOp

Definition at line 222 of file microop_args.hh.

◆ MiscSrc1Op

Definition at line 230 of file microop_args.hh.

◆ MsrMap

typedef std::unordered_map<Addr, MiscRegIndex> gem5::X86ISA::MsrMap

Definition at line 43 of file msr.hh.

◆ MsrVal

typedef MsrMap::value_type gem5::X86ISA::MsrVal

Definition at line 37 of file msr.cc.

◆ RegOpT

template<typename ... Operands>
using gem5::X86ISA::RegOpT = typedef InstOperands<RegOpBase, Operands...>

Definition at line 74 of file microregop.hh.

◆ SegDestOp

Definition at line 221 of file microop_args.hh.

◆ SegSrc1Op

Definition at line 229 of file microop_args.hh.

◆ VecElem

Definition at line 56 of file vecregs.hh.

◆ VecPredRegContainer

Definition at line 61 of file vecregs.hh.

◆ VecRegContainer

Definition at line 57 of file vecregs.hh.

Enumeration Type Documentation

◆ ApicRegIndex

Enumerator
APIC_ID 
APIC_VERSION 
APIC_TASK_PRIORITY 
APIC_ARBITRATION_PRIORITY 
APIC_PROCESSOR_PRIORITY 
APIC_EOI 
APIC_LOGICAL_DESTINATION 
APIC_DESTINATION_FORMAT 
APIC_SPURIOUS_INTERRUPT_VECTOR 
APIC_IN_SERVICE_BASE 
APIC_TRIGGER_MODE_BASE 
APIC_INTERRUPT_REQUEST_BASE 
APIC_ERROR_STATUS 
APIC_INTERRUPT_COMMAND_LOW 
APIC_INTERRUPT_COMMAND_HIGH 
APIC_LVT_TIMER 
APIC_LVT_THERMAL_SENSOR 
APIC_LVT_PERFORMANCE_MONITORING_COUNTERS 
APIC_LVT_LINT0 
APIC_LVT_LINT1 
APIC_LVT_ERROR 
APIC_INITIAL_COUNT 
APIC_CURRENT_COUNT 
APIC_DIVIDE_CONFIGURATION 
APIC_INTERNAL_STATE 
NUM_APIC_REGS 

Definition at line 39 of file apic.hh.

◆ CCRegIndex

Enumerator
CCREG_ZAPS 
CCREG_CFOF 
CCREG_DF 
CCREG_ECF 
CCREG_EZF 
NUM_CCREGS 

Definition at line 48 of file ccr.hh.

◆ CondFlagBit

Enumerator
CFBit 
PFBit 
ECFBit 
AFBit 
EZFBit 
ZFBit 
SFBit 
DFBit 
OFBit 

Definition at line 57 of file misc.hh.

◆ ExtendedCpuidFunctions

Enumerator
VendorAndLargestExtFunc 
FamilyModelSteppingBrandFeatures 
NameString1 
NameString2 
NameString3 
L1CacheAndTLB 
L2L3CacheAndL2TLB 
APMInfo 
LongModeAddressSize 
NumExtendedCpuidFuncs 

Definition at line 52 of file cpuid.cc.

◆ FlagBit

Enumerator
CPL0FlagBit 
AddrSizeFlagBit 
StoreCheck 

Definition at line 55 of file ldstflags.hh.

◆ FloatRegIndex

Enumerator
FLOATREG_MMX_BASE 
FLOATREG_FPR_BASE 
FLOATREG_MMX0 
FLOATREG_MMX1 
FLOATREG_MMX2 
FLOATREG_MMX3 
FLOATREG_MMX4 
FLOATREG_MMX5 
FLOATREG_MMX6 
FLOATREG_MMX7 
FLOATREG_FPR0 
FLOATREG_FPR1 
FLOATREG_FPR2 
FLOATREG_FPR3 
FLOATREG_FPR4 
FLOATREG_FPR5 
FLOATREG_FPR6 
FLOATREG_FPR7 
FLOATREG_XMM_BASE 
FLOATREG_XMM0_LOW 
FLOATREG_XMM0_HIGH 
FLOATREG_XMM1_LOW 
FLOATREG_XMM1_HIGH 
FLOATREG_XMM2_LOW 
FLOATREG_XMM2_HIGH 
FLOATREG_XMM3_LOW 
FLOATREG_XMM3_HIGH 
FLOATREG_XMM4_LOW 
FLOATREG_XMM4_HIGH 
FLOATREG_XMM5_LOW 
FLOATREG_XMM5_HIGH 
FLOATREG_XMM6_LOW 
FLOATREG_XMM6_HIGH 
FLOATREG_XMM7_LOW 
FLOATREG_XMM7_HIGH 
FLOATREG_XMM8_LOW 
FLOATREG_XMM8_HIGH 
FLOATREG_XMM9_LOW 
FLOATREG_XMM9_HIGH 
FLOATREG_XMM10_LOW 
FLOATREG_XMM10_HIGH 
FLOATREG_XMM11_LOW 
FLOATREG_XMM11_HIGH 
FLOATREG_XMM12_LOW 
FLOATREG_XMM12_HIGH 
FLOATREG_XMM13_LOW 
FLOATREG_XMM13_HIGH 
FLOATREG_XMM14_LOW 
FLOATREG_XMM14_HIGH 
FLOATREG_XMM15_LOW 
FLOATREG_XMM15_HIGH 
FLOATREG_MICROFP_BASE 
FLOATREG_MICROFP0 
FLOATREG_MICROFP1 
FLOATREG_MICROFP2 
FLOATREG_MICROFP3 
FLOATREG_MICROFP4 
FLOATREG_MICROFP5 
FLOATREG_MICROFP6 
FLOATREG_MICROFP7 
NUM_FLOATREGS 

Definition at line 49 of file float.hh.

◆ MediaFlag

Enumerator
MediaMultHiOp 
MediaSignedOp 
MediaScalarOp 

Definition at line 40 of file micromediaop.hh.

◆ MiscRegIndex

Enumerator
MISCREG_CR_BASE 
MISCREG_CR0 
MISCREG_CR1 
MISCREG_CR2 
MISCREG_CR3 
MISCREG_CR4 
MISCREG_CR5 
MISCREG_CR6 
MISCREG_CR7 
MISCREG_CR8 
MISCREG_CR9 
MISCREG_CR10 
MISCREG_CR11 
MISCREG_CR12 
MISCREG_CR13 
MISCREG_CR14 
MISCREG_CR15 
MISCREG_DR_BASE 
MISCREG_DR0 
MISCREG_DR1 
MISCREG_DR2 
MISCREG_DR3 
MISCREG_DR4 
MISCREG_DR5 
MISCREG_DR6 
MISCREG_DR7 
MISCREG_RFLAGS 
MISCREG_M5_REG 
MISCREG_TSC 
MISCREG_MTRRCAP 
MISCREG_SYSENTER_CS 
MISCREG_SYSENTER_ESP 
MISCREG_SYSENTER_EIP 
MISCREG_MCG_CAP 
MISCREG_MCG_STATUS 
MISCREG_MCG_CTL 
MISCREG_DEBUG_CTL_MSR 
MISCREG_LAST_BRANCH_FROM_IP 
MISCREG_LAST_BRANCH_TO_IP 
MISCREG_LAST_EXCEPTION_FROM_IP 
MISCREG_LAST_EXCEPTION_TO_IP 
MISCREG_MTRR_PHYS_BASE_BASE 
MISCREG_MTRR_PHYS_BASE_0 
MISCREG_MTRR_PHYS_BASE_1 
MISCREG_MTRR_PHYS_BASE_2 
MISCREG_MTRR_PHYS_BASE_3 
MISCREG_MTRR_PHYS_BASE_4 
MISCREG_MTRR_PHYS_BASE_5 
MISCREG_MTRR_PHYS_BASE_6 
MISCREG_MTRR_PHYS_BASE_7 
MISCREG_MTRR_PHYS_BASE_END 
MISCREG_MTRR_PHYS_MASK_BASE 
MISCREG_MTRR_PHYS_MASK_0 
MISCREG_MTRR_PHYS_MASK_1 
MISCREG_MTRR_PHYS_MASK_2 
MISCREG_MTRR_PHYS_MASK_3 
MISCREG_MTRR_PHYS_MASK_4 
MISCREG_MTRR_PHYS_MASK_5 
MISCREG_MTRR_PHYS_MASK_6 
MISCREG_MTRR_PHYS_MASK_7 
MISCREG_MTRR_PHYS_MASK_END 
MISCREG_MTRR_FIX_64K_00000 
MISCREG_MTRR_FIX_16K_80000 
MISCREG_MTRR_FIX_16K_A0000 
MISCREG_MTRR_FIX_4K_C0000 
MISCREG_MTRR_FIX_4K_C8000 
MISCREG_MTRR_FIX_4K_D0000 
MISCREG_MTRR_FIX_4K_D8000 
MISCREG_MTRR_FIX_4K_E0000 
MISCREG_MTRR_FIX_4K_E8000 
MISCREG_MTRR_FIX_4K_F0000 
MISCREG_MTRR_FIX_4K_F8000 
MISCREG_PAT 
MISCREG_DEF_TYPE 
MISCREG_MC_CTL_BASE 
MISCREG_MC0_CTL 
MISCREG_MC1_CTL 
MISCREG_MC2_CTL 
MISCREG_MC3_CTL 
MISCREG_MC4_CTL 
MISCREG_MC5_CTL 
MISCREG_MC6_CTL 
MISCREG_MC7_CTL 
MISCREG_MC_CTL_END 
MISCREG_MC_STATUS_BASE 
MISCREG_MC0_STATUS 
MISCREG_MC1_STATUS 
MISCREG_MC2_STATUS 
MISCREG_MC3_STATUS 
MISCREG_MC4_STATUS 
MISCREG_MC5_STATUS 
MISCREG_MC6_STATUS 
MISCREG_MC7_STATUS 
MISCREG_MC_STATUS_END 
MISCREG_MC_ADDR_BASE 
MISCREG_MC0_ADDR 
MISCREG_MC1_ADDR 
MISCREG_MC2_ADDR 
MISCREG_MC3_ADDR 
MISCREG_MC4_ADDR 
MISCREG_MC5_ADDR 
MISCREG_MC6_ADDR 
MISCREG_MC7_ADDR 
MISCREG_MC_ADDR_END 
MISCREG_MC_MISC_BASE 
MISCREG_MC0_MISC 
MISCREG_MC1_MISC 
MISCREG_MC2_MISC 
MISCREG_MC3_MISC 
MISCREG_MC4_MISC 
MISCREG_MC5_MISC 
MISCREG_MC6_MISC 
MISCREG_MC7_MISC 
MISCREG_MC_MISC_END 
MISCREG_EFER 
MISCREG_STAR 
MISCREG_LSTAR 
MISCREG_CSTAR 
MISCREG_SF_MASK 
MISCREG_KERNEL_GS_BASE 
MISCREG_TSC_AUX 
MISCREG_PERF_EVT_SEL_BASE 
MISCREG_PERF_EVT_SEL0 
MISCREG_PERF_EVT_SEL1 
MISCREG_PERF_EVT_SEL2 
MISCREG_PERF_EVT_SEL3 
MISCREG_PERF_EVT_SEL_END 
MISCREG_PERF_EVT_CTR_BASE 
MISCREG_PERF_EVT_CTR0 
MISCREG_PERF_EVT_CTR1 
MISCREG_PERF_EVT_CTR2 
MISCREG_PERF_EVT_CTR3 
MISCREG_PERF_EVT_CTR_END 
MISCREG_SYSCFG 
MISCREG_IORR_BASE_BASE 
MISCREG_IORR_BASE0 
MISCREG_IORR_BASE1 
MISCREG_IORR_BASE_END 
MISCREG_IORR_MASK_BASE 
MISCREG_IORR_MASK0 
MISCREG_IORR_MASK1 
MISCREG_IORR_MASK_END 
MISCREG_TOP_MEM 
MISCREG_TOP_MEM2 
MISCREG_VM_CR 
MISCREG_IGNNE 
MISCREG_SMM_CTL 
MISCREG_VM_HSAVE_PA 
MISCREG_SEG_SEL_BASE 
MISCREG_ES 
MISCREG_CS 
MISCREG_SS 
MISCREG_DS 
MISCREG_FS 
MISCREG_GS 
MISCREG_HS 
MISCREG_TSL 
MISCREG_TSG 
MISCREG_LS 
MISCREG_MS 
MISCREG_TR 
MISCREG_IDTR 
MISCREG_SEG_BASE_BASE 
MISCREG_ES_BASE 
MISCREG_CS_BASE 
MISCREG_SS_BASE 
MISCREG_DS_BASE 
MISCREG_FS_BASE 
MISCREG_GS_BASE 
MISCREG_HS_BASE 
MISCREG_TSL_BASE 
MISCREG_TSG_BASE 
MISCREG_LS_BASE 
MISCREG_MS_BASE 
MISCREG_TR_BASE 
MISCREG_IDTR_BASE 
MISCREG_SEG_EFF_BASE_BASE 
MISCREG_ES_EFF_BASE 
MISCREG_CS_EFF_BASE 
MISCREG_SS_EFF_BASE 
MISCREG_DS_EFF_BASE 
MISCREG_FS_EFF_BASE 
MISCREG_GS_EFF_BASE 
MISCREG_HS_EFF_BASE 
MISCREG_TSL_EFF_BASE 
MISCREG_TSG_EFF_BASE 
MISCREG_LS_EFF_BASE 
MISCREG_MS_EFF_BASE 
MISCREG_TR_EFF_BASE 
MISCREG_IDTR_EFF_BASE 
MISCREG_SEG_LIMIT_BASE 
MISCREG_ES_LIMIT 
MISCREG_CS_LIMIT 
MISCREG_SS_LIMIT 
MISCREG_DS_LIMIT 
MISCREG_FS_LIMIT 
MISCREG_GS_LIMIT 
MISCREG_HS_LIMIT 
MISCREG_TSL_LIMIT 
MISCREG_TSG_LIMIT 
MISCREG_LS_LIMIT 
MISCREG_MS_LIMIT 
MISCREG_TR_LIMIT 
MISCREG_IDTR_LIMIT 
MISCREG_SEG_ATTR_BASE 
MISCREG_ES_ATTR 
MISCREG_CS_ATTR 
MISCREG_SS_ATTR 
MISCREG_DS_ATTR 
MISCREG_FS_ATTR 
MISCREG_GS_ATTR 
MISCREG_HS_ATTR 
MISCREG_TSL_ATTR 
MISCREG_TSG_ATTR 
MISCREG_LS_ATTR 
MISCREG_MS_ATTR 
MISCREG_TR_ATTR 
MISCREG_IDTR_ATTR 
MISCREG_X87_TOP 
MISCREG_MXCSR 
MISCREG_FCW 
MISCREG_FSW 
MISCREG_FTW 
MISCREG_FTAG 
MISCREG_FISEG 
MISCREG_FIOFF 
MISCREG_FOSEG 
MISCREG_FOOFF 
MISCREG_FOP 
MISCREG_APIC_BASE 
MISCREG_PCI_CONFIG_ADDRESS 
NUM_MISCREGS 

Definition at line 106 of file misc.hh.

◆ Prefixes

Enumerator
NoOverride 
ESOverride 
CSOverride 
SSOverride 
DSOverride 
FSOverride 
GSOverride 
RexPrefix 
OperandSizeOverride 
AddressSizeOverride 
Lock 
Rep 
Repne 
Vex2Prefix 
Vex3Prefix 
XopPrefix 

Definition at line 58 of file types.hh.

◆ RFLAGBit

Enumerator
TFBit 
IFBit 
NTBit 
RFBit 
VMBit 
ACBit 
VIFBit 
VIPBit 
IDBit 

Definition at line 73 of file misc.hh.

◆ SegmentRegIndex

Enumerator
SEGMENT_REG_ES 
SEGMENT_REG_CS 
SEGMENT_REG_SS 
SEGMENT_REG_DS 
SEGMENT_REG_FS 
SEGMENT_REG_GS 
SEGMENT_REG_HS 
SEGMENT_REG_TSL 
SEGMENT_REG_TSG 
SEGMENT_REG_LS 
SEGMENT_REG_MS 
SYS_SEGMENT_REG_TR 
SYS_SEGMENT_REG_IDTR 
NUM_SEGMENTREGS 

Definition at line 46 of file segment.hh.

◆ SizeType

Enumerator
NoImm 
NI 
ByteImm 
BY 
WordImm 
WO 
DWordImm 
DW 
QWordImm 
QW 
OWordImm 
OW 
VWordImm 
VW 
ZWordImm 
ZW 
Enter 
EN 
Pointer 
PO 

Definition at line 170 of file decoder_tables.cc.

◆ StandardCpuidFunction

Enumerator
VendorAndLargestStdFunc 
FamilyModelStepping 
CacheAndTLB 
SerialNumber 
CacheParams 
MonitorMwait 
ThermalPowerMgmt 
ExtendedFeatures 
NumStandardCpuidFuncs 

Definition at line 39 of file cpuid.cc.

◆ X86SubMode

Enumerator
SixtyFourBitMode 
CompatabilityMode 
ProtectedMode 
Virtual8086Mode 
RealMode 

Definition at line 196 of file types.hh.

◆ X87StatusBit

Enumerator
IEBit 
DEBit 
ZEBit 
OEBit 
UEBit 
PEBit 
StackFaultBit 
ErrSummaryBit 
CC0Bit 
CC1Bit 
CC2Bit 
CC3Bit 
BusyBit 

Definition at line 86 of file misc.hh.

Function Documentation

◆ APIC_IN_SERVICE()

static ApicRegIndex gem5::X86ISA::APIC_IN_SERVICE ( int  index)
inlinestatic

Definition at line 76 of file apic.hh.

References APIC_IN_SERVICE_BASE, and index.

Referenced by decodeAddr(), and gem5::X86ISA::Interrupts::setReg().

◆ APIC_INTERRUPT_REQUEST()

static ApicRegIndex gem5::X86ISA::APIC_INTERRUPT_REQUEST ( int  index)
inlinestatic

Definition at line 88 of file apic.hh.

References APIC_INTERRUPT_REQUEST_BASE, and index.

Referenced by decodeAddr(), and gem5::X86ISA::Interrupts::setReg().

◆ APIC_TRIGGER_MODE()

static ApicRegIndex gem5::X86ISA::APIC_TRIGGER_MODE ( int  index)
inlinestatic

◆ archPrctlFunc()

SyscallReturn gem5::X86ISA::archPrctlFunc ( SyscallDesc desc,
ThreadContext tc,
int  code,
uint64_t  addr 
)

◆ BitUnion32() [1/3]

gem5::X86ISA::BitUnion32 ( InterruptCommandRegLow  )

◆ BitUnion32() [2/3]

gem5::X86ISA::BitUnion32 ( TriggerIntMessage  )

◆ BitUnion32() [3/3]

gem5::X86ISA::BitUnion32 ( UserDescFlags  )

◆ BitUnion64() [1/4]

gem5::X86ISA::BitUnion64 ( CCFlagBits  )

A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode.

◆ BitUnion64() [2/4]

gem5::X86ISA::BitUnion64 ( SegDescriptor  )

◆ BitUnion64() [3/4]

gem5::X86ISA::BitUnion64 ( VAddr  )

◆ BitUnion64() [4/4]

gem5::X86ISA::BitUnion64 ( X86IntReg  )

◆ BitUnion8() [1/2]

gem5::X86ISA::BitUnion8 ( LegacyPrefixVector  )

◆ BitUnion8() [2/2]

gem5::X86ISA::BitUnion8 ( Opcode  )

◆ buildIntPacket()

template<class T >
PacketPtr gem5::X86ISA::buildIntPacket ( Addr  addr,
payload 
)

◆ buildIntTriggerPacket()

static PacketPtr gem5::X86ISA::buildIntTriggerPacket ( int  id,
TriggerIntMessage  message 
)
inlinestatic

◆ convX87TagsToXTags()

uint8_t gem5::X86ISA::convX87TagsToXTags ( uint16_t  ftw)

Convert an x87 tag word to abridged tag format.

Convert from the x87 tag representation to the tag abridged representation used in the FXSAVE area. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Parameters
ftwTag word in classic x87 format.
Returns
Tag word in the abridged format.

Definition at line 90 of file utility.cc.

References gem5::ArmISA::i.

Referenced by gem5::updateKvmStateFPUCommon().

◆ convX87XTagsToTags()

uint16_t gem5::X86ISA::convX87XTagsToTags ( uint8_t  ftwx)

Convert an x87 xtag word to normal tags format.

Convert from the abridged x87 tag representation used in the FXSAVE area to a full x87 tag. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Todo:
Reconstruct the correct state of stack positions instead of just valid/invalid.
Parameters
ftwxTag word in the abridged format.
Returns
Tag word in classic x87 format.

Definition at line 115 of file utility.cc.

References gem5::ArmISA::i.

Referenced by gem5::updateThreadContextFPUCommon().

◆ copyMiscRegs()

static void gem5::X86ISA::copyMiscRegs ( ThreadContext src,
ThreadContext dest 
)
static

◆ decodeAddr()

ApicRegIndex gem5::X86ISA::decodeAddr ( Addr  paddr)

◆ doCpuid()

bool gem5::X86ISA::doCpuid ( ThreadContext tc,
uint32_t  function,
uint32_t  index,
CpuidResult result 
)

◆ EndBitUnion() [1/54]

gem5::X86ISA::EndBitUnion ( CCFlagBits  )

RFLAGS.

◆ EndBitUnion() [2/54]

gem5::X86ISA::EndBitUnion ( CR0  )

◆ EndBitUnion() [3/54]

gem5::X86ISA::EndBitUnion ( CR2  )

◆ EndBitUnion() [4/54]

gem5::X86ISA::EndBitUnion ( CR3  )

◆ EndBitUnion() [5/54]

gem5::X86ISA::EndBitUnion ( CR4  )

◆ EndBitUnion() [6/54]

gem5::X86ISA::EndBitUnion ( CR8  )

◆ EndBitUnion() [7/54]

gem5::X86ISA::EndBitUnion ( DebugCtlMsr  )

◆ EndBitUnion() [8/54]

gem5::X86ISA::EndBitUnion ( DR6  )

◆ EndBitUnion() [9/54]

gem5::X86ISA::EndBitUnion ( DR7  )

◆ EndBitUnion() [10/54]

gem5::X86ISA::EndBitUnion ( Efer  )

◆ EndBitUnion() [11/54]

gem5::X86ISA::EndBitUnion ( GateDescriptor  )

Long Mode Gate Descriptor.

◆ EndBitUnion() [12/54]

gem5::X86ISA::EndBitUnion ( GateDescriptorHigh  )

Descriptor-Table Registers.

Task Register Local APIC Base Register

◆ EndBitUnion() [13/54]

gem5::X86ISA::EndBitUnion ( GateDescriptorLow  )

◆ EndBitUnion() [14/54]

gem5::X86ISA::EndBitUnion ( HandyM5Reg  )

Control registers.

◆ EndBitUnion() [15/54]

gem5::X86ISA::EndBitUnion ( IgnneMsr  )

◆ EndBitUnion() [16/54]

gem5::X86ISA::EndBitUnion ( InterruptCommandRegLow  )

◆ EndBitUnion() [17/54]

gem5::X86ISA::EndBitUnion ( IorrBase  )

◆ EndBitUnion() [18/54]

gem5::X86ISA::EndBitUnion ( IorrMask  )

◆ EndBitUnion() [19/54]

gem5::X86ISA::EndBitUnion ( LegacyPrefixVector  )

◆ EndBitUnion() [20/54]

gem5::X86ISA::EndBitUnion ( McgCap  )

◆ EndBitUnion() [21/54]

gem5::X86ISA::EndBitUnion ( McgStatus  )

◆ EndBitUnion() [22/54]

gem5::X86ISA::EndBitUnion ( McStatus  )

◆ EndBitUnion() [23/54]

gem5::X86ISA::EndBitUnion ( ModRM  )

◆ EndBitUnion() [24/54]

gem5::X86ISA::EndBitUnion ( MTRRcap  )

SYSENTER configuration registers.

◆ EndBitUnion() [25/54]

gem5::X86ISA::EndBitUnion ( MtrrDefType  )

Machine check.

◆ EndBitUnion() [26/54]

gem5::X86ISA::EndBitUnion ( MtrrPhysBase  )

◆ EndBitUnion() [27/54]

gem5::X86ISA::EndBitUnion ( MtrrPhysMask  )

◆ EndBitUnion() [28/54]

gem5::X86ISA::EndBitUnion ( Opcode  )

◆ EndBitUnion() [29/54]

gem5::X86ISA::EndBitUnion ( OperatingMode  )

Definition at line 188 of file types.hh.

◆ EndBitUnion() [30/54]

gem5::X86ISA::EndBitUnion ( PageTableEntry  )

◆ EndBitUnion() [31/54]

gem5::X86ISA::EndBitUnion ( PerfEvtSel  )

◆ EndBitUnion() [32/54]

gem5::X86ISA::EndBitUnion ( Rex  )

◆ EndBitUnion() [33/54]

gem5::X86ISA::EndBitUnion ( RFLAGS  )

◆ EndBitUnion() [34/54]

gem5::X86ISA::EndBitUnion ( SegAttr  )

◆ EndBitUnion() [35/54]

gem5::X86ISA::EndBitUnion ( SegSelector  )

Segment Descriptors.

Definition at line 869 of file misc.hh.

References base, gem5::bits(), and gem5::replaceBits().

◆ EndBitUnion() [36/54]

gem5::X86ISA::EndBitUnion ( SfMask  )

◆ EndBitUnion() [37/54]

gem5::X86ISA::EndBitUnion ( Sib  )

◆ EndBitUnion() [38/54]

gem5::X86ISA::EndBitUnion ( SmmCtlMsr  )

Segment Selector.

◆ EndBitUnion() [39/54]

gem5::X86ISA::EndBitUnion ( Star  )

◆ EndBitUnion() [40/54]

gem5::X86ISA::EndBitUnion ( Syscfg  )

◆ EndBitUnion() [41/54]

gem5::X86ISA::EndBitUnion ( SysenterCS  )

◆ EndBitUnion() [42/54]

gem5::X86ISA::EndBitUnion ( SysenterEIP  )

Global machine check registers.

◆ EndBitUnion() [43/54]

gem5::X86ISA::EndBitUnion ( SysenterESP  )

◆ EndBitUnion() [44/54]

gem5::X86ISA::EndBitUnion ( Tom  )

◆ EndBitUnion() [45/54]

gem5::X86ISA::EndBitUnion ( TriggerIntMessage  )

◆ EndBitUnion() [46/54]

gem5::X86ISA::EndBitUnion ( TSShigh  )

◆ EndBitUnion() [47/54]

gem5::X86ISA::EndBitUnion ( UserDescFlags  )

Definition at line 55 of file syscalls.hh.

References limit.

◆ EndBitUnion() [48/54]

gem5::X86ISA::EndBitUnion ( VAddr  )

◆ EndBitUnion() [49/54]

gem5::X86ISA::EndBitUnion ( Vex2Of2  )

◆ EndBitUnion() [50/54]

gem5::X86ISA::EndBitUnion ( Vex2Of3  )

◆ EndBitUnion() [51/54]

gem5::X86ISA::EndBitUnion ( Vex3Of3  )

◆ EndBitUnion() [52/54]

gem5::X86ISA::EndBitUnion ( VexInfo  )

Definition at line 150 of file types.hh.

◆ EndBitUnion() [53/54]

gem5::X86ISA::EndBitUnion ( VmCrMsr  )

◆ EndBitUnion() [54/54]

gem5::X86ISA::EndBitUnion ( X86IntReg  )

Definition at line 61 of file int.hh.

References NumMicroIntRegs.

◆ EndSubBitUnion()

gem5::X86ISA::EndSubBitUnion ( type  )

TSS Descriptor (long mode - 128 bits) the lower 64 bits.

TSS Descriptor (long mode - 128 bits) the upper 64 bits.

◆ FLOATREG_FPR()

static FloatRegIndex gem5::X86ISA::FLOATREG_FPR ( int  index)
inlinestatic

◆ FLOATREG_MICROFP()

static FloatRegIndex gem5::X86ISA::FLOATREG_MICROFP ( int  index)
inlinestatic

Definition at line 144 of file float.hh.

References FLOATREG_MICROFP_BASE, and index.

◆ FLOATREG_MMX()

static FloatRegIndex gem5::X86ISA::FLOATREG_MMX ( int  index)
inlinestatic

Definition at line 120 of file float.hh.

References FLOATREG_MMX_BASE, and index.

Referenced by gem5::Trace::X86NativeTrace::ThreadState::update().

◆ FLOATREG_STACK()

static FloatRegIndex gem5::X86ISA::FLOATREG_STACK ( int  index,
int  top 
)
inlinestatic

Definition at line 150 of file float.hh.

References FLOATREG_FPR(), and index.

Referenced by gem5::X86ISA::ISA::flattenFloatIndex().

◆ FLOATREG_XMM_HIGH()

static FloatRegIndex gem5::X86ISA::FLOATREG_XMM_HIGH ( int  index)
inlinestatic

Definition at line 138 of file float.hh.

References FLOATREG_XMM_BASE, and index.

Referenced by gem5::updateKvmStateFPUCommon(), and gem5::updateThreadContextFPUCommon().

◆ FLOATREG_XMM_LOW()

static FloatRegIndex gem5::X86ISA::FLOATREG_XMM_LOW ( int  index)
inlinestatic

Definition at line 132 of file float.hh.

References FLOATREG_XMM_BASE, and index.

Referenced by gem5::updateKvmStateFPUCommon(), and gem5::updateThreadContextFPUCommon().

◆ GEM5_DEPRECATED_NAMESPACE() [1/3]

gem5::X86ISA::GEM5_DEPRECATED_NAMESPACE ( ConditionTests  ,
condition_tests   
)

◆ GEM5_DEPRECATED_NAMESPACE() [2/3]

gem5::X86ISA::GEM5_DEPRECATED_NAMESPACE ( IntelMP  ,
intelmp   
)

◆ GEM5_DEPRECATED_NAMESPACE() [3/3]

gem5::X86ISA::GEM5_DEPRECATED_NAMESPACE ( SMBios  ,
smbios   
)

◆ genX87Tags()

uint16_t gem5::X86ISA::genX87Tags ( uint16_t  ftw,
uint8_t  top,
int8_t  spm 
)

Generate and updated x87 tag register after a push/pop operation.

Note
There is currently no support for setting other tags than valid and invalid. A real x87 will set the tag value to zero or special for some special floating point values.
Parameters
ftwCurrent value of the FTW register.
topCurrent x87 TOP value.
spmStack displacement.
Returns
New value of the FTW register.

Definition at line 136 of file utility.cc.

References gem5::ArmISA::i.

◆ getMem() [1/2]

template<size_t N>
static void gem5::X86ISA::getMem ( PacketPtr  pkt,
std::array< uint64_t, N > &  mem,
unsigned  dataSize,
Trace::InstRecord traceData 
)
static

Definition at line 90 of file memhelpers.hh.

References mem, panic, and gem5::Trace::InstRecord::setData().

◆ getMem() [2/2]

static void gem5::X86ISA::getMem ( PacketPtr  pkt,
uint64_t &  mem,
unsigned  dataSize,
Trace::InstRecord traceData 
)
static

Definition at line 56 of file memhelpers.hh.

References gem5::Packet::getLE(), mem, panic, and gem5::Trace::InstRecord::setData().

◆ getPackedMem()

template<typename T , size_t N>
static void gem5::X86ISA::getPackedMem ( PacketPtr  pkt,
std::array< uint64_t, N > &  mem,
unsigned  dataSize 
)
static

Definition at line 81 of file memhelpers.hh.

References gem5::Packet::getLE(), gem5::ArmISA::i, and mem.

◆ getRFlags()

uint64_t gem5::X86ISA::getRFlags ( ThreadContext tc)

Reconstruct the rflags register from the internal gem5 register state.

gem5 stores rflags in several different registers to avoid pipeline dependencies. In order to get the true rflags value, we can't simply read the value of MISCREG_RFLAGS. Instead, we need to read out various state from microcode registers and merge that with MISCREG_RFLAGS.

Parameters
tcThread context to read rflags from.
Returns
rflags as seen by the guest.

Definition at line 58 of file utility.cc.

References CCREG_CFOF, CCREG_DF, CCREG_ZAPS, MISCREG_RFLAGS, gem5::ThreadContext::readCCReg(), and gem5::ThreadContext::readMiscRegNoEffect().

Referenced by gem5::X86KvmCPU::updateKvmStateRegs().

◆ initiateMemRead()

static Fault gem5::X86ISA::initiateMemRead ( ExecContext xc,
Trace::InstRecord traceData,
Addr  addr,
unsigned  dataSize,
Request::Flags  flags 
)
static

Initiate a read from memory in timing mode.

Definition at line 48 of file memhelpers.hh.

References addr, and gem5::ExecContext::initiateMemRead().

◆ installSegDesc()

void gem5::X86ISA::installSegDesc ( ThreadContext tc,
SegmentRegIndex  seg,
SegDescriptor  desc,
bool  longmode 
)

◆ INTREG_FOLDED()

static IntRegIndex gem5::X86ISA::INTREG_FOLDED ( int  index,
int  foldBit 
)
inlinestatic

Definition at line 181 of file int.hh.

References index.

◆ INTREG_MICRO()

static IntRegIndex gem5::X86ISA::INTREG_MICRO ( int  index)
inlinestatic

Definition at line 175 of file int.hh.

References index.

Referenced by gem5::X86ISA::X86FaultBase::invoke().

◆ isValidMiscReg()

static bool gem5::X86ISA::isValidMiscReg ( int  index)
inlinestatic

◆ loadFloat80()

double gem5::X86ISA::loadFloat80 ( const void *  mem)

Load an 80-bit float from memory and convert it to double.

Parameters
memPointer to an 80-bit float.
Returns
double representation of the 80-bit float.

Definition at line 156 of file utility.cc.

Referenced by gem5::dumpFpuCommon(), and gem5::updateThreadContextFPUCommon().

◆ MISCREG_CR()

static MiscRegIndex gem5::X86ISA::MISCREG_CR ( int  index)
inlinestatic

Definition at line 417 of file misc.hh.

References index, MISCREG_CR_BASE, and NumCRegs.

◆ MISCREG_DR()

static MiscRegIndex gem5::X86ISA::MISCREG_DR ( int  index)
inlinestatic

Definition at line 424 of file misc.hh.

References index, MISCREG_DR_BASE, and NumDRegs.

◆ MISCREG_IORR_BASE()

static MiscRegIndex gem5::X86ISA::MISCREG_IORR_BASE ( int  index)
inlinestatic

Definition at line 495 of file misc.hh.

References index, MISCREG_IORR_BASE_BASE, and MISCREG_IORR_BASE_END.

◆ MISCREG_IORR_MASK()

static MiscRegIndex gem5::X86ISA::MISCREG_IORR_MASK ( int  index)
inlinestatic

Definition at line 503 of file misc.hh.

References index, MISCREG_IORR_MASK_BASE, and MISCREG_IORR_MASK_END.

◆ MISCREG_MC_ADDR()

static MiscRegIndex gem5::X86ISA::MISCREG_MC_ADDR ( int  index)
inlinestatic

Definition at line 463 of file misc.hh.

References index, MISCREG_MC_ADDR_BASE, and MISCREG_MC_ADDR_END.

◆ MISCREG_MC_CTL()

static MiscRegIndex gem5::X86ISA::MISCREG_MC_CTL ( int  index)
inlinestatic

Definition at line 447 of file misc.hh.

References index, MISCREG_MC_CTL_BASE, and MISCREG_MC_CTL_END.

◆ MISCREG_MC_MISC()

static MiscRegIndex gem5::X86ISA::MISCREG_MC_MISC ( int  index)
inlinestatic

Definition at line 471 of file misc.hh.

References index, MISCREG_MC_MISC_BASE, and MISCREG_MC_MISC_END.

◆ MISCREG_MC_STATUS()

static MiscRegIndex gem5::X86ISA::MISCREG_MC_STATUS ( int  index)
inlinestatic

Definition at line 455 of file misc.hh.

References index, MISCREG_MC_STATUS_BASE, and MISCREG_MC_STATUS_END.

◆ MISCREG_MTRR_PHYS_BASE()

static MiscRegIndex gem5::X86ISA::MISCREG_MTRR_PHYS_BASE ( int  index)
inlinestatic

Definition at line 431 of file misc.hh.

References index, MISCREG_MTRR_PHYS_BASE_BASE, and MISCREG_MTRR_PHYS_BASE_END.

◆ MISCREG_MTRR_PHYS_MASK()

static MiscRegIndex gem5::X86ISA::MISCREG_MTRR_PHYS_MASK ( int  index)
inlinestatic

Definition at line 439 of file misc.hh.

References index, MISCREG_MTRR_PHYS_MASK_BASE, and MISCREG_MTRR_PHYS_MASK_END.

◆ MISCREG_PERF_EVT_CTR()

static MiscRegIndex gem5::X86ISA::MISCREG_PERF_EVT_CTR ( int  index)
inlinestatic

Definition at line 487 of file misc.hh.

References index, MISCREG_PERF_EVT_CTR_BASE, and MISCREG_PERF_EVT_CTR_END.

◆ MISCREG_PERF_EVT_SEL()

static MiscRegIndex gem5::X86ISA::MISCREG_PERF_EVT_SEL ( int  index)
inlinestatic

Definition at line 479 of file misc.hh.

References index, MISCREG_PERF_EVT_SEL_BASE, and MISCREG_PERF_EVT_SEL_END.

◆ MISCREG_SEG_ATTR()

static MiscRegIndex gem5::X86ISA::MISCREG_SEG_ATTR ( int  index)
inlinestatic

◆ MISCREG_SEG_BASE()

static MiscRegIndex gem5::X86ISA::MISCREG_SEG_BASE ( int  index)
inlinestatic

◆ MISCREG_SEG_EFF_BASE()

static MiscRegIndex gem5::X86ISA::MISCREG_SEG_EFF_BASE ( int  index)
inlinestatic

◆ MISCREG_SEG_LIMIT()

static MiscRegIndex gem5::X86ISA::MISCREG_SEG_LIMIT ( int  index)
inlinestatic

◆ MISCREG_SEG_SEL()

static MiscRegIndex gem5::X86ISA::MISCREG_SEG_SEL ( int  index)
inlinestatic

◆ msrAddrToIndex()

bool gem5::X86ISA::msrAddrToIndex ( MiscRegIndex regNum,
Addr  addr 
)

Find and return the misc reg corresponding to an MSR address.

Look for an MSR (addr) in msrMap and return the corresponding misc reg in regNum. The value of regNum is undefined if the MSR was not found.

Parameters
regNummisc reg index (out).
addrMSR address
Returns
True if the MSR was found, false otherwise.

Definition at line 150 of file msr.cc.

References addr, and msrMap.

Referenced by gem5::X86ISA::TLB::translateInt(), and gem5::X86ISA::GpuTLB::translateInt().

◆ msrMap()

const MsrMap gem5::X86ISA::msrMap ( msrMapData  ,
msrMapData msrMapSize 
)

◆ opcodeTypeToStr()

static const char* gem5::X86ISA::opcodeTypeToStr ( OpcodeType  type)
inlinestatic

Definition at line 162 of file types.hh.

References type.

Referenced by operator<<().

◆ operator<<()

static std::ostream& gem5::X86ISA::operator<< ( std::ostream &  os,
const ExtMachInst emi 
)
inlinestatic

◆ operator==()

static bool gem5::X86ISA::operator== ( const ExtMachInst emi1,
const ExtMachInst emi2 
)
inlinestatic

◆ readMemAtomic() [1/2]

template<size_t N>
static Fault gem5::X86ISA::readMemAtomic ( ExecContext xc,
Trace::InstRecord traceData,
Addr  addr,
std::array< uint64_t, N > &  mem,
unsigned  dataSize,
unsigned  flags 
)
static

Definition at line 148 of file memhelpers.hh.

References addr, mem, gem5::NoFault, panic, and gem5::Trace::InstRecord::setData().

◆ readMemAtomic() [2/2]

static Fault gem5::X86ISA::readMemAtomic ( ExecContext xc,
Trace::InstRecord traceData,
Addr  addr,
uint64_t &  mem,
unsigned  dataSize,
Request::Flags  flags 
)
static

◆ readPackedMemAtomic()

template<typename T , size_t N>
static Fault gem5::X86ISA::readPackedMemAtomic ( ExecContext xc,
Addr  addr,
std::array< uint64_t, N > &  mem,
unsigned  flags 
)
static

◆ setRFlags()

void gem5::X86ISA::setRFlags ( ThreadContext tc,
uint64_t  val 
)

Set update the rflags register and internal gem5 state.

Note
This function does not update MISCREG_M5_REG. You might need to update this register by writing anything to MISCREG_M5_REG with side-effects.
See also
X86ISA::getRFlags()
Parameters
tcThread context to update
valNew rflags value to store in TC

Definition at line 74 of file utility.cc.

References ccFlagMask, CCREG_CFOF, CCREG_DF, CCREG_ECF, CCREG_EZF, CCREG_ZAPS, cfofMask, DFBit, MISCREG_RFLAGS, gem5::ThreadContext::setCCReg(), gem5::ThreadContext::setMiscReg(), and val.

Referenced by gem5::X86KvmCPU::updateThreadContextRegs().

◆ setThreadArea32Func()

SyscallReturn gem5::X86ISA::setThreadArea32Func ( SyscallDesc desc,
ThreadContext tc,
VPtr< UserDesc32 >  userDesc 
)

◆ storeFloat80()

void gem5::X86ISA::storeFloat80 ( void *  mem,
double  value 
)

Convert and store a double as an 80-bit float.

Parameters
memPointer to destination for the 80-bit float.
valueDouble precision float to store.

Definition at line 165 of file utility.cc.

Referenced by gem5::updateKvmStateFPUCommon().

◆ stringToRegister()

uint64_t gem5::X86ISA::stringToRegister ( const char *  str)

Definition at line 80 of file cpuid.cc.

References reg.

Referenced by doCpuid().

◆ SubBitUnion()

gem5::X86ISA::SubBitUnion ( type  ,
43  ,
40   
)

◆ unameFunc()

SyscallReturn gem5::X86ISA::unameFunc ( SyscallDesc desc,
ThreadContext tc,
VPtr< Linux::utsname name 
)

Target uname() handler.

Definition at line 48 of file syscalls.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

◆ writeMemAtomic() [1/2]

template<size_t N>
static Fault gem5::X86ISA::writeMemAtomic ( ExecContext xc,
Trace::InstRecord traceData,
std::array< uint64_t, N > &  mem,
unsigned  dataSize,
Addr  addr,
unsigned  flags,
uint64_t *  res 
)
static

◆ writeMemAtomic() [2/2]

static Fault gem5::X86ISA::writeMemAtomic ( ExecContext xc,
Trace::InstRecord traceData,
uint64_t  mem,
unsigned  dataSize,
Addr  addr,
Request::Flags  flags,
uint64_t *  res 
)
static

◆ writeMemTiming() [1/2]

template<size_t N>
static Fault gem5::X86ISA::writeMemTiming ( ExecContext xc,
Trace::InstRecord traceData,
std::array< uint64_t, N > &  mem,
unsigned  dataSize,
Addr  addr,
unsigned  flags,
uint64_t *  res 
)
static

Definition at line 200 of file memhelpers.hh.

References addr, mem, panic, and gem5::Trace::InstRecord::setData().

◆ writeMemTiming() [2/2]

static Fault gem5::X86ISA::writeMemTiming ( ExecContext xc,
Trace::InstRecord traceData,
uint64_t  mem,
unsigned  dataSize,
Addr  addr,
Request::Flags  flags,
uint64_t *  res 
)
static

◆ writePackedMem()

template<typename T , size_t N>
static Fault gem5::X86ISA::writePackedMem ( ExecContext xc,
std::array< uint64_t, N > &  mem,
Addr  addr,
unsigned  flags,
uint64_t *  res 
)
static

Definition at line 171 of file memhelpers.hh.

References addr, gem5::htole(), gem5::ArmISA::i, mem, and gem5::ExecContext::writeMem().

◆ x86InterruptAddress()

static Addr gem5::X86ISA::x86InterruptAddress ( const uint8_t  id,
const uint16_t  addr 
)
inlinestatic

◆ x86IOAddress()

static Addr gem5::X86ISA::x86IOAddress ( const uint32_t  port)
inlinestatic

Definition at line 76 of file x86_traits.hh.

References PhysAddrPrefixIO.

Referenced by gem5::X86KvmCPU::handleKvmExitIO().

◆ x86LocalAPICAddress()

static Addr gem5::X86ISA::x86LocalAPICAddress ( const uint8_t  id,
const uint16_t  addr 
)
inlinestatic

◆ x86PciConfigAddress()

static Addr gem5::X86ISA::x86PciConfigAddress ( const uint32_t  addr)
inlinestatic

Definition at line 82 of file x86_traits.hh.

References addr, and PhysAddrPrefixPciConfig.

Referenced by gem5::X86KvmCPU::handleKvmExitIO().

Variable Documentation

◆ a

Bitfield< 40 > gem5::X86ISA::a

Definition at line 146 of file pagetable.hh.

◆ ac

Bitfield<18> gem5::X86ISA::ac

◆ addr

Bitfield<3> gem5::X86ISA::addr

Definition at line 84 of file types.hh.

Referenced by gem5::MemChecker::abortWrite(), gem5::prefetch::SBOOE::Sandbox::access(), gem5::SimpleCache::accessTiming(), gem5::memory::AbstractMemory::addLockedAddr(), gem5::addrBlockAlign(), gem5::addrBlockOffset(), gem5::o3::LSQ::LSQRequest::addRequest(), gem5::ArmISA::VectorCatch::addressMatching(), gem5::ruby::addressOffset(), gem5::ruby::addressToInt(), gem5::ruby::Network::addressToNodeID(), gem5::pseudo_inst::addsymbol(), gem5::memory::MemCtrl::addToReadQueue(), gem5::memory::MemCtrl::addToWriteQueue(), gem5::BaseCache::allocateBlock(), gem5::AtomicSimpleCPU::amoMem(), gem5::SimpleExecContext::amoMem(), gem5::amoMemAtomic(), gem5::amoMemAtomicBE(), gem5::amoMemAtomicLE(), archPrctlFunc(), gem5::ruby::bitSelect(), gem5::BaseTags::blkAlign(), gem5::MemTest::blockAlign(), gem5::ruby::AbstractController::blockOnQueue(), gem5::PowerISA::BranchOp::branchTarget(), gem5::PowerISA::BranchDispCondOp::branchTarget(), gem5::PowerISA::BranchRegCondOp::branchTarget(), buildIntPacket(), buildIntTriggerPacket(), gem5::memory::MemCtrl::burstAlign(), gem5::SMMUTranslationProcess::bypass(), gem5::Gcn3ISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_DS::calcAddr(), gem5::Gcn3ISA::Inst_DS::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddr(), gem5::Gcn3ISA::Inst_FLAT::calcAddr(), gem5::prefetch::IrregularStreamBuffer::calculatePrefetch(), gem5::prefetch::BOP::calculatePrefetch(), gem5::prefetch::IndirectMemory::calculatePrefetch(), gem5::ArmSemihosting::callGetCmdLine(), gem5::ArmSemihosting::callRead(), gem5::ArmSemihosting::callTmpNam(), gem5::ArmSemihosting::callWrite(), gem5::memory::DRAMsim3Wrapper::canAccept(), gem5::prefetch::IndirectMemory::checkAccessMatchOnActiveEntries(), gem5::ArmISA::TableWalker::checkAddrSizeFaultAArch64(), gem5::ruby::CacheMemory::checkResourceAvailable(), gem5::decode_cache::AddrMap< gem5::GenericISA::BasicDecodeCache::AddrMapEntry >::chunkOffset(), gem5::decode_cache::AddrMap< gem5::GenericISA::BasicDecodeCache::AddrMapEntry >::chunkStart(), gem5::GenericPciHost::clearInt(), gem5::BaseRemoteGDB::cmdClrHwBkpt(), gem5::BaseRemoteGDB::cmdMemR(), gem5::BaseRemoteGDB::cmdMemW(), gem5::BaseRemoteGDB::cmdSetHwBkpt(), gem5::prefetch::PIF::CompactorEntry::CompactorEntry(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::MemChecker::completeRead(), gem5::MemChecker::completeWrite(), gem5::connectFunc(), gem5::loader::MemoryImage::contains(), gem5::GenericTimerMem::counterCtrlRead(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::GenericTimerMem::counterStatusRead(), gem5::GenericTimerMem::counterStatusWrite(), gem5::prefetch::Queued::createPrefetchRequest(), gem5::GenericISA::BasicDecodeCache< gem5::ArmISA::Decoder, gem5::X86ISA::ExtMachInst >::decode(), gem5::RiscvISA::Decoder::decode(), gem5::PowerISA::Decoder::decode(), gem5::MipsISA::Decoder::decode(), gem5::SparcISA::Decoder::decode(), gem5::ArmISA::Decoder::decode(), gem5::GenericPciHost::decodeAddress(), gem5::memory::MemInterface::decodePacket(), gem5::ruby::MessageBuffer::deferEnqueueingMessage(), gem5::SkewedAssociative::dehash(), gem5::X86ISA::PageFault::describe(), gem5::SkewedAssociative::deskew(), gem5::IdeController::dispatchAccess(), gem5::DmaPort::dmaAction(), gem5::PciHost::DeviceInterface::dmaAddr(), gem5::DmaDevice::dmaRead(), gem5::DmaVirtDevice::dmaVirt(), gem5::DmaDevice::dmaWrite(), gem5::SMMUProcess::doRead(), gem5::ItsProcess::doRead(), gem5::SMMUTranslationProcess::doReadConfig(), gem5::SMMUTranslationProcess::doReadPTE(), gem5::SMMUProcess::doWrite(), gem5::ItsProcess::doWrite(), gem5::BaseStackTrace::dump(), gem5::Trace::IntelTraceRecord::dump(), gem5::ProfileNode::dump(), gem5::memory::DRAMsim3Wrapper::enqueue(), gem5::memory::DRAMSim2Wrapper::enqueue(), gem5::ruby::MessageBuffer::enqueueDeferredMessages(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), gem5::Gcn3ISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORD::execute(), gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2::execute(), gem5::Gcn3ISA::Inst_SMEM__S_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE2_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE2ST64_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B8::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B16::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B8::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B16::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ2_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ2ST64_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ_U8::execute(), gem5::VegaISA::Inst_DS__DS_READ2_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ2ST64_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ_U16::execute(), gem5::VegaISA::Inst_DS__DS_READ_U8::execute(), gem5::Gcn3ISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ_U16::execute(), gem5::Gcn3ISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE2_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ2_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ2ST64_B64::execute(), gem5::VegaISA::Inst_DS__DS_READ_B64::execute(), gem5::VegaISA::Inst_DS__DS_READ2_B64::execute(), gem5::VegaISA::Inst_DS__DS_READ2ST64_B64::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B96::execute(), gem5::Gcn3ISA::Inst_DS__DS_WRITE_B128::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ_B96::execute(), gem5::Gcn3ISA::Inst_DS__DS_READ_B128::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_UBYTE::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_SBYTE::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_USHORT::execute(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_UBYTE::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORD::execute(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_USHORT::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX3::execute(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORD::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_BYTE::execute(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX3::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_SHORT::execute(), gem5::VegaISA::Inst_FLAT__FLAT_LOAD_DWORDX4::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORD::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_BYTE::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_SHORT::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX3::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORD::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_STORE_DWORDX4::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SWAP::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX3::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute(), gem5::VegaISA::Inst_FLAT__FLAT_STORE_DWORDX4::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD::execute(), gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_SWAP::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB::execute(), gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP::execute(), gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_SUB_X2::execute(), gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_CMPSWAP_X2::execute(), gem5::VegaISA::Inst_FLAT__FLAT_ATOMIC_ADD_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_INC_X2::execute(), gem5::Gcn3ISA::Inst_FLAT__FLAT_ATOMIC_DEC_X2::execute(), gem5::exitFutexWake(), gem5::BaseTags::extractBlkOffset(), gem5::SectorTags::extractSectorOffset(), gem5::SetAssociative::extractSet(), gem5::SkewedAssociative::extractSet(), gem5::prefetch::StridePrefetcherHashedSetAssociative::extractTag(), gem5::BaseIndexingPolicy::extractTag(), gem5::FALRU::extractTag(), gem5::BaseTags::extractTag(), gem5::o3::Fetch::fetchBufferAlignPC(), gem5::SectorTags::findBlock(), gem5::BaseTags::findBlock(), gem5::FALRU::findBlock(), gem5::AssociativeSet< gem5::prefetch::SignaturePath::PatternEntry >::findEntry(), gem5::loader::SymbolTable::findNearest(), gem5::AssociativeSet< gem5::prefetch::SignaturePath::PatternEntry >::findVictim(), gem5::CompressedTags::findVictim(), gem5::BaseSetAssoc::findVictim(), gem5::SectorTags::findVictim(), gem5::SnoopFilter::finishRequest(), gem5::Workload::fixFuncEventAddr(), gem5::ArmISA::FsWorkload::fixFuncEventAddr(), gem5::SETranslatingPortProxy::fixupAddr(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::Gicv2m::frameFromAddr(), gem5::ruby::RubySystem::functionalWrite(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value > >::get(), gem5::ArmSemihosting::AbiBase::StateBase< Arg >::getAddr(), gem5::Gicv2m::getAddrRanges(), gem5::PciDevice::getBAR(), gem5::MemChecker::getByteTracker(), gem5::prefetch::DeltaCorrelatingPredictionTables::DCPTEntry::getCandidates(), gem5::decode_cache::AddrMap< gem5::GenericISA::BasicDecodeCache::AddrMapEntry >::getChunk(), gem5::bloom_filter::MultiBitSel::getCount(), gem5::bloom_filter::Block::getCount(), gem5::bloom_filter::Perfect::getCount(), gem5::bloom_filter::Multi::getCount(), gem5::memory::MemInterface::getCtrlAddr(), gem5::PciHost::getDevice(), gem5::RandomGen::getNextPacket(), gem5::ruby::getOffset(), gem5::BaseKvmCPU::getOneReg(), gem5::BaseGen::getPacket(), gem5::AssociativeSet< gem5::prefetch::SignaturePath::PatternEntry >::getPossibleEntries(), gem5::SetAssociative::getPossibleEntries(), gem5::SkewedAssociative::getPossibleEntries(), gem5::Gicv3::getRedistributorByAddr(), gem5::BaseStackTrace::getSymbol(), gem5::SparcISA::TLB::GetTsbPtr(), gem5::BaseCache::handleFill(), gem5::DmaPort::handleResp(), gem5::prefetch::Base::hasBeenPrefetched(), gem5::BaseCache::hasBeenPrefetched(), gem5::bloom_filter::H3::hash(), gem5::bloom_filter::Bulk::hash(), gem5::bloom_filter::MultiBitSel::hash(), gem5::bloom_filter::Block::hash(), gem5::SkewedAssociative::hash(), gem5::prefetch::BOP::hash(), gem5::ruby::MessageBuffer::hasStalledMsg(), gem5::DmaThread::hitCallback(), gem5::GpuWavefront::hitCallback(), gem5::RubyDirectedTester::hitCallback(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::o3::CPU::htmSendAbortSignal(), gem5::prefetch::Base::inCache(), gem5::BaseCache::inCache(), gem5::ruby::AbstractController::incomingTransactionEnd(), gem5::ruby::AbstractController::incomingTransactionStart(), tlm::tlm_dmi::init(), gem5::TimingSimpleCPU::initiateHtmCmd(), gem5::minor::ExecContext::initiateMemAMO(), gem5::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::o3::DynInst::initiateMemAMO(), gem5::SimpleExecContext::initiateMemAMO(), initiateMemRead(), gem5::initiateMemRead(), gem5::minor::ExecContext::initiateMemRead(), gem5::TimingSimpleCPU::initiateMemRead(), gem5::o3::DynInst::initiateMemRead(), gem5::SimpleExecContext::initiateMemRead(), gem5::ArmLinuxProcess32::initState(), gem5::prefetch::Base::inMissQueue(), gem5::BaseCache::inMissQueue(), gem5::BaseCache::inRange(), gem5::TempCacheBlk::insert(), gem5::MemFootprintProbe::insertAddr(), gem5::AssociativeSet< gem5::prefetch::SignaturePath::PatternEntry >::insertEntry(), gem5::BaseRemoteGDB::insertHardBreak(), gem5::prefetch::BOP::insertIntoRR(), gem5::BaseRemoteGDB::insertSoftBreak(), gem5::ruby::intToAddress(), gem5::RiscvISA::RiscvFault::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::ruby::VIPERCoalescer::invTCP(), gem5::ioctlFunc(), gem5::ruby::AbstractController::isBlocked(), gem5::isCanonicalAddress(), gem5::ruby::MessageBuffer::isDeferredMsgMapEmpty(), gem5::ArmISA::WatchPoint::isDoubleAligned(), gem5::Shader::isGpuVmApe(), gem5::Shader::isLdsApe(), gem5::memory::PhysicalMemory::isMemAddr(), gem5::System::isMemAddr(), gem5::TesterThread::isNextActionReady(), gem5::ruby::RubyPort::MemResponsePort::isPhysMemAddress(), gem5::AMDMMIOReader::isRelevant(), gem5::AMDGPUDevice::isROM(), gem5::Shader::isScratchApe(), gem5::bloom_filter::Multi::isSet(), gem5::bloom_filter::Base::isSet(), gem5::ruby::RubyPort::MemResponsePort::isShadowRomAddress(), gem5::SMMUTranslationProcess::issuePrefetch(), gem5::PMAChecker::isUncacheable(), gem5::pseudo_inst::loadsymbol(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::qos::MemCtrl::logResponse(), gem5::decode_cache::AddrMap< gem5::GenericISA::BasicDecodeCache::AddrMapEntry >::lookup(), gem5::ruby::lookupTraceForAddress(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ruby::makeLineAddress(), gem5::ruby::makeNextStrideAddress(), gem5::ruby::AbstractController::mapAddressToDownstreamMachine(), gem5::ruby::AbstractController::mapAddressToMachine(), gem5::ruby::mapAddressToRange(), gem5::GenericArmPciHost::mapPciInterrupt(), gem5::GenericPciHost::mapPciInterrupt(), gem5::ruby::maskLowOrderBits(), gem5::WriteQueueEntry::matchBlockAddr(), gem5::MSHR::matchBlockAddr(), gem5::PciHost::DeviceInterface::memAddr(), gem5::PortProxy::memsetBlob(), gem5::PortProxy::memsetBlobPhys(), msrAddrToIndex(), gem5::BaseCPU::mwaitAtomic(), gem5::operator<<(), Access::operator==(), gem5::ruby::AbstractController::outgoingTransactionEnd(), gem5::ruby::AbstractController::outgoingTransactionStart(), gem5::X86ISA::LongModePTE::paddr(), gem5::ArmISA::TableWalker::LongDescriptor::paddr(), gem5::ruby::RubyPrefetcher::pageAddress(), gem5::Iris::ThreadContext::pcState(), gem5::bloom_filter::Bulk::permute(), gem5::PciHost::DeviceInterface::pioAddr(), gem5::TesterThread::popOutstandingReq(), gem5::GenericPciHost::postInt(), gem5::ruby::printAddress(), gem5::ArmISA::ArmStaticInst::printMemSymbol(), gem5::SMMUv3::processCommand(), gem5::ArmISA::purifyTaggedAddr(), gem5::o3::CPU::pushRequest(), gem5::minor::LSQ::pushRequest(), gem5::o3::LSQ::pushRequest(), BackingStore::rangeCheck(), gem5::SimpleDisk::read(), gem5::Sp805::read(), gem5::NoMaliGpu::read(), gem5::GenericWatchdog::read(), gem5::FVPBasePwrCtrl::read(), gem5::Gicv3::read(), gem5::X86ISA::I8042::read(), gem5::MHU::read(), gem5::Gicv3Its::read(), gem5::VGic::read(), gem5::Gicv3Redistributor::read(), gem5::Gicv3Distributor::read(), gem5::BaseRemoteGDB::read(), gem5::GenericTimerFrame::read(), gem5::GicV2::read(), gem5::GenericTimerMem::read(), gem5::RegisterBank< ByteOrder::little >::read(), gem5::MHU::read32(), gem5::PortProxy::readBlob(), gem5::PortProxy::readBlobPhys(), gem5::memory::DRAMSim2::readComplete(), gem5::memory::DRAMsim3::readComplete(), gem5::GenericWatchdog::readControl(), gem5::MC146818::readData(), gem5::AtomicSimpleCPU::readMem(), gem5::SimpleExecContext::readMem(), gem5::CheckerCPU::readMem(), gem5::readMemAtomic(), readMemAtomic(), gem5::readMemAtomicBE(), gem5::readMemAtomicLE(), readPackedMemAtomic(), gem5::GenericWatchdog::readRefresh(), gem5::PortProxy::readString(), gem5::ruby::MessageBuffer::reanalyzeMessages(), gem5::ruby::CacheMemory::recordRequestType(), gem5::SMMUControlPort::recvAtomic(), gem5::MemCheckerMonitor::recvFunctional(), gem5::MemCheckerMonitor::recvFunctionalSnoop(), gem5::MemCheckerMonitor::recvTimingReq(), gem5::CoherentXBar::recvTimingReq(), gem5::MemCheckerMonitor::recvTimingResp(), gem5::RealViewCtrl::registerDevice(), gem5::RangeAddrMapper::remapAddr(), gem5::BaseRemoteGDB::removeHardBreak(), gem5::BaseRemoteGDB::removeSoftBreak(), gem5::MemChecker::reset(), gem5::ruby::AbstractController::respondsTo(), gem5::MipsISA::RoundPage(), gem5::ArmISA::roundPage(), SC_MODULE(), gem5::TraceCPU::FixedRetryGen::send(), gem5::bloom_filter::MultiBitSel::set(), gem5::bloom_filter::Perfect::set(), gem5::bloom_filter::Block::set(), gem5::bloom_filter::Multi::set(), gem5::ruby::SubBlock::setAddress(), gem5::ruby::AccessTraceForAddress::setAddress(), gem5::VirtQueue::VirtRing< struct vring_used_elem >::setAddress(), gem5::X86ISA::TLB::setConfigAddress(), gem5::X86ISA::GpuTLB::setConfigAddress(), gem5::BaseKvmCPU::setOneReg(), gem5::ArmSystem::setResetAddr(), gem5::X86ISA::intelmp::FloatingPointer::setTableAddr(), gem5::X86ISA::smbios::SMBiosTable::setTableAddr(), gem5::MipsISA::setThreadAreaFunc(), gem5::X86ISA::Walker::WalkerState::setupWalk(), gem5::SkewedAssociative::skew(), gem5::ruby::AbstractController::stallBuffer(), gem5::ruby::MessageBuffer::stallMessage(), gem5::RiscvISA::Walker::WalkerState::startFunctional(), gem5::X86ISA::Walker::WalkerState::startFunctional(), gem5::RiscvISA::Walker::startFunctional(), gem5::X86ISA::Walker::startFunctional(), gem5::MemChecker::startRead(), gem5::MemChecker::startWrite(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value > >::store(), gem5::ruby::StoreTrace::StoreTrace(), gem5::ruby::SubBlock::SubBlock(), gem5::FutexMap::suspend(), gem5::FutexMap::suspend_bitset(), gem5::prefetch::BOP::tag(), gem5::ArmISA::WatchPoint::test(), TEST(), gem5::ruby::testAndRead(), gem5::ruby::testAndReadMask(), gem5::ruby::testAndWrite(), gem5::prefetch::BOP::testRR(), gem5::ArmISA::SelfDebug::testVectorCatch(), gem5::GenericTimerMem::timerCtrlRead(), gem5::GenericTimerMem::timerCtrlWrite(), gem5::GenericTimerFrame::timerRead(), gem5::GenericTimerFrame::timerWrite(), gem5::memory::AbstractMemory::toHostAddr(), gem5::AMDMMIOReader::traceGetBAR(), gem5::AMDMMIOReader::traceGetOffset(), gem5::Trace::ExeTracerRecord::traceInst(), gem5::transferNeedsBurst(), gem5::X86ISA::TLB::translateFunctional(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), gem5::MipsISA::TruncPage(), gem5::ArmISA::truncPage(), gem5::BaseStackTrace::tryGetSymbol(), gem5::PortProxy::tryMemsetBlob(), gem5::TranslatingPortProxy::tryReadBlob(), gem5::PortProxy::tryReadBlob(), gem5::PortProxy::tryReadString(), gem5::tryTranslate(), gem5::TranslatingPortProxy::tryWriteBlob(), gem5::PortProxy::tryWriteBlob(), gem5::PortProxy::tryWriteString(), gem5::ruby::AbstractController::unblock(), gem5::bloom_filter::Perfect::unset(), gem5::bloom_filter::Block::unset(), gem5::bloom_filter::Multi::unset(), gem5::ComputeUnit::updatePageDivergenceDist(), gem5::loader::SymbolTable::upperBound(), gem5::TesterThread::validateAtomicResp(), gem5::TesterThread::validateLoadResp(), gem5::FutexMap::wakeup(), gem5::FutexMap::wakeup_bitset(), gem5::ruby::AbstractController::wakeUpAllBuffers(), gem5::ruby::AbstractController::wakeUpBuffer(), gem5::ruby::AbstractController::wakeUpBuffers(), gem5::SMMUTranslationProcess::walkCacheLookup(), gem5::SMMUTranslationProcess::walkStage1And2(), gem5::SMMUTranslationProcess::walkStage2(), gem5::Sp805::write(), gem5::NoMaliGpu::write(), gem5::GenericWatchdog::write(), gem5::FVPBasePwrCtrl::write(), gem5::Gicv3::write(), gem5::X86ISA::ACPI::RSDP::write(), gem5::X86ISA::I8042::write(), gem5::MHU::write(), gem5::Gicv3Its::write(), gem5::VGic::write(), gem5::Gicv3Redistributor::write(), gem5::Gicv3Distributor::write(), gem5::BaseRemoteGDB::write(), gem5::GenericTimerFrame::write(), gem5::GicV2::write(), gem5::GenericTimerMem::write(), gem5::RegisterBank< ByteOrder::little >::write(), gem5::PortProxy::writeBlob(), gem5::PortProxy::writeBlobPhys(), gem5::X86ISA::ACPI::SysDescTable::writeBuf(), gem5::memory::DRAMSim2::writeComplete(), gem5::memory::DRAMsim3::writeComplete(), gem5::ruby::VIPERCoalescer::writeCompleteCallback(), gem5::GenericWatchdog::writeControl(), gem5::MC146818::writeData(), gem5::minor::ExecContext::writeMem(), gem5::AtomicSimpleCPU::writeMem(), gem5::TimingSimpleCPU::writeMem(), gem5::o3::DynInst::writeMem(), gem5::SimpleExecContext::writeMem(), gem5::CheckerCPU::writeMem(), gem5::writeMemAtomic(), writeMemAtomic(), gem5::writeMemAtomicBE(), gem5::writeMemAtomicLE(), gem5::writeMemTiming(), writeMemTiming(), gem5::writeMemTimingBE(), gem5::writeMemTimingLE(), gem5::X86ISA::smbios::SMBiosStructure::writeOut(), gem5::X86ISA::intelmp::FloatingPointer::writeOut(), gem5::X86ISA::intelmp::BaseConfigEntry::writeOut(), gem5::X86ISA::intelmp::ExtConfigEntry::writeOut(), gem5::X86ISA::smbios::BiosInformation::writeOut(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::intelmp::Processor::writeOut(), gem5::X86ISA::intelmp::Bus::writeOut(), gem5::X86ISA::intelmp::IOAPIC::writeOut(), gem5::X86ISA::smbios::SMBiosTable::writeOut(), gem5::X86ISA::intelmp::IntAssignment::writeOut(), gem5::X86ISA::intelmp::AddrSpaceMapping::writeOut(), gem5::X86ISA::intelmp::BusHierarchy::writeOut(), gem5::X86ISA::intelmp::CompatAddrSpaceMod::writeOut(), gem5::writeOutField(), gem5::writeOutString(), gem5::X86ISA::smbios::SMBiosStructure::writeOutStrings(), writePackedMem(), gem5::GenericWatchdog::writeRefresh(), gem5::PortProxy::writeString(), gem5::X86ISA::E820Table::writeTo(), gem5::writeVal(), x86InterruptAddress(), x86LocalAPICAddress(), and x86PciConfigAddress().

◆ addrv

Bitfield<58> gem5::X86ISA::addrv

Definition at line 770 of file misc.hh.

◆ af

Bitfield< 4 > gem5::X86ISA::af

Definition at line 554 of file misc.hh.

◆ altAddr

Bitfield<15, 14> gem5::X86ISA::altAddr

Definition at line 592 of file misc.hh.

◆ altOp

Bitfield<11, 10> gem5::X86ISA::altOp

Definition at line 590 of file misc.hh.

◆ am

Bitfield<18> gem5::X86ISA::am

Definition at line 603 of file misc.hh.

◆ AO

const uint8_t gem5::X86ISA::AO = AddressSizeOverride

Definition at line 54 of file decoder_tables.cc.

◆ avl

Bitfield< 5 > gem5::X86ISA::avl

Definition at line 142 of file pagetable.hh.

◆ b

Bitfield< 5 > gem5::X86ISA::b

Definition at line 925 of file misc.hh.

◆ b1

Bitfield<1> gem5::X86ISA::b1

Definition at line 653 of file misc.hh.

◆ b2

Bitfield<2> gem5::X86ISA::b2

Definition at line 654 of file misc.hh.

◆ b3

Bitfield<3> gem5::X86ISA::b3

Definition at line 655 of file misc.hh.

◆ badMicroop

const StaticInstPtr gem5::X86ISA::badMicroop
Initial value:
=
new MicroDebug(dummyMachInst, "panic", "BAD",
StaticInst::IsMicroop | StaticInst::IsLastMicroop,
new GenericISA::M5PanicFault("Invalid microop!"))

Definition at line 59 of file badmicroop.cc.

Referenced by gem5::X86ISAInst::MicrocodeRom::fetchMicroop(), and gem5::X86ISA::MacroopBase::fetchMicroop().

◆ base

Bitfield< 2, 0 > gem5::X86ISA::base

Definition at line 141 of file pagetable.hh.

Referenced by gem5::ruby::addressOffset(), gem5::statistics::Hdf5::beginGroup(), gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp(), gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp(), gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::X86ISA::Interrupts::clearRegArrayBit(), gem5::SMMUTranslationProcess::doReadPTE(), gem5::dumpDmesgEntry(), EndBitUnion(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::X86ISA::Interrupts::findRegArrayMSB(), sc_dt::scfx_rep::from_string(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::get(), gem5::X86ISA::Interrupts::getRegArrayBit(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::X86ISA::FsWorkload::initState(), gem5::compression::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), gem5::statistics::VectorPrint::operator()(), gem5::statistics::DistPrint::operator()(), gem5::statistics::SparseHistPrint::operator()(), gem5::Gicv3Its::pageAddress(), sc_gem5::Object::pickUniqueName(), sc_gem5::pickUniqueName(), gem5::PMP::pmpDecodeNapot(), gem5::X86ISA::X86StaticInst::printMem(), BackingStore::rangeCheck(), BackingStore::readBlob(), gem5::ItsProcess::readDeviceTable(), gem5::ItsProcess::readIrqCollectionTable(), gem5::X86ISA::ISA::readMiscReg(), gem5::PacketFifoEntry::serialize(), gem5::EthPacketData::serialize(), gem5::EtherLink::Link::serialize(), gem5::IdeController::Channel::serialize(), gem5::MC146818::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::Time::serialize(), gem5::PacketFifo::serialize(), gem5::Intel8254Timer::serialize(), gem5::loader::SymbolTable::serialize(), gem5::X86ISA::Interrupts::setRegArrayBit(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ArmISA::SyscallTable32::SyscallTable32(), gem5::ArmISA::SyscallTable64::SyscallTable64(), gem5::MemTest::tick(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::PacketFifoEntry::unserialize(), gem5::EthPacketData::unserialize(), gem5::EtherLink::Link::unserialize(), gem5::IdeController::Channel::unserialize(), gem5::MC146818::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::Time::unserialize(), gem5::PacketFifo::unserialize(), gem5::Intel8254Timer::unserialize(), gem5::loader::SymbolTable::unserialize(), BackingStore::writeBlob(), gem5::Packet::writeData(), gem5::ItsProcess::writeDeviceTable(), gem5::ItsProcess::writeIrqCollectionTable(), and gem5::X86ISA::smbios::SMBiosTable::writeOut().

◆ baseHigh

gem5::X86ISA::baseHigh

Definition at line 920 of file misc.hh.

◆ baseLow

Bitfield< 39, 16 > gem5::X86ISA::baseLow

Definition at line 921 of file misc.hh.

◆ bd

Bitfield<13> gem5::X86ISA::bd

Definition at line 656 of file misc.hh.

◆ bottom3

Bitfield<2,0> gem5::X86ISA::bottom3

Definition at line 182 of file types.hh.

◆ bs

Bitfield<14> gem5::X86ISA::bs

Definition at line 657 of file misc.hh.

◆ bsp

Bitfield<8> gem5::X86ISA::bsp

Definition at line 1058 of file misc.hh.

◆ bt

Bitfield<15> gem5::X86ISA::bt

Definition at line 658 of file misc.hh.

◆ btf

Bitfield<1> gem5::X86ISA::btf

Definition at line 721 of file misc.hh.

◆ c

Bitfield< 42 > gem5::X86ISA::c

Definition at line 939 of file misc.hh.

◆ ccFlagMask

const uint32_t gem5::X86ISA::ccFlagMask = PFBit | AFBit | ZFBit | SFBit

Definition at line 71 of file misc.hh.

Referenced by setRFlags().

◆ cd

Bitfield<30> gem5::X86ISA::cd

Definition at line 601 of file misc.hh.

◆ cf

Bitfield< 0 > gem5::X86ISA::cf

Definition at line 557 of file misc.hh.

◆ cfofMask

const uint32_t gem5::X86ISA::cfofMask = CFBit | OFBit

Definition at line 70 of file misc.hh.

Referenced by setRFlags().

◆ contents

Bitfield<2, 1> gem5::X86ISA::contents

Definition at line 50 of file syscalls.hh.

◆ count

Bitfield< 36, 32 > gem5::X86ISA::count

Definition at line 709 of file misc.hh.

Referenced by gem5::FlashDevice::accessDevice(), sc_gem5::VcdTraceFile::addTraceVal(), gem5::Aapcs32Vfp::State::allocate(), gem5::fastmodel::PL330::allocateIrq(), gem5::o3::Commit::commitInsts(), gem5::ruby::countBoolVec(), gem5::fastmodel::SCGIC::Terminator::countUnbound(), gem5::Gcn3ISA::dppInstImpl(), gem5::VegaISA::dppInstImpl(), gem5::IGbE::drain(), gem5::FunctionProfile::dump(), gem5::guest_abi::dumpArgsFrom(), gem5::loader::ElfObject::ElfObject(), gem5::UFSHostDevice::finalUTP(), gem5::Gcn3ISA::firstOppositeSignBit(), gem5::VegaISA::firstOppositeSignBit(), gem5::X86ISA::InstOperands< X86MicroopBase >::generateDisassembly(), gem5::bloom_filter::MultiBitSel::getCount(), gem5::bloom_filter::Multi::getCount(), gem5::Iris::ThreadContext::getCurrentInstCount(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::LocalBP::getPrediction(), gem5::bloom_filter::Multi::getTotalCount(), gem5::bloom_filter::Base::getTotalCount(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::FlashDevice::initializeFlash(), gem5::ruby::UncoalescedTable::initPacketsRemaining(), gem5::bloom_filter::Multi::isSet(), gem5::UFSHostDevice::manageReadTransfer(), gem5::UFSHostDevice::manageWriteTransfer(), gem5::BasePixelPump::nextLine(), gem5::System::Threads::numActive(), gem5::System::Threads::numRunning(), gem5::MipsISA::Interrupts::onCpuTimerInterrupt(), gem5::StackDistCalc::printStack(), gem5::prefetch::Queued::processMissingTranslations(), gem5::ruby::AddressProfiler::profileRetry(), gem5::SimpleDisk::read(), gem5::Intel8254Timer::Counter::read(), gem5::UFSHostDevice::UFSSCSIDevice::readFlash(), gem5::AMDMMIOReader::readFromTrace(), gem5::readvFunc(), gem5::FlashDevice::remap(), gem5::UFSHostDevice::requestHandler(), gem5::FutexMap::requeue(), gem5::SafeRead(), gem5::SafeWrite(), SC_MODULE(), gem5::o3::ThreadContext::scheduleInstCountEvent(), gem5::CheckerThreadContext< TC >::scheduleInstCountEvent(), gem5::Iris::ThreadContext::scheduleInstCountEvent(), gem5::SimpleThread::scheduleInstCountEvent(), gem5::UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), gem5::UFSHostDevice::SCSIResume(), gem5::FlashDevice::serialize(), gem5::EmulationPageTable::serialize(), gem5::MemState::serialize(), gem5::sinic::Device::serialize(), gem5::ActivityRecorder::setActivityCount(), gem5::ruby::UncoalescedTable::setPacketsRemaining(), gem5::CacheBlk::setRefCount(), gem5::UFSHostDevice::UFSSCSIDevice::statusCheck(), gem5::Iris::BaseCPU::totalInsts(), gem5::FlashDevice::unserialize(), gem5::EmulationPageTable::unserialize(), gem5::MemState::unserialize(), gem5::ActivityRecorder::validate(), gem5::Checker< gem5::RefCountingPtr >::verify(), sc_gem5::Process::waitCount(), gem5::FutexMap::wakeup(), gem5::UFSHostDevice::UFSSCSIDevice::writeFlash(), gem5::AMDMMIOReader::writeFromTrace(), and gem5::writevFunc().

◆ counterMask

Bitfield<31,24> gem5::X86ISA::counterMask

Definition at line 815 of file misc.hh.

◆ cpl

Bitfield<5, 4> gem5::X86ISA::cpl

Definition at line 586 of file misc.hh.

◆ CS

const uint8_t gem5::X86ISA::CS = CSOverride

Definition at line 46 of file decoder_tables.cc.

Referenced by SC_MODULE().

◆ d

Bitfield< 54 > gem5::X86ISA::d

Definition at line 145 of file pagetable.hh.

◆ de

Bitfield<3> gem5::X86ISA::de

Definition at line 641 of file misc.hh.

Referenced by gem5::dumpDmesgEntry(), and gem5::OutputDirectory::remove().

◆ decodeVal

gem5::X86ISA::decodeVal

Definition at line 79 of file types.hh.

◆ defAddr

Bitfield<13, 12> gem5::X86ISA::defAddr

Definition at line 591 of file misc.hh.

◆ defaultSize

Bitfield<3> gem5::X86ISA::defaultSize

Definition at line 994 of file misc.hh.

◆ defOp

Bitfield<9, 8> gem5::X86ISA::defOp

Definition at line 589 of file misc.hh.

◆ delivery_mode

gem5::X86ISA::delivery_mode

Definition at line 55 of file intmessage.hh.

◆ deliveryMode

Bitfield< 10, 8 > gem5::X86ISA::deliveryMode

Definition at line 49 of file intmessage.hh.

Referenced by gem5::X86ISA::Interrupts::requestInterrupt().

◆ deliveryStatus

Bitfield<12> gem5::X86ISA::deliveryStatus

Definition at line 97 of file apic.hh.

◆ destination

gem5::X86ISA::destination

◆ destMode

Bitfield< 11 > gem5::X86ISA::destMode

Definition at line 50 of file intmessage.hh.

◆ destShorthand

Bitfield<19, 18> gem5::X86ISA::destShorthand

Definition at line 100 of file apic.hh.

◆ df

Bitfield<10> gem5::X86ISA::df

Definition at line 573 of file misc.hh.

◆ disA20M

Bitfield<2> gem5::X86ISA::disA20M

Definition at line 843 of file misc.hh.

◆ dpl

Bitfield< 46, 45 > gem5::X86ISA::dpl

Definition at line 932 of file misc.hh.

◆ DS

const uint8_t gem5::X86ISA::DS = DSOverride

Definition at line 47 of file decoder_tables.cc.

◆ E

Bitfield<31,0> gem5::X86ISA::E

Definition at line 53 of file int.hh.

Referenced by gem5::ArmISA::ArmStaticInst::cSwap().

◆ e

Bitfield< 42 > gem5::X86ISA::e

Definition at line 759 of file misc.hh.

Referenced by gem5::dumpKvm().

◆ ecf

Bitfield<3> gem5::X86ISA::ecf

Definition at line 555 of file misc.hh.

◆ eipv

Bitfield<1> gem5::X86ISA::eipv

Definition at line 715 of file misc.hh.

◆ em

Bitfield<2> gem5::X86ISA::em

Definition at line 608 of file misc.hh.

◆ en

Bitfield< 22 > gem5::X86ISA::en

Definition at line 772 of file misc.hh.

◆ enable

Bitfield<11> gem5::X86ISA::enable

◆ enter

Bitfield<1> gem5::X86ISA::enter

Definition at line 852 of file misc.hh.

◆ ES

const uint8_t gem5::X86ISA::ES = ESOverride

Definition at line 48 of file decoder_tables.cc.

◆ esi

gem5::X86ISA::esi

Definition at line 865 of file misc.hh.

◆ et

Bitfield<4> gem5::X86ISA::et

Definition at line 606 of file misc.hh.

◆ eventMask

gem5::X86ISA::eventMask

Definition at line 806 of file misc.hh.

◆ exit

Bitfield<3> gem5::X86ISA::exit

◆ expandDown

Bitfield<14> gem5::X86ISA::expandDown

Definition at line 1002 of file misc.hh.

Referenced by gem5::X86ISA::TLB::translate(), and gem5::X86ISA::GpuTLB::translate().

◆ ezf

Bitfield<5> gem5::X86ISA::ezf

Definition at line 553 of file misc.hh.

◆ fe

Bitfield<10> gem5::X86ISA::fe

Definition at line 758 of file misc.hh.

◆ ffxsr

Bitfield<14> gem5::X86ISA::ffxsr

Definition at line 792 of file misc.hh.

◆ fix

Bitfield<8> gem5::X86ISA::fix

Definition at line 686 of file misc.hh.

◆ FlagShift

const int gem5::X86ISA::FlagShift = 4

◆ FS

const uint8_t gem5::X86ISA::FS = FSOverride

Definition at line 49 of file decoder_tables.cc.

◆ fsgsbase

Bitfield<16> gem5::X86ISA::fsgsbase

Definition at line 631 of file misc.hh.

◆ g

Bitfield< 55 > gem5::X86ISA::g

Definition at line 143 of file pagetable.hh.

Referenced by gem5::X86ISA::SegDescriptorLimit::setter().

◆ g0

Bitfield<1> gem5::X86ISA::g0

Definition at line 663 of file misc.hh.

◆ g1

Bitfield<3> gem5::X86ISA::g1

Definition at line 665 of file misc.hh.

◆ g2

Bitfield<5> gem5::X86ISA::g2

Definition at line 667 of file misc.hh.

◆ g3

Bitfield<7> gem5::X86ISA::g3

Definition at line 669 of file misc.hh.

◆ gd

Bitfield<13> gem5::X86ISA::gd

Definition at line 672 of file misc.hh.

◆ GDTVirtAddr

const Addr gem5::X86ISA::GDTVirtAddr = 0xffff800000001000

Definition at line 41 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

◆ ge

Bitfield<9> gem5::X86ISA::ge

Definition at line 671 of file misc.hh.

◆ granularity

Bitfield<6> gem5::X86ISA::granularity

Definition at line 997 of file misc.hh.

◆ GS

const uint8_t gem5::X86ISA::GS = GSOverride

Definition at line 50 of file decoder_tables.cc.

◆ H

Bitfield<15,8> gem5::X86ISA::H

Definition at line 57 of file int.hh.

◆ IDTVirtAddr

const Addr gem5::X86ISA::IDTVirtAddr = 0xffff800000002000

Definition at line 42 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

◆ index

Bitfield<5,3> gem5::X86ISA::index

◆ IntAddrPrefixCPUID

const Addr gem5::X86ISA::IntAddrPrefixCPUID = 0x100000000ULL

◆ IntAddrPrefixIO

const Addr gem5::X86ISA::IntAddrPrefixIO = 0x300000000ULL

◆ IntAddrPrefixMask

const Addr gem5::X86ISA::IntAddrPrefixMask = 0xffffffff00000000ULL

◆ IntAddrPrefixMSR

const Addr gem5::X86ISA::IntAddrPrefixMSR = 0x200000000ULL

◆ intEn

Bitfield<20> gem5::X86ISA::intEn

Definition at line 812 of file misc.hh.

◆ intf

Bitfield<9> gem5::X86ISA::intf

Definition at line 574 of file misc.hh.

◆ IntFoldBit

const IntRegIndex gem5::X86ISA::IntFoldBit = (IntRegIndex)(1 << 6)
static

◆ inv

Bitfield<23> gem5::X86ISA::inv

Definition at line 814 of file misc.hh.

Referenced by gem5::prefetch::Base::observeAccess().

◆ iopl

Bitfield<13, 12> gem5::X86ISA::iopl

Definition at line 571 of file misc.hh.

◆ IST

Bitfield<35, 32> gem5::X86ISA::IST

Definition at line 1024 of file misc.hh.

◆ ISTVirtAddr

const Addr gem5::X86ISA::ISTVirtAddr = 0xffff800000004000

◆ L

Bitfield<7, 0> gem5::X86ISA::L

◆ l

Bitfield< 2 > gem5::X86ISA::l

Definition at line 926 of file misc.hh.

◆ l1

Bitfield<2> gem5::X86ISA::l1

Definition at line 664 of file misc.hh.

Referenced by gem5::ruby::operator<().

◆ l2

Bitfield<4> gem5::X86ISA::l2

Definition at line 666 of file misc.hh.

Referenced by gem5::ruby::operator<().

◆ l3

Bitfield<6> gem5::X86ISA::l3

Definition at line 668 of file misc.hh.

◆ le

Bitfield<8> gem5::X86ISA::le

Definition at line 670 of file misc.hh.

◆ legacy

gem5::X86ISA::legacy

Definition at line 615 of file misc.hh.

Referenced by gem5::PciIoBar::EndBitUnion().

◆ len0

Bitfield<19, 18> gem5::X86ISA::len0

Definition at line 674 of file misc.hh.

Referenced by tlm::no_b1(), tlm::tlm_from_hostendian_word(), and tlm::tlm_to_hostendian_word().

◆ len1

Bitfield<23, 22> gem5::X86ISA::len1

Definition at line 676 of file misc.hh.

◆ len2

Bitfield<27, 26> gem5::X86ISA::len2

Definition at line 678 of file misc.hh.

◆ len3

Bitfield<31, 30> gem5::X86ISA::len3

Definition at line 680 of file misc.hh.

◆ level

Bitfield< 14 > gem5::X86ISA::level

Definition at line 51 of file intmessage.hh.

Referenced by gem5::Trie< Key, Value >::Node::dump(), gem5::SparcISA::Interrupts::getInterrupt(), gem5::getsockoptFunc(), gem5::StackDistCalc::getSum(), gem5::V7LPageTableOps::index(), gem5::V8PageTableOps4k::index(), gem5::V8PageTableOps16k::index(), gem5::V8PageTableOps64k::index(), gem5::SparcISA::Interrupts::InterruptLevel(), gem5::SparcISA::SparcFaultBase::invoke(), gem5::V7LPageTableOps::isLeaf(), gem5::V8PageTableOps4k::isLeaf(), gem5::V8PageTableOps16k::isLeaf(), gem5::V8PageTableOps64k::isLeaf(), gem5::V7LPageTableOps::isValid(), gem5::V8PageTableOps4k::isValid(), gem5::V8PageTableOps16k::isValid(), gem5::V8PageTableOps64k::isValid(), gem5::WalkCache::lookup(), gem5::V7LPageTableOps::nextLevelPointer(), gem5::V8PageTableOps4k::nextLevelPointer(), gem5::V8PageTableOps16k::nextLevelPointer(), gem5::V8PageTableOps64k::nextLevelPointer(), gem5::V7LPageTableOps::pageMask(), gem5::V8PageTableOps4k::pageMask(), gem5::V8PageTableOps16k::pageMask(), gem5::V8PageTableOps64k::pageMask(), gem5::WalkCache::pickEntryIdxToReplace(), gem5::WalkCache::pickSetIdx(), gem5::X86ISA::Interrupts::requestInterrupt(), gem5::StackDistCalc::sanityCheckTree(), gem5::setsockoptFunc(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), gem5::StackDistCalc::updateSum(), gem5::StackDistCalc::updateSumsLeavesToRoot(), gem5::SMMUTranslationProcess::walkCacheLookup(), gem5::SMMUTranslationProcess::walkCacheUpdate(), gem5::V7LPageTableOps::walkMask(), gem5::V8PageTableOps4k::walkMask(), gem5::V8PageTableOps16k::walkMask(), gem5::V8PageTableOps64k::walkMask(), gem5::SMMUTranslationProcess::walkStage1And2(), and gem5::SMMUTranslationProcess::walkStage2().

◆ limit

BitfieldType< SegDescriptorLimit > gem5::X86ISA::limit

◆ limit_in_pages

Bitfield<4> gem5::X86ISA::limit_in_pages

Definition at line 52 of file syscalls.hh.

◆ limitHigh

Bitfield< 51, 48 > gem5::X86ISA::limitHigh

Definition at line 928 of file misc.hh.

◆ limitLow

Bitfield< 15, 0 > gem5::X86ISA::limitLow

Definition at line 929 of file misc.hh.

◆ lma

Bitfield<10> gem5::X86ISA::lma

Definition at line 789 of file misc.hh.

◆ lme

Bitfield<8> gem5::X86ISA::lme

Definition at line 788 of file misc.hh.

◆ LO

const uint8_t gem5::X86ISA::LO = Lock

Definition at line 55 of file decoder_tables.cc.

◆ lock

Bitfield<5> gem5::X86ISA::lock

◆ longl1

gem5::X86ISA::longl1

Definition at line 123 of file pagetable.hh.

◆ longl2

Bitfield<29, 21> gem5::X86ISA::longl2

Definition at line 124 of file pagetable.hh.

◆ longl3

Bitfield<38, 30> gem5::X86ISA::longl3

Definition at line 125 of file pagetable.hh.

◆ longl4

Bitfield<47, 39> gem5::X86ISA::longl4

Definition at line 126 of file pagetable.hh.

◆ longMode

Bitfield<4> gem5::X86ISA::longMode

Definition at line 995 of file misc.hh.

◆ longPdtb

gem5::X86ISA::longPdtb

Definition at line 619 of file misc.hh.

◆ m

Bitfield<4, 0> gem5::X86ISA::m

Definition at line 118 of file types.hh.

◆ mask

gem5::X86ISA::mask

◆ mcaErrorCode

gem5::X86ISA::mcaErrorCode

Definition at line 766 of file misc.hh.

◆ mce

Bitfield<6> gem5::X86ISA::mce

Definition at line 638 of file misc.hh.

◆ MCGCP

Bitfield<8> gem5::X86ISA::MCGCP

Definition at line 710 of file misc.hh.

◆ mcip

Bitfield<2> gem5::X86ISA::mcip

Definition at line 716 of file misc.hh.

◆ mfdm

Bitfield<19> gem5::X86ISA::mfdm

Definition at line 820 of file misc.hh.

◆ miscv

Bitfield<59> gem5::X86ISA::miscv

Definition at line 771 of file misc.hh.

◆ MMIORegionPhysAddr

const Addr gem5::X86ISA::MMIORegionPhysAddr = 0xffff0000

Definition at line 48 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

◆ MMIORegionVirtAddr

const Addr gem5::X86ISA::MMIORegionVirtAddr = 0xffffc90000000000

Definition at line 47 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

◆ mod

gem5::X86ISA::mod

◆ modelSpecificCode

Bitfield<31,16> gem5::X86ISA::modelSpecificCode

Definition at line 767 of file misc.hh.

◆ mp

Bitfield<1> gem5::X86ISA::mp

Definition at line 609 of file misc.hh.

◆ msrMap

const MsrMap gem5::X86ISA::msrMap

Map between MSR addresses and their corresponding misc registers.

Note
This map is usually only used when enumeration of supported MSRs is needed (e.g., in virtualized CPUs). Code that needs to look-up specific MSRs should use msrAddrToIndex().

Referenced by gem5::X86KvmCPU::getMsrIntersection(), msrAddrToIndex(), gem5::X86KvmCPU::updateKvmStateMSRs(), and gem5::X86KvmCPU::updateThreadContextMSRs().

◆ msrMapData

const MsrMap::value_type gem5::X86ISA::msrMapData[]

Definition at line 39 of file msr.cc.

◆ msrMapSize

const unsigned gem5::X86ISA::msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])
static

Definition at line 145 of file msr.cc.

◆ mvdm

Bitfield<20> gem5::X86ISA::mvdm

Definition at line 821 of file misc.hh.

◆ nameString

const char gem5::X86ISA::nameString[nameStringSize] = "Fake M5 x86_64 CPU"
static

Definition at line 77 of file cpuid.cc.

Referenced by doCpuid().

◆ nameStringSize

const int gem5::X86ISA::nameStringSize = 48
static

Definition at line 76 of file cpuid.cc.

Referenced by doCpuid().

◆ ne

Bitfield<5> gem5::X86ISA::ne

Definition at line 605 of file misc.hh.

◆ norml1

Bitfield<21, 12> gem5::X86ISA::norml1

Definition at line 132 of file pagetable.hh.

◆ norml2

Bitfield<31, 22> gem5::X86ISA::norml2

Definition at line 133 of file pagetable.hh.

◆ nt

Bitfield<14> gem5::X86ISA::nt

Definition at line 570 of file misc.hh.

◆ NumCRegs

const int gem5::X86ISA::NumCRegs = 16

Definition at line 56 of file x86_traits.hh.

Referenced by MISCREG_CR().

◆ NumDRegs

const int gem5::X86ISA::NumDRegs = 8

Definition at line 57 of file x86_traits.hh.

Referenced by MISCREG_DR().

◆ NumFloatRegs

const int gem5::X86ISA::NumFloatRegs
Initial value:

Definition at line 157 of file float.hh.

Referenced by gem5::X86ISA::ISA::copyRegsFrom(), and gem5::X86ISA::ISA::ISA().

◆ NumIntRegs

const int gem5::X86ISA::NumIntRegs = NUM_INTREGS

Definition at line 188 of file int.hh.

Referenced by gem5::X86ISA::ISA::copyRegsFrom(), and gem5::X86ISA::ISA::ISA().

◆ NumMicroFpRegs

const int gem5::X86ISA::NumMicroFpRegs = 8

Definition at line 54 of file x86_traits.hh.

Referenced by gem5::X86ISA::X86StaticInst::printReg().

◆ NumMicroIntRegs

const int gem5::X86ISA::NumMicroIntRegs = 16

Definition at line 50 of file x86_traits.hh.

Referenced by EndBitUnion().

◆ NumMMXRegs

const int gem5::X86ISA::NumMMXRegs = 8

Definition at line 52 of file x86_traits.hh.

Referenced by gem5::X86ISA::X86StaticInst::printReg().

◆ NumSegments

const int gem5::X86ISA::NumSegments = 6

Definition at line 59 of file x86_traits.hh.

◆ NumSysSegments

const int gem5::X86ISA::NumSysSegments = 4

Definition at line 60 of file x86_traits.hh.

◆ NumVecElemPerVecReg

constexpr unsigned gem5::X86ISA::NumVecElemPerVecReg = ::gem5::DummyNumVecElemPerVecReg
constexpr

Definition at line 58 of file vecregs.hh.

◆ NumXMMRegs

const int gem5::X86ISA::NumXMMRegs = 16

Definition at line 53 of file x86_traits.hh.

Referenced by gem5::X86ISA::X86StaticInst::printReg().

◆ nw

Bitfield<29> gem5::X86ISA::nw

◆ nxe

Bitfield<11> gem5::X86ISA::nxe

Definition at line 790 of file misc.hh.

◆ of

Bitfield<11> gem5::X86ISA::of

Definition at line 572 of file misc.hh.

◆ offset

gem5::X86ISA::offset

◆ offsetHigh

gem5::X86ISA::offsetHigh

Definition at line 1007 of file misc.hh.

◆ offsetLow

Bitfield< 15, 0 > gem5::X86ISA::offsetLow

Definition at line 1008 of file misc.hh.

◆ OO

const uint8_t gem5::X86ISA::OO = OperandSizeOverride

Definition at line 53 of file decoder_tables.cc.

◆ op

Bitfield<4> gem5::X86ISA::op

Definition at line 83 of file types.hh.

Referenced by gem5::ArmISA::Crypto::_sha1Op(), gem5::ArmSemihosting::call32(), gem5::ArmSemihosting::call64(), gem5::MipsISA::dspCmp(), gem5::MipsISA::dspCmpg(), gem5::MipsISA::dspCmpgd(), gem5::ArmISA::flushToZero(), gem5::ArmISA::fp16_FPConvertNaN_32(), gem5::ArmISA::fp16_FPConvertNaN_64(), gem5::ArmISA::fp32_FPConvertNaN_16(), gem5::ArmISA::fp32_FPConvertNaN_64(), gem5::ArmISA::fp64_FPConvertNaN_16(), gem5::ArmISA::fp64_FPConvertNaN_32(), gem5::ArmISA::fplibAbs(), gem5::ArmISA::fplibConvert(), gem5::ArmISA::fplibExpA(), gem5::ArmISA::fplibFixedToFP(), gem5::ArmISA::fplibFPToFixed(), gem5::ArmISA::fplibFPToFixedJS(), gem5::ArmISA::fplibNeg(), gem5::ArmISA::fplibRecipEstimate(), gem5::ArmISA::fplibRecpX(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRSqrtEstimate(), gem5::ArmISA::fplibSqrt(), gem5::ArmISA::fpRecipEstimate(), gem5::ArmISA::fprSqrtEstimate(), gem5::futexFunc(), gem5::GPUStaticInst::initDynOperandInfo(), gem5::loader::SymbolTable::mask(), gem5::loader::SymbolTable::offset(), gem5::loader::SymbolTable::operate(), gem5::loader::SymbolTable::rename(), gem5::statistics::UnaryNode< Op >::result(), gem5::statistics::BinaryNode< Op >::result(), gem5::statistics::SumNode< Op >::result(), gem5::ArmISA::ArmStaticInst::satInt(), SC_MODULE(), gem5::ArmISA::Crypto::sha1Op(), gem5::ArmISA::simd_modified_imm(), gem5::MipsISA::sys_getsysinfoFunc(), gem5::MipsISA::sys_setsysinfoFunc(), gem5::statistics::BinaryNode< Op >::total(), gem5::statistics::SumNode< Op >::total(), gem5::ArmSemihosting::unrecognizedCall(), gem5::ArmISA::unsignedRecipEstimate(), gem5::ArmISA::unsignedRSqrtEstimate(), gem5::ArmISA::ArmStaticInst::uSatInt(), gem5::ArmISA::vcvtFpDFpH(), gem5::ArmISA::vcvtFpHFp(), gem5::ArmISA::vcvtFpHFpD(), gem5::ArmISA::vcvtFpHFpS(), gem5::ArmISA::vcvtFpSFpH(), and gem5::ArmISA::vfpFlushToZero().

◆ os

Bitfield<17> gem5::X86ISA::os

Definition at line 809 of file misc.hh.

Referenced by gem5::arrayParamOut(), sc_dt::b_xor(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::Trie< Key, Value >::Node::dump(), gem5::ProfileNode::dump(), sc_dt::sc_fxnum_bitref::dump(), gem5::FunctionProfile::dump(), sc_core::sc_fifo< T >::dump(), sc_dt::sc_fxnum_fast_bitref::dump(), sc_gem5::ScSignalBaseT< bool, WRITER_POLICY >::dump(), sc_dt::scfx_rep::dump(), sc_dt::sc_fxnum_subref::dump(), gem5::Trie< Addr, TlbEntry >::dump(), gem5::guest_abi::dumpArgsFrom(), gem5::dumpDebugFlags(), gem5::linux::dumpDmesg(), gem5::dumpDmesgEntry(), gem5::OutputDirectory::findOrCreate(), sc_gem5::UniqueNameGen::gen(), getString(), sc_dt::scfx_params::iwl(), gem5::mappingParamOut(), gem5::minor::LSQ::StoreBuffer::minorTrace(), gem5::OutputDirectory::open(), sc_dt::sc_bit::operator!(), gem5::ruby::operator<<(), gem5::minor::operator<<(), sc_dt::operator<<(), operator<<(), gem5::loader::operator<<(), sc_core::operator<<(), gem5::guest_abi::operator<<(), gem5::GenericISA::operator<<(), operator<<(), gem5::operator<<(), sc_dt::sc_bitref_r< T >::operator~(), sc_gem5::VcdTraceScope::output(), sc_gem5::VcdTraceValBool::output(), sc_gem5::VcdTraceValFloat< T >::output(), sc_gem5::VcdTraceValScLogic::output(), sc_gem5::VcdTraceValFxval< T >::output(), sc_gem5::VcdTraceValEvent::output(), sc_gem5::VcdTraceValTime::output(), gem5::paramOut(), sc_core::sc_time::print(), gem5::WriteQueueEntry::TargetList::print(), gem5::X86ISA::IntOp< Base >::print(), gem5::X86ISA::FoldedOp< Base >::print(), sc_dt::sc_fxnum_bitref::print(), gem5::X86ISA::CrOp< Base >::print(), sc_core::sc_fifo< T >::print(), gem5::X86ISA::DbgOp< Base >::print(), gem5::WriteQueueEntry::print(), gem5::X86ISA::SegOp< Base >::print(), gem5::X86ISA::MiscOp< Base >::print(), sc_dt::sc_uint_bitref_r::print(), gem5::X86ISA::FloatOp< Base >::print(), sc_gem5::ScSignalBaseT< bool, WRITER_POLICY >::print(), sc_dt::sc_int_bitref_r::print(), sc_dt::scfx_rep::print(), gem5::X86ISA::Imm8Op::print(), gem5::X86ISA::Imm64Op::print(), gem5::MSHR::TargetList::print(), gem5::X86ISA::UpcOp::print(), gem5::X86ISA::FaultOp::print(), gem5::X86ISA::AddrOp::print(), sc_dt::sc_uint_subref_r::print(), sc_dt::sc_int_subref_r::print(), sc_dt::sc_concatref::print(), gem5::MSHR::print(), gem5::CacheBlkPrintWrapper::print(), sc_dt::sc_unsigned_bitref_r::print(), sc_dt::sc_signed_bitref_r::print(), sc_dt::sc_unsigned_subref_r::print(), sc_dt::sc_uint_base::print(), sc_dt::sc_signed_subref_r::print(), sc_dt::sc_int_base::print(), sc_dt::sc_unsigned::print(), sc_dt::sc_signed::print(), gem5::ArmISA::ArmStaticInst::printCCReg(), gem5::ArmISA::ArmStaticInst::printCondition(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::Memory::printDest(), gem5::ArmISA::MemoryExImm::printDest(), gem5::ArmISA::MemoryDImm::printDest(), gem5::ArmISA::MemoryExDImm::printDest(), gem5::ArmISA::MemoryDReg::printDest(), gem5::SparcISA::SparcStaticInst::printDestReg(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printFloatReg(), gem5::ArmISA::Memory::printInst(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::X86ISA::X86StaticInst::printMem(), gem5::ArmISA::ArmStaticInst::printMemSymbol(), gem5::ArmISA::ArmStaticInst::printMiscReg(), gem5::X86ISA::X86StaticInst::printMnemonic(), gem5::SparcISA::SparcStaticInst::printMnemonic(), gem5::ArmISA::ArmStaticInst::printMnemonic(), gem5::MsrBase::printMsrBase(), gem5::ArmISA::MemoryImm::printOffset(), gem5::ArmISA::MemoryReg::printOffset(), gem5::ArmISA::ArmStaticInst::printPFflags(), gem5::SparcISA::IntOp::printPseudoOps(), gem5::SparcISA::IntOpImm::printPseudoOps(), gem5::PowerISA::PowerStaticInst::printReg(), gem5::SparcISA::SparcStaticInst::printReg(), gem5::X86ISA::X86StaticInst::printReg(), gem5::SparcISA::SparcStaticInst::printRegArray(), gem5::minor::printRegName(), gem5::X86ISA::X86StaticInst::printSegment(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::SparcISA::SparcStaticInst::printSrcReg(), gem5::ArmISA::ArmStaticInst::printTarget(), sc_gem5::VcdTraceValBase::printVal(), gem5::ArmISA::ArmStaticInst::printVecPredReg(), gem5::ArmISA::ArmStaticInst::printVecReg(), gem5::linux::DmesgDump::process(), gem5::linux::KernelPanic::process(), gem5::minor::ReportTraitsAdaptor< ElemType >::reportData(), gem5::minor::ReportTraitsPtrAdaptor< PtrType >::reportData(), gem5::minor::Fetch1::FetchRequest::reportData(), gem5::minor::BranchData::reportData(), gem5::minor::QueuedInst::reportData(), gem5::minor::ForwardLineData::reportData(), gem5::minor::LSQ::LSQRequest::reportData(), gem5::minor::MinorDynInst::reportData(), gem5::minor::ForwardInstData::reportData(), gem5::CxxConfigManager::serialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< 12 >::serialize(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::serialize(), gem5::ShowParam< T, Enabled >::show(), gem5::ShowParam< T, std::enable_if_t< std::is_same< char, T >::value||std::is_same< unsigned char, T >::value||std::is_same< signed char, T >::value > >::show(), gem5::ShowParam< bool >::show(), gem5::ShowParam< VecRegContainer< Sz > >::show(), gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show(), gem5::ShowParam< BitUnionType< T > >::show(), gem5::ShowParam< T, std::enable_if_t< std::is_base_of< typename RegisterBankBase::RegisterBaseBase, T >::value > >::show(), gem5::ArmISA::Memory64::startDisassembly(), TEST(), TEST_F(), sc_dt::sc_fxval::to_bin(), sc_dt::sc_fxnum_fast::to_bin(), sc_dt::sc_fxval::to_string(), sc_dt::sc_fxval_fast::to_string(), sc_dt::sc_fxnum::to_string(), sc_dt::sc_fxnum_fast::to_string(), and gem5::pseudo_inst::writefile().

◆ osfxsr

Bitfield<9> gem5::X86ISA::osfxsr

Definition at line 635 of file misc.hh.

◆ osxmmexcpt

Bitfield<10> gem5::X86ISA::osxmmexcpt

Definition at line 633 of file misc.hh.

◆ otherInfo

Bitfield<56,32> gem5::X86ISA::otherInfo

Definition at line 768 of file misc.hh.

◆ over

Bitfield<62> gem5::X86ISA::over

Definition at line 774 of file misc.hh.

◆ p

Bitfield< 1, 0 > gem5::X86ISA::p

◆ pae

Bitfield<5> gem5::X86ISA::pae

Definition at line 639 of file misc.hh.

◆ pael1

Bitfield<20, 12> gem5::X86ISA::pael1

Definition at line 128 of file pagetable.hh.

◆ pael2

Bitfield<29, 21> gem5::X86ISA::pael2

Definition at line 129 of file pagetable.hh.

◆ pael3

Bitfield<31, 30> gem5::X86ISA::pael3

Definition at line 130 of file pagetable.hh.

◆ paePdtb

Bitfield<31, 5> gem5::X86ISA::paePdtb

Definition at line 623 of file misc.hh.

◆ PageBytes

const Addr gem5::X86ISA::PageBytes = 1ULL << PageShift

◆ PageShift

const Addr gem5::X86ISA::PageShift = 12

◆ paging

Bitfield<6> gem5::X86ISA::paging

Definition at line 587 of file misc.hh.

◆ pb0

Bitfield<2> gem5::X86ISA::pb0

Definition at line 722 of file misc.hh.

◆ pb1

Bitfield<3> gem5::X86ISA::pb1

Definition at line 723 of file misc.hh.

◆ pb2

Bitfield<4> gem5::X86ISA::pb2

Definition at line 724 of file misc.hh.

◆ pb3

Bitfield<5> gem5::X86ISA::pb3

Definition at line 725 of file misc.hh.

◆ pc

Bitfield<19> gem5::X86ISA::pc

◆ pcc

Bitfield<57> gem5::X86ISA::pcc

Definition at line 769 of file misc.hh.

◆ pcd

Bitfield< 4 > gem5::X86ISA::pcd

Definition at line 147 of file pagetable.hh.

◆ pce

Bitfield<8> gem5::X86ISA::pce

Definition at line 636 of file misc.hh.

◆ pdtb

Bitfield<31, 12> gem5::X86ISA::pdtb

Definition at line 621 of file misc.hh.

◆ pe

Bitfield<0> gem5::X86ISA::pe

Definition at line 610 of file misc.hh.

Referenced by gem5::EtherLink::Link::serialize().

◆ pf

Bitfield< 2 > gem5::X86ISA::pf

◆ PFHandlerVirtAddr

const Addr gem5::X86ISA::PFHandlerVirtAddr = 0xffff800000005000

◆ pge

Bitfield<7> gem5::X86ISA::pge

Definition at line 637 of file misc.hh.

◆ physAddr

gem5::X86ISA::physAddr

◆ PhysAddrAPICRangeSize

const Addr gem5::X86ISA::PhysAddrAPICRangeSize = 1 << 12

Definition at line 73 of file x86_traits.hh.

Referenced by gem5::X86ISA::Interrupts::getIntAddrRange(), and x86InterruptAddress().

◆ PhysAddrPrefixInterrupts

const Addr gem5::X86ISA::PhysAddrPrefixInterrupts = 0xA000000000000000ULL

Definition at line 70 of file x86_traits.hh.

Referenced by x86InterruptAddress().

◆ PhysAddrPrefixIO

const Addr gem5::X86ISA::PhysAddrPrefixIO = 0x8000000000000000ULL

◆ PhysAddrPrefixLocalAPIC

const Addr gem5::X86ISA::PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL

Definition at line 69 of file x86_traits.hh.

Referenced by x86LocalAPICAddress().

◆ PhysAddrPrefixPciConfig

const Addr gem5::X86ISA::PhysAddrPrefixPciConfig = 0xC000000000000000ULL

◆ physbase

Bitfield< 51, 12 > gem5::X86ISA::physbase

Definition at line 734 of file misc.hh.

◆ physmask

Bitfield< 51, 12 > gem5::X86ISA::physmask

Definition at line 739 of file misc.hh.

◆ present

Bitfield< 0 > gem5::X86ISA::present

◆ prot

Bitfield<7> gem5::X86ISA::prot

Definition at line 588 of file misc.hh.

Referenced by gem5::mmap2Func(), gem5::mmapFunc(), gem5::socketFunc(), and gem5::socketpairFunc().

◆ ps

Bitfield<7> gem5::X86ISA::ps

Definition at line 144 of file pagetable.hh.

◆ pse

Bitfield<4> gem5::X86ISA::pse

Definition at line 640 of file misc.hh.

◆ pvi

Bitfield<1> gem5::X86ISA::pvi

Definition at line 643 of file misc.hh.

◆ pwt

Bitfield< 3 > gem5::X86ISA::pwt

Definition at line 148 of file pagetable.hh.

◆ R

gem5::X86ISA::R

Definition at line 51 of file int.hh.

Referenced by SC_MODULE().

◆ r

Bitfield< 2 > gem5::X86ISA::r

◆ rd

Bitfield<4> gem5::X86ISA::rd

Definition at line 827 of file misc.hh.

◆ RE

const uint8_t gem5::X86ISA::RE = Rep

Definition at line 56 of file decoder_tables.cc.

Referenced by SC_MODULE().

◆ read_exec_only

Bitfield<3> gem5::X86ISA::read_exec_only

Definition at line 51 of file syscalls.hh.

◆ readable

Bitfield<13> gem5::X86ISA::readable

Definition at line 1001 of file misc.hh.

◆ reg

Bitfield<5,3> gem5::X86ISA::reg

Definition at line 92 of file types.hh.

Referenced by gem5::ArmISA::AArch32isUndefinedGenericTimer(), gem5::o3::SimpleFreeList::addReg(), gem5::Trace::TarmacTracerRecordV8::addRegEntry(), gem5::Trace::TarmacTracerRecord::addRegEntry(), gem5::RegisterBank< ByteOrder::little >::addRegister(), gem5::RegisterBank< ByteOrder::little >::addRegisters(), gem5::o3::SimpleFreeList::addRegs(), gem5::minor::Scoreboard::canInstIssue(), gem5::ArmISA::canReadAArch64SysReg(), gem5::ArmISA::canReadCoprocReg(), gem5::ArmISA::canWriteAArch64SysReg(), gem5::ArmISA::canWriteCoprocReg(), gem5::minor::Scoreboard::clearInstDests(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::defaultPartialReader(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::defaultPartialWriter(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::defaultReader(), gem5::RegisterBank< BankByteOrder >::Register< BackingType >::defaultWriter(), gem5::ArmV8KvmCPU::dump(), gem5::minor::Scoreboard::execSeqNumToWaitFor(), gem5::minor::Scoreboard::findIndex(), gem5::RiscvISA::ISA::flattenCCIndex(), gem5::X86ISA::ISA::flattenCCIndex(), gem5::PowerISA::ISA::flattenCCIndex(), gem5::MipsISA::ISA::flattenCCIndex(), gem5::SparcISA::ISA::flattenCCIndex(), gem5::ArmISA::ISA::flattenCCIndex(), gem5::RiscvISA::ISA::flattenFloatIndex(), gem5::X86ISA::ISA::flattenFloatIndex(), gem5::PowerISA::ISA::flattenFloatIndex(), gem5::MipsISA::ISA::flattenFloatIndex(), gem5::SparcISA::ISA::flattenFloatIndex(), gem5::ArmISA::ISA::flattenFloatIndex(), gem5::RiscvISA::ISA::flattenIntIndex(), gem5::X86ISA::ISA::flattenIntIndex(), gem5::PowerISA::ISA::flattenIntIndex(), gem5::MipsISA::ISA::flattenIntIndex(), gem5::SparcISA::ISA::flattenIntIndex(), gem5::ArmISA::ISA::flattenIntIndex(), gem5::ArmISA::flattenIntRegModeIndex(), gem5::RiscvISA::ISA::flattenMiscIndex(), gem5::X86ISA::ISA::flattenMiscIndex(), gem5::PowerISA::ISA::flattenMiscIndex(), gem5::MipsISA::ISA::flattenMiscIndex(), gem5::SparcISA::ISA::flattenMiscIndex(), gem5::ArmISA::ISA::flattenMiscIndex(), gem5::minor::flattenRegIndex(), gem5::RiscvISA::ISA::flattenVecElemIndex(), gem5::X86ISA::ISA::flattenVecElemIndex(), gem5::PowerISA::ISA::flattenVecElemIndex(), gem5::MipsISA::ISA::flattenVecElemIndex(), gem5::SparcISA::ISA::flattenVecElemIndex(), gem5::ArmISA::ISA::flattenVecElemIndex(), gem5::RiscvISA::ISA::flattenVecIndex(), gem5::X86ISA::ISA::flattenVecIndex(), gem5::PowerISA::ISA::flattenVecIndex(), gem5::MipsISA::ISA::flattenVecIndex(), gem5::SparcISA::ISA::flattenVecIndex(), gem5::ArmISA::ISA::flattenVecIndex(), gem5::RiscvISA::ISA::flattenVecPredIndex(), gem5::X86ISA::ISA::flattenVecPredIndex(), gem5::PowerISA::ISA::flattenVecPredIndex(), gem5::MipsISA::ISA::flattenVecPredIndex(), gem5::SparcISA::ISA::flattenVecPredIndex(), gem5::ArmISA::ISA::flattenVecPredIndex(), gem5::MrsOp::generateDisassembly(), gem5::Trace::TarmacTracerRecord::genRegister(), gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::get(), gem5::KvmKernelGicV2::getGicReg(), gem5::BaseKvmCPU::getOneReg(), gem5::o3::PhysRegFile::getRegElemIds(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::o3::PhysRegFile::getTrueId(), gem5::CheckerThreadContext< TC >::getWritableVecPredReg(), gem5::SimpleThread::getWritableVecPredReg(), gem5::SimpleThread::getWritableVecPredRegFlat(), gem5::minor::ExecContext::getWritableVecPredRegOperand(), gem5::CheckerCPU::getWritableVecPredRegOperand(), gem5::SimpleExecContext::getWritableVecPredRegOperand(), gem5::CheckerThreadContext< TC >::getWritableVecReg(), gem5::SimpleThread::getWritableVecReg(), gem5::SimpleThread::getWritableVecRegFlat(), gem5::minor::ExecContext::getWritableVecRegOperand(), gem5::CheckerCPU::getWritableVecRegOperand(), gem5::SimpleExecContext::getWritableVecRegOperand(), gem5::Gcn3ISA::Inst_SOP2::initOperandInfo(), gem5::VegaISA::Inst_SOP2::initOperandInfo(), gem5::Gcn3ISA::Inst_SOPK::initOperandInfo(), gem5::VegaISA::Inst_SOPK::initOperandInfo(), gem5::VegaISA::Inst_SOP1::initOperandInfo(), gem5::Gcn3ISA::Inst_SOP1::initOperandInfo(), gem5::Gcn3ISA::Inst_SOPC::initOperandInfo(), gem5::VegaISA::Inst_SOPC::initOperandInfo(), gem5::Gcn3ISA::Inst_SOPP::initOperandInfo(), gem5::VegaISA::Inst_SOPP::initOperandInfo(), gem5::VegaISA::Inst_SMEM::initOperandInfo(), gem5::Gcn3ISA::Inst_SMEM::initOperandInfo(), gem5::VegaISA::Inst_VOP2::initOperandInfo(), gem5::Gcn3ISA::Inst_VOP2::initOperandInfo(), gem5::Gcn3ISA::Inst_VOP1::initOperandInfo(), gem5::VegaISA::Inst_VOP1::initOperandInfo(), gem5::Gcn3ISA::Inst_VOPC::initOperandInfo(), gem5::VegaISA::Inst_VOPC::initOperandInfo(), gem5::Gcn3ISA::Inst_VOP3::initOperandInfo(), gem5::VegaISA::Inst_VOP3A::initOperandInfo(), gem5::Gcn3ISA::Inst_VOP3_SDST_ENC::initOperandInfo(), gem5::VegaISA::Inst_VOP3B::initOperandInfo(), gem5::Gcn3ISA::Inst_DS::initOperandInfo(), gem5::VegaISA::Inst_DS::initOperandInfo(), gem5::VegaISA::Inst_MUBUF::initOperandInfo(), gem5::Gcn3ISA::Inst_MUBUF::initOperandInfo(), gem5::VegaISA::Inst_MTBUF::initOperandInfo(), gem5::VegaISA::Inst_MIMG::initOperandInfo(), gem5::Gcn3ISA::Inst_MTBUF::initOperandInfo(), gem5::VegaISA::Inst_FLAT::initOperandInfo(), gem5::Gcn3ISA::Inst_MIMG::initOperandInfo(), gem5::Gcn3ISA::Inst_FLAT::initOperandInfo(), gem5::ArmISA::ISA::InitReg(), gem5::ArmISA::intRegInMode(), gem5::ArmISA::isSP(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::makeSP(), gem5::ArmISA::makeZero(), gem5::minor::Scoreboard::markupInstDests(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::X86ISA::X86StaticInst::merge(), gem5::Trace::TarmacTracerRecord::mergeCCEntry(), gem5::CustomNoMaliGpu::onReset(), gem5::networking::EthAddr::operator uint64_t(), gem5::X86ISA::X86StaticInst::pick(), gem5::ArmISA::preUnflattenMiscReg(), gem5::SparcISA::SparcStaticInst::printDestReg(), gem5::MsrBase::printMsrBase(), gem5::PowerISA::PowerStaticInst::printReg(), gem5::SparcISA::SparcStaticInst::printReg(), gem5::X86ISA::X86StaticInst::printReg(), gem5::minor::printRegName(), gem5::SparcISA::SparcStaticInst::printSrcReg(), gem5::EnergyCtrl::read(), gem5::X86ISA::Interrupts::read(), gem5::sinic::Device::read(), gem5::NSGigE::read(), gem5::RegisterBank< ByteOrder::little >::read(), gem5::CheckerCPU::readCCRegOperand(), gem5::minor::ExecContext::readCCRegOperand(), gem5::SimpleExecContext::readCCRegOperand(), gem5::Plic::readClaim(), gem5::minor::ExecContext::readFloatRegOperandBits(), gem5::CheckerCPU::readFloatRegOperandBits(), gem5::SimpleExecContext::readFloatRegOperandBits(), gem5::minor::ExecContext::readIntRegOperand(), gem5::CheckerCPU::readIntRegOperand(), gem5::SimpleExecContext::readIntRegOperand(), gem5::GenericTimer::readMiscReg(), gem5::GenericTimerISA::readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::minor::ExecContext::readMiscRegOperand(), gem5::SimpleExecContext::readMiscRegOperand(), gem5::CheckerCPU::readMiscRegOperand(), gem5::o3::DynInst::readMiscRegOperand(), gem5::Clint::readMSIP(), gem5::NoMaliGpu::readReg(), gem5::X86ISA::Interrupts::readReg(), gem5::X86ISA::Cmos::readRegister(), gem5::MipsISA::readRegOtherThread(), gem5::NoMaliGpu::readRegRaw(), gem5::o3::ThreadContext::readVecElem(), gem5::CheckerThreadContext< TC >::readVecElem(), gem5::SimpleThread::readVecElem(), gem5::SimpleThread::readVecElemFlat(), gem5::minor::ExecContext::readVecElemOperand(), gem5::CheckerCPU::readVecElemOperand(), gem5::SimpleExecContext::readVecElemOperand(), gem5::CheckerThreadContext< TC >::readVecPredReg(), gem5::Iris::ThreadContext::readVecPredReg(), gem5::SimpleThread::readVecPredReg(), gem5::SimpleThread::readVecPredRegFlat(), gem5::minor::ExecContext::readVecPredRegOperand(), gem5::CheckerCPU::readVecPredRegOperand(), gem5::SimpleExecContext::readVecPredRegOperand(), gem5::CheckerThreadContext< TC >::readVecReg(), gem5::Iris::ThreadContext::readVecReg(), gem5::SimpleThread::readVecReg(), gem5::SimpleThread::readVecRegFlat(), gem5::minor::ExecContext::readVecRegOperand(), gem5::CheckerCPU::readVecRegOperand(), gem5::SimpleExecContext::readVecRegOperand(), gem5::RiscvISA::registerName(), gem5::Uart8250::Registers::Registers(), gem5::Plic::serialize(), gem5::Clint::serialize(), gem5::sinic::Device::serialize(), gem5::CheckerCPU::setCCRegOperand(), gem5::minor::ExecContext::setCCRegOperand(), gem5::SimpleExecContext::setCCRegOperand(), gem5::minor::ExecContext::setFloatRegOperandBits(), gem5::CheckerCPU::setFloatRegOperandBits(), gem5::SimpleExecContext::setFloatRegOperandBits(), gem5::KvmKernelGicV2::setGicReg(), gem5::minor::ExecContext::setIntRegOperand(), gem5::CheckerCPU::setIntRegOperand(), gem5::SimpleExecContext::setIntRegOperand(), gem5::GenericTimer::setMiscReg(), gem5::GenericTimerISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::minor::ExecContext::setMiscRegOperand(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::CheckerCPU::setMiscRegOperand(), gem5::o3::DynInst::setMiscRegOperand(), gem5::BaseKvmCPU::setOneReg(), gem5::X86ISA::Interrupts::setReg(), gem5::X86ISA::Interrupts::setRegNoEffect(), gem5::MipsISA::setRegOtherThread(), gem5::o3::ThreadContext::setVecElem(), gem5::CheckerThreadContext< TC >::setVecElem(), gem5::SimpleThread::setVecElem(), gem5::SimpleThread::setVecElemFlat(), gem5::minor::ExecContext::setVecElemOperand(), gem5::CheckerCPU::setVecElemOperand(), gem5::SimpleExecContext::setVecElemOperand(), gem5::o3::ThreadContext::setVecPredReg(), gem5::CheckerThreadContext< TC >::setVecPredReg(), gem5::SimpleThread::setVecPredReg(), gem5::SimpleThread::setVecPredRegFlat(), gem5::minor::ExecContext::setVecPredRegOperand(), gem5::CheckerCPU::setVecPredRegOperand(), gem5::SimpleExecContext::setVecPredRegOperand(), gem5::o3::ThreadContext::setVecReg(), gem5::CheckerThreadContext< TC >::setVecReg(), gem5::SimpleThread::setVecReg(), gem5::SimpleThread::setVecRegFlat(), gem5::minor::ExecContext::setVecRegOperand(), gem5::CheckerCPU::setVecRegOperand(), gem5::SimpleExecContext::setVecRegOperand(), gem5::X86ISA::X86StaticInst::signedPick(), gem5::MipsISA::simdPack(), gem5::MipsISA::simdUnpack(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::ISA::snsBankedIndex64(), gem5::ArmISA::snsBankedIndex64(), gem5::guest_abi::Result< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::store(), stringToRegister(), TEST_F(), gem5::ArmISA::unflattenMiscReg(), gem5::Plic::unserialize(), gem5::Clint::unserialize(), gem5::sinic::Device::unserialize(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateKvmStateCoProc(), gem5::ArmKvmCPU::updateTCStateCoProc(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::VectorRegisterFile::VectorRegisterFile(), gem5::EnergyCtrl::write(), gem5::X86ISA::Interrupts::write(), gem5::NSGigE::write(), gem5::RegisterBank< ByteOrder::little >::write(), gem5::Plic::writeClaim(), gem5::Plic::writeEnable(), gem5::Uart8250::writeIer(), gem5::Clint::writeMSIP(), gem5::X86ISA::I8237::WriteOnlyReg::WriteOnlyReg(), gem5::Plic::writePriority(), gem5::NoMaliGpu::writeReg(), gem5::X86ISA::Cmos::writeRegister(), gem5::NoMaliGpu::writeRegRaw(), and gem5::Plic::writeThreshold().

◆ rep

Bitfield<6> gem5::X86ISA::rep

Definition at line 81 of file types.hh.

Referenced by sc_gem5::VcdTraceValBase::printVal().

◆ repne

Bitfield<7> gem5::X86ISA::repne

Definition at line 80 of file types.hh.

◆ rf

Bitfield<16> gem5::X86ISA::rf

Definition at line 569 of file misc.hh.

Referenced by gem5::RegisterFile::MarkRegBusyScbEvent::process().

◆ rInit

Bitfield<1> gem5::X86ISA::rInit

Definition at line 842 of file misc.hh.

◆ rm

Bitfield<2,0> gem5::X86ISA::rm

Definition at line 93 of file types.hh.

Referenced by gem5::X86ISA::EmulEnv::doModRM().

◆ RN

const uint8_t gem5::X86ISA::RN = Repne

Definition at line 57 of file decoder_tables.cc.

◆ rpl

Bitfield<1, 0> gem5::X86ISA::rpl

Definition at line 868 of file misc.hh.

◆ rsmCycle

Bitfield<4> gem5::X86ISA::rsmCycle

Definition at line 855 of file misc.hh.

◆ rw0

Bitfield<17, 16> gem5::X86ISA::rw0

Definition at line 673 of file misc.hh.

◆ rw1

Bitfield<21, 20> gem5::X86ISA::rw1

Definition at line 675 of file misc.hh.

◆ rw2

Bitfield<25, 24> gem5::X86ISA::rw2

Definition at line 677 of file misc.hh.

◆ rw3

Bitfield<29, 28> gem5::X86ISA::rw3

Definition at line 679 of file misc.hh.

◆ RX

const uint8_t gem5::X86ISA::RX = RexPrefix

Definition at line 58 of file decoder_tables.cc.

◆ s

Bitfield<44> gem5::X86ISA::s

Definition at line 933 of file misc.hh.

Referenced by gem5::Float16::Float16(), and gem5::Float16::operator float().

◆ scale

gem5::X86ISA::scale

◆ SE

SignedBitfield<31,0> gem5::X86ISA::SE

Definition at line 54 of file int.hh.

◆ seg

Bitfield<2,0> gem5::X86ISA::seg

◆ seg_not_present

Bitfield<5> gem5::X86ISA::seg_not_present

Definition at line 53 of file syscalls.hh.

◆ SegmentFlagMask

const GEM5_VAR_USED Request::FlagsType gem5::X86ISA::SegmentFlagMask = mask(4)

◆ selector

Bitfield< 31, 16 > gem5::X86ISA::selector

◆ sf

Bitfield< 7 > gem5::X86ISA::sf

Definition at line 551 of file misc.hh.

◆ SH

SignedBitfield<15,8> gem5::X86ISA::SH

Definition at line 58 of file int.hh.

◆ si

Bitfield<15, 3> gem5::X86ISA::si

Definition at line 866 of file misc.hh.

Referenced by gem5::X86ISA::Decoder::decode().

◆ SL

SignedBitfield<7, 0> gem5::X86ISA::SL

Definition at line 60 of file int.hh.

◆ smiCycle

Bitfield<2> gem5::X86ISA::smiCycle

Definition at line 853 of file misc.hh.

◆ SR

SignedBitfield<63,0> gem5::X86ISA::SR

Definition at line 52 of file int.hh.

◆ SS

const uint8_t gem5::X86ISA::SS = SSOverride

Definition at line 51 of file decoder_tables.cc.

◆ stack

Bitfield<17, 16> gem5::X86ISA::stack

◆ submode

Bitfield< 2, 0 > gem5::X86ISA::submode

Definition at line 585 of file misc.hh.

◆ svme

Bitfield<12> gem5::X86ISA::svme

Definition at line 791 of file misc.hh.

◆ SX

SignedBitfield<15,0> gem5::X86ISA::SX

Definition at line 56 of file int.hh.

◆ syscallCodeVirtAddr

const Addr gem5::X86ISA::syscallCodeVirtAddr = 0xffff800000000000

◆ syscallCsAndSs

Bitfield<47,32> gem5::X86ISA::syscallCsAndSs

Definition at line 797 of file misc.hh.

◆ sysretCsAndSs

Bitfield<63,48> gem5::X86ISA::sysretCsAndSs

Definition at line 798 of file misc.hh.

◆ system

Bitfield<15> gem5::X86ISA::system

◆ targetCS

gem5::X86ISA::targetCS

Definition at line 694 of file misc.hh.

◆ targetEIP

gem5::X86ISA::targetEIP

Definition at line 702 of file misc.hh.

◆ targetEip

gem5::X86ISA::targetEip

Definition at line 796 of file misc.hh.

◆ targetESP

gem5::X86ISA::targetESP

Definition at line 698 of file misc.hh.

◆ tf

Bitfield<8> gem5::X86ISA::tf

◆ ti

Bitfield<2> gem5::X86ISA::ti

Definition at line 867 of file misc.hh.

Referenced by gem5::ArmISA::TLB::setTestInterface().

◆ tom2

Bitfield<21> gem5::X86ISA::tom2

Definition at line 822 of file misc.hh.

◆ top5

gem5::X86ISA::top5

Definition at line 181 of file types.hh.

◆ tpr

gem5::X86ISA::tpr

Definition at line 648 of file misc.hh.

◆ trigger

Bitfield< 15 > gem5::X86ISA::trigger

◆ TriggerIntOffset

const Addr gem5::X86ISA::TriggerIntOffset = 0
static

Definition at line 82 of file intmessage.hh.

Referenced by buildIntTriggerPacket().

◆ ts

Bitfield<3> gem5::X86ISA::ts

Definition at line 607 of file misc.hh.

◆ tsd

Bitfield<2> gem5::X86ISA::tsd

Definition at line 642 of file misc.hh.

◆ TSSPhysAddr

const Addr gem5::X86ISA::TSSPhysAddr = 0x63000

Definition at line 44 of file se_workload.hh.

◆ TSSVirtAddr

const Addr gem5::X86ISA::TSSVirtAddr = 0xffff800000003000

Definition at line 43 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

◆ type

Bitfield< 43, 40 > gem5::X86ISA::type

Definition at line 733 of file misc.hh.

Referenced by gem5::__to_number(), gem5::ruby::RubyPrefetcher::accessNonunitFilter(), gem5::ruby::RubyPrefetcher::accessUnitFilter(), gem5::statistics::Hdf5::addMetaData(), gem5::ruby::CacheRecorder::addRecord(), gem5::ruby::AddressProfiler::addTraceSample(), gem5::PowerProcess::argsInit(), gem5::ArmProcess::argsInit(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::ruby::broadcast(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::KvmVM::createDevice(), gem5::createImgWriter(), gem5::ruby::createMachineID(), gem5::ArmV8KvmCPU::dump(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::floorLog2(), gem5::Iob::generateIpi(), gem5::ArmISA::PMU::getCounterTypeRegister(), gem5::ruby::Throttle::getMsgCount(), gem5::ruby::Switch::getMsgCount(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::ruby::Sequencer::hitCallback(), gem5::ruby::GPUCoalescer::hitCallback(), gem5::ruby::AbstractController::incomingTransactionStart(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::ArmISA::MMU::invalidateMiscReg(), gem5::Episode::Action::isAtomicAction(), gem5::ruby::isDataReadRequest(), gem5::ruby::isHtmCmdRequest(), gem5::Episode::Action::isMemFenceAction(), gem5::ruby::isReadRequest(), gem5::igbreg::txd_op::isType(), gem5::compression::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), gem5::ruby::isWriteRequest(), gem5::ruby::MachineTypeAndNodeIDToMachineID(), gem5::ruby::mapAddressToRange(), gem5::ruby::RubyPrefetcher::observeMiss(), opcodeTypeToStr(), std::hash< gem5::ruby::MachineID >::operator()(), RegisterBankTest::Access::operator==(), gem5::ruby::AbstractController::outgoingTransactionStart(), gem5::PerfKvmCounterConfig::PerfKvmCounterConfig(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::X86ISA::ACPI::MADT::Record::prepareBuf(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::Episode::Action::printType(), gem5::ruby::AddressProfiler::profileRetry(), gem5::ruby::Sequencer::recordMissLatency(), tlm_utils::ispex_base::register_private_extension(), gem5::ruby::SimpleNetwork::regStats(), gem5::ruby::Throttle::regStats(), gem5::ruby::Switch::regStats(), gem5::NSGigE::rxFilter(), gem5::PipeFDEntry::setEndType(), gem5::KvmKernelGicV2::setIntState(), gem5::ruby::CoalescedRequest::setRubyType(), gem5::ruby::garnet::NetworkLink::setType(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::socketFunc(), gem5::socketpairFunc(), gem5::ArmISA::TLB::tranTypeEL(), gem5::ruby::CacheMemory::tryCacheAccess(), gem5::o3::ElasticTrace::TraceInfo::typeToStr(), gem5::TraceCPU::ElasticDataGen::GraphNode::typeToStr(), gem5::ruby::AccessTraceForAddress::update(), gem5::Iob::writeIob(), gem5::X86ISA::intelmp::BaseConfigEntry::writeOut(), gem5::X86ISA::intelmp::ExtConfigEntry::writeOut(), and gem5::X86ISA::E820Table::writeTo().

◆ u

Bitfield<2> gem5::X86ISA::u

Definition at line 149 of file pagetable.hh.

Referenced by gem5::X86ISA::LongModePTE::uncacheable().

◆ uc

Bitfield<61> gem5::X86ISA::uc

Definition at line 773 of file misc.hh.

◆ unitMask

Bitfield<15,8> gem5::X86ISA::unitMask

Definition at line 807 of file misc.hh.

◆ unusable

Bitfield<2> gem5::X86ISA::unusable

Definition at line 993 of file misc.hh.

◆ useable

Bitfield<6> gem5::X86ISA::useable

Definition at line 54 of file syscalls.hh.

◆ usr

Bitfield<16> gem5::X86ISA::usr

Definition at line 808 of file misc.hh.

Referenced by gem5::NoMaliGpu::_interrupt(), and gem5::NoMaliGpu::_reset().

◆ v

Bitfield< 6, 3 > gem5::X86ISA::v

Definition at line 125 of file types.hh.

◆ V2

const uint8_t gem5::X86ISA::V2 = Vex2Prefix

Definition at line 59 of file decoder_tables.cc.

◆ V3

const uint8_t gem5::X86ISA::V3 = Vex3Prefix

Definition at line 60 of file decoder_tables.cc.

◆ val

Bitfield<63> gem5::X86ISA::val

Definition at line 775 of file misc.hh.

Referenced by gem5::ruby::ExpectedMap< RespType, DataType >::addExpectedCount(), gem5::ruby::ExpectedMap< RespType, DataType >::addExpectedDataType(), gem5::ruby::ExpectedMap< RespType, DataType >::addExpectedRespType(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< DataType >::addExpectedType(), gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::alignToPowerOfTwo(), gem5::ArmISA::AbortFault< DataAbort >::annotate(), gem5::ArmISA::DataAbort::annotate(), gem5::ArmISA::Watchpoint::annotate(), sc_core::sc_module::async_reset_signal_is(), gem5::bcdize(), gem5::bits(), gem5::bitsToFloat(), gem5::bitsToFloat32(), gem5::bitsToFloat64(), gem5::ArmISA::bitsToFp(), gem5::bitfield_backend::BitUnionOperators< Base >::BitUnionOperators(), gem5::Trace::NativeTrace::checkReg(), gem5::MhuDoorbell::clear(), gem5::composeBitVector(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), sc_dt::sc_uint_subref_r::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_data(), sc_dt::sc_uint_base::concat_get_data(), sc_dt::sc_int_base::concat_get_data(), sc_dt::sc_int_subref_r::concat_get_uint64(), gem5::statistics::constant(), gem5::statistics::constantVector(), gem5::MuxingKvmGic::copyCpuRegister(), gem5::MuxingKvmGic::copyDistRegister(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::Gcn3ISA::countZeroBits(), gem5::VegaISA::countZeroBits(), gem5::Gcn3ISA::countZeroBitsMsb(), gem5::VegaISA::countZeroBitsMsb(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::ArmISA::ArmStaticInst::cSwap(), gem5::ArmISA::FpOp::dblHi(), gem5::ArmISA::FpOp::dblLow(), gem5::statistics::StatStor::dec(), gem5::statistics::AvgStor::dec(), gem5::GenericISA::DelaySlotPCState< 4 >::DelaySlotPCState(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::DelaySlotUPCState(), gem5::PerfKvmCounterConfig::disabled(), gem5::ArmV8KvmCPU::dump(), gem5::compression::encoder::Huffman::encode(), gem5::GenericTimer::CoreTimers::EventStream::eventTargetValue(), gem5::PerfKvmCounterConfig::exclude_host(), gem5::PerfKvmCounterConfig::exclude_hv(), gem5::MipsISA::ISA::filterCP0Write(), gem5::VegaISA::findFirstOne(), gem5::Gcn3ISA::findFirstOne(), gem5::Gcn3ISA::findFirstOneMsb(), gem5::VegaISA::findFirstOneMsb(), gem5::Gcn3ISA::findFirstZero(), gem5::VegaISA::findFirstZero(), gem5::findLsbSet(), gem5::findMsbSet(), gem5::ruby::WriteMask::firstBitSet(), gem5::VegaISA::firstOppositeSignBit(), gem5::Gcn3ISA::firstOppositeSignBit(), gem5::ArmISA::fixDest(), gem5::ArmISA::fixDivDest(), gem5::ArmISA::fixFpDFpSDest(), gem5::ArmISA::fixFpSFpDDest(), gem5::floatToBits(), gem5::floatToBits32(), gem5::floatToBits64(), gem5::ArmISA::fpToBits(), gem5::futexFunc(), gem5::Gicv3CPUInterface::generateSGI(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32Composite< Composite >::value > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, Float, typename std::enable_if_t< std::is_floating_point< Float >::value > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::get(), gem5::branch_prediction::TAGEBase::getGHR(), gem5::getsockoptFunc(), gem5::HSAQueueEntry::globalWgId(), gem5::bloom_filter::H3::hash(), gem5::ArmISA::highFromDouble(), gem5::statistics::StatStor::inc(), gem5::statistics::AvgStor::inc(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< DataType >::increaseReceived(), gem5::ArmISA::PMU::PMUEvent::increment(), gem5::Trie< Addr, TlbEntry >::insert(), gem5::insertBits(), gem5::AddressManager::AtomicStruct::isExpectedValue(), gem5::PowerISA::FloatOp::isNan(), gem5::RiscvISA::isquietnan< double >(), gem5::RiscvISA::isquietnan< float >(), gem5::ArmISA::AbortFault< DataAbort >::iss(), gem5::ArmISA::DataAbort::iss(), gem5::RiscvISA::issignalingnan< double >(), gem5::RiscvISA::issignalingnan< float >(), gem5::ArmISA::isSnan(), gem5::guest_abi::Aapcs32ArgumentBase::loadFromStack(), sc_dt::sc_fxnum::lock_observer(), gem5::PciMemUpperBar::lower(), gem5::ArmISA::lowFromDouble(), sc_core::sc_report::make_warnings_errors(), gem5::mappingParamIn(), gem5::mbits(), gem5::X86ISA::X86StaticInst::merge(), gem5::ruby::mod(), gem5::mulSigned(), gem5::mulUnsigned(), gem5::GenericISA::DelaySlotPCState< 4 >::nnpc(), gem5::ProbeListenerArg< T, Arg >::notify(), gem5::ArmISA::PMU::RegularEvent::RegularProbe::notify(), gem5::GenericISA::SimplePCState< 4 >::npc(), gem5::ArmISA::number_of_ones(), gem5::GenericISA::UPCState< 8 >::nupc(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::nupc(), sc_dt::sc_uint_subref_r::operator uint_type(), sc_dt::sc_int_subref_r::operator uint_type(), gem5::bitfield_backend::BitUnionOperators< Base >::operator%=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator&=(), std::hash< gem5::BitUnionType< T > >::operator()(), gem5::bitfield_backend::BitUnionOperators< Base >::operator*=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator+=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator-=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator/=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator<<=(), gem5::BitfieldTypeImpl< Base >::operator=(), gem5::BitfieldType< Base >::operator=(), gem5::BitfieldWOType< Base >::operator=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator=(), sc_dt::sc_uint_subref::operator=(), sc_dt::sc_int_subref::operator=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator>>=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator^=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator|=(), sc_gem5::VcdTraceValTime::output(), sc_gem5::VcdTraceValInt< T >::output(), sc_dt::overflow(), gem5::GenericISA::SimplePCState< 4 >::pc(), gem5::PowerISA::PCState::PCState(), gem5::X86ISA::PCState::PCState(), gem5::o3::ThreadContext::pcState(), gem5::minor::ExecContext::pcState(), gem5::o3::Commit::pcState(), gem5::CheckerThreadContext< TC >::pcState(), gem5::Iris::ThreadContext::pcState(), gem5::CheckerCPU::pcState(), gem5::o3::CPU::pcState(), gem5::SimpleThread::pcState(), gem5::SimpleExecContext::pcState(), gem5::o3::DynInst::pcState(), gem5::GenericISA::PCStateBase::PCStateBase(), gem5::o3::ThreadContext::pcStateNoRecord(), gem5::Iris::ThreadContext::pcStateNoRecord(), gem5::CheckerThreadContext< TC >::pcStateNoRecord(), gem5::SimpleThread::pcStateNoRecord(), gem5::PerfKvmCounterConfig::pinned(), gem5::popCount(), prepareCheckDistStor(), prepareCheckHistStor(), gem5::CircularQueue< Tick >::push_back(), gem5::Gcn3ISA::quadMask(), gem5::VegaISA::quadMask(), gem5::DistIface::rankParam(), gem5::X86ISA::Interrupts::read(), gem5::VncServer::read(), gem5::Gicv3Distributor::read(), gem5::VegaISA::GPUISA::readConstVal(), gem5::Gcn3ISA::GPUISA::readConstVal(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), gem5::RiscvISA::ISA::readMiscReg(), gem5::ArmISA::PMU::readMiscReg(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::X86ISA::Interrupts::readReg(), gem5::X86ISA::Cmos::readRegister(), gem5::o3::PhysRegFile::readVecElem(), gem5::ruby::ExpectedMap< RespType, DataType >::receiveData(), gem5::ruby::ExpectedMap< RespType, DataType >::receivedDataType(), gem5::ruby::ExpectedMap< RespType, DataType >::receivedRespType(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< DataType >::receivedType(), gem5::ruby::ExpectedMap< RespType, DataType >::receiveResp(), gem5::CheckerCPU::recordPCChange(), gem5::Trie< Addr, TlbEntry >::remove(), gem5::replaceBits(), sc_core::sc_module::reset_signal_is(), gem5::Sp804::Timer::restartCounter(), gem5::CpuLocalTimer::Timer::restartTimerCounter(), gem5::CpuLocalTimer::Timer::restartWatchdogCounter(), gem5::reverseBits(), gem5::roundDown(), gem5::MipsISA::roundFP(), gem5::VegaISA::roundNearestEven(), gem5::Gcn3ISA::roundNearestEven(), gem5::ArmISA::roundNEven(), gem5::roundUp(), gem5::RiscvISA::PCState::rv32(), gem5::statistics::DistStor::sample(), gem5::statistics::HistStor::sample(), gem5::statistics::SampleStor::sample(), gem5::statistics::AvgSampleStor::sample(), gem5::statistics::SparseHistStor::sample(), gem5::Shader::ScheduleAdd(), gem5::PowerISA::PCState::set(), gem5::X86ISA::PCState::set(), gem5::MhuDoorbell::set(), gem5::statistics::StatStor::set(), gem5::statistics::AvgStor::set(), gem5::GenericISA::SimplePCState< 4 >::set(), gem5::GenericISA::UPCState< 8 >::set(), gem5::GenericISA::DelaySlotPCState< 4 >::set(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::set(), gem5::fastmodel::CortexR52::set_evs_param(), gem5::fastmodel::CortexA76::set_evs_param(), gem5::fastmodel::CortexR52Cluster::set_evs_param(), gem5::fastmodel::CortexA76Cluster::set_evs_param(), gem5::ArmISA::ArmStaticInst::setAIWNextPC(), gem5::o3::CPU::setArchCCReg(), gem5::o3::CPU::setArchFloatReg(), gem5::o3::CPU::setArchIntReg(), gem5::o3::CPU::setArchVecElem(), gem5::o3::CPU::setArchVecPredReg(), gem5::o3::CPU::setArchVecReg(), gem5::Gicv3CPUInterface::setBankedMiscReg(), gem5::ArmISA::SelfDebug::setbSDD(), gem5::MipsISA::setCauseIP(), gem5::o3::ThreadContext::setCCReg(), gem5::CheckerThreadContext< TC >::setCCReg(), gem5::Iris::ThreadContext::setCCReg(), gem5::o3::PhysRegFile::setCCReg(), gem5::o3::CPU::setCCReg(), gem5::SimpleThread::setCCReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), gem5::o3::ThreadContext::setCCRegFlat(), gem5::Iris::ThreadContext::setCCRegFlat(), gem5::CheckerThreadContext< TC >::setCCRegFlat(), gem5::SimpleThread::setCCRegFlat(), gem5::CheckerCPU::setCCRegOperand(), gem5::minor::ExecContext::setCCRegOperand(), gem5::SimpleExecContext::setCCRegOperand(), gem5::o3::DynInst::setCCRegOperand(), gem5::ArchTimer::setCompareValue(), gem5::ArchTimer::setControl(), gem5::ArmISA::PMU::setControlReg(), gem5::ArmISA::PMU::setCounterTypeRegister(), gem5::ArmISA::PMU::setCounterValue(), gem5::StaticInst::setDestRegIdx(), gem5::ruby::ExpectedMap< RespType, DataType >::setExpectedCount(), gem5::Trace::InstRecord::setFaulting(), gem5::o3::ThreadContext::setFloatReg(), gem5::o3::PhysRegFile::setFloatReg(), gem5::CheckerThreadContext< TC >::setFloatReg(), gem5::o3::CPU::setFloatReg(), gem5::SimpleThread::setFloatReg(), gem5::o3::ThreadContext::setFloatRegFlat(), gem5::CheckerThreadContext< TC >::setFloatRegFlat(), gem5::SimpleThread::setFloatRegFlat(), gem5::minor::ExecContext::setFloatRegOperandBits(), gem5::CheckerCPU::setFloatRegOperandBits(), gem5::SimpleExecContext::setFloatRegOperandBits(), gem5::o3::DynInst::setFloatRegOperandBits(), gem5::SparcISA::ISA::setFSReg(), gem5::Request::setHtmAbortCause(), gem5::RiscvISA::Interrupts::setIE(), gem5::ruby::AbstractCacheEntry::setInHtmReadSet(), gem5::ruby::AbstractCacheEntry::setInHtmWriteSet(), gem5::Request::setInstCount(), gem5::fastmodel::CortexR52TC::setIntReg(), gem5::o3::ThreadContext::setIntReg(), gem5::o3::PhysRegFile::setIntReg(), gem5::CheckerThreadContext< TC >::setIntReg(), gem5::Iris::ThreadContext::setIntReg(), gem5::o3::CPU::setIntReg(), gem5::SimpleThread::setIntReg(), gem5::fastmodel::CortexA76TC::setIntRegFlat(), gem5::o3::ThreadContext::setIntRegFlat(), gem5::Iris::ThreadContext::setIntRegFlat(), gem5::CheckerThreadContext< TC >::setIntRegFlat(), gem5::SimpleThread::setIntRegFlat(), gem5::minor::ExecContext::setIntRegOperand(), gem5::CheckerCPU::setIntRegOperand(), gem5::SimpleExecContext::setIntRegOperand(), gem5::o3::DynInst::setIntRegOperand(), gem5::RiscvISA::Interrupts::setIP(), gem5::ArmISA::ArmStaticInst::setIWNextPC(), gem5::ruby::WriteMask::setMask(), gem5::ArmISA::SelfDebug::setMDBGen(), gem5::ArmISA::SelfDebug::setMDSCRvals(), gem5::minor::ExecContext::setMemAccPredicate(), gem5::minor::MinorDynInst::setMemAccPredicate(), gem5::CheckerCPU::setMemAccPredicate(), gem5::SimpleThread::setMemAccPredicate(), gem5::SimpleExecContext::setMemAccPredicate(), gem5::o3::DynInst::setMemAccPredicate(), gem5::X86ISA::ISA::setMiscReg(), gem5::RiscvISA::ISA::setMiscReg(), gem5::ArmISA::DummyISADevice::setMiscReg(), gem5::MipsISA::ISA::setMiscReg(), gem5::ArmISA::PMU::setMiscReg(), gem5::SparcISA::ISA::setMiscReg(), gem5::GenericTimer::setMiscReg(), gem5::o3::CPU::setMiscReg(), gem5::minor::ExecContext::setMiscReg(), gem5::o3::ThreadContext::setMiscReg(), gem5::Gicv3CPUInterface::setMiscReg(), gem5::Iris::ThreadContext::setMiscReg(), gem5::CheckerThreadContext< TC >::setMiscReg(), gem5::GenericTimerISA::setMiscReg(), gem5::CheckerCPU::setMiscReg(), gem5::SimpleExecContext::setMiscReg(), gem5::SimpleThread::setMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::o3::DynInst::setMiscReg(), gem5::X86ISA::ISA::setMiscRegNoEffect(), gem5::RiscvISA::ISA::setMiscRegNoEffect(), gem5::MipsISA::ISA::setMiscRegNoEffect(), gem5::SparcISA::ISA::setMiscRegNoEffect(), gem5::o3::CPU::setMiscRegNoEffect(), gem5::o3::ThreadContext::setMiscRegNoEffect(), gem5::Iris::ThreadContext::setMiscRegNoEffect(), gem5::CheckerThreadContext< TC >::setMiscRegNoEffect(), gem5::CheckerCPU::setMiscRegNoEffect(), gem5::SimpleThread::setMiscRegNoEffect(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::minor::ExecContext::setMiscRegOperand(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::CheckerCPU::setMiscRegOperand(), gem5::o3::DynInst::setMiscRegOperand(), gem5::ArmISA::ArmStaticInst::setNextPC(), gem5::X86ISA::PCState::setNPC(), gem5::GenericISA::SimplePCState< 4 >::setNPC(), gem5::ThreadContext::setNPC(), gem5::CheckerThreadContext< TC >::setNPC(), gem5::ArchTimer::setOffset(), gem5::Trace::InstRecord::setPredicate(), gem5::minor::ExecContext::setPredicate(), gem5::minor::MinorDynInst::setPredicate(), gem5::CheckerCPU::setPredicate(), gem5::SimpleThread::setPredicate(), gem5::SimpleExecContext::setPredicate(), gem5::o3::DynInst::setPredicate(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::setRaw(), gem5::X86ISA::Interrupts::setReg(), gem5::MipsISA::ISA::setRegMask(), gem5::X86ISA::Interrupts::setRegNoEffect(), gem5::MipsISA::setRegOtherThread(), setRFlags(), gem5::StaticInst::setSrcRegIdx(), gem5::bitfield_backend::Unsigned< Storage, first, last >::setter(), gem5::bitfield_backend::Signed< Storage, first, last >::setter(), gem5::ArchTimer::setTimerValue(), gem5::ArmISA::PMU::CounterState::setValue(), gem5::o3::ThreadContext::setVecElem(), gem5::o3::PhysRegFile::setVecElem(), gem5::CheckerThreadContext< TC >::setVecElem(), gem5::o3::CPU::setVecElem(), gem5::SimpleThread::setVecElem(), gem5::o3::ThreadContext::setVecElemFlat(), gem5::CheckerThreadContext< TC >::setVecElemFlat(), gem5::SimpleThread::setVecElemFlat(), gem5::minor::ExecContext::setVecElemOperand(), gem5::CheckerCPU::setVecElemOperand(), gem5::SimpleExecContext::setVecElemOperand(), gem5::o3::DynInst::setVecElemOperand(), gem5::o3::ThreadContext::setVecPredReg(), gem5::CheckerThreadContext< TC >::setVecPredReg(), gem5::o3::PhysRegFile::setVecPredReg(), gem5::o3::CPU::setVecPredReg(), gem5::SimpleThread::setVecPredReg(), gem5::o3::ThreadContext::setVecPredRegFlat(), gem5::CheckerThreadContext< TC >::setVecPredRegFlat(), gem5::SimpleThread::setVecPredRegFlat(), gem5::minor::ExecContext::setVecPredRegOperand(), gem5::CheckerCPU::setVecPredRegOperand(), gem5::SimpleExecContext::setVecPredRegOperand(), gem5::o3::DynInst::setVecPredRegOperand(), gem5::o3::ThreadContext::setVecReg(), gem5::o3::PhysRegFile::setVecReg(), gem5::CheckerThreadContext< TC >::setVecReg(), gem5::o3::CPU::setVecReg(), gem5::SimpleThread::setVecReg(), gem5::o3::ThreadContext::setVecRegFlat(), gem5::CheckerThreadContext< TC >::setVecRegFlat(), gem5::SimpleThread::setVecRegFlat(), gem5::minor::ExecContext::setVecRegOperand(), gem5::CheckerCPU::setVecRegOperand(), gem5::SimpleExecContext::setVecRegOperand(), gem5::o3::DynInst::setVecRegOperand(), gem5::sext(), gem5::GenericISA::SimplePCState< 4 >::SimplePCState(), gem5::DistIface::sizeParam(), gem5::ArmISA::ArmStaticInst::spsrWriteByInstr(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of< ArmISA::EmuFreebsd::BaseSyscallABI, ABI >::value > >::store(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of< SparcISA::SEWorkload::BaseSyscallABI, ABI >::value > >::store(), gem5::guest_abi::enable_if_t< std::is_integral< Integer >::value &&(sizeof(Integer)< sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32Composite< Composite >::value > >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64Composite< Composite >::value &&!IsAapcs64Hxa< Composite >::value > >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregate< HA >::value > >::store(), gem5::statistics::sum(), gem5::szext(), TEST(), gem5::MipsISA::truncFP(), gem5::PortProxy::tryMemsetBlob(), gem5::unbcdize(), gem5::GenericISA::UPCState< 8 >::upc(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::upc(), gem5::GenericISA::UPCState< 8 >::UPCState(), gem5::statistics::ScalarPrint::update(), gem5::ArmISA::BrkPoint::updateControl(), gem5::ArmISA::WatchPoint::updateControl(), gem5::ArmISA::SelfDebug::updateDBGBCR(), gem5::ArmISA::SelfDebug::updateDBGWCR(), gem5::GPUDispatcher::updateInvCounter(), gem5::ArmISA::SelfDebug::updateOSLock(), gem5::HSAQueueEntry::updateOutstandingInvs(), gem5::HSAQueueEntry::updateOutstandingWbs(), gem5::GPUDispatcher::updateWbCounter(), gem5::PciMemBar::upper(), gem5::statistics::ValueToString(), gem5::ArmISA::vfpFpToFixed(), gem5::ArmISA::vfpSFixedToFpD(), gem5::ArmISA::vfpSFixedToFpS(), gem5::ArmISA::vfpUFixedToFpD(), gem5::ArmISA::vfpUFixedToFpS(), gem5::HSAQueueEntry::wgId(), gem5::Gcn3ISA::wholeQuadMode(), gem5::VegaISA::wholeQuadMode(), gem5::PciMemBar::wide(), gem5::X86ISA::Speaker::write(), gem5::X86ISA::I8259::write(), gem5::PciIoBar::write(), gem5::Gicv3Its::write(), gem5::CopyEngine::write(), gem5::ArmSemihosting::InPlaceArg::write(), gem5::PciMemBar::write(), gem5::X86ISA::Interrupts::write(), gem5::PciMemUpperBar::write(), gem5::VncServer::write(), gem5::ArmISA::PMU::SWIncrementEvent::write(), gem5::IGbE::write(), gem5::X86ISA::I8254::writeControl(), gem5::GPUExecContext::writeMiscReg(), gem5::writeOutField(), gem5::X86ISA::Cmos::writeRegister(), gem5::writeVal(), sc_dt::sc_uint_base::xor_reduce(), sc_dt::sc_int_base::xor_reduce(), and gem5::o3::DynInst::~DynInst().

◆ vcnt

gem5::X86ISA::vcnt

Definition at line 685 of file misc.hh.

◆ vector

gem5::X86ISA::vector

◆ vif

Bitfield<19> gem5::X86ISA::vif

Definition at line 566 of file misc.hh.

◆ vip

Bitfield<20> gem5::X86ISA::vip

Definition at line 565 of file misc.hh.

◆ vm

Bitfield<17> gem5::X86ISA::vm

Definition at line 568 of file misc.hh.

Referenced by gem5::ArmISA::TLB::translateFs(), and gem5::ArmISA::TLB::updateMiscReg().

◆ vme

Bitfield<0> gem5::X86ISA::vme

Definition at line 644 of file misc.hh.

◆ w

Bitfield< 3 > gem5::X86ISA::w

Definition at line 150 of file pagetable.hh.

Referenced by gem5::ArmISA::TLB::checkPermissions64().

◆ wc

Bitfield<10> gem5::X86ISA::wc

Definition at line 687 of file misc.hh.

◆ wp

Bitfield<16> gem5::X86ISA::wp

Definition at line 604 of file misc.hh.

◆ writable

Bitfield<12> gem5::X86ISA::writable

Definition at line 1000 of file misc.hh.

◆ X

Bitfield<15,0> gem5::X86ISA::X

◆ x

Bitfield< 6 > gem5::X86ISA::x

◆ zf

Bitfield< 6 > gem5::X86ISA::zf

Definition at line 552 of file misc.hh.

gem5::X86ISA::NumXMMRegs
const int NumXMMRegs
Definition: x86_traits.hh:53
gem5::X86ISA::NumMMXRegs
const int NumMMXRegs
Definition: x86_traits.hh:52
gem5::X86ISA::NumMicroFpRegs
const int NumMicroFpRegs
Definition: x86_traits.hh:54

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