gem5::X86ISA Namespace Reference

This is exposed globally, independent of the ISA. More...

Namespaces
namespace	ACPI
namespace	auxv
namespace	cc_reg
namespace	condition_tests
namespace	float_reg
namespace	int_reg
namespace	intelmp
namespace	misc_reg
namespace	segment_idx
namespace	smbios

Classes
struct	AddrOp
class	AlignmentCheck
class	BareMetalWorkload
class	BoundRange
class	Breakpoint
class	Cmos
struct	CpuidResult
struct	CrOp
struct	CrRegIndex
struct	CtrlRegIndex
struct	DataHiOp
struct	DataLowOp
struct	DataOp
struct	DbgOp
struct	DbgRegIndex
class	DebugException
class	DecodeFaultInst
class	Decoder
struct	DestOp
class	DeviceNotAvailable
class	DivideError
class	DoubleFault
class	E820Entry
class	E820Table
struct	EmulEnv
class	EmuLinux
class	ExternalInterrupt
struct	ExtMachInst
struct	FaultOp
class	FlatFloatRegClassOps
class	FlatIntRegClassOps
struct	FloatOp
class	FloatRegClassOps
struct	FoldedOp
class	FpOp
struct	FpRegIndex
class	FsLinux
class	FsWorkload
class	GeneralProtection
struct	GpRegIndex
	Classes for register indices passed to instruction constructors. More...
class	GpuTLB
struct	HasDataSize
struct	HasDataSize< T, decltype((void)&T::dataSize)>
class	I386Process
class	I8042
class	I82094AA
class	I8237
class	I8254
class	I8259
struct	Imm64Op
struct	Imm8Op
class	InitInterrupt
class	InstOperands
class	Interrupts
struct	IntOp
class	IntRegClassOps
class	IntRequestPort
class	IntResponsePort
class	InvalidOpcode
class	InvalidTSS
class	ISA
class	LdStFpOp
	Base class for load ops using one FP register. More...
class	LdStOp
	Base class for load ops using one integer register. More...
class	LdStSplitOp
	Base class for load and store ops using two registers, we will call them split ops for this reason. More...
class	LongModePTE
class	MachineCheck
class	MacroopBase
class	MediaOpBase
class	MemNoDataOp
	Base class for the tia microop which has no destination register. More...
class	MemOp
	Base class for memory ops. More...
class	MicroCondBase
class	MicroDebug
class	MicroHalt
struct	MiscOp
class	MMU
class	NonMaskableInterrupt
class	OverflowTrap
class	PageFault
class	PCState
class	RegOpBase
class	RemoteGDB
class	SecurityException
class	SegDescriptorLimit
class	SegmentNotPresent
struct	SegOp
struct	SegRegIndex
class	SIMDFloatingPointFault
class	Speaker
struct	Src1Op
struct	Src2Op
struct	Src3Op
class	StackFault
class	StackTrace
class	StartupInterrupt
class	SystemManagementInterrupt
class	TLB
struct	TlbEntry
class	UnimpInstFault
struct	UpcOp
class	Walker
class	X86_64Process
class	X86Abort
class	X86CPUID
class	X86Fault
class	X86FaultBase
class	X86Interrupt
class	X86MicroopBase
class	X86Process
class	X86StaticInst
	Base class for all X86 static instructions. More...
class	X86Trap
class	X87FpExceptionPending

Typedefs
using	FoldedDestOp = FoldedOp<DestOp>
using	DbgDestOp = DbgOp<DestOp>
using	CrDestOp = CrOp<DestOp>
using	SegDestOp = SegOp<DestOp>
using	MiscDestOp = MiscOp<DestOp>
using	FloatDestOp = FloatOp<DestOp>
using	IntDestOp = IntOp<DestOp>
using	FoldedSrc1Op = FoldedOp<Src1Op>
using	DbgSrc1Op = DbgOp<Src1Op>
using	CrSrc1Op = CrOp<Src1Op>
using	SegSrc1Op = SegOp<Src1Op>
using	MiscSrc1Op = MiscOp<Src1Op>
using	FloatSrc1Op = FloatOp<Src1Op>
using	IntSrc1Op = IntOp<Src1Op>
using	FoldedSrc2Op = FoldedOp<Src2Op>
using	FloatSrc2Op = FloatOp<Src2Op>
using	IntSrc2Op = IntOp<Src2Op>
using	FloatSrc3Op = FloatOp<Src3Op>
using	FoldedDataOp = FoldedOp<DataOp>
using	FloatDataOp = FloatOp<DataOp>
using	FoldedDataHiOp = FoldedOp<DataHiOp>
using	FoldedDataLowOp = FoldedOp<DataLowOp>
template<typename ... Operands>
using	RegOpT = InstOperands<RegOpBase, Operands...>
typedef MsrMap::value_type	MsrVal
typedef std::unordered_map< Addr, RegIndex >	MsrMap
typedef uint64_t	MachInst

Enumerations
enum	StandardCpuidFunction {   VendorAndLargestStdFunc , FamilyModelStepping , CacheAndTLB , SerialNumber ,   CacheParams , MonitorMwait , ThermalPowerMgmt , ExtendedFeatures ,   ExtendedState = 0xD , NumStandardCpuidFuncs }
enum	ExtendedCpuidFunctions {   VendorAndLargestExtFunc , FamilyModelSteppingBrandFeatures , NameString1 , NameString2 ,   NameString3 , L1CacheAndTLB , L2L3CacheAndL2TLB , APMInfo ,   LongModeAddressSize , NumExtendedCpuidFuncs }
enum	SizeType {   NoImm , NI = NoImm , ByteImm , BY = ByteImm ,   WordImm , WO = WordImm , DWordImm , DW = DWordImm ,   QWordImm , QW = QWordImm , OWordImm , OW = OWordImm ,   VWordImm , VW = VWordImm , ZWordImm , ZW = ZWordImm ,   Enter , EN = Enter , Pointer , PO = Pointer }
enum	MediaFlag { MediaMultHiOp = 1 , MediaPartHiOp = 32 , MediaSignedOp = 64 , MediaScalarOp = 128 }
enum	ApicRegIndex {   APIC_ID , APIC_VERSION , APIC_TASK_PRIORITY , APIC_ARBITRATION_PRIORITY ,   APIC_PROCESSOR_PRIORITY , APIC_EOI , APIC_LOGICAL_DESTINATION , APIC_DESTINATION_FORMAT ,   APIC_SPURIOUS_INTERRUPT_VECTOR , APIC_IN_SERVICE_BASE , APIC_TRIGGER_MODE_BASE = APIC_IN_SERVICE_BASE + 16 , APIC_INTERRUPT_REQUEST_BASE = APIC_TRIGGER_MODE_BASE + 16 ,   APIC_ERROR_STATUS = APIC_INTERRUPT_REQUEST_BASE + 16 , APIC_INTERRUPT_COMMAND_LOW , APIC_INTERRUPT_COMMAND_HIGH , APIC_LVT_TIMER ,   APIC_LVT_THERMAL_SENSOR , APIC_LVT_PERFORMANCE_MONITORING_COUNTERS , APIC_LVT_LINT0 , APIC_LVT_LINT1 ,   APIC_LVT_ERROR , APIC_INITIAL_COUNT , APIC_CURRENT_COUNT , APIC_DIVIDE_CONFIGURATION ,   APIC_INTERNAL_STATE , NUM_APIC_REGS }
enum	CondFlagBit {   CFBit = 1 << 0 , PFBit = 1 << 2 , ECFBit = 1 << 3 , AFBit = 1 << 4 ,   EZFBit = 1 << 5 , ZFBit = 1 << 6 , SFBit = 1 << 7 , DFBit = 1 << 10 ,   OFBit = 1 << 11 }
enum	RFLAGBit {   TFBit = 1 << 8 , IFBit = 1 << 9 , NTBit = 1 << 14 , RFBit = 1 << 16 ,   VMBit = 1 << 17 , ACBit = 1 << 18 , VIFBit = 1 << 19 , VIPBit = 1 << 20 ,   IDBit = 1 << 21 }
enum	X87StatusBit {   IEBit = 1 << 0 , DEBit = 1 << 1 , ZEBit = 1 << 2 , OEBit = 1 << 3 ,   UEBit = 1 << 4 , PEBit = 1 << 5 , StackFaultBit = 1 << 6 , ErrSummaryBit = 1 << 7 ,   CC0Bit = 1 << 8 , CC1Bit = 1 << 9 , CC2Bit = 1 << 10 , CC3Bit = 1 << 14 ,   BusyBit = 1 << 15 }
enum	Prefixes {   NoOverride , ESOverride , CSOverride , SSOverride ,   DSOverride , FSOverride , GSOverride , RexPrefix ,   OperandSizeOverride , AddressSizeOverride , Lock , Rep ,   Repne , Vex2Prefix , Vex3Prefix , XopPrefix }
enum	X86SubMode {   SixtyFourBitMode , CompatabilityMode , ProtectedMode , Virtual8086Mode ,   RealMode }

Functions
void	installSegDesc (ThreadContext *tc, int seg, SegDescriptor desc, bool longmode)
ApicRegIndex	decodeAddr (Addr paddr)
	BitUnion32 (TriggerIntMessage) Bitfield< 7
	EndBitUnion (TriggerIntMessage) namespace delivery_mode
static PacketPtr	buildIntTriggerPacket (int id, TriggerIntMessage message)
static PacketPtr	buildIntAcknowledgePacket ()
static void	copyMiscRegs (ThreadContext *src, ThreadContext *dest)
SyscallReturn	unameFunc (SyscallDesc *desc, ThreadContext *tc, VPtr< Linux::utsname > name)
	Target uname() handler.
SyscallReturn	archPrctlFunc (SyscallDesc *desc, ThreadContext *tc, int code, uint64_t addr)
SyscallReturn	setThreadArea32Func (SyscallDesc *desc, ThreadContext *tc, VPtr< UserDesc32 > userDesc)
	BitUnion32 (UserDescFlags) Bitfield< 0 > seg_32bit
	EndBitUnion (UserDescFlags) struct UserDesc32
static Fault	initiateMemRead (ExecContext *xc, trace::InstRecord *traceData, Addr addr, unsigned dataSize, Request::Flags flags)
	Initiate a read from memory in timing mode.
static void	getMem (PacketPtr pkt, uint64_t &mem, unsigned dataSize, trace::InstRecord *traceData)
template<typename T , size_t N>
static void	getPackedMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize)
template<size_t N>
static void	getMem (PacketPtr pkt, std::array< uint64_t, N > &mem, unsigned dataSize, trace::InstRecord *traceData)
static Fault	readMemAtomic (ExecContext *xc, trace::InstRecord *traceData, Addr addr, uint64_t &mem, unsigned dataSize, Request::Flags flags)
template<typename T , size_t N>
static Fault	readPackedMemAtomic (ExecContext *xc, Addr addr, std::array< uint64_t, N > &mem, unsigned flags)
template<size_t N>
static Fault	readMemAtomic (ExecContext *xc, trace::InstRecord *traceData, Addr addr, std::array< uint64_t, N > &mem, unsigned dataSize, unsigned flags)
template<typename T , size_t N>
static Fault	writePackedMem (ExecContext *xc, std::array< uint64_t, N > &mem, Addr addr, unsigned flags, uint64_t *res)
static Fault	writeMemTiming (ExecContext *xc, trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)
template<size_t N>
static Fault	writeMemTiming (ExecContext *xc, trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
static Fault	writeMemAtomic (ExecContext *xc, trace::InstRecord *traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t *res)
template<size_t N>
static Fault	writeMemAtomic (ExecContext *xc, trace::InstRecord *traceData, std::array< uint64_t, N > &mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
	BitUnion64 (VAddr) Bitfield< 20
	EndBitUnion (VAddr) BitUnion64(PageTableEntry) Bitfield< 63 > nx
	EndBitUnion (PageTableEntry) template< int first
static ApicRegIndex	APIC_IN_SERVICE (int index)
static ApicRegIndex	APIC_TRIGGER_MODE (int index)
static ApicRegIndex	APIC_INTERRUPT_REQUEST (int index)
	BitUnion32 (InterruptCommandRegLow) Bitfield< 7
	EndBitUnion (InterruptCommandRegLow) BitUnion32(InterruptCommandRegHigh) Bitfield< 31
constexpr RegClass	ccRegClass (CCRegClass, CCRegClassName, cc_reg::NumRegs, debug::CCRegs)
	BitUnion64 (X86IntReg) Bitfield< 63
	EndBitUnion (X86IntReg) namespace int_reg
static constexpr RegId	intRegMicro (int index)
static constexpr RegId	intRegFolded (RegIndex index, RegIndex foldBit)
constexpr RegClass	miscRegClass (MiscRegClass, MiscRegClassName, misc_reg::NumRegs, debug::MiscRegs)
	BitUnion64 (CCFlagBits) Bitfield< 11 > of
	A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode.
	EndBitUnion (CCFlagBits) BitUnion64(RFLAGS) Bitfield< 21 > id
	RFLAGS.
	EndBitUnion (RFLAGS) BitUnion64(HandyM5Reg) Bitfield< 0 > mode
	EndBitUnion (HandyM5Reg) BitUnion64(CR0) Bitfield< 31 > pg
	Control registers.
	EndBitUnion (CR0) BitUnion64(CR2) Bitfield< 31
	EndBitUnion (CR2) BitUnion64(CR3) Bitfield< 51
	EndBitUnion (CR3) BitUnion64(CR4) Bitfield< 18 > osxsave
	EndBitUnion (CR4) BitUnion64(CR8) Bitfield< 3
	EndBitUnion (CR8) BitUnion64(XCR0) Bitfield< 0 > x87
	EndBitUnion (XCR0) BitUnion64(DR6) Bitfield< 0 > b0
	EndBitUnion (DR6) BitUnion64(DR7) Bitfield< 0 > l0
	EndBitUnion (DR7) BitUnion64(MTRRcap) Bitfield< 7
	EndBitUnion (MTRRcap) BitUnion64(SysenterCS) Bitfield< 15
	SYSENTER configuration registers.
	EndBitUnion (SysenterCS) BitUnion64(SysenterESP) Bitfield< 31
	EndBitUnion (SysenterESP) BitUnion64(SysenterEIP) Bitfield< 31
	EndBitUnion (SysenterEIP) BitUnion64(McgCap) Bitfield< 7
	Global machine check registers.
	EndBitUnion (McgCap) BitUnion64(McgStatus) Bitfield< 0 > ripv
	EndBitUnion (McgStatus) BitUnion64(DebugCtlMsr) Bitfield< 0 > lbr
	EndBitUnion (DebugCtlMsr) BitUnion64(MtrrPhysBase) Bitfield< 7
	EndBitUnion (MtrrPhysBase) BitUnion64(MtrrPhysMask) Bitfield< 11 > valid
	EndBitUnion (MtrrPhysMask) BitUnion64(MtrrFixed) EndBitUnion(MtrrFixed) BitUnion64(Pat) EndBitUnion(Pat) BitUnion64(MtrrDefType) Bitfield< 7
	EndBitUnion (MtrrDefType) BitUnion64(McStatus) Bitfield< 15
	Machine check.
	EndBitUnion (McStatus) BitUnion64(McCtl) EndBitUnion(McCtl) BitUnion64(Efer) Bitfield< 0 > sce
	EndBitUnion (Efer) BitUnion64(Star) Bitfield< 31
	EndBitUnion (Star) BitUnion64(SfMask) Bitfield< 31
	EndBitUnion (SfMask) BitUnion64(PerfEvtSel) Bitfield< 7
	EndBitUnion (PerfEvtSel) BitUnion32(Syscfg) Bitfield< 18 > mfde
	EndBitUnion (Syscfg) BitUnion64(IorrBase) Bitfield< 3 > wr
	EndBitUnion (IorrBase) BitUnion64(IorrMask) Bitfield< 11 > v
	EndBitUnion (IorrMask) BitUnion64(Tom) Bitfield< 51
	EndBitUnion (Tom) BitUnion64(VmCrMsr) Bitfield< 0 > dpd
	EndBitUnion (VmCrMsr) BitUnion64(IgnneMsr) Bitfield< 0 > ignne
	EndBitUnion (IgnneMsr) BitUnion64(SmmCtlMsr) Bitfield< 0 > dismiss
	EndBitUnion (SmmCtlMsr) BitUnion64(SegSelector) Bitfield< 63
	Segment Selector.
	EndBitUnion (SegSelector) class SegDescriptorBase
	Segment Descriptors.
	BitUnion64 (SegDescriptor) Bitfield< 63
	SubBitUnion (type, 43, 40) Bitfield< 43 > codeOrData
	EndSubBitUnion (type) EndBitUnion(SegDescriptor) BitUnion64(TSSlow) Bitfield< 63
	TSS Descriptor (long mode - 128 bits) the lower 64 bits.
	EndBitUnion (TSShigh) BitUnion64(SegAttr) Bitfield< 1
	EndBitUnion (SegAttr) BitUnion64(GateDescriptor) Bitfield< 63
	EndBitUnion (GateDescriptor) BitUnion64(GateDescriptorLow) Bitfield< 63
	Long Mode Gate Descriptor.
	EndBitUnion (GateDescriptorLow) BitUnion64(GateDescriptorHigh) Bitfield< 31
	EndBitUnion (GateDescriptorHigh) BitUnion64(GDTR) EndBitUnion(GDTR) BitUnion64(IDTR) EndBitUnion(IDTR) BitUnion64(LDTR) EndBitUnion(LDTR) BitUnion64(TR) EndBitUnion(TR) BitUnion64(LocalApicBase) Bitfield< 51
	Descriptor-Table Registers.
const MsrMap	msrMap (msrMapData, msrMapData+msrMapSize)
bool	msrAddrToIndex (RegIndex &regNum, Addr addr)
	Find and return the misc reg corresponding to an MSR address.
	BitUnion8 (LegacyPrefixVector) Bitfield< 7
	EndBitUnion (LegacyPrefixVector) BitUnion8(ModRM) Bitfield< 7
	EndBitUnion (ModRM) BitUnion8(Sib) Bitfield< 7
	EndBitUnion (Sib) BitUnion8(Rex) Bitfield< 6 > present
	EndBitUnion (Rex) BitUnion8(Vex2Of3) Bitfield< 7 > r
	EndBitUnion (Vex2Of3) BitUnion8(Vex3Of3) Bitfield< 7 > w
	EndBitUnion (Vex3Of3) BitUnion8(Vex2Of2) Bitfield< 7 > r
	EndBitUnion (Vex2Of2) BitUnion8(VexInfo) Bitfield< 6
	EndBitUnion (VexInfo) enum OpcodeType
static const char *	opcodeTypeToStr (OpcodeType type)
	BitUnion8 (Opcode) Bitfield< 7
	EndBitUnion (Opcode) BitUnion8(OperatingMode) Bitfield< 3 > mode
	EndBitUnion (OperatingMode) BitUnion8(OperatingModeAndCPL) Bitfield< 5
	EndBitUnion (OperatingModeAndCPL) enum X86Mode
static std::ostream &	operator<< (std::ostream &os, const ExtMachInst &emi)
static bool	operator== (const ExtMachInst &emi1, const ExtMachInst &emi2)
uint64_t	getRFlags (ThreadContext *tc)
	Reconstruct the rflags register from the internal gem5 register state.
void	setRFlags (ThreadContext *tc, uint64_t val)
	Set update the rflags register and internal gem5 state.
uint8_t	convX87TagsToXTags (uint16_t ftw)
	Convert an x87 tag word to abridged tag format.
uint16_t	convX87XTagsToTags (uint8_t ftwx)
	Convert an x87 xtag word to normal tags format.
uint16_t	genX87Tags (uint16_t ftw, uint8_t top, int8_t spm)
	Generate and updated x87 tag register after a push/pop operation.
double	loadFloat80 (const void *mem)
	Load an 80-bit float from memory and convert it to double.
void	storeFloat80 (void *mem, double value)
	Convert and store a double as an 80-bit float.
static Addr	x86IOAddress (const uint32_t port)
static Addr	x86PciConfigAddress (const uint32_t addr)
static Addr	x86LocalAPICAddress (const uint8_t id, const uint16_t addr)
static Addr	x86InterruptAddress (const uint8_t id, const uint16_t addr)
template<class T >
PacketPtr	buildIntPacket (Addr addr, T payload)

Variables
constexpr int	nameStringSize = 48
const uint8_t	CS = CSOverride
const uint8_t	DS = DSOverride
const uint8_t	ES = ESOverride
const uint8_t	FS = FSOverride
const uint8_t	GS = GSOverride
const uint8_t	SS = SSOverride
const uint8_t	OO = OperandSizeOverride
const uint8_t	AO = AddressSizeOverride
const uint8_t	LO = Lock
const uint8_t	RE = Rep
const uint8_t	RN = Repne
const uint8_t	RX = RexPrefix
const uint8_t	V2 = Vex2Prefix
const uint8_t	V3 = Vex3Prefix
const StaticInstPtr	badMicroop
template<class T >
constexpr bool	HasDataSizeV = HasDataSize<T>::value
	destination
Bitfield< 15, 8 >	vector
Bitfield< 18, 16 >	deliveryMode
Bitfield< 19 >	destMode
Bitfield< 20 >	level
Bitfield< 21 >	trigger
static const Addr	TriggerIntOffset = 0
constexpr Request::FlagsType	SegmentFlagMask = mask(4)
constexpr auto	CPL0FlagShift = 4
constexpr auto	CPL0FlagBit = 1 << CPL0FlagShift
constexpr auto	AddrSizeFlagShift = CPL0FlagShift + 1
constexpr auto	AddrSizeFlagMask = mask(2)
Bitfield< 2, 1 >	contents
Bitfield< 3 >	read_exec_only
Bitfield< 4 >	limit_in_pages
Bitfield< 5 >	seg_not_present
Bitfield< 6 >	useable
const Addr	PageShift = 12
const Addr	PageBytes = 1ULL << PageShift
	longl1
Bitfield< 29, 21 >	longl2
Bitfield< 38, 30 >	longl3
Bitfield< 47, 39 >	longl4
Bitfield< 20, 12 >	pael1
Bitfield< 29, 21 >	pael2
Bitfield< 31, 30 >	pael3
Bitfield< 21, 12 >	norml1
Bitfield< 31, 22 >	norml2
Bitfield< 51, 12 >	base
Bitfield< 11, 9 >	avl
Bitfield< 8 >	g
Bitfield< 7 >	ps
Bitfield< 6 >	d
Bitfield< 5 >	a
Bitfield< 4 >	pcd
Bitfield< 3 >	pwt
Bitfield< 2 >	u
Bitfield< 1 >	w
Bitfield< 0 >	p
Bitfield< 12 >	deliveryStatus
Bitfield< 19, 18 >	destShorthand
constexpr FlatFloatRegClassOps	flatFloatRegClassOps
constexpr RegClass	flatFloatRegClass
constexpr FloatRegClassOps	floatRegClassOps
constexpr RegClass	floatRegClass
	R
SignedBitfield< 63, 0 >	SR
Bitfield< 31, 0 >	E
SignedBitfield< 31, 0 >	SE
Bitfield< 15, 0 >	X
SignedBitfield< 15, 0 >	SX
Bitfield< 15, 8 >	H
SignedBitfield< 15, 8 >	SH
Bitfield< 7, 0 >	L
SignedBitfield< 7, 0 >	SL
constexpr FlatIntRegClassOps	flatIntRegClassOps
constexpr RegClass	flatIntRegClass
constexpr IntRegClassOps	intRegClassOps
constexpr RegClass	intRegClass
constexpr RegIndex	IntFoldBit = 1 << 6
constexpr uint32_t	CfofMask = CFBit | OFBit
constexpr uint32_t	CcFlagMask = PFBit | AFBit | ZFBit | SFBit
Bitfield< 7 >	sf
Bitfield< 6 >	zf
Bitfield< 5 >	ezf
Bitfield< 4 >	af
Bitfield< 3 >	ecf
Bitfield< 2 >	pf
Bitfield< 0 >	cf
Bitfield< 20 >	vip
Bitfield< 19 >	vif
Bitfield< 18 >	ac
Bitfield< 17 >	vm
Bitfield< 16 >	rf
Bitfield< 14 >	nt
Bitfield< 13, 12 >	iopl
Bitfield< 11 >	of
Bitfield< 10 >	df
Bitfield< 9 >	intf
Bitfield< 8 >	tf
Bitfield< 3, 1 >	submode
Bitfield< 5, 4 >	cpl
Bitfield< 6 >	paging
Bitfield< 7 >	prot
Bitfield< 9, 8 >	defOp
Bitfield< 11, 10 >	altOp
Bitfield< 13, 12 >	defAddr
Bitfield< 15, 14 >	altAddr
Bitfield< 17, 16 >	stack
Bitfield< 30 >	cd
Bitfield< 29 >	nw
Bitfield< 18 >	am
Bitfield< 16 >	wp
Bitfield< 5 >	ne
Bitfield< 4 >	et
Bitfield< 3 >	ts
Bitfield< 2 >	em
Bitfield< 1 >	mp
Bitfield< 0 >	pe
	legacy
	longPdtb
Bitfield< 31, 12 >	pdtb
Bitfield< 31, 5 >	paePdtb
Bitfield< 11, 0 >	pcid
Bitfield< 17 >	pcide
Bitfield< 16 >	fsgsbase
Bitfield< 10 >	osxmmexcpt
Bitfield< 9 >	osfxsr
Bitfield< 8 >	pce
Bitfield< 7 >	pge
Bitfield< 6 >	mce
Bitfield< 5 >	pae
Bitfield< 4 >	pse
Bitfield< 3 >	de
Bitfield< 2 >	tsd
Bitfield< 1 >	pvi
Bitfield< 0 >	vme
	tpr
Bitfield< 1 >	sse
Bitfield< 2 >	avx
Bitfield< 3 >	bndreg
Bitfield< 4 >	bndsrc
Bitfield< 5 >	opmask
Bitfield< 6 >	zmm_hi256
Bitfield< 7 >	hi16_zmm
Bitfield< 9 >	pkru
Bitfield< 1 >	b1
Bitfield< 2 >	b2
Bitfield< 3 >	b3
Bitfield< 13 >	bd
Bitfield< 14 >	bs
Bitfield< 15 >	bt
Bitfield< 1 >	g0
Bitfield< 2 >	l1
Bitfield< 3 >	g1
Bitfield< 4 >	l2
Bitfield< 5 >	g2
Bitfield< 6 >	l3
Bitfield< 7 >	g3
Bitfield< 8 >	le
Bitfield< 9 >	ge
Bitfield< 13 >	gd
Bitfield< 17, 16 >	rw0
Bitfield< 19, 18 >	len0
Bitfield< 21, 20 >	rw1
Bitfield< 23, 22 >	len1
Bitfield< 25, 24 >	rw2
Bitfield< 27, 26 >	len2
Bitfield< 29, 28 >	rw3
Bitfield< 31, 30 >	len3
	vcnt
Bitfield< 8 >	fix
Bitfield< 10 >	wc
	targetCS
	targetESP
	targetEIP
	count
Bitfield< 8 >	MCGCP
Bitfield< 1 >	eipv
Bitfield< 2 >	mcip
Bitfield< 1 >	btf
Bitfield< 2 >	pb0
Bitfield< 3 >	pb1
Bitfield< 4 >	pb2
Bitfield< 5 >	pb3
	type
Bitfield< 51, 12 >	physbase
Bitfield< 51, 12 >	physmask
Bitfield< 10 >	fe
Bitfield< 11 >	e
	mcaErrorCode
Bitfield< 31, 16 >	modelSpecificCode
Bitfield< 56, 32 >	otherInfo
Bitfield< 57 >	pcc
Bitfield< 58 >	addrv
Bitfield< 59 >	miscv
Bitfield< 60 >	en
Bitfield< 61 >	uc
Bitfield< 62 >	over
Bitfield< 63 >	val
Bitfield< 8 >	lme
Bitfield< 10 >	lma
Bitfield< 11 >	nxe
Bitfield< 12 >	svme
Bitfield< 14 >	ffxsr
	targetEip
Bitfield< 47, 32 >	syscallCsAndSs
Bitfield< 63, 48 >	sysretCsAndSs
	mask
	eventMask
Bitfield< 15, 8 >	unitMask
Bitfield< 16 >	usr
Bitfield< 17 >	os
Bitfield< 19 >	pc
Bitfield< 20 >	intEn
Bitfield< 23 >	inv
Bitfield< 31, 24 >	counterMask
Bitfield< 19 >	mfdm
Bitfield< 20 >	mvdm
Bitfield< 21 >	tom2
Bitfield< 4 >	rd
	physAddr
Bitfield< 1 >	rInit
Bitfield< 2 >	disA20M
Bitfield< 1 >	enter
Bitfield< 2 >	smiCycle
Bitfield< 3 >	exit
Bitfield< 4 >	rsmCycle
	esi
Bitfield< 15, 3 >	si
Bitfield< 2 >	ti
Bitfield< 1, 0 >	rpl
	baseHigh
Bitfield< 39, 16 >	baseLow
Bitfield< 54 >	b
Bitfield< 53 >	l
Bitfield< 51, 48 >	limitHigh
Bitfield< 15, 0 >	limitLow
BitfieldType< SegDescriptorLimit >	limit
Bitfield< 46, 45 >	dpl
Bitfield< 44 >	s
Bitfield< 42 >	c
Bitfield< 41 >	r
Bitfield< 2 >	unusable
Bitfield< 3 >	defaultSize
Bitfield< 4 >	longMode
Bitfield< 6 >	granularity
Bitfield< 7 >	present
Bitfield< 12 >	writable
Bitfield< 13 >	readable
Bitfield< 14 >	expandDown
Bitfield< 15 >	system
	offsetHigh
Bitfield< 15, 0 >	offsetLow
Bitfield< 31, 16 >	selector
Bitfield< 35, 32 >	IST
	offset
Bitfield< 11 >	enable
Bitfield< 8 >	bsp
const MsrMap::value_type	msrMapData []
static const unsigned	msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])
const MsrMap	msrMap
	Map between MSR addresses and their corresponding misc registers.
const Addr	syscallCodeVirtAddr = 0xffff800000000000
const Addr	GDTVirtAddr = 0xffff800000001000
const Addr	IDTVirtAddr = 0xffff800000002000
const Addr	TSSVirtAddr = 0xffff800000003000
const Addr	TSSPhysAddr = 0x63000
const Addr	ISTVirtAddr = 0xffff800000004000
const Addr	PFHandlerVirtAddr = 0xffff800000005000
const Addr	MMIORegionVirtAddr = 0xffffc90000000000
	decodeVal
Bitfield< 7 >	repne
Bitfield< 6 >	rep
Bitfield< 5 >	lock
Bitfield< 4 >	op
Bitfield< 3 >	addr
Bitfield< 2, 0 >	seg
	mod
Bitfield< 5, 3 >	reg
Bitfield< 2, 0 >	rm
	scale
Bitfield< 5, 3 >	index
Bitfield< 1 >	x
Bitfield< 4, 0 >	m
Bitfield< 6, 3 >	v
	top5
Bitfield< 2, 0 >	bottom3
Bitfield< 3 >	mode
const int	NumMicroIntRegs = 16
const int	NumMMXRegs = 8
const int	NumXMMRegs = 16
const int	NumMicroFpRegs = 8
const int	NumCRegs = 16
const int	NumDRegs = 8
const int	NumXCRegs = 1
const int	NumSegments = 6
const int	NumSysSegments = 4
const Addr	IntAddrPrefixMask = 0xffffffff00000000ULL
const Addr	IntAddrPrefixCPUID = 0x100000000ULL
const Addr	IntAddrPrefixMSR = 0x200000000ULL
const Addr	IntAddrPrefixIO = 0x300000000ULL
const Addr	PhysAddrPrefixIO = 0x8000000000000000ULL
const Addr	PhysAddrPrefixPciConfig = 0xC000000000000000ULL
const Addr	PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL
const Addr	PhysAddrPrefixInterrupts = 0xA000000000000000ULL
const Addr	PhysAddrAPICRangeSize = 1 << 12
const Addr	PhysAddrIntA = 0x8000000100000000ULL

Detailed Description

This is exposed globally, independent of the ISA.

Typedef Documentation

CrDestOp

using gem5::X86ISA::CrDestOp = CrOp<DestOp>

Definition at line 269 of file microop_args.hh.

CrSrc1Op

using gem5::X86ISA::CrSrc1Op = CrOp<Src1Op>

Definition at line 277 of file microop_args.hh.

DbgDestOp

using gem5::X86ISA::DbgDestOp = DbgOp<DestOp>

Definition at line 268 of file microop_args.hh.

DbgSrc1Op

using gem5::X86ISA::DbgSrc1Op = DbgOp<Src1Op>

Definition at line 276 of file microop_args.hh.

FloatDataOp

using gem5::X86ISA::FloatDataOp = FloatOp<DataOp>

Definition at line 290 of file microop_args.hh.

FloatDestOp

using gem5::X86ISA::FloatDestOp = FloatOp<DestOp>

Definition at line 272 of file microop_args.hh.

FloatSrc1Op

using gem5::X86ISA::FloatSrc1Op = FloatOp<Src1Op>

Definition at line 280 of file microop_args.hh.

FloatSrc2Op

using gem5::X86ISA::FloatSrc2Op = FloatOp<Src2Op>

Definition at line 284 of file microop_args.hh.

FloatSrc3Op

using gem5::X86ISA::FloatSrc3Op = FloatOp<Src3Op>

Definition at line 287 of file microop_args.hh.

FoldedDataHiOp

using gem5::X86ISA::FoldedDataHiOp = FoldedOp<DataHiOp>

Definition at line 291 of file microop_args.hh.

FoldedDataLowOp

using gem5::X86ISA::FoldedDataLowOp = FoldedOp<DataLowOp>

Definition at line 292 of file microop_args.hh.

FoldedDataOp

using gem5::X86ISA::FoldedDataOp = FoldedOp<DataOp>

Definition at line 289 of file microop_args.hh.

FoldedDestOp

using gem5::X86ISA::FoldedDestOp = FoldedOp<DestOp>

Definition at line 267 of file microop_args.hh.

FoldedSrc1Op

using gem5::X86ISA::FoldedSrc1Op = FoldedOp<Src1Op>

Definition at line 275 of file microop_args.hh.

FoldedSrc2Op

using gem5::X86ISA::FoldedSrc2Op = FoldedOp<Src2Op>

Definition at line 283 of file microop_args.hh.

IntDestOp

using gem5::X86ISA::IntDestOp = IntOp<DestOp>

Definition at line 273 of file microop_args.hh.

IntSrc1Op

using gem5::X86ISA::IntSrc1Op = IntOp<Src1Op>

Definition at line 281 of file microop_args.hh.

IntSrc2Op

using gem5::X86ISA::IntSrc2Op = IntOp<Src2Op>

Definition at line 285 of file microop_args.hh.

MachInst

typedef uint64_t gem5::X86ISA::MachInst

Definition at line 56 of file types.hh.

MiscDestOp

using gem5::X86ISA::MiscDestOp = MiscOp<DestOp>

Definition at line 271 of file microop_args.hh.

MiscSrc1Op

using gem5::X86ISA::MiscSrc1Op = MiscOp<Src1Op>

Definition at line 279 of file microop_args.hh.

MsrMap

typedef std::unordered_map<Addr, RegIndex> gem5::X86ISA::MsrMap

Definition at line 43 of file msr.hh.

MsrVal

typedef MsrMap::value_type gem5::X86ISA::MsrVal

Definition at line 37 of file msr.cc.

RegOpT

template<typename ... Operands>

using gem5::X86ISA::RegOpT = InstOperands<RegOpBase, Operands...>

Definition at line 74 of file microregop.hh.

SegDestOp

using gem5::X86ISA::SegDestOp = SegOp<DestOp>

Definition at line 270 of file microop_args.hh.

SegSrc1Op

using gem5::X86ISA::SegSrc1Op = SegOp<Src1Op>

Definition at line 278 of file microop_args.hh.

Enumeration Type Documentation

ApicRegIndex

enum gem5::X86ISA::ApicRegIndex

Enumerator
APIC_ID
APIC_VERSION
APIC_TASK_PRIORITY
APIC_ARBITRATION_PRIORITY
APIC_PROCESSOR_PRIORITY
APIC_EOI
APIC_LOGICAL_DESTINATION
APIC_DESTINATION_FORMAT
APIC_SPURIOUS_INTERRUPT_VECTOR
APIC_IN_SERVICE_BASE
APIC_TRIGGER_MODE_BASE
APIC_INTERRUPT_REQUEST_BASE
APIC_ERROR_STATUS
APIC_INTERRUPT_COMMAND_LOW
APIC_INTERRUPT_COMMAND_HIGH
APIC_LVT_TIMER
APIC_LVT_THERMAL_SENSOR
APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
APIC_LVT_LINT0
APIC_LVT_LINT1
APIC_LVT_ERROR
APIC_INITIAL_COUNT
APIC_CURRENT_COUNT
APIC_DIVIDE_CONFIGURATION
APIC_INTERNAL_STATE
NUM_APIC_REGS

Definition at line 39 of file apic.hh.

CondFlagBit

enum gem5::X86ISA::CondFlagBit

Enumerator
CFBit
PFBit
ECFBit
AFBit
EZFBit
ZFBit
SFBit
DFBit
OFBit

Definition at line 59 of file misc.hh.

ExtendedCpuidFunctions

enum gem5::X86ISA::ExtendedCpuidFunctions

Enumerator
VendorAndLargestExtFunc
FamilyModelSteppingBrandFeatures
NameString1
NameString2
NameString3
L1CacheAndTLB
L2L3CacheAndL2TLB
APMInfo
LongModeAddressSize
NumExtendedCpuidFuncs

Definition at line 59 of file cpuid.hh.

MediaFlag

enum gem5::X86ISA::MediaFlag

Enumerator
MediaMultHiOp
MediaPartHiOp
MediaSignedOp
MediaScalarOp

Definition at line 40 of file micromediaop.hh.

Prefixes

enum gem5::X86ISA::Prefixes

Enumerator
NoOverride
ESOverride
CSOverride
SSOverride
DSOverride
FSOverride
GSOverride
RexPrefix
OperandSizeOverride
AddressSizeOverride
Lock
Rep
Repne
Vex2Prefix
Vex3Prefix
XopPrefix

Definition at line 58 of file types.hh.

RFLAGBit

enum gem5::X86ISA::RFLAGBit

Enumerator
TFBit
IFBit
NTBit
RFBit
VMBit
ACBit
VIFBit
VIPBit
IDBit

Definition at line 75 of file misc.hh.

SizeType

enum gem5::X86ISA::SizeType

Enumerator
NoImm
NI
ByteImm
BY
WordImm
WO
DWordImm
DW
QWordImm
QW
OWordImm
OW
VWordImm
VW
ZWordImm
ZW
Enter
EN
Pointer
PO

Definition at line 191 of file decoder_tables.cc.

StandardCpuidFunction

enum gem5::X86ISA::StandardCpuidFunction

Enumerator
VendorAndLargestStdFunc
FamilyModelStepping
CacheAndTLB
SerialNumber
CacheParams
MonitorMwait
ThermalPowerMgmt
ExtendedFeatures
ExtendedState
NumStandardCpuidFuncs

Definition at line 45 of file cpuid.hh.

X86SubMode

enum gem5::X86ISA::X86SubMode

Enumerator
SixtyFourBitMode
CompatabilityMode
ProtectedMode
Virtual8086Mode
RealMode

Definition at line 202 of file types.hh.

X87StatusBit

enum gem5::X86ISA::X87StatusBit

Enumerator
IEBit
DEBit
ZEBit
OEBit
UEBit
PEBit
StackFaultBit
ErrSummaryBit
CC0Bit
CC1Bit
CC2Bit
CC3Bit
BusyBit

Definition at line 88 of file misc.hh.

Function Documentation

APIC_IN_SERVICE()

static ApicRegIndex gem5::X86ISA::APIC_IN_SERVICE ( int index )

inlinestatic

Definition at line 76 of file apic.hh.

References APIC_IN_SERVICE_BASE, and index.

Referenced by decodeAddr(), and gem5::X86ISA::Interrupts::setReg().

APIC_INTERRUPT_REQUEST()

static ApicRegIndex gem5::X86ISA::APIC_INTERRUPT_REQUEST ( int index )

inlinestatic

Definition at line 88 of file apic.hh.

References APIC_INTERRUPT_REQUEST_BASE, and index.

Referenced by decodeAddr(), and gem5::X86ISA::Interrupts::setReg().

APIC_TRIGGER_MODE()

static ApicRegIndex gem5::X86ISA::APIC_TRIGGER_MODE ( int index )

inlinestatic

Definition at line 82 of file apic.hh.

References APIC_TRIGGER_MODE_BASE, and index.

Referenced by decodeAddr(), gem5::X86ISA::Interrupts::readReg(), and gem5::X86ISA::Interrupts::setReg().

archPrctlFunc()

SyscallReturn gem5::X86ISA::archPrctlFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		int	code,
		uint64_t	addr )

Definition at line 63 of file syscalls.cc.

References addr, gem5::X86ISA::misc_reg::FsBase, gem5::X86ISA::misc_reg::FsEffBase, gem5::X86ISA::misc_reg::GsBase, gem5::X86ISA::misc_reg::GsEffBase, p, gem5::ThreadContext::readMiscRegNoEffect(), and gem5::ThreadContext::setMiscRegNoEffect().

BitUnion32() [1/3]

gem5::X86ISA::BitUnion32

(

InterruptCommandRegLow

)

BitUnion32() [2/3]

gem5::X86ISA::BitUnion32

(

TriggerIntMessage

)

BitUnion32() [3/3]

gem5::X86ISA::BitUnion32

(

UserDescFlags

)

BitUnion64() [1/4]

gem5::X86ISA::BitUnion64

(

CCFlagBits

)

A type to describe the condition code bits of the RFLAGS register, plus two flags, EZF and ECF, which are only visible to microcode.

BitUnion64() [2/4]

gem5::X86ISA::BitUnion64

(

SegDescriptor

)

BitUnion64() [3/4]

gem5::X86ISA::BitUnion64

(

VAddr

)

BitUnion64() [4/4]

gem5::X86ISA::BitUnion64

(

X86IntReg

)

BitUnion8() [1/2]

gem5::X86ISA::BitUnion8

(

LegacyPrefixVector

)

BitUnion8() [2/2]

gem5::X86ISA::BitUnion8

(

Opcode

)

buildIntAcknowledgePacket()

static PacketPtr gem5::X86ISA::buildIntAcknowledgePacket ( )

inlinestatic

Definition at line 91 of file intmessage.hh.

References gem5::Packet::allocate(), gem5::Request::intRequestorId, PhysAddrIntA, gem5::MemCmd::ReadReq, and gem5::Request::UNCACHEABLE.

Referenced by gem5::X86ISA::Interrupts::raiseInterruptPin(), and gem5::X86ISA::I82094AA::requestInterrupt().

buildIntPacket()

template<class T >

PacketPtr gem5::X86ISA::buildIntPacket	(	Addr	addr,
		T	payload )

Definition at line 89 of file intdev.hh.

References addr, gem5::Packet::allocate(), gem5::Request::intRequestorId, gem5::Packet::setRaw(), gem5::Request::UNCACHEABLE, and gem5::MemCmd::WriteReq.

Referenced by buildIntTriggerPacket().

buildIntTriggerPacket()

static PacketPtr gem5::X86ISA::buildIntTriggerPacket ( int id, TriggerIntMessage message )

inlinestatic

Definition at line 84 of file intmessage.hh.

References addr, buildIntPacket(), TriggerIntOffset, and x86InterruptAddress().

Referenced by gem5::X86ISA::Interrupts::setReg(), and gem5::X86ISA::I82094AA::signalInterrupt().

ccRegClass()

RegClass gem5::X86ISA::ccRegClass ( CCRegClass , CCRegClassName , cc_reg::NumRegs , debug::CCRegs  )

inlineconstexpr

convX87TagsToXTags()

uint8_t gem5::X86ISA::convX87TagsToXTags

(

uint16_t

ftw

)

Convert an x87 tag word to abridged tag format.

Convert from the x87 tag representation to the tag abridged representation used in the FXSAVE area. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Parameters

ftw	Tag word in classic x87 format.

Returns

Tag word in the abridged format.

Definition at line 90 of file utility.cc.

References gem5::ArmISA::i.

Referenced by gem5::updateKvmStateFPUCommon().

convX87XTagsToTags()

uint16_t gem5::X86ISA::convX87XTagsToTags

(

uint8_t

ftwx

)

Convert an x87 xtag word to normal tags format.

Convert from the abridged x87 tag representation used in the FXSAVE area to a full x87 tag. The classic format uses 2 bits per stack position to indicate if a position is valid, zero, special, or empty. The abridged format only stores whether a position is empty or not.

Todo

Reconstruct the correct state of stack positions instead of just valid/invalid.

Parameters

ftwx	Tag word in the abridged format.

Returns

Tag word in classic x87 format.

Definition at line 115 of file utility.cc.

References gem5::ArmISA::i.

Referenced by gem5::updateThreadContextFPUCommon().

copyMiscRegs()

static void gem5::X86ISA::copyMiscRegs ( ThreadContext * src, ThreadContext * dest )

static

Definition at line 182 of file isa.cc.

References gem5::BaseMMU::flushAll(), gem5::ThreadContext::getMMUPtr(), gem5::ArmISA::i, gem5::X86ISA::misc_reg::isValid(), gem5::X86ISA::misc_reg::NumRegs, gem5::ThreadContext::readMiscReg(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setMiscRegNoEffect(), and gem5::X86ISA::misc_reg::Tsc.

Referenced by gem5::X86ISA::ISA::copyRegsFrom().

decodeAddr()

ApicRegIndex gem5::X86ISA::decodeAddr

(

Addr

paddr

)

Definition at line 85 of file interrupts.cc.

References APIC_ARBITRATION_PRIORITY, APIC_CURRENT_COUNT, APIC_DESTINATION_FORMAT, APIC_DIVIDE_CONFIGURATION, APIC_EOI, APIC_ERROR_STATUS, APIC_ID, APIC_IN_SERVICE(), APIC_INITIAL_COUNT, APIC_INTERRUPT_COMMAND_HIGH, APIC_INTERRUPT_COMMAND_LOW, APIC_INTERRUPT_REQUEST(), APIC_LOGICAL_DESTINATION, APIC_LVT_ERROR, APIC_LVT_LINT0, APIC_LVT_LINT1, APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, APIC_LVT_THERMAL_SENSOR, APIC_LVT_TIMER, APIC_PROCESSOR_PRIORITY, APIC_SPURIOUS_INTERRUPT_VECTOR, APIC_TASK_PRIORITY, APIC_TRIGGER_MODE(), APIC_VERSION, and panic.

Referenced by gem5::X86ISA::Interrupts::read(), and gem5::X86ISA::Interrupts::write().

EndBitUnion() [1/56]

gem5::X86ISA::EndBitUnion

(

CCFlagBits

)

RFLAGS.

EndBitUnion() [2/56]

gem5::X86ISA::EndBitUnion

(

CR0

)

EndBitUnion() [3/56]

gem5::X86ISA::EndBitUnion

(

CR2

)

EndBitUnion() [4/56]

gem5::X86ISA::EndBitUnion

(

CR3

)

EndBitUnion() [5/56]

gem5::X86ISA::EndBitUnion

(

CR4

)

EndBitUnion() [6/56]

gem5::X86ISA::EndBitUnion

(

CR8

)

EndBitUnion() [7/56]

gem5::X86ISA::EndBitUnion

(

DebugCtlMsr

)

EndBitUnion() [8/56]

gem5::X86ISA::EndBitUnion

(

DR6

)

EndBitUnion() [9/56]

gem5::X86ISA::EndBitUnion

(

DR7

)

EndBitUnion() [10/56]

gem5::X86ISA::EndBitUnion

(

Efer

)

EndBitUnion() [11/56]

gem5::X86ISA::EndBitUnion

(

GateDescriptor

)

Long Mode Gate Descriptor.

EndBitUnion() [12/56]

gem5::X86ISA::EndBitUnion

(

GateDescriptorHigh

)

Descriptor-Table Registers.

Task Register Local APIC Base Register

EndBitUnion() [13/56]

gem5::X86ISA::EndBitUnion

(

GateDescriptorLow

)

EndBitUnion() [14/56]

gem5::X86ISA::EndBitUnion

(

HandyM5Reg

)

Control registers.

EndBitUnion() [15/56]

gem5::X86ISA::EndBitUnion

(

IgnneMsr

)

EndBitUnion() [16/56]

gem5::X86ISA::EndBitUnion

(

InterruptCommandRegLow

)

EndBitUnion() [17/56]

gem5::X86ISA::EndBitUnion

(

IorrBase

)

EndBitUnion() [18/56]

gem5::X86ISA::EndBitUnion

(

IorrMask

)

EndBitUnion() [19/56]

gem5::X86ISA::EndBitUnion

(

LegacyPrefixVector

)

EndBitUnion() [20/56]

gem5::X86ISA::EndBitUnion

(

McgCap

)

EndBitUnion() [21/56]

gem5::X86ISA::EndBitUnion

(

McgStatus

)

EndBitUnion() [22/56]

gem5::X86ISA::EndBitUnion

(

McStatus

)

EndBitUnion() [23/56]

gem5::X86ISA::EndBitUnion

(

ModRM

)

EndBitUnion() [24/56]

gem5::X86ISA::EndBitUnion

(

MTRRcap

)

SYSENTER configuration registers.

EndBitUnion() [25/56]

gem5::X86ISA::EndBitUnion

(

MtrrDefType

)

Machine check.

EndBitUnion() [26/56]

gem5::X86ISA::EndBitUnion

(

MtrrPhysBase

)

EndBitUnion() [27/56]

gem5::X86ISA::EndBitUnion

(

MtrrPhysMask

)

EndBitUnion() [28/56]

gem5::X86ISA::EndBitUnion

(

Opcode

)

EndBitUnion() [29/56]

gem5::X86ISA::EndBitUnion

(

OperatingMode

)

EndBitUnion() [30/56]

gem5::X86ISA::EndBitUnion

(

OperatingModeAndCPL

)

Definition at line 194 of file types.hh.

EndBitUnion() [31/56]

gem5::X86ISA::EndBitUnion

(

PageTableEntry

)

EndBitUnion() [32/56]

gem5::X86ISA::EndBitUnion

(

PerfEvtSel

)

EndBitUnion() [33/56]

gem5::X86ISA::EndBitUnion

(

Rex

)

EndBitUnion() [34/56]

gem5::X86ISA::EndBitUnion

(

RFLAGS

)

EndBitUnion() [35/56]

gem5::X86ISA::EndBitUnion

(

SegAttr

)

EndBitUnion() [36/56]

gem5::X86ISA::EndBitUnion

(

SegSelector

)

Segment Descriptors.

Definition at line 898 of file misc.hh.

References base, gem5::bits(), and gem5::replaceBits().

EndBitUnion() [37/56]

gem5::X86ISA::EndBitUnion

(

SfMask

)

EndBitUnion() [38/56]

gem5::X86ISA::EndBitUnion

(

Sib

)

EndBitUnion() [39/56]

gem5::X86ISA::EndBitUnion

(

SmmCtlMsr

)

Segment Selector.

EndBitUnion() [40/56]

gem5::X86ISA::EndBitUnion

(

Star

)

EndBitUnion() [41/56]

gem5::X86ISA::EndBitUnion

(

Syscfg

)

EndBitUnion() [42/56]

gem5::X86ISA::EndBitUnion

(

SysenterCS

)

EndBitUnion() [43/56]

gem5::X86ISA::EndBitUnion

(

SysenterEIP

)

Global machine check registers.

EndBitUnion() [44/56]

gem5::X86ISA::EndBitUnion

(

SysenterESP

)

EndBitUnion() [45/56]

gem5::X86ISA::EndBitUnion

(

Tom

)

EndBitUnion() [46/56]

gem5::X86ISA::EndBitUnion

(

TriggerIntMessage

)

Definition at line 53 of file intmessage.hh.

References mode.

EndBitUnion() [47/56]

gem5::X86ISA::EndBitUnion

(

TSShigh

)

EndBitUnion() [48/56]

gem5::X86ISA::EndBitUnion

(

UserDescFlags

)

Definition at line 55 of file syscalls.hh.

References flags, and limit.

EndBitUnion() [49/56]

gem5::X86ISA::EndBitUnion

(

VAddr

)

EndBitUnion() [50/56]

gem5::X86ISA::EndBitUnion

(

Vex2Of2

)

EndBitUnion() [51/56]

gem5::X86ISA::EndBitUnion

(

Vex2Of3

)

EndBitUnion() [52/56]

gem5::X86ISA::EndBitUnion

(

Vex3Of3

)

EndBitUnion() [53/56]

gem5::X86ISA::EndBitUnion

(

VexInfo

)

Definition at line 150 of file types.hh.

EndBitUnion() [54/56]

gem5::X86ISA::EndBitUnion

(

VmCrMsr

)

EndBitUnion() [55/56]

gem5::X86ISA::EndBitUnion

(

X86IntReg

)

Definition at line 64 of file int.hh.

References NumMicroIntRegs.

EndBitUnion() [56/56]

gem5::X86ISA::EndBitUnion

(

XCR0

)

EndSubBitUnion()

gem5::X86ISA::EndSubBitUnion

(

type

)

TSS Descriptor (long mode - 128 bits) the lower 64 bits.

TSS Descriptor (long mode - 128 bits) the upper 64 bits.

genX87Tags()

uint16_t gem5::X86ISA::genX87Tags	(	uint16_t	ftw,
		uint8_t	top,
		int8_t	spm )

Generate and updated x87 tag register after a push/pop operation.

Note

There is currently no support for setting other tags than valid and invalid. A real x87 will set the tag value to zero or special for some special floating point values.

Parameters

ftw	Current value of the FTW register.
top	Current x87 TOP value.
spm	Stack displacement.

Returns

New value of the FTW register.

Definition at line 136 of file utility.cc.

References gem5::ArmISA::i.

getMem() [1/2]

template<size_t N>

static void gem5::X86ISA::getMem ( PacketPtr pkt, std::array< uint64_t, N > & mem, unsigned dataSize, trace::InstRecord * traceData )

static

Definition at line 90 of file memhelpers.hh.

References getPackedMem(), mem, panic, and gem5::trace::InstRecord::setData().

getMem() [2/2]

static void gem5::X86ISA::getMem ( PacketPtr pkt, uint64_t & mem, unsigned dataSize, trace::InstRecord * traceData )

static

Definition at line 56 of file memhelpers.hh.

References gem5::Packet::getLE(), mem, panic, and gem5::trace::InstRecord::setData().

getPackedMem()

template<typename T , size_t N>

static void gem5::X86ISA::getPackedMem ( PacketPtr pkt, std::array< uint64_t, N > & mem, unsigned dataSize )

static

Definition at line 81 of file memhelpers.hh.

References gem5::Packet::getLE(), gem5::ArmISA::i, and mem.

Referenced by getMem().

getRFlags()

uint64_t gem5::X86ISA::getRFlags

(

ThreadContext *

tc

)

Reconstruct the rflags register from the internal gem5 register state.

gem5 stores rflags in several different registers to avoid pipeline dependencies. In order to get the true rflags value, we can't simply read the value of misc_reg::Rflags. Instead, we need to read out various state from microcode registers and merge that with misc_reg::Rflags.

Parameters

tc	Thread context to read rflags from.

Returns

rflags as seen by the guest.

Definition at line 58 of file utility.cc.

References gem5::X86ISA::cc_reg::Cfof, gem5::X86ISA::cc_reg::Df, gem5::ThreadContext::getReg(), gem5::ThreadContext::readMiscRegNoEffect(), gem5::X86ISA::misc_reg::Rflags, and gem5::X86ISA::cc_reg::Zaps.

Referenced by gem5::X86KvmCPU::updateKvmStateRegs().

initiateMemRead()

static Fault gem5::X86ISA::initiateMemRead ( ExecContext * xc, trace::InstRecord * traceData, Addr addr, unsigned dataSize, Request::Flags flags )

static

Initiate a read from memory in timing mode.

Definition at line 48 of file memhelpers.hh.

References addr, flags, and gem5::ExecContext::initiateMemRead().

installSegDesc()

void gem5::X86ISA::installSegDesc	(	ThreadContext *	tc,
		int	seg,
		SegDescriptor	desc,
		bool	longmode )

Definition at line 66 of file fs_workload.cc.

References gem5::ArmISA::attr, gem5::X86ISA::segment_idx::Fs, gem5::X86ISA::segment_idx::Gs, seg, gem5::X86ISA::misc_reg::segAttr(), gem5::X86ISA::misc_reg::segBase(), gem5::X86ISA::misc_reg::segEffBase(), gem5::X86ISA::misc_reg::segLimit(), gem5::ThreadContext::setMiscReg(), and gem5::Workload::system.

Referenced by gem5::X86ISA::FsWorkload::initState(), and gem5::X86ISA::X86_64Process::initState().

intRegFolded()

static constexpr RegId gem5::X86ISA::intRegFolded ( RegIndex index, RegIndex foldBit )

inlinestaticconstexpr

Definition at line 187 of file int.hh.

References index, and intRegClass.

intRegMicro()

static constexpr RegId gem5::X86ISA::intRegMicro ( int index )

inlinestaticconstexpr

Definition at line 181 of file int.hh.

References index, and intRegClass.

Referenced by gem5::X86ISA::X86FaultBase::invoke().

loadFloat80()

double gem5::X86ISA::loadFloat80

(

const void *

mem

)

Load an 80-bit float from memory and convert it to double.

Parameters

mem	Pointer to an 80-bit float.

Returns

double representation of the 80-bit float.

Definition at line 156 of file utility.cc.

Referenced by gem5::dumpFpuCommon(), and gem5::updateThreadContextFPUCommon().

miscRegClass()

RegClass gem5::X86ISA::miscRegClass ( MiscRegClass , MiscRegClassName , misc_reg::NumRegs , debug::MiscRegs  )

inlineconstexpr

msrAddrToIndex()

bool gem5::X86ISA::msrAddrToIndex	(	RegIndex &	regNum,
		Addr	addr )

Find and return the misc reg corresponding to an MSR address.

Look for an MSR (addr) in msrMap and return the corresponding misc reg in regNum. The value of regNum is undefined if the MSR was not found.

Parameters

regNum	misc reg index (out).
addr	MSR address

Returns

True if the MSR was found, false otherwise.

Definition at line 150 of file msr.cc.

References addr, and msrMap.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), and gem5::X86ISA::TLB::translateInt().

msrMap()

const MsrMap gem5::X86ISA::msrMap	(	msrMapData	,
		msrMapData+	msrMapSize )

opcodeTypeToStr()

static const char * gem5::X86ISA::opcodeTypeToStr ( OpcodeType type )

inlinestatic

Definition at line 162 of file types.hh.

References type.

Referenced by operator<<().

operator<<()

static std::ostream & gem5::X86ISA::operator<< ( std::ostream & os, const ExtMachInst & emi )

inlinestatic

Definition at line 248 of file types.hh.

References gem5::ccprintf(), gem5::X86ISA::ExtMachInst::displacement, gem5::X86ISA::ExtMachInst::dispSize, gem5::X86ISA::ExtMachInst::immediate, gem5::X86ISA::ExtMachInst::legacy, gem5::X86ISA::ExtMachInst::modRM, gem5::X86ISA::ExtMachInst::op, gem5::X86ISA::ExtMachInst::opcode, opcodeTypeToStr(), os, gem5::X86ISA::ExtMachInst::rex, gem5::X86ISA::ExtMachInst::sib, gem5::X86ISA::ExtMachInst::type, and gem5::X86ISA::ExtMachInst::vex.

operator==()

static bool gem5::X86ISA::operator== ( const ExtMachInst & emi1, const ExtMachInst & emi2 )

inlinestatic

Definition at line 266 of file types.hh.

References gem5::X86ISA::ExtMachInst::addrSize, gem5::X86ISA::ExtMachInst::displacement, gem5::X86ISA::ExtMachInst::dispSize, gem5::X86ISA::ExtMachInst::immediate, gem5::X86ISA::ExtMachInst::legacy, gem5::X86ISA::ExtMachInst::mode, gem5::X86ISA::ExtMachInst::modRM, gem5::X86ISA::ExtMachInst::op, gem5::X86ISA::ExtMachInst::opcode, gem5::X86ISA::ExtMachInst::opSize, gem5::X86ISA::ExtMachInst::rex, gem5::X86ISA::ExtMachInst::sib, gem5::X86ISA::ExtMachInst::stackSize, gem5::X86ISA::ExtMachInst::type, and gem5::X86ISA::ExtMachInst::vex.

readMemAtomic() [1/2]

template<size_t N>

static Fault gem5::X86ISA::readMemAtomic ( ExecContext * xc, trace::InstRecord * traceData, Addr addr, std::array< uint64_t, N > & mem, unsigned dataSize, unsigned flags )

static

Definition at line 148 of file memhelpers.hh.

References addr, flags, mem, gem5::NoFault, panic, readPackedMemAtomic(), and gem5::trace::InstRecord::setData().

readMemAtomic() [2/2]

static Fault gem5::X86ISA::readMemAtomic ( ExecContext * xc, trace::InstRecord * traceData, Addr addr, uint64_t & mem, unsigned dataSize, Request::Flags flags )

static

Definition at line 109 of file memhelpers.hh.

References addr, flags, gem5::letoh(), mem, gem5::NoFault, gem5::ExecContext::readMem(), and gem5::trace::InstRecord::setData().

readPackedMemAtomic()

template<typename T , size_t N>

static Fault gem5::X86ISA::readPackedMemAtomic ( ExecContext * xc, Addr addr, std::array< uint64_t, N > & mem, unsigned flags )

static

Definition at line 129 of file memhelpers.hh.

References addr, flags, gem5::ArmISA::i, gem5::letoh(), mem, gem5::NoFault, and gem5::ExecContext::readMem().

Referenced by readMemAtomic().

setRFlags()

void gem5::X86ISA::setRFlags	(	ThreadContext *	tc,
		uint64_t	val )

Set update the rflags register and internal gem5 state.

Note

This function does not update misc_reg::M5Reg. You might need to update this register by writing anything to misc_reg::M5Reg with side-effects.

See also

X86ISA::getRFlags()

Parameters

tc	Thread context to update
val	New rflags value to store in TC

Definition at line 74 of file utility.cc.

References CcFlagMask, gem5::X86ISA::cc_reg::Cfof, CfofMask, gem5::X86ISA::cc_reg::Df, DFBit, gem5::X86ISA::cc_reg::Ecf, gem5::X86ISA::cc_reg::Ezf, gem5::X86ISA::misc_reg::Rflags, gem5::ThreadContext::setMiscReg(), gem5::ThreadContext::setReg(), val, and gem5::X86ISA::cc_reg::Zaps.

Referenced by gem5::X86KvmCPU::updateThreadContextRegs().

setThreadArea32Func()

SyscallReturn gem5::X86ISA::setThreadArea32Func	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< UserDesc32 >	userDesc )

Definition at line 100 of file syscalls.cc.

References gem5::bits(), gem5::BaseBufferArg::copyIn(), gem5::BaseBufferArg::copyOut(), flags, gem5::X86ISA::X86Process::gdtSize(), gem5::X86ISA::X86Process::gdtStart(), gem5::ThreadContext::getProcessPtr(), gem5::ArmISA::i, index, gem5::SyscallDesc::name(), and panic.

storeFloat80()

void gem5::X86ISA::storeFloat80	(	void *	mem,
		double	value )

Convert and store a double as an 80-bit float.

Parameters

mem	Pointer to destination for the 80-bit float.
value	Double precision float to store.

Definition at line 165 of file utility.cc.

Referenced by gem5::updateKvmStateFPUCommon().

SubBitUnion()

gem5::X86ISA::SubBitUnion	(	type	,
		43	,
		40	)

unameFunc()

SyscallReturn gem5::X86ISA::unameFunc	(	SyscallDesc *	desc,
		ThreadContext *	tc,
		VPtr< Linux::utsname >	name )

Target uname() handler.

Definition at line 49 of file syscalls.cc.

References gem5::ThreadContext::getProcessPtr(), and name().

writeMemAtomic() [1/2]

template<size_t N>

static Fault gem5::X86ISA::writeMemAtomic ( ExecContext * xc, trace::InstRecord * traceData, std::array< uint64_t, N > & mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t * res )

static

Definition at line 235 of file memhelpers.hh.

References addr, flags, gem5::letoh(), mem, gem5::NoFault, panic, gem5::trace::InstRecord::setData(), and writePackedMem().

writeMemAtomic() [2/2]

static Fault gem5::X86ISA::writeMemAtomic ( ExecContext * xc, trace::InstRecord * traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t * res )

static

Definition at line 218 of file memhelpers.hh.

References addr, flags, gem5::htole(), gem5::letoh(), mem, gem5::NoFault, gem5::trace::InstRecord::setData(), and gem5::ExecContext::writeMem().

writeMemTiming() [1/2]

template<size_t N>

static Fault gem5::X86ISA::writeMemTiming ( ExecContext * xc, trace::InstRecord * traceData, std::array< uint64_t, N > & mem, unsigned dataSize, Addr addr, unsigned flags, uint64_t * res )

static

Definition at line 200 of file memhelpers.hh.

References addr, flags, mem, panic, gem5::trace::InstRecord::setData(), and writePackedMem().

writeMemTiming() [2/2]

static Fault gem5::X86ISA::writeMemTiming ( ExecContext * xc, trace::InstRecord * traceData, uint64_t mem, unsigned dataSize, Addr addr, Request::Flags flags, uint64_t * res )

static

Definition at line 186 of file memhelpers.hh.

References addr, flags, gem5::htole(), mem, gem5::trace::InstRecord::setData(), and gem5::ExecContext::writeMem().

writePackedMem()

template<typename T , size_t N>

static Fault gem5::X86ISA::writePackedMem ( ExecContext * xc, std::array< uint64_t, N > & mem, Addr addr, unsigned flags, uint64_t * res )

static

Definition at line 171 of file memhelpers.hh.

References addr, flags, gem5::htole(), gem5::ArmISA::i, mem, and gem5::ExecContext::writeMem().

Referenced by writeMemAtomic(), and writeMemTiming().

x86InterruptAddress()

static Addr gem5::X86ISA::x86InterruptAddress ( const uint8_t id, const uint16_t addr )

inlinestatic

Definition at line 99 of file x86_traits.hh.

References addr, PhysAddrAPICRangeSize, and PhysAddrPrefixInterrupts.

Referenced by buildIntTriggerPacket(), gem5::X86ISA::Interrupts::getIntAddrRange(), and gem5::X86ISA::Interrupts::recvMessage().

x86IOAddress()

static Addr gem5::X86ISA::x86IOAddress ( const uint32_t port )

inlinestatic

Definition at line 80 of file x86_traits.hh.

References PhysAddrPrefixIO.

Referenced by gem5::X86KvmCPU::handleKvmExitIO().

x86LocalAPICAddress()

static Addr gem5::X86ISA::x86LocalAPICAddress ( const uint8_t id, const uint16_t addr )

inlinestatic

Definition at line 92 of file x86_traits.hh.

References addr, and PhysAddrPrefixLocalAPIC.

Referenced by gem5::X86ISA::TLB::finalizePhysical(), gem5::X86ISA::Interrupts::setThreadContext(), and gem5::X86ISA::GpuTLB::translate().

x86PciConfigAddress()

static Addr gem5::X86ISA::x86PciConfigAddress ( const uint32_t addr )

inlinestatic

Definition at line 86 of file x86_traits.hh.

References addr, and PhysAddrPrefixPciConfig.

Referenced by gem5::X86KvmCPU::handleKvmExitIO().

Variable Documentation

a

Bitfield< 40 > gem5::X86ISA::a

Definition at line 146 of file pagetable.hh.

ac

Bitfield<18> gem5::X86ISA::ac

Definition at line 576 of file misc.hh.

Referenced by gem5::MipsISA::dspDpaq(), gem5::MipsISA::dspDpsq(), gem5::MipsISA::dspMaq(), gem5::MipsISA::dspMulsaq(), and gem5::ArmISA::FsLinux::initState().

addr

Bitfield<3> gem5::X86ISA::addr

Definition at line 84 of file types.hh.

Referenced by gem5::MemChecker::abortWrite(), gem5::ListenSocket::acceptCloexec(), gem5::prefetch::SBOOE::Sandbox::access(), gem5::AssociativeCache< Entry >::accessEntryByAddr(), gem5::SimpleCache::accessTiming(), gem5::TracingExtension::add(), gem5::memory::AbstractMemory::addLockedAddr(), gem5::addrBlockAlign(), gem5::addrBlockOffset(), gem5::o3::LSQ::LSQRequest::addReq(), gem5::RiscvISA::PMAChecker::addressAlign(), gem5::ruby::addressOffset(), gem5::ruby::addressToInt(), gem5::ruby::Network::addressToNodeID(), gem5::pseudo_inst::addsymbol(), gem5::memory::MemCtrl::addToReadQueue(), gem5::memory::MemCtrl::addToWriteQueue(), gem5::BaseCache::allocateBlock(), gem5::AtomicSimpleCPU::amoMem(), gem5::SimpleExecContext::amoMem(), gem5::amoMemAtomic(), gem5::amoMemAtomicBE(), gem5::amoMemAtomicLE(), archPrctlFunc(), gem5::ruby::bitSelect(), gem5::BaseTags::blkAlign(), gem5::MemTest::blockAlign(), gem5::ruby::AbstractController::blockOnQueue(), gem5::PowerISA::BranchDispCondOp::branchTarget(), gem5::PowerISA::BranchOp::branchTarget(), gem5::PowerISA::BranchRegCondOp::branchTarget(), buildIntPacket(), buildIntTriggerPacket(), gem5::memory::HeteroMemCtrl::burstAlign(), gem5::memory::MemCtrl::burstAlign(), gem5::SMMUTranslationProcess::bypass(), gem5::VegaISA::Inst_DS::calcAddr(), gem5::VegaISA::Inst_SMEM::calcAddr(), gem5::VegaISA::Inst_FLAT::calcAddrVgpr(), gem5::prefetch::BOP::calculatePrefetch(), gem5::prefetch::IndirectMemory::calculatePrefetch(), gem5::prefetch::IrregularStreamBuffer::calculatePrefetch(), gem5::BaseSemihosting::callGetCmdLine(), gem5::BaseSemihosting::callRead(), gem5::BaseSemihosting::callTmpNam(), gem5::BaseSemihosting::callWrite(), gem5::memory::DRAMsim3Wrapper::canAccept(), gem5::prefetch::IndirectMemory::checkAccessMatchOnActiveEntries(), gem5::ArmISA::TableWalker::checkAddrSizeFaultAArch64(), gem5::ruby::CacheMemory::checkResourceAvailable(), gem5::decode_cache::AddrMap< Value, CacheChunkShift >::chunkOffset(), gem5::decode_cache::AddrMap< Value, CacheChunkShift >::chunkStart(), gem5::GenericPciHost::clearInt(), gem5::BaseRemoteGDB::cmdClrHwBkpt(), gem5::BaseRemoteGDB::cmdMemR(), gem5::BaseRemoteGDB::cmdMemW(), gem5::BaseRemoteGDB::cmdSetHwBkpt(), gem5::prefetch::PIF::CompactorEntry::CompactorEntry(), gem5::ArmISA::WatchPoint::compareAddress(), gem5::ruby::RubyPrefetcherProxy::completePrefetch(), gem5::MemChecker::completeRead(), gem5::MemChecker::completeWrite(), gem5::connectFunc(), gem5::loader::MemoryImage::contains(), gem5::GenericTimerMem::counterCtrlRead(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::GenericTimerMem::counterStatusRead(), gem5::GenericTimerMem::counterStatusWrite(), gem5::GUPSGen::createNextReq(), gem5::SpatterAccess::createPacket(), gem5::prefetch::Queued::createPrefetchRequest(), gem5::BackdoorManager::createRevertedBackdoor(), gem5::ArmISA::Decoder::decode(), gem5::GenericISA::BasicDecodeCache< Decoder, EMI >::decode(), gem5::MipsISA::Decoder::decode(), gem5::PowerISA::Decoder::decode(), gem5::RiscvISA::Decoder::decode(), gem5::SparcISA::Decoder::decode(), gem5::GenericPciHost::decodeAddress(), gem5::PM4PacketProcessor::decodeNext(), gem5::memory::DRAMInterface::decodePacket(), gem5::memory::NVMInterface::decodePacket(), gem5::ruby::MessageBuffer::deferEnqueueingMessage(), gem5::SkewedAssociative::dehash(), gem5::X86ISA::PageFault::describe(), gem5::SkewedAssociative::deskew(), gem5::IdeController::dispatchAccess(), gem5::DmaPort::dmaAction(), gem5::DmaPort::dmaAction(), gem5::PciHost::DeviceInterface::dmaAddr(), gem5::DmaDevice::dmaRead(), gem5::DmaDevice::dmaRead(), gem5::DmaVirtDevice::dmaVirt(), gem5::DmaDevice::dmaWrite(), gem5::DmaDevice::dmaWrite(), gem5::PM4PacketProcessor::doneMQDWrite(), gem5::ItsProcess::doRead(), gem5::SMMUProcess::doRead(), gem5::SMMUTranslationProcess::doReadConfig(), gem5::SMMUTranslationProcess::doReadPTE(), gem5::ItsProcess::doWrite(), gem5::SMMUProcess::doWrite(), gem5::BaseStackTrace::dump(), gem5::ProfileNode::dump(), gem5::memory::DRAMSim2Wrapper::enqueue(), gem5::memory::DRAMsim3Wrapper::enqueue(), gem5::ruby::MessageBuffer::enqueueDeferredMessages(), gem5::VegaISA::Inst_DS__DS_ADD_F32::execute(), gem5::VegaISA::Inst_DS__DS_ADD_U32::execute(), gem5::VegaISA::Inst_DS__DS_ADD_U64::execute(), gem5::VegaISA::Inst_DS__DS_BPERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_OR_B32::execute(), gem5::VegaISA::Inst_DS__DS_PERMUTE_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ2_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ2_B64::execute(), gem5::VegaISA::Inst_DS__DS_READ2ST64_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ2ST64_B64::execute(), gem5::VegaISA::Inst_DS__DS_READ_B128::execute(), gem5::VegaISA::Inst_DS__DS_READ_B32::execute(), gem5::VegaISA::Inst_DS__DS_READ_B64::execute(), gem5::VegaISA::Inst_DS__DS_READ_B96::execute(), gem5::VegaISA::Inst_DS__DS_READ_I8::execute(), gem5::VegaISA::Inst_DS__DS_READ_U16::execute(), gem5::VegaISA::Inst_DS__DS_READ_U16_D16::execute(), gem5::VegaISA::Inst_DS__DS_READ_U16_D16_HI::execute(), gem5::VegaISA::Inst_DS__DS_READ_U8::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE2ST64_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B128::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B16::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B32::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B64::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B8::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B8_D16_HI::execute(), gem5::VegaISA::Inst_DS__DS_WRITE_B96::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX16::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX4::execute(), gem5::VegaISA::Inst_SMEM__S_LOAD_DWORDX8::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORD::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX2::execute(), gem5::VegaISA::Inst_SMEM__S_STORE_DWORDX4::execute(), gem5::exitFutexWake(), gem5::BaseTags::extractBlkOffset(), gem5::SectorTags::extractSectorOffset(), gem5::SetAssociative::extractSet(), gem5::SkewedAssociative::extractSet(), gem5::BaseIndexingPolicy::extractTag(), gem5::BaseTags::extractTag(), gem5::FALRU::extractTag(), gem5::prefetch::StridePrefetcherHashedSetAssociative::extractTag(), gem5::o3::Fetch::fetchBufferAlignPC(), gem5::BackdoorManager::findBackdoor(), gem5::BaseTags::findBlock(), gem5::FALRU::findBlock(), gem5::SectorTags::findBlock(), gem5::AssociativeCache< Entry >::findEntry(), gem5::AssociativeSet< Entry >::findEntry(), gem5::loader::SymbolTable::findNearest(), gem5::loader::SymbolTable::findNearest(), gem5::AssociativeCache< Entry >::findVictim(), gem5::BaseSetAssoc::findVictim(), gem5::CompressedTags::findVictim(), gem5::SectorTags::findVictim(), gem5::SnoopFilter::finishRequest(), gem5::ArmISA::FsWorkload::fixFuncEventAddr(), gem5::Workload::fixFuncEventAddr(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::Gicv2m::frameFromAddr(), gem5::ruby::RubySystem::functionalWrite(), gem5::qemu::FwCfgItemE820::FwCfgItemE820(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::BaseSemihosting::AbiBase::StateBase< Arg, BaseSemihostingImpl >::getAddr(), gem5::Gicv2m::getAddrRanges(), gem5::PciDevice::getBAR(), gem5::MemChecker::getByteTracker(), gem5::prefetch::DeltaCorrelatingPredictionTables::DCPTEntry::getCandidates(), gem5::decode_cache::AddrMap< Value, CacheChunkShift >::getChunk(), gem5::bloom_filter::Block::getCount(), gem5::bloom_filter::Multi::getCount(), gem5::bloom_filter::MultiBitSel::getCount(), gem5::bloom_filter::Perfect::getCount(), gem5::memory::MemInterface::getCtrlAddr(), gem5::PciHost::getDevice(), gem5::PciHost::getDevice(), gem5::RiscvISA::ISA::getFaultHandlerAddr(), gem5::AMDGPUVM::getFrameAperture(), gem5::PM4PacketProcessor::getGARTAddr(), gem5::SDMAEngine::getGARTAddr(), gem5::RandomGen::getNextPacket(), gem5::ruby::getOffset(), gem5::BaseKvmCPU::getOneReg(), gem5::BaseGen::getPacket(), gem5::AssociativeCache< Entry >::getPossibleEntries(), gem5::SetAssociative::getPossibleEntries(), gem5::SkewedAssociative::getPossibleEntries(), gem5::GUPSGen::getReadPacket(), gem5::Gicv3::getRedistributorByAddr(), gem5::AMDGPUDevice::getRegVal(), gem5::BaseStackTrace::getSymbol(), gem5::AssociativeCache< Entry >::getTag(), gem5::SparcISA::TLB::GetTsbPtr(), gem5::GUPSGen::getWritePacket(), gem5::BaseCache::handleFill(), gem5::DmaPort::handleResp(), gem5::BaseCache::CacheAccessorImpl::hasBeenPrefetched(), gem5::BaseCache::CacheAccessorImpl::hasBeenPrefetched(), gem5::BaseCache::hasBeenPrefetched(), gem5::BaseCache::hasBeenPrefetched(), gem5::ruby::RubyPrefetcherProxy::hasBeenPrefetched(), gem5::ruby::RubyPrefetcherProxy::hasBeenPrefetched(), gem5::bloom_filter::Block::hash(), gem5::bloom_filter::Bulk::hash(), gem5::bloom_filter::H3::hash(), gem5::bloom_filter::MultiBitSel::hash(), gem5::prefetch::BOP::hash(), gem5::SkewedAssociative::hash(), gem5::ruby::MessageBuffer::hasStalledMsg(), gem5::DmaThread::hitCallback(), gem5::GpuWavefront::hitCallback(), gem5::RubyDirectedTester::hitCallback(), gem5::o3::CPU::htmSendAbortSignal(), gem5::TimingSimpleCPU::htmSendAbortSignal(), gem5::BaseCache::CacheAccessorImpl::inCache(), gem5::BaseCache::inCache(), gem5::ruby::RubyPrefetcherProxy::inCache(), gem5::ruby::AbstractController::incomingTransactionEnd(), gem5::ruby::AbstractController::incomingTransactionStart(), gem5::initiateMemAMO(), gem5::minor::ExecContext::initiateMemAMO(), gem5::o3::DynInst::initiateMemAMO(), gem5::SimpleExecContext::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemAMO(), gem5::TimingSimpleCPU::initiateMemMgmtCmd(), gem5::initiateMemRead(), gem5::initiateMemRead(), gem5::minor::ExecContext::initiateMemRead(), gem5::o3::DynInst::initiateMemRead(), gem5::SimpleExecContext::initiateMemRead(), gem5::TimingSimpleCPU::initiateMemRead(), initiateMemRead(), gem5::ArmLinuxProcess32::initState(), gem5::BaseCache::CacheAccessorImpl::inMissQueue(), gem5::BaseCache::inMissQueue(), gem5::ruby::RubyPrefetcherProxy::inMissQueue(), gem5::BaseCache::inRange(), gem5::TempCacheBlk::insert(), gem5::MemFootprintProbe::insertAddr(), gem5::AssociativeCache< Entry >::insertEntry(), gem5::AssociativeSet< Entry >::insertEntry(), gem5::BaseRemoteGDB::insertHardBreak(), gem5::prefetch::BOP::insertIntoRR(), gem5::BaseRemoteGDB::insertSoftBreak(), gem5::ruby::intToAddress(), gem5::ruby::Sequencer::invL1(), gem5::RiscvISA::RiscvFault::invoke(), gem5::X86ISA::PageFault::invoke(), gem5::ruby::VIPERCoalescer::invTCC(), gem5::ruby::VIPERCoalescer::invTCCCallback(), gem5::ruby::VIPERCoalescer::invTCP(), gem5::ioctlFunc(), gem5::ruby::AbstractController::isBlocked(), gem5::ruby::AbstractController::isBlocked(), gem5::isCanonicalAddress(), gem5::ruby::MessageBuffer::isDeferredMsgMapEmpty(), gem5::ArmISA::WatchPoint::isDoubleAligned(), gem5::Shader::isGpuVmApe(), gem5::Shader::isLdsApe(), gem5::memory::PhysicalMemory::isMemAddr(), gem5::System::isMemAddr(), gem5::TesterThread::isNextActionReady(), gem5::ruby::RubyPort::MemResponsePort::isPhysMemAddress(), gem5::AMDMMIOReader::isRelevant(), gem5::AMDGPUDevice::isROM(), gem5::Shader::isScratchApe(), gem5::bloom_filter::Base::isSet(), gem5::bloom_filter::Multi::isSet(), gem5::ruby::RubyPort::MemResponsePort::isShadowRomAddress(), gem5::SMMUTranslationProcess::issuePrefetch(), gem5::RiscvISA::PMAChecker::isUncacheable(), gem5::pseudo_inst::loadsymbol(), gem5::memory::qos::MemCtrl::logRequest(), gem5::memory::qos::MemCtrl::logResponse(), gem5::decode_cache::AddrMap< Value, CacheChunkShift >::lookup(), gem5::ruby::lookupTraceForAddress(), gem5::LupioBLK::lupioBLKRead(), gem5::LupioBLK::lupioBLKWrite(), gem5::LupioIPI::lupioIPIRead(), gem5::LupioIPI::lupioIPIWrite(), gem5::LupioPIC::lupioPicRead(), gem5::LupioPIC::lupioPicWrite(), gem5::LupioRNG::lupioRNGRead(), gem5::LupioRNG::lupioRNGWrite(), gem5::LupioRTC::lupioRTCRead(), gem5::LupioSYS::lupioSYSWrite(), gem5::LupioTMR::lupioTMRRead(), gem5::LupioTMR::lupioTMRWrite(), gem5::LupioTTY::lupioTTYRead(), gem5::LupioTTY::lupioTTYWrite(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::ruby::makeLineAddress(), gem5::ruby::makeLineAddress(), gem5::ruby::makeNextStrideAddress(), gem5::ruby::AbstractController::mapAddressToDownstreamMachine(), gem5::ruby::AbstractController::mapAddressToMachine(), gem5::ruby::mapAddressToRange(), gem5::GenericArmPciHost::mapPciInterrupt(), gem5::GenericPciHost::mapPciInterrupt(), gem5::GenericRiscvPciHost::mapPciInterrupt(), gem5::PM4PacketProcessor::mapQueues(), gem5::ruby::maskLowOrderBits(), gem5::ArmISA::maskTaggedAddr(), gem5::MSHR::matchBlockAddr(), gem5::WriteQueueEntry::matchBlockAddr(), gem5::PciHost::DeviceInterface::memAddr(), gem5::PortProxy::memsetBlob(), gem5::PortProxy::memsetBlobPhys(), msrAddrToIndex(), gem5::BaseCPU::mwaitAtomic(), gem5::SpatterAccess::nextPacket(), gem5::operator<<(), gem5::pseudo_inst::operator<<(), gem5::ruby::AbstractController::outgoingTransactionEnd(), gem5::ruby::AbstractController::outgoingTransactionStart(), gem5::ArmISA::TableWalker::LongDescriptor::paddr(), gem5::X86ISA::LongModePTE::paddr(), gem5::ruby::RubyPrefetcher::pageAddress(), gem5::RiscvISA::PCState::PCState(), gem5::RiscvISA::PCState::PCState(), gem5::Iris::ThreadContext::pcState(), gem5::ThreadContext::pcState(), gem5::bloom_filter::Bulk::permute(), gem5::PciHost::DeviceInterface::pioAddr(), gem5::TesterThread::popOutstandingReq(), gem5::GenericPciHost::postInt(), gem5::ListenSocketUnixAbstract::prepSockaddrUn(), gem5::ListenSocketUnixFile::prepSockaddrUn(), gem5::ruby::printAddress(), gem5::ArmISA::ArmStaticInst::printMemSymbol(), gem5::SMMUv3::processCommand(), gem5::PM4PacketProcessor::processSDMAMQD(), gem5::ArmISA::purifyTaggedAddr(), gem5::ArmISA::purifyTaggedAddr(), gem5::minor::LSQ::pushRequest(), gem5::o3::CPU::pushRequest(), gem5::o3::LSQ::pushRequest(), gem5::PM4PacketProcessor::queryStatus(), BackingStore::rangeCheck(), gem5::BaseRemoteGDB::read(), gem5::FVPBasePwrCtrl::read(), gem5::GenericTimerFrame::read(), gem5::GenericTimerMem::read(), gem5::GenericWatchdog::read(), gem5::GicV2::read(), gem5::Gicv3::read(), gem5::Gicv3Distributor::read(), gem5::Gicv3Its::read(), gem5::Gicv3Redistributor::read(), gem5::LupioBLK::read(), gem5::MHU::read(), gem5::NoMaliGpu::read(), gem5::qemu::FwCfgIo::read(), gem5::qemu::FwCfgMmio::read(), gem5::RegisterBank< BankByteOrder >::read(), gem5::SimpleDisk::read(), gem5::Sp805::read(), gem5::VGic::read(), gem5::X86ISA::I8042::read(), gem5::MHU::read32(), gem5::PortProxy::readBlob(), gem5::PortProxy::readBlobPhys(), gem5::memory::DRAMSim2::readComplete(), gem5::memory::DRAMsim3::readComplete(), gem5::GenericWatchdog::readControl(), gem5::MC146818::readData(), gem5::AtomicSimpleCPU::readMem(), gem5::CheckerCPU::readMem(), gem5::Iris::ThreadContext::readMem(), gem5::SimpleExecContext::readMem(), gem5::readMemAtomic(), gem5::readMemAtomic(), gem5::readMemAtomic(), readMemAtomic(), readMemAtomic(), gem5::readMemAtomicBE(), gem5::readMemAtomicLE(), gem5::readMemAtomicLE(), readPackedMemAtomic(), gem5::GenericWatchdog::readRefresh(), gem5::AMDGPUMemoryManager::readRequest(), gem5::PortProxy::readString(), gem5::PortProxy::readString(), gem5::ruby::MessageBuffer::reanalyzeMessages(), gem5::ruby::CacheMemory::recordRequestType(), gem5::SMMUControlPort::recvAtomic(), gem5::MemCheckerMonitor::recvFunctional(), gem5::MemCheckerMonitor::recvFunctionalSnoop(), gem5::CoherentXBar::recvTimingReq(), gem5::MemCheckerMonitor::recvTimingReq(), gem5::MemCheckerMonitor::recvTimingResp(), gem5::RealViewCtrl::registerDevice(), gem5::PM4PacketProcessor::releaseMem(), gem5::PM4PacketProcessor::releaseMemDone(), gem5::RangeAddrMapper::remapAddr(), gem5::BaseRemoteGDB::removeHardBreak(), gem5::BaseRemoteGDB::removeSoftBreak(), gem5::ruby::ALUFreeListArray::reserve(), gem5::MemChecker::reset(), gem5::ruby::AbstractController::respondsTo(), gem5::MipsISA::RoundPage(), gem5::ArmISA::roundPage(), gem5::TraceCPU::FixedRetryGen::send(), gem5::fastmodel::CortexR52TC::sendFunctional(), gem5::Iris::ThreadContext::sendFunctional(), gem5::AMDGPUSystemHub::sendNextRequest(), gem5::bloom_filter::Block::set(), gem5::bloom_filter::Multi::set(), gem5::bloom_filter::MultiBitSel::set(), gem5::bloom_filter::Perfect::set(), gem5::ruby::AccessTraceForAddress::setAddress(), gem5::ruby::SubBlock::setAddress(), gem5::VirtQueue::VirtRing< T >::setAddress(), gem5::X86ISA::GpuTLB::setConfigAddress(), gem5::X86ISA::TLB::setConfigAddress(), gem5::BaseKvmCPU::setOneReg(), gem5::AMDGPUDevice::setRegVal(), gem5::ArmSystem::setResetAddr(), gem5::fastmodel::CortexA76::setResetAddr(), gem5::fastmodel::CortexR52::setResetAddr(), gem5::fastmodel::ScxEvsCortexA76< Types >::setResetAddr(), gem5::fastmodel::ScxEvsCortexR52< Types >::setResetAddr(), gem5::X86ISA::intelmp::FloatingPointer::setTableAddr(), gem5::X86ISA::smbios::SMBiosTable::setTableAddr(), gem5::MipsISA::setThreadAreaFunc(), gem5::X86ISA::Walker::WalkerState::setupWalk(), gem5::SkewedAssociative::skew(), gem5::ruby::AbstractController::stallBuffer(), gem5::ruby::MessageBuffer::stallMessage(), gem5::RiscvISA::Walker::startFunctional(), gem5::RiscvISA::Walker::WalkerState::startFunctional(), gem5::VegaISA::Walker::startFunctional(), gem5::X86ISA::Walker::startFunctional(), gem5::X86ISA::Walker::WalkerState::startFunctional(), gem5::MemChecker::startRead(), gem5::GUPSGen::startup(), gem5::MemChecker::startWrite(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::ruby::StoreTrace::StoreTrace(), gem5::ruby::SubBlock::SubBlock(), gem5::FutexMap::suspend(), gem5::FutexMap::suspend_bitset(), gem5::prefetch::BOP::tag(), TEST(), TEST(), TEST(), gem5::ArmISA::WatchPoint::test(), gem5::ruby::testAndRead(), gem5::ruby::testAndReadMask(), gem5::ruby::testAndWrite(), gem5::prefetch::BOP::testRR(), gem5::GenericTimerMem::timerCtrlRead(), gem5::GenericTimerMem::timerCtrlWrite(), gem5::GenericTimerFrame::timerRead(), gem5::GenericTimerFrame::timerWrite(), gem5::memory::AbstractMemory::toHostAddr(), gem5::AMDMMIOReader::traceGetBAR(), gem5::AMDMMIOReader::traceGetOffset(), gem5::transferNeedsBurst(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), gem5::MipsISA::TruncPage(), gem5::ArmISA::truncPage(), gem5::ruby::ALUFreeListArray::tryAccess(), gem5::BaseStackTrace::tryGetSymbol(), gem5::PortProxy::tryMemsetBlob(), gem5::TranslatingPortProxy::tryMemsetBlob(), gem5::PortProxy::tryReadBlob(), gem5::TranslatingPortProxy::tryReadBlob(), gem5::PortProxy::tryReadString(), gem5::PortProxy::tryReadString(), gem5::tryTranslate(), gem5::PortProxy::tryWriteBlob(), gem5::TranslatingPortProxy::tryWriteBlob(), gem5::PortProxy::tryWriteString(), gem5::ruby::AbstractController::unblock(), gem5::PM4PacketProcessor::unmapQueues(), gem5::bloom_filter::Block::unset(), gem5::bloom_filter::Multi::unset(), gem5::bloom_filter::Perfect::unset(), gem5::ComputeUnit::updatePageDivergenceDist(), gem5::loader::SymbolTable::upperBound(), gem5::TesterThread::validateAtomicResp(), gem5::TesterThread::validateLoadResp(), gem5::FutexMap::wakeup(), gem5::FutexMap::wakeup_bitset(), gem5::ruby::AbstractController::wakeUpAllBuffers(), gem5::ruby::AbstractController::wakeUpBuffer(), gem5::ruby::AbstractController::wakeUpBuffers(), gem5::SMMUTranslationProcess::walkCacheLookup(), gem5::SMMUTranslationProcess::walkStage1And2(), gem5::SMMUTranslationProcess::walkStage2(), gem5::BaseRemoteGDB::write(), gem5::fastmodel::ResetControllerExample::write(), gem5::FVPBasePwrCtrl::write(), gem5::GenericTimerFrame::write(), gem5::GenericTimerMem::write(), gem5::GenericWatchdog::write(), gem5::GicV2::write(), gem5::Gicv3::write(), gem5::Gicv3Distributor::write(), gem5::Gicv3Its::write(), gem5::Gicv3Redistributor::write(), gem5::MHU::write(), gem5::NoMaliGpu::write(), gem5::qemu::FwCfgIo::write(), gem5::qemu::FwCfgMmio::write(), gem5::RegisterBank< BankByteOrder >::write(), gem5::Sp805::write(), gem5::VGic::write(), gem5::X86ISA::ACPI::RSDP::write(), gem5::X86ISA::I8042::write(), gem5::PortProxy::writeBlob(), gem5::PortProxy::writeBlobPhys(), gem5::X86ISA::ACPI::SysDescTable::writeBuf(), gem5::memory::DRAMSim2::writeComplete(), gem5::memory::DRAMsim3::writeComplete(), gem5::ruby::VIPERCoalescer::writeCompleteCallback(), gem5::GenericWatchdog::writeControl(), gem5::MC146818::writeData(), gem5::PM4PacketProcessor::writeData(), gem5::PM4PacketProcessor::writeDataDone(), gem5::AtomicSimpleCPU::writeMem(), gem5::CheckerCPU::writeMem(), gem5::Iris::ThreadContext::writeMem(), gem5::minor::ExecContext::writeMem(), gem5::o3::DynInst::writeMem(), gem5::SimpleExecContext::writeMem(), gem5::TimingSimpleCPU::writeMem(), gem5::writeMemAtomic(), gem5::writeMemAtomic(), gem5::writeMemAtomic(), writeMemAtomic(), writeMemAtomic(), gem5::writeMemAtomicBE(), gem5::writeMemAtomicLE(), gem5::writeMemAtomicLE(), gem5::writeMemTiming(), gem5::writeMemTiming(), gem5::writeMemTiming(), writeMemTiming(), writeMemTiming(), gem5::writeMemTimingBE(), gem5::writeMemTimingLE(), gem5::writeMemTimingLE(), gem5::X86ISA::intelmp::AddrSpaceMapping::writeOut(), gem5::X86ISA::intelmp::BaseConfigEntry::writeOut(), gem5::X86ISA::intelmp::Bus::writeOut(), gem5::X86ISA::intelmp::BusHierarchy::writeOut(), gem5::X86ISA::intelmp::CompatAddrSpaceMod::writeOut(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::intelmp::ExtConfigEntry::writeOut(), gem5::X86ISA::intelmp::FloatingPointer::writeOut(), gem5::X86ISA::intelmp::IntAssignment::writeOut(), gem5::X86ISA::intelmp::IOAPIC::writeOut(), gem5::X86ISA::intelmp::Processor::writeOut(), gem5::X86ISA::smbios::BiosInformation::writeOut(), gem5::X86ISA::smbios::SMBiosStructure::writeOut(), gem5::X86ISA::smbios::SMBiosTable::writeOut(), gem5::writeOutField(), gem5::writeOutString(), gem5::X86ISA::smbios::SMBiosStructure::writeOutStrings(), writePackedMem(), gem5::GenericWatchdog::writeRefresh(), gem5::AMDGPUMemoryManager::writeRequest(), gem5::PortProxy::writeString(), gem5::X86ISA::E820Table::writeTo(), gem5::writeVal(), x86InterruptAddress(), x86LocalAPICAddress(), and x86PciConfigAddress().

AddrSizeFlagMask

auto gem5::X86ISA::AddrSizeFlagMask = mask(2)

constexpr

Definition at line 58 of file ldstflags.hh.

Referenced by gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

AddrSizeFlagShift

auto gem5::X86ISA::AddrSizeFlagShift = CPL0FlagShift + 1

constexpr

Definition at line 57 of file ldstflags.hh.

Referenced by gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

addrv

Bitfield<58> gem5::X86ISA::addrv

Definition at line 799 of file misc.hh.

af

Bitfield< 4 > gem5::X86ISA::af

Definition at line 563 of file misc.hh.

altAddr

Bitfield<15, 14> gem5::X86ISA::altAddr

Definition at line 601 of file misc.hh.

altOp

Bitfield<11, 10> gem5::X86ISA::altOp

Definition at line 599 of file misc.hh.

am

Bitfield<18> gem5::X86ISA::am

Definition at line 612 of file misc.hh.

AO

const uint8_t gem5::X86ISA::AO = AddressSizeOverride

Definition at line 54 of file decoder_tables.cc.

avl

Bitfield< 5 > gem5::X86ISA::avl

Definition at line 142 of file pagetable.hh.

avx

Bitfield<2> gem5::X86ISA::avx

Definition at line 665 of file misc.hh.

b

Bitfield< 5 > gem5::X86ISA::b

Definition at line 954 of file misc.hh.

b1

Bitfield<1> gem5::X86ISA::b1

Definition at line 682 of file misc.hh.

b2

Bitfield<2> gem5::X86ISA::b2

Definition at line 683 of file misc.hh.

b3

Bitfield<3> gem5::X86ISA::b3

Definition at line 684 of file misc.hh.

badMicroop

const StaticInstPtr gem5::X86ISA::badMicroop

Initial value:

=
    new MicroDebug(dummyMachInst, "panic", "BAD",
        StaticInst::IsMicroop | StaticInst::IsLastMicroop,
        new GenericISA::M5PanicFault("Invalid microop!"))

Definition at line 59 of file badmicroop.cc.

Referenced by gem5::X86ISA::MacroopBase::fetchMicroop(), and gem5::X86ISAInst::MicrocodeRom::fetchMicroop().

base

Bitfield< 2, 0 > gem5::X86ISA::base

Definition at line 141 of file pagetable.hh.

Referenced by gem5::ruby::addressOffset(), gem5::statistics::Hdf5::beginGroup(), gem5::ArmISA::BigFpMemImmOp::BigFpMemImmOp(), gem5::ArmISA::BigFpMemPostOp::BigFpMemPostOp(), gem5::ArmISA::BigFpMemPreOp::BigFpMemPreOp(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::X86ISA::Interrupts::clearRegArrayBit(), gem5::SMMUTranslationProcess::doReadPTE(), EndBitUnion(), gem5::exclude(), gem5::exclude(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::X86ISA::Interrupts::findRegArrayMSB(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::X86ISA::Interrupts::getRegArrayBit(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::getRegs(), gem5::ArmISA::ArmFault::getVector(), gem5::ArmISA::Reset::getVector(), gem5::EmbeddedPyBind::init(), gem5::X86ISA::FsWorkload::initState(), gem5::compression::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), gem5::statistics::DistPrint::operator()(), gem5::statistics::SparseHistPrint::operator()(), gem5::statistics::VectorPrint::operator()(), gem5::operator-(), gem5::operator-(), gem5::operator-=(), gem5::operator-=(), gem5::Gicv3Its::pageAddress(), gem5::RiscvISA::PMP::pmpDecodeNapot(), gem5::X86ISA::X86StaticInst::printMem(), gem5::ItsProcess::readDeviceTable(), gem5::ItsProcess::readIrqCollectionTable(), gem5::X86ISA::ISA::readMiscReg(), gem5::VegaISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::EtherLink::Link::serialize(), gem5::EthPacketData::serialize(), gem5::IdeController::Channel::serialize(), gem5::Intel8254Timer::Counter::serialize(), gem5::Intel8254Timer::serialize(), gem5::loader::SymbolTable::serialize(), gem5::MC146818::serialize(), gem5::PacketFifo::serialize(), gem5::PacketFifoEntry::serialize(), gem5::PM4PacketProcessor::serialize(), gem5::SDMAEngine::serialize(), gem5::Time::serialize(), gem5::Shader::setLdsApe(), gem5::AMDGPUVM::setMMHUBBase(), gem5::X86ISA::Interrupts::setRegArrayBit(), gem5::ArmISA::RemoteGDB::AArch64GdbRegCache::setRegs(), gem5::Shader::setScratchApe(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::startFunctional(), gem5::VegaISA::Walker::startTiming(), gem5::ArmISA::SyscallTable32::SyscallTable32(), gem5::ArmISA::SyscallTable64::SyscallTable64(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST_F(), TEST_F(), TEST_F(), gem5::MemTest::tick(), gem5::AMDGPUVM::UserTranslationGen::translate(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::TLB::translate(), gem5::VegaISA::GpuTLB::translationReturn(), gem5::EtherLink::Link::unserialize(), gem5::EthPacketData::unserialize(), gem5::IdeController::Channel::unserialize(), gem5::Intel8254Timer::Counter::unserialize(), gem5::Intel8254Timer::unserialize(), gem5::loader::SymbolTable::unserialize(), gem5::MC146818::unserialize(), gem5::PacketFifo::unserialize(), gem5::PacketFifoEntry::unserialize(), gem5::PM4PacketProcessor::unserialize(), gem5::SDMAEngine::unserialize(), gem5::Time::unserialize(), gem5::MipsISA::MipsFaultBase::vect(), gem5::Packet::writeData(), gem5::ItsProcess::writeDeviceTable(), gem5::ItsProcess::writeIrqCollectionTable(), and gem5::X86ISA::smbios::SMBiosTable::writeOut().

baseHigh

gem5::X86ISA::baseHigh

Definition at line 949 of file misc.hh.

baseLow

Bitfield< 39, 16 > gem5::X86ISA::baseLow

Definition at line 950 of file misc.hh.

bd

Bitfield<13> gem5::X86ISA::bd

Definition at line 685 of file misc.hh.

bndreg

Bitfield<3> gem5::X86ISA::bndreg

Definition at line 667 of file misc.hh.

bndsrc

Bitfield<4> gem5::X86ISA::bndsrc

Definition at line 669 of file misc.hh.

bottom3

Bitfield<2,0> gem5::X86ISA::bottom3

Definition at line 182 of file types.hh.

bs

Bitfield<14> gem5::X86ISA::bs

Definition at line 686 of file misc.hh.

Referenced by gem5::RiscvISA::_rvk_emu_aes32dsi(), gem5::RiscvISA::_rvk_emu_aes32dsmi(), gem5::RiscvISA::_rvk_emu_aes32esi(), gem5::RiscvISA::_rvk_emu_aes32esmi(), gem5::RiscvISA::_rvk_emu_sm4ed(), gem5::RiscvISA::_rvk_emu_sm4ks(), gem5::findLsbSet(), and TEST().

bsp

Bitfield<8> gem5::X86ISA::bsp

Definition at line 1087 of file misc.hh.

bt

Bitfield<15> gem5::X86ISA::bt

Definition at line 687 of file misc.hh.

btf

Bitfield<1> gem5::X86ISA::btf

Definition at line 750 of file misc.hh.

c

Bitfield< 42 > gem5::X86ISA::c

Definition at line 968 of file misc.hh.

CcFlagMask

uint32_t gem5::X86ISA::CcFlagMask = PFBit | AFBit | ZFBit | SFBit

constexpr

Definition at line 73 of file misc.hh.

Referenced by setRFlags().

cd

Bitfield<30> gem5::X86ISA::cd

Definition at line 610 of file misc.hh.

cf

Bitfield< 0 > gem5::X86ISA::cf

Definition at line 566 of file misc.hh.

CfofMask

uint32_t gem5::X86ISA::CfofMask = CFBit | OFBit

constexpr

Definition at line 72 of file misc.hh.

Referenced by setRFlags().

contents

Bitfield<2, 1> gem5::X86ISA::contents

Definition at line 50 of file syscalls.hh.

Referenced by gem5::SerializationFixture::simulateSerialization().

count

Bitfield< 36, 32 > gem5::X86ISA::count

Definition at line 738 of file misc.hh.

Referenced by gem5::FlashDevice::accessDevice(), gem5::SpatterGen::addKernel(), gem5::AddrRange::AddrRange(), gem5::Aapcs32Vfp::State::allocate(), gem5::Aapcs32Vfp::State::allocate(), gem5::fastmodel::PL330::allocateIrq(), gem5::PcCountTrackerManager::checkCount(), gem5::o3::Commit::commitInsts(), gem5::ruby::WriteMask::count(), gem5::ruby::countBoolVec(), gem5::fastmodel::SCGIC::Terminator::countUnbound(), gem5::trace::CapstoneDisassembler::disassemble(), gem5::VegaISA::dppInstImpl(), gem5::IGbE::drain(), gem5::FunctionProfile::dump(), gem5::guest_abi::dumpArgsFrom(), gem5::loader::ElfObject::ElfObject(), gem5::UFSHostDevice::finalUTP(), gem5::VegaISA::firstOppositeSignBit(), gem5::VegaISA::firstOppositeSignBit(), gem5::qemu::FwCfgItemE820::FwCfgItemE820(), gem5::X86ISA::InstOperands< Base, Operands >::generateDisassembly(), gem5::bloom_filter::Multi::getCount(), gem5::bloom_filter::MultiBitSel::getCount(), gem5::Iris::ThreadContext::getCurrentInstCount(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::branch_prediction::LocalBP::getPrediction(), gem5::getrandomFunc(), gem5::VecRegContainer< SIZE >::getString(), gem5::bloom_filter::Base::getTotalCount(), gem5::bloom_filter::Multi::getTotalCount(), gem5::X86KvmCPU::handleKvmExitIO(), gem5::FlashDevice::initializeFlash(), gem5::ruby::UncoalescedTable::initPacketsRemaining(), gem5::bloom_filter::Multi::isSet(), gem5::ArmISA::MacroVFPMemOp::MacroVFPMemOp(), gem5::UFSHostDevice::manageReadTransfer(), gem5::UFSHostDevice::manageWriteTransfer(), gem5::BasePixelPump::nextLine(), gem5::System::Threads::numActive(), gem5::System::Threads::numRunning(), gem5::MipsISA::Interrupts::onCpuTimerInterrupt(), gem5::o3::DynInst::operator new(), gem5::SDMAEngine::pollRegMemRead(), gem5::StackDistCalc::printStack(), gem5::prefetch::Queued::processMissingTranslations(), gem5::ruby::AddressProfiler::profileRetry(), gem5::SimpleDisk::read(), gem5::UFSHostDevice::UFSSCSIDevice::readFlash(), gem5::AMDMMIOReader::readFromTrace(), gem5::readvFunc(), gem5::FlashDevice::remap(), gem5::UFSHostDevice::requestHandler(), gem5::FutexMap::requeue(), gem5::SafeRead(), gem5::SafeWrite(), gem5::CheckerThreadContext< TC >::scheduleInstCountEvent(), gem5::Iris::ThreadContext::scheduleInstCountEvent(), gem5::o3::ThreadContext::scheduleInstCountEvent(), gem5::SimpleThread::scheduleInstCountEvent(), gem5::UFSHostDevice::UFSSCSIDevice::SCSICMDHandle(), gem5::UFSHostDevice::SCSIResume(), gem5::EmulationPageTable::serialize(), gem5::FlashDevice::serialize(), gem5::MemState::serialize(), gem5::sinic::Device::serialize(), gem5::ActivityRecorder::setActivityCount(), gem5::ruby::UncoalescedTable::setPacketsRemaining(), gem5::CacheBlk::setRefCount(), gem5::UFSHostDevice::UFSSCSIDevice::statusCheck(), gem5::Iris::BaseCPU::totalInsts(), gem5::EmulationPageTable::unserialize(), gem5::FlashDevice::unserialize(), gem5::MemState::unserialize(), gem5::qemu::FwCfg::Directory::update(), gem5::ActivityRecorder::validate(), gem5::Checker< class >::verify(), gem5::FutexMap::wakeup(), gem5::partitioning_policy::WayPartitioningPolicy::WayPartitioningPolicy(), gem5::UFSHostDevice::UFSSCSIDevice::writeFlash(), gem5::AMDMMIOReader::writeFromTrace(), and gem5::writevFunc().

counterMask

Bitfield<31,24> gem5::X86ISA::counterMask

Definition at line 844 of file misc.hh.

cpl

gem5::X86ISA::cpl

Definition at line 595 of file misc.hh.

CPL0FlagBit

auto gem5::X86ISA::CPL0FlagBit = 1 << CPL0FlagShift

constexpr

Definition at line 56 of file ldstflags.hh.

Referenced by gem5::X86ISA::GpuTLB::pagingProtectionChecks(), gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

CPL0FlagShift

auto gem5::X86ISA::CPL0FlagShift = 4

constexpr

Definition at line 55 of file ldstflags.hh.

CS

const uint8_t gem5::X86ISA::CS = CSOverride

Definition at line 46 of file decoder_tables.cc.

d

Bitfield< 54 > gem5::X86ISA::d

Definition at line 145 of file pagetable.hh.

de

Bitfield<3> gem5::X86ISA::de

Definition at line 652 of file misc.hh.

Referenced by gem5::OutputDirectory::remove().

decodeVal

gem5::X86ISA::decodeVal

Definition at line 79 of file types.hh.

defAddr

Bitfield<13, 12> gem5::X86ISA::defAddr

Definition at line 600 of file misc.hh.

defaultSize

Bitfield<3> gem5::X86ISA::defaultSize

Definition at line 1023 of file misc.hh.

defOp

Bitfield<9, 8> gem5::X86ISA::defOp

Definition at line 598 of file misc.hh.

deliveryMode

Bitfield< 10, 8 > gem5::X86ISA::deliveryMode

Definition at line 49 of file intmessage.hh.

Referenced by gem5::X86ISA::Interrupts::requestInterrupt().

deliveryStatus

Bitfield<12> gem5::X86ISA::deliveryStatus

Definition at line 97 of file apic.hh.

destination

gem5::X86ISA::destination

Definition at line 47 of file intmessage.hh.

Referenced by gem5::GarnetSyntheticTraffic::generatePkt(), gem5::UFSHostDevice::readDevice(), gem5::UFSHostDevice::transferDone(), and gem5::UFSHostDevice::writeDevice().

destMode

Bitfield< 11 > gem5::X86ISA::destMode

Definition at line 50 of file intmessage.hh.

destShorthand

Bitfield<19, 18> gem5::X86ISA::destShorthand

Definition at line 100 of file apic.hh.

df

Bitfield<10> gem5::X86ISA::df

Definition at line 582 of file misc.hh.

disA20M

Bitfield<2> gem5::X86ISA::disA20M

Definition at line 872 of file misc.hh.

dpl

Bitfield< 46, 45 > gem5::X86ISA::dpl

Definition at line 961 of file misc.hh.

DS

const uint8_t gem5::X86ISA::DS = DSOverride

Definition at line 47 of file decoder_tables.cc.

E

Bitfield<31,0> gem5::X86ISA::E

Definition at line 56 of file int.hh.

Referenced by gem5::ArmISA::ArmStaticInst::cSwap().

e

Bitfield< 42 > gem5::X86ISA::e

Definition at line 788 of file misc.hh.

ecf

Bitfield<3> gem5::X86ISA::ecf

Definition at line 564 of file misc.hh.

eipv

Bitfield<1> gem5::X86ISA::eipv

Definition at line 744 of file misc.hh.

em

Bitfield<2> gem5::X86ISA::em

Definition at line 617 of file misc.hh.

en

Bitfield< 22 > gem5::X86ISA::en

Definition at line 801 of file misc.hh.

enable

Bitfield<11> gem5::X86ISA::enable

Definition at line 1086 of file misc.hh.

Referenced by gem5::ArmISA::addPACDA(), gem5::ArmISA::addPACDB(), gem5::ArmISA::addPACIA(), gem5::ArmISA::addPACIB(), gem5::ArmISA::authDA(), gem5::ArmISA::authDB(), gem5::ArmISA::authIA(), gem5::ArmISA::authIB(), gem5::Gicv3CPUInterface::setMiscReg(), gem5::ArmISA::PMU::updateAllCounters(), and gem5::Gicv3Distributor::write().

enter

Bitfield<1> gem5::X86ISA::enter

Definition at line 881 of file misc.hh.

ES

const uint8_t gem5::X86ISA::ES = ESOverride

Definition at line 48 of file decoder_tables.cc.

esi

gem5::X86ISA::esi

Definition at line 894 of file misc.hh.

et

Bitfield<4> gem5::X86ISA::et

Definition at line 615 of file misc.hh.

eventMask

gem5::X86ISA::eventMask

Definition at line 835 of file misc.hh.

exit

Bitfield<3> gem5::X86ISA::exit

Definition at line 883 of file misc.hh.

Referenced by gem5::ruby::garnet::RoutingUnit::lookupRoutingTable(), gem5::NSGigE::rxKick(), gem5::sinic::Device::rxKick(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::NSGigE::txKick(), and gem5::sinic::Device::txKick().

expandDown

Bitfield<14> gem5::X86ISA::expandDown

Definition at line 1031 of file misc.hh.

Referenced by gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

ezf

Bitfield<5> gem5::X86ISA::ezf

Definition at line 562 of file misc.hh.

fe

Bitfield<10> gem5::X86ISA::fe

Definition at line 787 of file misc.hh.

ffxsr

Bitfield<14> gem5::X86ISA::ffxsr

Definition at line 821 of file misc.hh.

fix

Bitfield<8> gem5::X86ISA::fix

Definition at line 715 of file misc.hh.

flatFloatRegClass

RegClass gem5::X86ISA::flatFloatRegClass

inlineconstexpr

Initial value:

=
    RegClass(FloatRegClass, FloatRegClassName, float_reg::NumRegs,
            debug::FloatRegs).
    ops(flatFloatRegClassOps)

Definition at line 131 of file float.hh.

Referenced by gem5::X86ISA::ISA::copyRegsFrom(), gem5::X86ISA::FloatRegClassOps::flatten(), and gem5::X86ISA::ISA::ISA().

flatFloatRegClassOps

FlatFloatRegClassOps gem5::X86ISA::flatFloatRegClassOps

inlineconstexpr

Definition at line 129 of file float.hh.

flatIntRegClass

RegClass gem5::X86ISA::flatIntRegClass

inlineconstexpr

Initial value:

=
    RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs).
    ops(flatIntRegClassOps)

Definition at line 112 of file int.hh.

Referenced by gem5::X86ISA::ISA::copyRegsFrom(), gem5::X86ISA::IntRegClassOps::flatten(), and gem5::X86ISA::ISA::ISA().

flatIntRegClassOps

FlatIntRegClassOps gem5::X86ISA::flatIntRegClassOps

inlineconstexpr

Definition at line 110 of file int.hh.

floatRegClass

RegClass gem5::X86ISA::floatRegClass

inlineconstexpr

Initial value:

=
    RegClass(FloatRegClass, FloatRegClassName, float_reg::NumRegs,
            debug::FloatRegs).
    ops(floatRegClassOps).
    needsFlattening()

Definition at line 143 of file float.hh.

Referenced by gem5::MipsISA::ISA::copyRegsFrom(), gem5::PowerISA::ISA::copyRegsFrom(), gem5::RiscvISA::ISA::copyRegsFrom(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::X86ISA::float_reg::fpr(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::getRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::getRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::getRegs(), gem5::ArmISA::ISA::ISA(), gem5::MipsISA::ISA::ISA(), gem5::PowerISA::ISA::ISA(), gem5::RiscvISA::ISA::ISA(), gem5::SparcISA::ISA::ISA(), gem5::X86ISA::float_reg::microfp(), gem5::X86ISA::float_reg::mmx(), gem5::X86ISA::FloatOp< Base >::print(), gem5::MipsISA::RemoteGDB::MipsGdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::Power64GdbRegCache::setRegs(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv32GdbRegCache::setRegs(), gem5::RiscvISA::RemoteGDB::Riscv64GdbRegCache::setRegs(), gem5::ArmKvmCPU::updateKvmStateVFP(), gem5::ArmKvmCPU::updateTCStateVFP(), gem5::X86ISA::float_reg::xmm(), gem5::X86ISA::float_reg::xmmHigh(), and gem5::X86ISA::float_reg::xmmLow().

floatRegClassOps

FloatRegClassOps gem5::X86ISA::floatRegClassOps

inlineconstexpr

Definition at line 141 of file float.hh.

FS

const uint8_t gem5::X86ISA::FS = FSOverride

Definition at line 49 of file decoder_tables.cc.

fsgsbase

Bitfield<16> gem5::X86ISA::fsgsbase

Definition at line 642 of file misc.hh.

g

Bitfield< 55 > gem5::X86ISA::g

Definition at line 143 of file pagetable.hh.

Referenced by gem5::X86ISA::SegDescriptorLimit::setter().

g0

Bitfield<1> gem5::X86ISA::g0

Definition at line 692 of file misc.hh.

g1

Bitfield<3> gem5::X86ISA::g1

Definition at line 694 of file misc.hh.

g2

Bitfield<5> gem5::X86ISA::g2

Definition at line 696 of file misc.hh.

g3

Bitfield<7> gem5::X86ISA::g3

Definition at line 698 of file misc.hh.

gd

Bitfield<13> gem5::X86ISA::gd

Definition at line 701 of file misc.hh.

GDTVirtAddr

const Addr gem5::X86ISA::GDTVirtAddr = 0xffff800000001000

Definition at line 41 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

ge

Bitfield<9> gem5::X86ISA::ge

Definition at line 700 of file misc.hh.

granularity

Bitfield<6> gem5::X86ISA::granularity

Definition at line 1026 of file misc.hh.

GS

const uint8_t gem5::X86ISA::GS = GSOverride

Definition at line 50 of file decoder_tables.cc.

H

Bitfield<15,8> gem5::X86ISA::H

Definition at line 60 of file int.hh.

Referenced by gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA< _delta, M, N, K, B, T1, T2, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_I8< M, N, K, B, MNEMONIC >::execute(), gem5::VegaISA::Inst_VOP3P_MAI__V_MFMA_MXFP< M, N, K, B, MXFPT, MNEMONIC >::execute(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), and gem5::SparcISA::SparcFault< T >::vals().

HasDataSizeV

template<class T >

bool gem5::X86ISA::HasDataSizeV = HasDataSize<T>::value

constexpr

Definition at line 142 of file microop_args.hh.

hi16_zmm

Bitfield<7> gem5::X86ISA::hi16_zmm

Definition at line 675 of file misc.hh.

IDTVirtAddr

const Addr gem5::X86ISA::IDTVirtAddr = 0xffff800000002000

Definition at line 42 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

index

Bitfield<5,3> gem5::X86ISA::index

Definition at line 98 of file types.hh.

Referenced by APIC_IN_SERVICE(), APIC_INTERRUPT_REQUEST(), APIC_TRIGGER_MODE(), gem5::X86ISA::misc_reg::cr(), gem5::X86ISA::X86CPUID::doCpuid(), gem5::X86ISA::misc_reg::dr(), gem5::X86ISA::IntRegClassOps::flatten(), gem5::X86ISA::float_reg::fpr(), intRegFolded(), intRegMicro(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::misc_reg::iorrBase(), gem5::X86ISA::misc_reg::iorrMask(), gem5::X86ISA::misc_reg::isValid(), gem5::X86ISA::misc_reg::mcAddr(), gem5::X86ISA::misc_reg::mcCtl(), gem5::X86ISA::misc_reg::mcMisc(), gem5::X86ISA::misc_reg::mcStatus(), gem5::X86ISA::X86StaticInst::merge(), gem5::X86ISA::float_reg::microfp(), gem5::X86ISA::float_reg::mmx(), gem5::X86ISA::misc_reg::mtrrPhysBase(), gem5::X86ISA::misc_reg::mtrrPhysMask(), gem5::X86ISA::misc_reg::perfEvtCtr(), gem5::X86ISA::misc_reg::perfEvtSel(), gem5::X86ISA::X86StaticInst::pick(), gem5::X86ISA::X86StaticInst::printMem(), gem5::X86ISA::I82094AA::readReg(), gem5::X86ISA::misc_reg::segAttr(), gem5::X86ISA::misc_reg::segBase(), gem5::X86ISA::misc_reg::segEffBase(), gem5::X86ISA::misc_reg::segLimit(), gem5::X86ISA::misc_reg::segSel(), setThreadArea32Func(), gem5::X86ISA::X86StaticInst::signedPick(), gem5::X86ISA::float_reg::stack(), gem5::X86ISA::I82094AA::writeReg(), gem5::X86ISA::misc_reg::xcr(), gem5::X86ISA::float_reg::xmm(), gem5::X86ISA::float_reg::xmmHigh(), and gem5::X86ISA::float_reg::xmmLow().

IntAddrPrefixCPUID

const Addr gem5::X86ISA::IntAddrPrefixCPUID = 0x100000000ULL

Definition at line 64 of file x86_traits.hh.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), and gem5::X86ISA::TLB::translateInt().

IntAddrPrefixIO

const Addr gem5::X86ISA::IntAddrPrefixIO = 0x300000000ULL

Definition at line 66 of file x86_traits.hh.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), and gem5::X86ISA::TLB::translateInt().

IntAddrPrefixMask

const Addr gem5::X86ISA::IntAddrPrefixMask = 0xffffffff00000000ULL

Definition at line 63 of file x86_traits.hh.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), and gem5::X86ISA::TLB::translateInt().

IntAddrPrefixMSR

const Addr gem5::X86ISA::IntAddrPrefixMSR = 0x200000000ULL

Definition at line 65 of file x86_traits.hh.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), and gem5::X86ISA::TLB::translateInt().

intEn

Bitfield<20> gem5::X86ISA::intEn

Definition at line 841 of file misc.hh.

intf

Bitfield<9> gem5::X86ISA::intf

Definition at line 583 of file misc.hh.

IntFoldBit

RegIndex gem5::X86ISA::IntFoldBit = 1 << 6

inlineconstexpr

Definition at line 178 of file int.hh.

Referenced by gem5::X86ISA::X86StaticInst::merge(), gem5::X86ISA::X86StaticInst::pick(), gem5::X86ISA::X86StaticInst::printReg(), gem5::X86ISA::FlatIntRegClassOps::regName(), and gem5::X86ISA::X86StaticInst::signedPick().

intRegClass

RegClass gem5::X86ISA::intRegClass

inlineconstexpr

Initial value:

=
    RegClass(IntRegClass, IntRegClassName, int_reg::NumRegs, debug::IntRegs).
    ops(intRegClassOps).
    needsFlattening()

Definition at line 123 of file int.hh.

Referenced by gem5::X86ISA::EmulEnv::doModRM(), intRegFolded(), intRegMicro(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::FoldedOp< Base >::print(), gem5::X86ISA::IntOp< Base >::print(), and gem5::X86ISA::X86StaticInst::printMem().

intRegClassOps

IntRegClassOps gem5::X86ISA::intRegClassOps

inlineconstexpr

Definition at line 121 of file int.hh.

inv

Bitfield<23> gem5::X86ISA::inv

Definition at line 843 of file misc.hh.

Referenced by gem5::prefetch::Base::observeAccess().

iopl

Bitfield<13, 12> gem5::X86ISA::iopl

Definition at line 580 of file misc.hh.

IST

Bitfield<35, 32> gem5::X86ISA::IST

Definition at line 1053 of file misc.hh.

ISTVirtAddr

const Addr gem5::X86ISA::ISTVirtAddr = 0xffff800000004000

Definition at line 45 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState(), and gem5::X86ISA::EmuLinux::pageFault().

L

Bitfield<7, 0> gem5::X86ISA::L

Definition at line 62 of file int.hh.

Referenced by gem5::ArmISA::TableWalker::doLongDescriptor(), gem5::BaseKvmCPU::ioctl(), gem5::Kvm::ioctl(), gem5::KvmDevice::ioctl(), gem5::KvmVM::ioctl(), and gem5::PerfKvmCounter::ioctl().

l

Bitfield< 2 > gem5::X86ISA::l

Definition at line 955 of file misc.hh.

l1

Bitfield<2> gem5::X86ISA::l1

Definition at line 693 of file misc.hh.

l2

Bitfield<4> gem5::X86ISA::l2

Definition at line 695 of file misc.hh.

l3

Bitfield<6> gem5::X86ISA::l3

Definition at line 697 of file misc.hh.

le

Bitfield<8> gem5::X86ISA::le

Definition at line 699 of file misc.hh.

legacy

gem5::X86ISA::legacy

Definition at line 624 of file misc.hh.

Referenced by gem5::PciIoBar::EndBitUnion().

len0

Bitfield<19, 18> gem5::X86ISA::len0

Definition at line 703 of file misc.hh.

len1

Bitfield<23, 22> gem5::X86ISA::len1

Definition at line 705 of file misc.hh.

len2

Bitfield<27, 26> gem5::X86ISA::len2

Definition at line 707 of file misc.hh.

len3

Bitfield<31, 30> gem5::X86ISA::len3

Definition at line 709 of file misc.hh.

level

Bitfield< 14 > gem5::X86ISA::level

Definition at line 51 of file intmessage.hh.

Referenced by gem5::Trie< Key, Value >::Node::dump(), gem5::SparcISA::Interrupts::getInterrupt(), gem5::getsockoptFunc(), gem5::StackDistCalc::getSum(), gem5::ArmISA::V7LPageTableOps::index(), gem5::ArmISA::V8PageTableOps16k::index(), gem5::ArmISA::V8PageTableOps4k::index(), gem5::ArmISA::V8PageTableOps64k::index(), gem5::SparcISA::Interrupts::InterruptLevel(), gem5::SparcISA::SparcFaultBase::invoke(), gem5::ArmISA::V7LPageTableOps::isLeaf(), gem5::ArmISA::V8PageTableOps16k::isLeaf(), gem5::ArmISA::V8PageTableOps4k::isLeaf(), gem5::ArmISA::V8PageTableOps64k::isLeaf(), gem5::ArmISA::V7LPageTableOps::isValid(), gem5::ArmISA::V8PageTableOps16k::isValid(), gem5::ArmISA::V8PageTableOps4k::isValid(), gem5::ArmISA::V8PageTableOps64k::isValid(), gem5::WalkCache::lookup(), gem5::ArmISA::V7LPageTableOps::nextLevelPointer(), gem5::ArmISA::V8PageTableOps16k::nextLevelPointer(), gem5::ArmISA::V8PageTableOps4k::nextLevelPointer(), gem5::ArmISA::V8PageTableOps64k::nextLevelPointer(), gem5::ArmISA::V7LPageTableOps::pageMask(), gem5::ArmISA::V8PageTableOps16k::pageMask(), gem5::ArmISA::V8PageTableOps4k::pageMask(), gem5::ArmISA::V8PageTableOps64k::pageMask(), gem5::WalkCache::pickEntryIdxToReplace(), gem5::WalkCache::pickSetIdx(), gem5::X86ISA::Interrupts::requestInterrupt(), gem5::StackDistCalc::sanityCheckTree(), gem5::setsockoptFunc(), gem5::RiscvISA::Walker::WalkerState::setupWalk(), gem5::RiscvISA::Walker::WalkerState::stepWalk(), gem5::SMMUTranslationProcess::translateStage1And2(), gem5::SMMUTranslationProcess::translateStage2(), gem5::LupioTMR::updateIRQ(), gem5::StackDistCalc::updateSum(), gem5::StackDistCalc::updateSumsLeavesToRoot(), gem5::ArmISA::V7LPageTableOps::walkBits(), gem5::ArmISA::V8PageTableOps16k::walkBits(), gem5::ArmISA::V8PageTableOps4k::walkBits(), gem5::ArmISA::V8PageTableOps64k::walkBits(), gem5::SMMUTranslationProcess::walkCacheLookup(), gem5::SMMUTranslationProcess::walkCacheUpdate(), gem5::ArmISA::PageTableOps::walkMask(), gem5::SMMUTranslationProcess::walkStage1And2(), and gem5::SMMUTranslationProcess::walkStage2().

limit

BitfieldType< SegDescriptorLimit > gem5::X86ISA::limit

Definition at line 959 of file misc.hh.

Referenced by EndBitUnion(), gem5::X86ISA::SegDescriptorLimit::getter(), gem5::MemFootprintProbe::insertAddr(), gem5::compression::DictionaryCompressor< T >::DeltaPattern< DeltaSizeBits >::isValidDelta(), gem5::Shader::setLdsApe(), gem5::Shader::setScratchApe(), gem5::X86ISA::SegDescriptorLimit::setter(), gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

limit_in_pages

Bitfield<4> gem5::X86ISA::limit_in_pages

Definition at line 52 of file syscalls.hh.

limitHigh

Bitfield< 51, 48 > gem5::X86ISA::limitHigh

Definition at line 957 of file misc.hh.

limitLow

Bitfield< 15, 0 > gem5::X86ISA::limitLow

Definition at line 958 of file misc.hh.

lma

Bitfield<10> gem5::X86ISA::lma

Definition at line 818 of file misc.hh.

lme

Bitfield<8> gem5::X86ISA::lme

Definition at line 817 of file misc.hh.

LO

const uint8_t gem5::X86ISA::LO = Lock

Definition at line 55 of file decoder_tables.cc.

lock

Bitfield<5> gem5::X86ISA::lock

Definition at line 82 of file types.hh.

Referenced by gem5::DistIface::Sync::abort(), gem5::doSimLoop(), gem5::BaseKvmCPU::drain(), gem5::DrainManager::drainableCount(), gem5::DistIface::SyncNode::progress(), gem5::DistIface::SyncSwitch::progress(), gem5::DrainManager::registerDrainable(), gem5::DistIface::SyncNode::requestCkpt(), gem5::DistIface::SyncNode::requestExit(), gem5::DistIface::SyncNode::run(), gem5::DistIface::SyncSwitch::run(), gem5::DrainManager::unregisterDrainable(), and gem5::Barrier::wait().

longl1

gem5::X86ISA::longl1

Definition at line 123 of file pagetable.hh.

longl2

Bitfield<29, 21> gem5::X86ISA::longl2

Definition at line 124 of file pagetable.hh.

longl3

Bitfield<38, 30> gem5::X86ISA::longl3

Definition at line 125 of file pagetable.hh.

longl4

Bitfield<47, 39> gem5::X86ISA::longl4

Definition at line 126 of file pagetable.hh.

longMode

Bitfield<4> gem5::X86ISA::longMode

Definition at line 1024 of file misc.hh.

longPdtb

gem5::X86ISA::longPdtb

Definition at line 628 of file misc.hh.

m

Bitfield<4, 0> gem5::X86ISA::m

Definition at line 118 of file types.hh.

mask

gem5::X86ISA::mask

Definition at line 831 of file misc.hh.

Referenced by gem5::X86ISA::ISA::clear(), gem5::X86ISA::Decoder::decode(), gem5::X86ISA::Decoder::getImmediate(), gem5::X86ISA::SegDescriptorLimit::getter(), gem5::X86ISA::Interrupts::read(), gem5::X86ISA::ISA::setMiscRegNoEffect(), gem5::X86ISA::SegDescriptorLimit::setter(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translateInt(), gem5::X86ISA::TLB::translateInt(), gem5::X86ISA::I8259::write(), gem5::X86ISA::Interrupts::write(), and gem5::X86ISA::ACPI::RXSDT< T >::writeBuf().

mcaErrorCode

gem5::X86ISA::mcaErrorCode

Definition at line 795 of file misc.hh.

mce

Bitfield<6> gem5::X86ISA::mce

Definition at line 649 of file misc.hh.

MCGCP

Bitfield<8> gem5::X86ISA::MCGCP

Definition at line 739 of file misc.hh.

mcip

Bitfield<2> gem5::X86ISA::mcip

Definition at line 745 of file misc.hh.

mfdm

Bitfield<19> gem5::X86ISA::mfdm

Definition at line 849 of file misc.hh.

miscv

Bitfield<59> gem5::X86ISA::miscv

Definition at line 800 of file misc.hh.

MMIORegionVirtAddr

const Addr gem5::X86ISA::MMIORegionVirtAddr = 0xffffc90000000000

Definition at line 47 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

mod

gem5::X86ISA::mod

Definition at line 91 of file types.hh.

Referenced by gem5::EmbeddedPyBind::init(), gem5::EmbeddedPyBind::initAll(), gem5::ruby::mod(), and gem5::X86ISA::intelmp::CompatAddrSpaceMod::writeOut().

mode

Bitfield<3> gem5::X86ISA::mode

Definition at line 192 of file types.hh.

Referenced by EndBitUnion(), gem5::X86ISA::TLB::finalizePhysical(), gem5::X86ISA::I8259::getAddrRanges(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::GpuTLB::handleTranslationReturn(), gem5::X86ISA::Walker::WalkerState::initState(), gem5::X86ISA::PageFault::PageFault(), gem5::X86ISA::Walker::WalkerState::pageFault(), gem5::X86ISA::GpuTLB::pagingProtectionChecks(), gem5::X86ISA::I8259::read(), gem5::X86ISA::Walker::WalkerState::recvPacket(), gem5::X86ISA::I8259::serialize(), gem5::X86ISA::Walker::WalkerState::stepWalk(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translateAtomic(), gem5::X86ISA::TLB::translateAtomic(), gem5::X86ISA::MMU::translateFunctional(), gem5::X86ISA::GpuTLB::translateTiming(), gem5::X86ISA::TLB::translateTiming(), gem5::X86ISA::I8259::unserialize(), and gem5::X86ISA::I8259::write().

modelSpecificCode

Bitfield<31,16> gem5::X86ISA::modelSpecificCode

Definition at line 796 of file misc.hh.

mp

Bitfield<1> gem5::X86ISA::mp

Definition at line 618 of file misc.hh.

msrMap

const MsrMap gem5::X86ISA::msrMap

extern

Map between MSR addresses and their corresponding misc registers.

Note

This map is usually only used when enumeration of supported MSRs is needed (e.g., in virtualized CPUs). Code that needs to look-up specific MSRs should use msrAddrToIndex().

Referenced by gem5::X86KvmCPU::getMsrIntersection(), msrAddrToIndex(), gem5::X86KvmCPU::updateKvmStateMSRs(), and gem5::X86KvmCPU::updateThreadContextMSRs().

msrMapData

const MsrMap::value_type gem5::X86ISA::msrMapData[]

Definition at line 39 of file msr.cc.

msrMapSize

const unsigned gem5::X86ISA::msrMapSize = sizeof(msrMapData) / sizeof(msrMapData[0])

static

Definition at line 145 of file msr.cc.

mvdm

Bitfield<20> gem5::X86ISA::mvdm

Definition at line 850 of file misc.hh.

nameStringSize

int gem5::X86ISA::nameStringSize = 48

constexpr

Definition at line 73 of file cpuid.hh.

Referenced by gem5::X86ISA::X86CPUID::doCpuid().

ne

Bitfield<5> gem5::X86ISA::ne

Definition at line 614 of file misc.hh.

norml1

Bitfield<21, 12> gem5::X86ISA::norml1

Definition at line 132 of file pagetable.hh.

norml2

Bitfield<31, 22> gem5::X86ISA::norml2

Definition at line 133 of file pagetable.hh.

nt

Bitfield<14> gem5::X86ISA::nt

Definition at line 579 of file misc.hh.

NumCRegs

const int gem5::X86ISA::NumCRegs = 16

Definition at line 56 of file x86_traits.hh.

Referenced by gem5::X86ISA::misc_reg::cr().

NumDRegs

const int gem5::X86ISA::NumDRegs = 8

Definition at line 57 of file x86_traits.hh.

Referenced by gem5::X86ISA::misc_reg::dr().

NumMicroFpRegs

const int gem5::X86ISA::NumMicroFpRegs = 8

Definition at line 54 of file x86_traits.hh.

Referenced by gem5::X86ISA::X86StaticInst::printReg(), and gem5::X86ISA::FlatFloatRegClassOps::regName().

NumMicroIntRegs

const int gem5::X86ISA::NumMicroIntRegs = 16

Definition at line 50 of file x86_traits.hh.

Referenced by EndBitUnion().

NumMMXRegs

const int gem5::X86ISA::NumMMXRegs = 8

Definition at line 52 of file x86_traits.hh.

Referenced by gem5::X86ISA::X86StaticInst::printReg(), and gem5::X86ISA::FlatFloatRegClassOps::regName().

NumSegments

const int gem5::X86ISA::NumSegments = 6

Definition at line 60 of file x86_traits.hh.

NumSysSegments

const int gem5::X86ISA::NumSysSegments = 4

Definition at line 61 of file x86_traits.hh.

NumXCRegs

const int gem5::X86ISA::NumXCRegs = 1

Definition at line 58 of file x86_traits.hh.

Referenced by gem5::X86KvmCPU::updateKvmStateXCRs(), and gem5::X86ISA::misc_reg::xcr().

NumXMMRegs

const int gem5::X86ISA::NumXMMRegs = 16

Definition at line 53 of file x86_traits.hh.

Referenced by gem5::X86ISA::X86StaticInst::printReg(), and gem5::X86ISA::FlatFloatRegClassOps::regName().

nw

Bitfield<29> gem5::X86ISA::nw

Definition at line 611 of file misc.hh.

Referenced by gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::partialWriter(), and gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::writer().

nxe

Bitfield<11> gem5::X86ISA::nxe

Definition at line 819 of file misc.hh.

of

Bitfield<11> gem5::X86ISA::of

Definition at line 581 of file misc.hh.

Referenced by TEST_F().

offset

gem5::X86ISA::offset

Definition at line 1059 of file misc.hh.

Referenced by gem5::X86ISA::ACPI::LinearAllocator::alloc(), gem5::X86ISA::X86CPUID::doCpuid(), gem5::X86ISA::Interrupts::findRegArrayMSB(), gem5::X86ISA::FsWorkload::initState(), gem5::X86ISA::I82094AA::read(), gem5::X86ISA::I8254::read(), gem5::X86ISA::Interrupts::read(), gem5::X86ISA::I82094AA::readReg(), gem5::X86ISA::Interrupts::recvMessage(), gem5::X86ISA::Interrupts::setReg(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::I82094AA::write(), gem5::X86ISA::I8254::write(), gem5::X86ISA::Interrupts::write(), gem5::X86ISA::I8237::WriteOnlyReg::WriteOnlyReg(), gem5::X86ISA::intelmp::ConfigTable::writeOut(), gem5::X86ISA::smbios::SMBiosTable::writeOut(), gem5::X86ISA::smbios::SMBiosStructure::writeOutStrings(), and gem5::X86ISA::I82094AA::writeReg().

offsetHigh

gem5::X86ISA::offsetHigh

Definition at line 1036 of file misc.hh.

offsetLow

Bitfield< 15, 0 > gem5::X86ISA::offsetLow

Definition at line 1037 of file misc.hh.

OO

const uint8_t gem5::X86ISA::OO = OperandSizeOverride

Definition at line 53 of file decoder_tables.cc.

op

Bitfield<4> gem5::X86ISA::op

Definition at line 83 of file types.hh.

Referenced by gem5::ArmISA::Crypto::_sha1Op(), gem5::ArmSemihosting::call32(), gem5::RiscvSemihosting::call32(), gem5::ArmSemihosting::call64(), gem5::RiscvSemihosting::call64(), gem5::MipsISA::dspCmp(), gem5::MipsISA::dspCmpg(), gem5::MipsISA::dspCmpgd(), gem5::ArmISA::flushToZero(), gem5::ArmISA::fp16_FPConvertNaN_32(), gem5::ArmISA::fp16_FPConvertNaN_64(), gem5::ArmISA::fp32_FPConvertNaN_16(), gem5::ArmISA::fp32_FPConvertNaN_64(), gem5::ArmISA::fp64_FPConvertNaN_16(), gem5::ArmISA::fp64_FPConvertNaN_32(), gem5::ArmISA::fplibAbs(), gem5::ArmISA::fplibAbs(), gem5::ArmISA::fplibAbs(), gem5::ArmISA::fplibConvert(), gem5::ArmISA::fplibConvert(), gem5::ArmISA::fplibConvert(), gem5::ArmISA::fplibExpA(), gem5::ArmISA::fplibExpA(), gem5::ArmISA::fplibExpA(), gem5::ArmISA::fplibFixedToFP(), gem5::ArmISA::fplibFPToFixed(), gem5::ArmISA::fplibFPToFixed(), gem5::ArmISA::fplibFPToFixed(), gem5::ArmISA::fplibFPToFixedJS(), gem5::ArmISA::fplibNeg(), gem5::ArmISA::fplibNeg(), gem5::ArmISA::fplibNeg(), gem5::ArmISA::fplibRecipEstimate(), gem5::ArmISA::fplibRecipEstimate(), gem5::ArmISA::fplibRecipEstimate(), gem5::ArmISA::fplibRecpX(), gem5::ArmISA::fplibRecpX(), gem5::ArmISA::fplibRecpX(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRoundInt(), gem5::ArmISA::fplibRSqrtEstimate(), gem5::ArmISA::fplibRSqrtEstimate(), gem5::ArmISA::fplibRSqrtEstimate(), gem5::ArmISA::fplibSqrt(), gem5::ArmISA::fplibSqrt(), gem5::ArmISA::fplibSqrt(), gem5::ArmISA::fpRecipEstimate(), gem5::ArmISA::fprSqrtEstimate(), gem5::futexFunc(), gem5::GPUStaticInst::generateVirtToPhysMap(), gem5::loader::SymbolTable::mask(), gem5::loader::SymbolTable::offset(), gem5::loader::SymbolTable::operate(), gem5::loader::SymbolTable::rename(), gem5::statistics::BinaryNode< Op >::result(), gem5::statistics::SumNode< Op >::result(), gem5::statistics::UnaryNode< Op >::result(), gem5::ArmISA::ArmStaticInst::satInt(), gem5::ArmISA::Crypto::sha1Op(), gem5::ArmISA::simd_modified_imm(), gem5::MipsISA::sys_getsysinfoFunc(), gem5::MipsISA::sys_setsysinfoFunc(), gem5::statistics::BinaryNode< Op >::total(), gem5::statistics::SumNode< Op >::total(), gem5::BaseSemihosting::unrecognizedCall(), gem5::ArmISA::unsignedRecipEstimate(), gem5::ArmISA::unsignedRSqrtEstimate(), gem5::ArmISA::ArmStaticInst::uSatInt(), gem5::ArmISA::vcvtFpDFpH(), gem5::ArmISA::vcvtFpHFp(), gem5::ArmISA::vcvtFpHFpD(), gem5::ArmISA::vcvtFpHFpS(), gem5::ArmISA::vcvtFpSFpH(), and gem5::ArmISA::vfpFlushToZero().

opmask

Bitfield<5> gem5::X86ISA::opmask

Definition at line 671 of file misc.hh.

os

Bitfield<17> gem5::X86ISA::os

Definition at line 838 of file misc.hh.

Referenced by gem5::arrayParamOut(), gem5::arrayParamOut(), gem5::arrayParamOut(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::bitfield_backend::bitfieldBackendPrinter(), gem5::FunctionProfile::dump(), gem5::ProfileNode::dump(), gem5::Trie< Key, Value >::dump(), gem5::Trie< Key, Value >::Node::dump(), gem5::guest_abi::dumpArgsFrom(), gem5::dumpDebugFlags(), gem5::linux::dumpDmesg(), gem5::OutputDirectory::findOrCreate(), getString(), gem5::mappingParamOut(), gem5::minor::LSQ::StoreBuffer::minorTrace(), gem5::OutputDirectory::open(), gem5::guest_abi::operator<<(), gem5::loader::operator<<(), gem5::minor::operator<<(), gem5::minor::operator<<(), gem5::minor::operator<<(), gem5::minor::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::operator<<(), gem5::pseudo_inst::operator<<(), gem5::ruby::operator<<(), gem5::ruby::operator<<(), operator<<(), operator<<(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractPrimDisp(), gem5::stl_helpers::opExtract_impl::opExtractSecDisp(), gem5::GenericISA::DelaySlotPCState< InstWidth >::output(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::output(), gem5::GenericISA::PCStateWithNext::output(), gem5::GenericISA::UPCState< InstWidth >::output(), gem5::ListenSocketInet::output(), gem5::ListenSocketUnixAbstract::output(), gem5::ListenSocketUnixFile::output(), gem5::paramOut(), gem5::CacheBlkPrintWrapper::print(), gem5::MSHR::print(), gem5::MSHR::TargetList::print(), gem5::WriteQueueEntry::print(), gem5::WriteQueueEntry::TargetList::print(), gem5::X86ISA::AddrOp::print(), gem5::X86ISA::CrOp< Base >::print(), gem5::X86ISA::DbgOp< Base >::print(), gem5::X86ISA::FaultOp::print(), gem5::X86ISA::FloatOp< Base >::print(), gem5::X86ISA::FoldedOp< Base >::print(), gem5::X86ISA::Imm64Op::print(), gem5::X86ISA::Imm8Op::print(), gem5::X86ISA::IntOp< Base >::print(), gem5::X86ISA::MiscOp< Base >::print(), gem5::X86ISA::SegOp< Base >::print(), gem5::X86ISA::UpcOp::print(), gem5::ArmISA::ArmStaticInst::printCCReg(), gem5::ArmISA::ArmStaticInst::printCondition(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::Memory::printDest(), gem5::ArmISA::MemoryDImm::printDest(), gem5::ArmISA::MemoryDReg::printDest(), gem5::ArmISA::MemoryExDImm::printDest(), gem5::ArmISA::MemoryExImm::printDest(), gem5::SparcISA::SparcStaticInst::printDestReg(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printFloatReg(), gem5::ArmISA::Memory::printInst(), gem5::ArmISA::ArmStaticInst::printIntReg(), gem5::X86ISA::X86StaticInst::printMem(), gem5::ArmISA::ArmStaticInst::printMemSymbol(), gem5::ArmISA::ArmStaticInst::printMiscReg(), gem5::ArmISA::ArmStaticInst::printMnemonic(), gem5::SparcISA::SparcStaticInst::printMnemonic(), gem5::X86ISA::X86StaticInst::printMnemonic(), gem5::X86ISA::X86StaticInst::printMnemonic(), gem5::MsrBase::printMsrBase(), gem5::ArmISA::MemoryImm::printOffset(), gem5::ArmISA::MemoryReg::printOffset(), gem5::ArmISA::ArmStaticInst::printPFflags(), gem5::SparcISA::IntOp::printPseudoOps(), gem5::SparcISA::IntOpImm::printPseudoOps(), gem5::PowerISA::PowerStaticInst::printReg(), gem5::SparcISA::SparcStaticInst::printReg(), gem5::X86ISA::X86StaticInst::printReg(), gem5::SparcISA::SparcStaticInst::printRegArray(), gem5::minor::printRegName(), gem5::X86ISA::X86StaticInst::printSegment(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::SparcISA::SparcStaticInst::printSrcReg(), gem5::ArmISA::ArmStaticInst::printTarget(), gem5::ArmISA::ArmStaticInst::printVecPredReg(), gem5::ArmISA::ArmStaticInst::printVecReg(), gem5::linux::PanicOrOopsEvent::process(), gem5::minor::BranchData::reportData(), gem5::minor::Fetch1::FetchRequest::reportData(), gem5::minor::ForwardInstData::reportData(), gem5::minor::ForwardLineData::reportData(), gem5::minor::LSQ::LSQRequest::reportData(), gem5::minor::MinorDynInst::reportData(), gem5::minor::QueuedInst::reportData(), gem5::minor::ReportTraitsAdaptor< ElemType >::reportData(), gem5::minor::ReportTraitsPtrAdaptor< PtrType >::reportData(), gem5::CxxConfigManager::serialize(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::serialize(), gem5::RegisterBank< BankByteOrder >::RegisterLBuf< BufBytes >::serialize(), gem5::ShowParam< T, Enabled >::show(), gem5::ShowParam< BitUnionType< T > >::show(), gem5::ShowParam< bool >::show(), gem5::ShowParam< MatStore< X, Y > >::show(), gem5::ShowParam< T, std::enable_if_t< std::is_base_of_v< typename RegisterBankBase::RegisterBaseBase, T > > >::show(), gem5::ShowParam< T, std::enable_if_t< std::is_same_v< char, T >||std::is_same_v< unsigned char, T >||std::is_same_v< signed char, T > > >::show(), gem5::ShowParam< VecPredRegContainer< NumBits, Packed > >::show(), gem5::ShowParam< VecRegContainer< Sz > >::show(), gem5::ArmISA::Memory64::startDisassembly(), TEST(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), and gem5::pseudo_inst::writefile().

osfxsr

Bitfield<9> gem5::X86ISA::osfxsr

Definition at line 646 of file misc.hh.

osxmmexcpt

Bitfield<10> gem5::X86ISA::osxmmexcpt

Definition at line 644 of file misc.hh.

otherInfo

Bitfield<56,32> gem5::X86ISA::otherInfo

Definition at line 797 of file misc.hh.

over

Bitfield<62> gem5::X86ISA::over

Definition at line 803 of file misc.hh.

p

Bitfield< 1, 0 > gem5::X86ISA::p

Definition at line 151 of file pagetable.hh.

Referenced by archPrctlFunc(), gem5::X86ISA::smbios::BiosInformation::BiosInformation(), gem5::X86ISA::intelmp::BusHierarchy::BusHierarchy(), gem5::X86ISA::I386Process::clone(), gem5::X86ISA::X86_64Process::clone(), gem5::X86ISA::X86Process::clone(), gem5::X86ISA::intelmp::CompatAddrSpaceMod::CompatAddrSpaceMod(), gem5::X86ISA::I8042::I8042(), gem5::X86ISA::I82094AA::I82094AA(), gem5::X86ISA::I8254::I8254(), gem5::X86ISA::I8259::I8259(), gem5::X86ISA::intelmp::IOAPIC::IOAPIC(), gem5::X86ISA::ISA::ISA(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::X86ISA::EmuLinux::pageFault(), gem5::X86ISA::LongModePTE::present(), gem5::X86ISA::intelmp::Processor::Processor(), gem5::X86ISA::LongModePTE::read(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::X86ISA::ACPI::RSDT::RSDT(), gem5::X86ISA::smbios::SMBiosTable::SMBiosTable(), gem5::X86ISA::TLB::TLB(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::TLB::translate(), gem5::X86ISA::GpuTLB::translationReturn(), gem5::X86ISA::LongModePTE::write(), gem5::X86ISA::ACPI::SysDescTable::writeBuf(), and gem5::X86ISA::ACPI::XSDT::XSDT().

pae

Bitfield<5> gem5::X86ISA::pae

Definition at line 650 of file misc.hh.

pael1

Bitfield<20, 12> gem5::X86ISA::pael1

Definition at line 128 of file pagetable.hh.

pael2

Bitfield<29, 21> gem5::X86ISA::pael2

Definition at line 129 of file pagetable.hh.

pael3

Bitfield<31, 30> gem5::X86ISA::pael3

Definition at line 130 of file pagetable.hh.

paePdtb

Bitfield<31, 5> gem5::X86ISA::paePdtb

Definition at line 632 of file misc.hh.

PageBytes

const Addr gem5::X86ISA::PageBytes = 1ULL << PageShift

Definition at line 49 of file page_size.hh.

Referenced by gem5::X86ISA::X86Process::argsInit(), gem5::TLBCoalescer::canCoalesce(), gem5::X86ISA::TLB::finalizePhysical(), gem5::X86ISA::Interrupts::getAddrRanges(), gem5::X86ISA::GpuTLB::handleFuncTranslationReturn(), gem5::X86ISA::I386Process::I386Process(), gem5::X86ISA::X86_64Process::initState(), gem5::GPUComputeDriver::ioctl(), gem5::X86ISA::GpuTLB::issueTLBLookup(), gem5::Shader::mmap(), gem5::X86ISA::EmuLinux::pageFault(), gem5::TLBCoalescer::processProbeTLBEvent(), gem5::TLBCoalescer::CpuSidePort::recvFunctional(), gem5::X86ISA::GpuTLB::CpuSidePort::recvFunctional(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::X86ISA::GpuTLB::MemSidePort::recvTimingResp(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::MMU::translateFunctional(), gem5::ComputeUnit::updatePageDivergenceDist(), gem5::TLBCoalescer::updatePhysAddresses(), and gem5::X86ISA::X86_64Process::X86_64Process().

PageShift

const Addr gem5::X86ISA::PageShift = 12

Definition at line 48 of file page_size.hh.

Referenced by gem5::X86ISA::GpuTLB::demapPage(), gem5::X86ISA::GpuTLB::insert(), gem5::X86ISA::GpuTLB::lookup(), gem5::X86ISA::GpuTLB::lookupIt(), gem5::X86ISA::LongModePTE::paddr(), gem5::X86ISA::LongModePTE::paddr(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), gem5::X86ISA::LongModePTE::tableSize(), and gem5::X86ISA::TLB::translate().

paging

Bitfield<6> gem5::X86ISA::paging

Definition at line 596 of file misc.hh.

pb0

Bitfield<2> gem5::X86ISA::pb0

Definition at line 751 of file misc.hh.

pb1

Bitfield<3> gem5::X86ISA::pb1

Definition at line 752 of file misc.hh.

pb2

Bitfield<4> gem5::X86ISA::pb2

Definition at line 753 of file misc.hh.

pb3

Bitfield<5> gem5::X86ISA::pb3

Definition at line 754 of file misc.hh.

pc

Bitfield<19> gem5::X86ISA::pc

Definition at line 840 of file misc.hh.

Referenced by gem5::X86ISA::X86MicroopBase::advancePC(), gem5::X86ISA::X86StaticInst::advancePC(), gem5::X86ISA::PCState::branching(), gem5::X86ISA::EmuLinux::event(), gem5::X86ISA::BareMetalWorkload::initState(), gem5::X86ISA::InitInterrupt::invoke(), gem5::X86ISA::X86FaultBase::invoke(), gem5::X86ISA::Decoder::moreBytes(), and gem5::X86ISA::EmuLinux::syscall().

pcc

Bitfield<57> gem5::X86ISA::pcc

Definition at line 798 of file misc.hh.

pcd

Bitfield< 4 > gem5::X86ISA::pcd

Definition at line 147 of file pagetable.hh.

pce

Bitfield<8> gem5::X86ISA::pce

Definition at line 647 of file misc.hh.

pcid

Bitfield<11, 0> gem5::X86ISA::pcid

Definition at line 634 of file misc.hh.

Referenced by gem5::X86ISA::TLB::concAddrPcid(), gem5::X86ISA::TLB::insert(), and gem5::X86ISA::TLB::translate().

pcide

Bitfield<17> gem5::X86ISA::pcide

Definition at line 641 of file misc.hh.

pdtb

Bitfield<31, 12> gem5::X86ISA::pdtb

Definition at line 630 of file misc.hh.

pe

Bitfield<0> gem5::X86ISA::pe

Definition at line 619 of file misc.hh.

Referenced by gem5::EtherLink::Link::serialize().

pf

Bitfield< 2 > gem5::X86ISA::pf

Definition at line 565 of file misc.hh.

Referenced by gem5::prefetch::Multi::getPacket(), gem5::Cache::handleTimingReqMiss(), gem5::prefetch::Multi::nextPrefetchReadyTime(), gem5::ComputeUnit::DTLBPort::recvTimingResp(), and gem5::prefetch::Multi::setParentInfo().

PFHandlerVirtAddr

const Addr gem5::X86ISA::PFHandlerVirtAddr = 0xffff800000005000

Definition at line 46 of file se_workload.hh.

Referenced by gem5::X86ISA::EmuLinux::event(), and gem5::X86ISA::X86_64Process::initState().

pge

Bitfield<7> gem5::X86ISA::pge

Definition at line 648 of file misc.hh.

physAddr

gem5::X86ISA::physAddr

Definition at line 866 of file misc.hh.

Referenced by gem5::TraceCPU::ElasticDataGen::GraphNode::writeElementAsTrace().

PhysAddrAPICRangeSize

const Addr gem5::X86ISA::PhysAddrAPICRangeSize = 1 << 12

Definition at line 74 of file x86_traits.hh.

Referenced by gem5::X86ISA::Interrupts::getIntAddrRange(), and x86InterruptAddress().

PhysAddrIntA

const Addr gem5::X86ISA::PhysAddrIntA = 0x8000000100000000ULL

Definition at line 77 of file x86_traits.hh.

Referenced by buildIntAcknowledgePacket(), gem5::X86ISA::I8259::getAddrRanges(), and gem5::X86ISA::I8259::read().

PhysAddrPrefixInterrupts

const Addr gem5::X86ISA::PhysAddrPrefixInterrupts = 0xA000000000000000ULL

Definition at line 71 of file x86_traits.hh.

Referenced by x86InterruptAddress().

PhysAddrPrefixIO

const Addr gem5::X86ISA::PhysAddrPrefixIO = 0x8000000000000000ULL

Definition at line 68 of file x86_traits.hh.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), gem5::X86ISA::TLB::translateInt(), and x86IOAddress().

PhysAddrPrefixLocalAPIC

const Addr gem5::X86ISA::PhysAddrPrefixLocalAPIC = 0x2000000000000000ULL

Definition at line 70 of file x86_traits.hh.

Referenced by x86LocalAPICAddress().

PhysAddrPrefixPciConfig

const Addr gem5::X86ISA::PhysAddrPrefixPciConfig = 0xC000000000000000ULL

Definition at line 69 of file x86_traits.hh.

Referenced by gem5::X86ISA::GpuTLB::translateInt(), gem5::X86ISA::TLB::translateInt(), and x86PciConfigAddress().

physbase

Bitfield< 51, 12 > gem5::X86ISA::physbase

Definition at line 763 of file misc.hh.

physmask

Bitfield< 51, 12 > gem5::X86ISA::physmask

Definition at line 768 of file misc.hh.

pkru

Bitfield<9> gem5::X86ISA::pkru

Definition at line 677 of file misc.hh.

present

Bitfield< 0 > gem5::X86ISA::present

Definition at line 1027 of file misc.hh.

Referenced by gem5::X86ISA::PageFault::PageFault(), gem5::VegaISA::Walker::WalkerState::pageFault(), gem5::X86ISA::Walker::WalkerState::pageFault(), gem5::ruby::PersistentTable::persistentRequestLock(), and gem5::X86ISA::LongModePTE::reset().

prot

Bitfield<7> gem5::X86ISA::prot

Definition at line 597 of file misc.hh.

Referenced by gem5::mmap2Func(), gem5::mmapFunc(), gem5::socketFunc(), and gem5::socketpairFunc().

ps

Bitfield<7> gem5::X86ISA::ps

Definition at line 144 of file pagetable.hh.

pse

Bitfield<4> gem5::X86ISA::pse

Definition at line 651 of file misc.hh.

pvi

Bitfield<1> gem5::X86ISA::pvi

Definition at line 654 of file misc.hh.

pwt

Bitfield< 3 > gem5::X86ISA::pwt

Definition at line 148 of file pagetable.hh.

R

gem5::X86ISA::R

Definition at line 54 of file int.hh.

r

Bitfield< 2 > gem5::X86ISA::r

Definition at line 969 of file misc.hh.

Referenced by gem5::X86ISA::LongModePTE::readonly().

rd

Bitfield<4> gem5::X86ISA::rd

Definition at line 856 of file misc.hh.

RE

const uint8_t gem5::X86ISA::RE = Rep

Definition at line 56 of file decoder_tables.cc.

read_exec_only

Bitfield<3> gem5::X86ISA::read_exec_only

Definition at line 51 of file syscalls.hh.

readable

Bitfield<13> gem5::X86ISA::readable

Definition at line 1030 of file misc.hh.

reg

Bitfield<5,3> gem5::X86ISA::reg

Definition at line 92 of file types.hh.

Referenced by gem5::ArmISA::AArch32isUndefinedGenericTimer(), gem5::o3::SimpleFreeList::addReg(), gem5::trace::TarmacTracerRecord::addRegEntry(), gem5::trace::TarmacTracerRecordV8::addRegEntry(), gem5::RegisterBank< BankByteOrder >::addRegister(), gem5::RegisterBank< BankByteOrder >::addRegisters(), gem5::RegisterBank< BankByteOrder >::addRegistersAt(), gem5::o3::SimpleFreeList::addRegs(), gem5::o3::UnifiedFreeList::addRegs(), gem5::SparcLinux::archClone(), gem5::InstResult::asString(), gem5::minor::Scoreboard::canInstIssue(), gem5::ArmISA::canReadCoprocReg(), gem5::ArmISA::canWriteCoprocReg(), gem5::ArmISA::checkFaultAccessAArch64SysReg(), gem5::minor::Scoreboard::clearInstDests(), gem5::SparcISA::ISA::copyRegsFrom(), gem5::ArmISA::couldBeSP(), gem5::ArmISA::couldBeZero(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::defaultPartialReader(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::defaultPartialWriter(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::defaultReader(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::defaultResetter(), gem5::RegisterBank< BankByteOrder >::Register< Data, RegByteOrder >::defaultWriter(), gem5::ArmV8KvmCPU::dump(), gem5::minor::Scoreboard::execSeqNumToWaitFor(), gem5::minor::Scoreboard::findIndex(), gem5::ArmISA::flattenIntRegModeIndex(), gem5::ArmISA::ISA::flattenMiscIndex(), gem5::SparcISA::SEWorkload::flushWindows(), gem5::MrsOp::generateDisassembly(), gem5::trace::TarmacTracerRecord::genRegister(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::o3::CPU::getArchReg(), gem5::o3::CPU::getArchReg(), gem5::KvmKernelGicV2::getGicReg(), gem5::KvmKernelGicV3::getGicReg(), gem5::ArmISA::getHSlice(), gem5::BaseKvmCPU::getOneReg(), gem5::CheckerThreadContext< TC >::getReg(), gem5::CheckerThreadContext< TC >::getReg(), gem5::Iris::ThreadContext::getReg(), gem5::Iris::ThreadContext::getReg(), gem5::o3::ThreadContext::getReg(), gem5::o3::ThreadContext::getReg(), gem5::SimpleThread::getReg(), gem5::SimpleThread::getReg(), gem5::ThreadContext::getReg(), gem5::minor::ExecContext::getRegOperand(), gem5::o3::DynInst::getRegOperand(), gem5::o3::DynInst::getRegOperand(), gem5::SimpleExecContext::getRegOperand(), gem5::SimpleExecContext::getRegOperand(), gem5::PowerISA::RemoteGDB::PowerGdbRegCache::getRegs(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::ArmISA::getTile(), gem5::ArmISA::getTileHSlice(), gem5::ArmISA::getTileVSlice(), gem5::ArmISA::getVSlice(), gem5::o3::CPU::getWritableArchReg(), gem5::CheckerThreadContext< TC >::getWritableReg(), gem5::Iris::ThreadContext::getWritableReg(), gem5::o3::ThreadContext::getWritableReg(), gem5::SimpleThread::getWritableReg(), gem5::SimpleExecContext::getWritableRegOperand(), gem5::VegaISA::Inst_FLAT::initFlatOperandInfo(), gem5::VegaISA::Inst_FLAT::initGlobalScratchOperandInfo(), gem5::VegaISA::Inst_DS::initOperandInfo(), gem5::VegaISA::Inst_MIMG::initOperandInfo(), gem5::VegaISA::Inst_MTBUF::initOperandInfo(), gem5::VegaISA::Inst_MUBUF::initOperandInfo(), gem5::VegaISA::Inst_SMEM::initOperandInfo(), gem5::VegaISA::Inst_SOP1::initOperandInfo(), gem5::VegaISA::Inst_SOP2::initOperandInfo(), gem5::VegaISA::Inst_SOPC::initOperandInfo(), gem5::VegaISA::Inst_SOPK::initOperandInfo(), gem5::VegaISA::Inst_SOPP::initOperandInfo(), gem5::VegaISA::Inst_VOP1::initOperandInfo(), gem5::VegaISA::Inst_VOP2::initOperandInfo(), gem5::VegaISA::Inst_VOP3A::initOperandInfo(), gem5::VegaISA::Inst_VOP3B::initOperandInfo(), gem5::VegaISA::Inst_VOP3P::initOperandInfo(), gem5::VegaISA::Inst_VOP3P_MAI::initOperandInfo(), gem5::VegaISA::Inst_VOPC::initOperandInfo(), gem5::ArmISA::ISA::InitReg(), gem5::ArmISA::isSP(), gem5::ArmISA::isZero(), gem5::LupioIPI::lupioIPIRead(), gem5::LupioIPI::lupioIPIWrite(), gem5::LupioPIC::lupioPicRead(), gem5::LupioPIC::lupioPicWrite(), gem5::LupioTMR::lupioTMRRead(), gem5::LupioTMR::lupioTMRWrite(), gem5::ArmISA::MacroMemOp::MacroMemOp(), gem5::ArmISA::makeSP(), gem5::ArmISA::makeZero(), gem5::minor::Scoreboard::markupInstDests(), gem5::ArmISA::TableWalker::memAttrsLPAE(), gem5::X86ISA::X86StaticInst::merge(), gem5::trace::TarmacTracerRecord::mergeCCEntry(), gem5::CustomNoMaliGpu::onReset(), gem5::networking::EthAddr::operator uint64_t(), gem5::X86ISA::X86StaticInst::pick(), gem5::ArmISA::preUnflattenMiscReg(), gem5::SparcISA::SparcStaticInst::printDestReg(), gem5::MsrBase::printMsrBase(), gem5::PowerISA::PowerStaticInst::printReg(), gem5::SparcISA::SparcStaticInst::printReg(), gem5::X86ISA::X86StaticInst::printReg(), gem5::minor::printRegName(), gem5::SparcISA::SparcStaticInst::printSrcReg(), gem5::EnergyCtrl::read(), gem5::NSGigE::read(), gem5::RegisterBank< BankByteOrder >::read(), gem5::sinic::Device::read(), gem5::X86ISA::Interrupts::read(), gem5::Plic::readClaim(), gem5::GenericTimer::readMiscReg(), gem5::GenericTimerISA::readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::CheckerCPU::readMiscRegOperand(), gem5::minor::ExecContext::readMiscRegOperand(), gem5::o3::DynInst::readMiscRegOperand(), gem5::SimpleExecContext::readMiscRegOperand(), gem5::Clint::readMSIP(), gem5::NoMaliGpu::readReg(), gem5::X86ISA::Interrupts::readReg(), gem5::X86ISA::Cmos::readRegister(), gem5::MipsISA::readRegOtherThread(), gem5::MipsISA::readRegOtherThread(), gem5::NoMaliGpu::readRegRaw(), gem5::Iris::ThreadContext::readVecPredReg(), gem5::Iris::ThreadContext::readVecReg(), gem5::ArmISA::int_reg::regInMode(), gem5::RiscvISA::registerName(), gem5::fastmodel::ResetControllerExample::Registers::Registers(), gem5::Uart8250::Registers::Registers(), gem5::Clint::serialize(), gem5::Plic::serialize(), gem5::sinic::Device::serialize(), gem5::o3::CPU::setArchReg(), gem5::o3::CPU::setArchReg(), gem5::KvmKernelGicV2::setGicReg(), gem5::KvmKernelGicV3::setGicReg(), gem5::GenericTimer::setMiscReg(), gem5::GenericTimerISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::CheckerCPU::setMiscRegOperand(), gem5::minor::ExecContext::setMiscRegOperand(), gem5::o3::DynInst::setMiscRegOperand(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::BaseKvmCPU::setOneReg(), gem5::CheckerThreadContext< TC >::setReg(), gem5::CheckerThreadContext< TC >::setReg(), gem5::Iris::ThreadContext::setReg(), gem5::Iris::ThreadContext::setReg(), gem5::o3::ThreadContext::setReg(), gem5::o3::ThreadContext::setReg(), gem5::SimpleThread::setReg(), gem5::SimpleThread::setReg(), gem5::ThreadContext::setReg(), gem5::X86ISA::Interrupts::setReg(), gem5::X86ISA::Interrupts::setRegNoEffect(), gem5::minor::ExecContext::setRegOperand(), gem5::o3::DynInst::setRegOperand(), gem5::o3::DynInst::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::MipsISA::setRegOtherThread(), gem5::MipsISA::setRegOtherThread(), gem5::X86ISA::X86StaticInst::signedPick(), gem5::MipsISA::simdPack(), gem5::MipsISA::simdUnpack(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::snsBankedIndex(), gem5::ArmISA::ISA::snsBankedIndex64(), gem5::ArmISA::snsBankedIndex64(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::guest_abi::Result< Aapcs64, Float, typename std::enable_if_t< std::is_floating_point_v< Float >||IsAapcs64ShortVectorV< Float > > >::store(), gem5::X86ISA::X86CPUID::stringToRegister(), gem5::ArmISA::syncVecElemsToRegs(), gem5::ArmISA::syncVecRegsToElems(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), TEST_F(), gem5::ArmISA::unflattenMiscReg(), gem5::Clint::unserialize(), gem5::Plic::unserialize(), gem5::sinic::Device::unserialize(), gem5::ArmV8KvmCPU::updateKvmState(), gem5::ArmKvmCPU::updateKvmStateCoProc(), gem5::ArmKvmCPU::updateTCStateCoProc(), gem5::ArmV8KvmCPU::updateThreadContext(), gem5::VectorRegisterFile::VectorRegisterFile(), gem5::EnergyCtrl::write(), gem5::NSGigE::write(), gem5::RegisterBank< BankByteOrder >::write(), gem5::X86ISA::Interrupts::write(), gem5::Plic::writeClaim(), gem5::Plic::writeEnable(), gem5::Uart8250::writeIer(), gem5::Clint::writeMSIP(), gem5::X86ISA::I8237::WriteOnlyReg::WriteOnlyReg(), gem5::Plic::writePriority(), gem5::NoMaliGpu::writeReg(), gem5::X86ISA::Cmos::writeRegister(), gem5::NoMaliGpu::writeRegRaw(), and gem5::Plic::writeThreshold().

rep

Bitfield<6> gem5::X86ISA::rep

Definition at line 81 of file types.hh.

repne

Bitfield<7> gem5::X86ISA::repne

Definition at line 80 of file types.hh.

rf

Bitfield<16> gem5::X86ISA::rf

Definition at line 578 of file misc.hh.

Referenced by gem5::SimpleThread::clearArchRegs(), and gem5::RegisterFile::MarkRegBusyScbEvent::process().

rInit

Bitfield<1> gem5::X86ISA::rInit

Definition at line 871 of file misc.hh.

rm

Bitfield<2,0> gem5::X86ISA::rm

Definition at line 93 of file types.hh.

Referenced by gem5::X86ISA::EmulEnv::doModRM().

RN

const uint8_t gem5::X86ISA::RN = Repne

Definition at line 57 of file decoder_tables.cc.

rpl

Bitfield<1, 0> gem5::X86ISA::rpl

Definition at line 897 of file misc.hh.

rsmCycle

Bitfield<4> gem5::X86ISA::rsmCycle

Definition at line 884 of file misc.hh.

rw0

Bitfield<17, 16> gem5::X86ISA::rw0

Definition at line 702 of file misc.hh.

rw1

Bitfield<21, 20> gem5::X86ISA::rw1

Definition at line 704 of file misc.hh.

rw2

Bitfield<25, 24> gem5::X86ISA::rw2

Definition at line 706 of file misc.hh.

rw3

Bitfield<29, 28> gem5::X86ISA::rw3

Definition at line 708 of file misc.hh.

RX

const uint8_t gem5::X86ISA::RX = RexPrefix

Definition at line 58 of file decoder_tables.cc.

s

Bitfield<44> gem5::X86ISA::s

Definition at line 962 of file misc.hh.

scale

gem5::X86ISA::scale

Definition at line 97 of file types.hh.

Referenced by gem5::ArmISA::fp16_muladd(), gem5::ArmISA::fp32_muladd(), gem5::ArmISA::fp64_muladd(), gem5::branch_prediction::MultiperspectivePerceptron::BLURRYPATH::getHash(), gem5::X86ISA::X86StaticInst::printMem(), gem5::ArmISA::vfpSFixedToFpD(), gem5::ArmISA::vfpSFixedToFpS(), gem5::ArmISA::vfpUFixedToFpD(), and gem5::ArmISA::vfpUFixedToFpS().

SE

SignedBitfield<31,0> gem5::X86ISA::SE

Definition at line 57 of file int.hh.

seg

Bitfield<2,0> gem5::X86ISA::seg

Definition at line 87 of file types.hh.

Referenced by gem5::loader::MemoryImage::addSegment(), gem5::loader::MemoryImage::addSegments(), gem5::checkSeg(), gem5::loader::MemoryImage::contains(), gem5::dumpKvm(), gem5::loader::ElfObject::ElfObject(), gem5::forceSegAccessed(), gem5::X86ISA::X86_64Process::initState(), installSegDesc(), gem5::X86ISA::InitInterrupt::invoke(), gem5::loader::MemoryImage::maxAddr(), gem5::loader::MemoryImage::MemoryImage(), gem5::loader::MemoryImage::minAddr(), gem5::loader::MemoryImage::move(), gem5::loader::operator<<(), gem5::X86ISA::GpuTLB::tlbLookup(), gem5::X86ISA::GpuTLB::translate(), gem5::X86ISA::TLB::translate(), gem5::loader::MemoryImage::write(), and gem5::loader::MemoryImage::writeSegment().

seg_not_present

Bitfield<5> gem5::X86ISA::seg_not_present

Definition at line 53 of file syscalls.hh.

SegmentFlagMask

Request::FlagsType gem5::X86ISA::SegmentFlagMask = mask(4)

constexpr

Definition at line 54 of file ldstflags.hh.

Referenced by gem5::X86ISA::GpuTLB::tlbLookup(), gem5::X86ISA::GpuTLB::translate(), and gem5::X86ISA::TLB::translate().

selector

Bitfield< 31, 16 > gem5::X86ISA::selector

Definition at line 1038 of file misc.hh.

Referenced by gem5::VegaISA::Inst_VOP3__V_PERM_B32::execute().

sf

Bitfield< 7 > gem5::X86ISA::sf

Definition at line 560 of file misc.hh.

SH

SignedBitfield<15,8> gem5::X86ISA::SH

Definition at line 61 of file int.hh.

Referenced by gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), gem5::SparcISA::SparcFault< T >::vals(), and gem5::SparcISA::SparcFault< T >::vals().

si

Bitfield<15, 3> gem5::X86ISA::si

Definition at line 895 of file misc.hh.

Referenced by gem5::X86ISA::Decoder::decode(), and gem5::X86ISA::Decoder::decode().

SL

SignedBitfield<7, 0> gem5::X86ISA::SL

Definition at line 63 of file int.hh.

smiCycle

Bitfield<2> gem5::X86ISA::smiCycle

Definition at line 882 of file misc.hh.

SR

SignedBitfield<63,0> gem5::X86ISA::SR

Definition at line 55 of file int.hh.

SS

const uint8_t gem5::X86ISA::SS = SSOverride

Definition at line 51 of file decoder_tables.cc.

sse

Bitfield<1> gem5::X86ISA::sse

Definition at line 664 of file misc.hh.

stack

Bitfield<17, 16> gem5::X86ISA::stack

Definition at line 602 of file misc.hh.

Referenced by gem5::ArmLinux32::archClone(), gem5::ArmLinux64::archClone(), gem5::PowerLinux::archClone(), gem5::RiscvLinux32::archClone(), gem5::RiscvLinux64::archClone(), gem5::SparcLinux::archClone(), gem5::X86Linux::archClone(), gem5::FunctionProfile::consume(), and gem5::setupAltStack().

submode

Bitfield< 2, 0 > gem5::X86ISA::submode

Definition at line 594 of file misc.hh.

svme

Bitfield<12> gem5::X86ISA::svme

Definition at line 820 of file misc.hh.

SX

SignedBitfield<15,0> gem5::X86ISA::SX

Definition at line 59 of file int.hh.

syscallCodeVirtAddr

const Addr gem5::X86ISA::syscallCodeVirtAddr = 0xffff800000000000

Definition at line 40 of file se_workload.hh.

Referenced by gem5::X86ISA::EmuLinux::event(), and gem5::X86ISA::X86_64Process::initState().

syscallCsAndSs

Bitfield<47,32> gem5::X86ISA::syscallCsAndSs

Definition at line 826 of file misc.hh.

sysretCsAndSs

Bitfield<63,48> gem5::X86ISA::sysretCsAndSs

Definition at line 827 of file misc.hh.

system

Bitfield<15> gem5::X86ISA::system

Definition at line 1032 of file misc.hh.

Referenced by gem5::ArmProcess64::armHwcapImpl(), gem5::ArmProcess64::armHwcapImpl2(), sc_gem5::TlmToGem5Bridge< BITWIDTH >::before_end_of_elaboration(), gem5::MuxingKvmGic< Types >::drainResume(), gem5::linux::dumpDmesg(), gem5::exitImpl(), gem5::MuxingKvmGic< Types >::fromKvmToGic(), gem5::ArmLinuxProcess32::initState(), gem5::ArmProcess32::initState(), gem5::ArmProcess64::initState(), gem5::RiscvProcess32::initState(), gem5::RiscvProcess64::initState(), gem5::Sparc32Process::initState(), gem5::Sparc64Process::initState(), gem5::X86ISA::FsLinux::initState(), gem5::X86ISA::FsWorkload::initState(), gem5::X86ISA::X86_64Process::initState(), gem5::Iob::Iob(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::nb_transport_bw(), gem5::AMDGPUDevice::readFrame(), gem5::RealViewTemperatureSensor::RealViewTemperatureSensor(), sc_gem5::Gem5ToTlmBridge< BITWIDTH >::recvTimingReq(), gem5::ArmISA::resetCPSR(), gem5::X86ISA::EmuLinux::setSystem(), gem5::X86ISA::FsWorkload::setSystem(), gem5::BaseArmKvmCPU::startup(), gem5::MuxingKvmGic< Types >::startup(), gem5::AtomicSimpleCPU::verifyMemoryMode(), gem5::NonCachingSimpleCPU::verifyMemoryMode(), gem5::TimingSimpleCPU::verifyMemoryMode(), gem5::AMDGPUDevice::writeFrame(), gem5::X86ISA::FsWorkload::writeOutACPITables(), gem5::X86ISA::FsWorkload::writeOutMPTable(), and gem5::X86ISA::FsWorkload::writeOutSMBiosTable().

targetCS

gem5::X86ISA::targetCS

Definition at line 723 of file misc.hh.

targetEIP

gem5::X86ISA::targetEIP

Definition at line 731 of file misc.hh.

targetEip

gem5::X86ISA::targetEip

Definition at line 825 of file misc.hh.

targetESP

gem5::X86ISA::targetESP

Definition at line 727 of file misc.hh.

tf

Bitfield<8> gem5::X86ISA::tf

Definition at line 584 of file misc.hh.

ti

Bitfield<2> gem5::X86ISA::ti

Definition at line 896 of file misc.hh.

tom2

Bitfield<21> gem5::X86ISA::tom2

Definition at line 851 of file misc.hh.

top5

gem5::X86ISA::top5

Definition at line 181 of file types.hh.

tpr

gem5::X86ISA::tpr

Definition at line 659 of file misc.hh.

trigger

Bitfield< 15 > gem5::X86ISA::trigger

Definition at line 52 of file intmessage.hh.

Referenced by gem5::prefetch::PIF::CompactorEntry::distanceFromTrigger(), gem5::prefetch::PIF::CompactorEntry::getPredictedAddresses(), gem5::prefetch::PIF::CompactorEntry::hasAddress(), gem5::prefetch::PIF::CompactorEntry::inSameSpatialRegion(), gem5::X86ISA::intelmp::IntAssignment::IntAssignment(), and gem5::X86ISA::Interrupts::raiseInterruptPin().

TriggerIntOffset

const Addr gem5::X86ISA::TriggerIntOffset = 0

static

Definition at line 81 of file intmessage.hh.

Referenced by buildIntTriggerPacket().

ts

Bitfield<3> gem5::X86ISA::ts

Definition at line 616 of file misc.hh.

tsd

Bitfield<2> gem5::X86ISA::tsd

Definition at line 653 of file misc.hh.

TSSPhysAddr

const Addr gem5::X86ISA::TSSPhysAddr = 0x63000

Definition at line 44 of file se_workload.hh.

TSSVirtAddr

const Addr gem5::X86ISA::TSSVirtAddr = 0xffff800000003000

Definition at line 43 of file se_workload.hh.

Referenced by gem5::X86ISA::X86_64Process::initState().

type

Bitfield< 43, 40 > gem5::X86ISA::type

Definition at line 762 of file misc.hh.

Referenced by gem5::ruby::RubyPrefetcher::accessNonunitFilter(), gem5::ruby::RubyPrefetcher::accessUnitFilter(), gem5::SpatterGen::addKernel(), gem5::statistics::Hdf5::addMetaData(), gem5::statistics::Hdf5::addMetaData(), gem5::ruby::CacheRecorder::addRecord(), gem5::ruby::AddressProfiler::addTraceSample(), gem5::ArmProcess::argsInit(), gem5::PowerProcess::argsInit(), gem5::ArmISA::BigFpMemRegOp::BigFpMemRegOp(), gem5::ruby::broadcast(), gem5::ruby::garnet::GarnetNetwork::collateStats(), gem5::KvmVM::createDevice(), gem5::createImgWriter(), gem5::ruby::createMachineID(), gem5::ArmV8KvmCPU::dump(), gem5::ArmISA::ArmStaticInst::extendReg64(), gem5::qemu::FwCfgItemE820::FwCfgItemE820(), gem5::Iob::generateIpi(), gem5::ArmISA::PMU::getCounterTypeRegister(), gem5::ruby::Switch::getMsgCount(), gem5::ruby::Throttle::getMsgCount(), gem5::Iris::ThreadContext::getReg(), gem5::o3::PhysRegFile::getReg(), gem5::o3::PhysRegFile::getReg(), gem5::o3::UnifiedFreeList::getReg(), gem5::ArmV8KvmCPU::getSysRegMap(), gem5::Iris::ThreadContext::getWritableReg(), gem5::o3::PhysRegFile::getWritableReg(), gem5::o3::UnifiedFreeList::hasFreeRegs(), gem5::ruby::GPUCoalescer::hitCallback(), gem5::ruby::Sequencer::hitCallback(), gem5::ruby::AbstractController::incomingTransactionStart(), gem5::branch_prediction::BranchTargetBuffer::incorrectTarget(), gem5::ruby::RubyPrefetcher::initializeStream(), gem5::ruby::UncoalescedTable::insertReqType(), gem5::o3::CPU::insertThread(), gem5::Episode::Action::isAtomicAction(), gem5::ruby::isDataReadRequest(), gem5::ruby::isHtmCmdRequest(), gem5::branch_prediction::SimpleIndirectPredictor::isIndirectNoReturn(), gem5::Episode::Action::isMemFenceAction(), gem5::ruby::isReadRequest(), gem5::ruby::isTlbiCmdRequest(), gem5::igbreg::txd_op::isType(), gem5::ruby::isWriteRequest(), gem5::branch_prediction::SimpleBTB::lookup(), gem5::ruby::MachineTypeAndNodeIDToMachineID(), gem5::ruby::mapAddressToRange(), gem5::RiscvISA::mulh(), gem5::RiscvISA::mulhsu(), gem5::RiscvISA::mulhu(), gem5::o3::DynInst::numDestRegs(), gem5::StaticInst::numDestRegs(), gem5::o3::UnifiedRenameMap::numFreeEntries(), gem5::o3::UnifiedFreeList::numFreeRegs(), gem5::ruby::RubyPrefetcher::observeMiss(), opcodeTypeToStr(), gem5::ruby::AbstractController::outgoingTransactionStart(), gem5::PerfKvmCounterConfig::PerfKvmCounterConfig(), gem5::ruby::PersistentTable::persistentRequestLock(), gem5::X86ISA::ACPI::MADT::Record::prepareBuf(), gem5::ArmISA::ArmStaticInst::printDataInst(), gem5::ArmISA::ArmStaticInst::printExtendOperand(), gem5::ArmISA::ArmStaticInst::printShiftOperand(), gem5::Episode::Action::printType(), gem5::ruby::AddressProfiler::profileRetry(), gem5::SDMAEngine::SDMAQueue::queueType(), gem5::ruby::Sequencer::recordMissLatency(), gem5::ruby::SimpleNetwork::regStats(), gem5::ruby::Switch::regStats(), gem5::NSGigE::rxFilter(), gem5::PipeFDEntry::setEndType(), gem5::KvmKernelGic::setIntState(), gem5::Iris::ThreadContext::setReg(), gem5::o3::PhysRegFile::setReg(), gem5::o3::PhysRegFile::setReg(), gem5::setRegNoEffectWithMask(), gem5::setRegWithMask(), gem5::ruby::CoalescedRequest::setRubyType(), gem5::ruby::garnet::NetworkLink::setType(), gem5::ArmISA::ArmStaticInst::shift_carry_imm(), gem5::ArmISA::ArmStaticInst::shift_carry_rs(), gem5::ArmISA::ArmStaticInst::shift_rm_imm(), gem5::ArmISA::ArmStaticInst::shift_rm_rs(), gem5::ArmISA::ArmStaticInst::shiftReg64(), gem5::ListenSocket::socketCloexec(), gem5::socketFunc(), gem5::socketpairFunc(), gem5::ruby::Throttle::ThrottleStats::ThrottleStats(), gem5::branch_prediction::toString(), gem5::ArmISA::MMU::tranTypeEL(), gem5::ruby::CacheMemory::tryCacheAccess(), gem5::o3::ElasticTrace::TraceInfo::typeToStr(), gem5::TraceCPU::ElasticDataGen::GraphNode::typeToStr(), gem5::loader::SymbolTable::unserialize(), gem5::branch_prediction::SimpleBTB::update(), gem5::ruby::AccessTraceForAddress::update(), gem5::Memoizer< Ret, Args >::validateMemoizer(), gem5::Iob::writeIob(), gem5::X86ISA::intelmp::BaseConfigEntry::writeOut(), gem5::X86ISA::intelmp::ExtConfigEntry::writeOut(), and gem5::X86ISA::E820Table::writeTo().

u

Bitfield<2> gem5::X86ISA::u

Definition at line 149 of file pagetable.hh.

Referenced by gem5::X86ISA::LongModePTE::uncacheable().

uc

Bitfield<61> gem5::X86ISA::uc

Definition at line 802 of file misc.hh.

unitMask

Bitfield<15,8> gem5::X86ISA::unitMask

Definition at line 836 of file misc.hh.

unusable

Bitfield<2> gem5::X86ISA::unusable

Definition at line 1022 of file misc.hh.

useable

Bitfield<6> gem5::X86ISA::useable

Definition at line 54 of file syscalls.hh.

usr

Bitfield<16> gem5::X86ISA::usr

Definition at line 837 of file misc.hh.

Referenced by gem5::NoMaliGpu::_interrupt(), and gem5::NoMaliGpu::_reset().

v

Bitfield< 6, 3 > gem5::X86ISA::v

Definition at line 125 of file types.hh.

V2

const uint8_t gem5::X86ISA::V2 = Vex2Prefix

Definition at line 59 of file decoder_tables.cc.

V3

const uint8_t gem5::X86ISA::V3 = Vex3Prefix

Definition at line 60 of file decoder_tables.cc.

val

Bitfield<63> gem5::X86ISA::val

Definition at line 804 of file misc.hh.

Referenced by gem5::ruby::ExpectedMap< RespType, DataType >::addExpectedCount(), gem5::ruby::ExpectedMap< RespType, DataType >::addExpectedDataType(), gem5::ruby::ExpectedMap< RespType, DataType >::addExpectedRespType(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >::addExpectedType(), gem5::ArmISA::ISA::addressTranslation(), gem5::ArmISA::ISA::addressTranslation64(), gem5::alignToPowerOfTwo(), gem5::ArmISA::AbortFault< T >::annotate(), gem5::ArmISA::DataAbort::annotate(), gem5::ArmISA::Watchpoint::annotate(), gem5::bcdize(), gem5::bits(), gem5::bits(), gem5::bitsToFloat(), gem5::bitsToFloat(), gem5::bitsToFloat32(), gem5::bitsToFloat64(), gem5::ArmISA::bitsToFp(), gem5::ArmISA::bitsToFp(), gem5::bitfield_backend::BitUnionOperators< Base >::BitUnionOperators(), gem5::trace::NativeTrace::checkReg(), gem5::MhuDoorbell::clear(), gem5::composeBitVector(), gem5::branch_prediction::MultiperspectivePerceptron::computeOutput(), gem5::statistics::constant(), gem5::statistics::constantVector(), gem5::GicV2Registers::copyCpuRegister(), gem5::Gicv3Registers::copyCpuRegister(), gem5::GicV2Registers::copyDistRegister(), gem5::Gicv3Registers::copyDistRegister(), gem5::Gicv3Registers::copyRedistRegister(), gem5::GenericTimerMem::counterCtrlWrite(), gem5::VegaISA::countZeroBits(), gem5::VegaISA::countZeroBitsMsb(), gem5::ArmISA::ArmStaticInst::cpsrWriteByInstr(), gem5::ArmISA::ArmStaticInst::cSwap(), gem5::ArmISA::FpOp::dblHi(), gem5::ArmISA::FpOp::dblLow(), gem5::statistics::AvgStor::dec(), gem5::statistics::StatStor::dec(), gem5::GenericISA::DelaySlotPCState< InstWidth >::DelaySlotPCState(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::DelaySlotUPCState(), gem5::PerfKvmCounterConfig::disabled(), gem5::ArmV8KvmCPU::dump(), gem5::compression::encoder::Huffman::encode(), gem5::GenericTimer::CoreTimers::EventStream::eventTargetValue(), gem5::PerfKvmCounterConfig::exclude_host(), gem5::PerfKvmCounterConfig::exclude_hv(), gem5::MipsISA::ISA::filterCP0Write(), gem5::VegaISA::findFirstOne(), gem5::VegaISA::findFirstOneMsb(), gem5::VegaISA::findFirstZero(), gem5::findLsbSet(), gem5::findMsbSet(), gem5::ruby::WriteMask::firstBitSet(), gem5::VegaISA::firstOppositeSignBit(), gem5::VegaISA::firstOppositeSignBit(), gem5::ArmISA::fixDest(), gem5::ArmISA::fixDest(), gem5::ArmISA::fixDivDest(), gem5::ArmISA::fixFpDFpSDest(), gem5::ArmISA::fixFpSFpDDest(), gem5::floatToBits(), gem5::floatToBits(), gem5::floatToBits32(), gem5::floatToBits64(), gem5::o3::DynInst::forwardOldRegs(), gem5::ArmISA::fpToBits(), gem5::ArmISA::fpToBits(), gem5::futexFunc(), gem5::Gicv3CPUInterface::generateSGI(), gem5::guest_abi::Argument< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::get(), gem5::guest_abi::Argument< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::get(), gem5::guest_abi::Argument< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::get(), gem5::RegFile::get(), gem5::o3::CPU::getArchReg(), gem5::branch_prediction::TAGEBase::getGHR(), gem5::CheckerThreadContext< TC >::getReg(), gem5::Iris::ThreadContext::getReg(), gem5::Iris::ThreadContext::getReg(), gem5::o3::CPU::getReg(), gem5::o3::PhysRegFile::getReg(), gem5::o3::PhysRegFile::getReg(), gem5::o3::ThreadContext::getReg(), gem5::SimpleThread::getReg(), gem5::SimpleThread::getReg(), gem5::ThreadContext::getReg(), gem5::CheckerCPU::getRegOperand(), gem5::minor::ExecContext::getRegOperand(), gem5::o3::DynInst::getRegOperand(), gem5::SimpleExecContext::getRegOperand(), gem5::getsockoptFunc(), gem5::Packet::getUintX(), gem5::HSAQueueEntry::globalWgId(), gem5::bloom_filter::H3::hash(), gem5::ArmISA::highFromDouble(), gem5::statistics::AvgStor::inc(), gem5::statistics::StatStor::inc(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >::increaseReceived(), gem5::ArmISA::PMU::PMUEvent::increment(), gem5::Trie< Key, Value >::insert(), gem5::insertBits(), gem5::insertBits(), gem5::InstResult::InstResult(), gem5::InstResult::InstResult(), gem5::AddressManager::AtomicStruct::isExpectedValue(), gem5::PowerISA::FloatOp::isNan(), gem5::PowerISA::FloatOp::isNan(), gem5::RiscvISA::isquietnan< double >(), gem5::RiscvISA::isquietnan< float >(), gem5::RiscvISA::issignalingnan< double >(), gem5::RiscvISA::issignalingnan< float >(), gem5::ArmISA::isSnan(), gem5::guest_abi::Aapcs32ArgumentBase::loadFromStack(), gem5::guest_abi::Aapcs64ArgumentBase::loadFromStack(), gem5::PciMemUpperBar::lower(), gem5::ArmISA::lowFromDouble(), gem5::LupioBLK::lupioBLKWrite(), gem5::LupioIPI::lupioIPIWrite(), gem5::LupioPIC::lupioPicWrite(), gem5::LupioTMR::lupioTMRWrite(), gem5::LupioTTY::lupioTTYWrite(), gem5::mappingParamIn(), gem5::RegisterFileCache::markRFC(), gem5::mbits(), gem5::X86ISA::X86StaticInst::merge(), gem5::ruby::mod(), gem5::mulSigned(), gem5::mulUnsigned(), gem5::GenericISA::DelaySlotPCState< InstWidth >::nnpc(), gem5::ArmISA::PMU::RegularEvent::RegularProbe::notify(), gem5::ProbeListenerArg< T, Arg >::notify(), gem5::ProbeListenerArgFunc< Arg >::notify(), gem5::GenericISA::PCStateWithNext::npc(), gem5::ArmISA::number_of_ones(), gem5::GenericISA::PCStateWithNext::nupc(), gem5::VegaISA::Inst_VOP3A::omodModifier(), gem5::bitfield_backend::BitUnionOperators< Base >::operator%=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator&=(), gem5::stl_helpers::hash_impl::hash< T, std::enable_if_t< !is_std_hash_enabled_v< T > &&is_iterable_v< T > > >::operator()(), gem5::bitfield_backend::BitUnionOperators< Base >::operator*=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator+=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator-=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator/=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator<<=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator=(), gem5::BitfieldType< Base >::operator=(), gem5::BitfieldTypeImpl< Base >::operator=(), gem5::BitfieldWOType< Base >::operator=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator>>=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator^=(), gem5::bitfield_backend::BitUnionOperators< Base >::operator|=(), gem5::GenericISA::PCStateWithNext::pc(), gem5::X86ISA::PCState::PCState(), gem5::CheckerCPU::pcState(), gem5::CheckerThreadContext< TC >::pcState(), gem5::Iris::ThreadContext::pcState(), gem5::minor::ExecContext::pcState(), gem5::o3::Commit::pcState(), gem5::o3::CPU::pcState(), gem5::o3::DynInst::pcState(), gem5::o3::ThreadContext::pcState(), gem5::SimpleExecContext::pcState(), gem5::SimpleThread::pcState(), gem5::CheckerThreadContext< TC >::pcStateNoRecord(), gem5::Iris::ThreadContext::pcStateNoRecord(), gem5::o3::ThreadContext::pcStateNoRecord(), gem5::SimpleThread::pcStateNoRecord(), gem5::PerfKvmCounterConfig::pinned(), gem5::popCount(), prepareCheckDistStor(), prepareCheckHistStor(), gem5::printUintX(), gem5::CircularQueue< T >::push_back(), gem5::VegaISA::quadMask(), gem5::DistIface::rankParam(), gem5::Gicv3Distributor::read(), gem5::LupioTTY::read(), gem5::VncServer::read(), gem5::X86ISA::Interrupts::read(), gem5::VegaISA::GPUISA::readConstVal(), gem5::fastmodel::CortexA76TC::readIntRegFlat(), gem5::ArmISA::ISA::readMiscReg(), gem5::ArmISA::PMU::readMiscReg(), gem5::RiscvISA::ISA::readMiscReg(), gem5::ArmISA::ISA::readMiscRegNoEffect(), gem5::X86ISA::Interrupts::readReg(), gem5::X86ISA::Cmos::readRegister(), gem5::ruby::ExpectedMap< RespType, DataType >::receiveData(), gem5::ruby::ExpectedMap< RespType, DataType >::receivedDataType(), gem5::ruby::ExpectedMap< RespType, DataType >::receivedRespType(), gem5::ruby::ExpectedMap< RespType, DataType >::ExpectedState< Type >::receivedType(), gem5::ruby::ExpectedMap< RespType, DataType >::receiveResp(), gem5::CheckerCPU::recordPCChange(), gem5::fastmodel::ResetControllerExample::Registers::Registers(), gem5::Trie< Key, Value >::remove(), gem5::replaceBits(), gem5::replaceBits(), gem5::Sp804::Timer::restartCounter(), gem5::CpuLocalTimer::Timer::restartTimerCounter(), gem5::CpuLocalTimer::Timer::restartWatchdogCounter(), gem5::reverseBits(), gem5::roundDown(), gem5::MipsISA::roundFP(), gem5::VegaISA::roundNearestEven(), gem5::ArmISA::roundNEven(), gem5::roundUp(), gem5::statistics::AvgSampleStor::sample(), gem5::statistics::DistStor::sample(), gem5::statistics::HistStor::sample(), gem5::statistics::SampleStor::sample(), gem5::statistics::SparseHistStor::sample(), gem5::Shader::ScheduleAdd(), gem5::GenericISA::DelaySlotPCState< InstWidth >::set(), gem5::GenericISA::DelaySlotUPCState< InstWidth >::set(), gem5::GenericISA::PCStateWithNext::set(), gem5::GenericISA::SimplePCState< InstWidth >::set(), gem5::GenericISA::UPCState< InstWidth >::set(), gem5::InstResult::set(), gem5::InstResult::set(), gem5::MhuDoorbell::set(), gem5::PCStateBase::set(), gem5::RegFile::set(), gem5::statistics::AvgStor::set(), gem5::statistics::StatStor::set(), gem5::X86ISA::PCState::set(), gem5::fastmodel::CortexA76::set_evs_param(), gem5::fastmodel::CortexA76Cluster::set_evs_param(), gem5::fastmodel::CortexR52::set_evs_param(), gem5::fastmodel::CortexR52Cluster::set_evs_param(), gem5::ArmISA::ArmStaticInst::setAIWNextPC(), gem5::o3::CPU::setArchReg(), gem5::o3::CPU::setArchReg(), gem5::Gicv3CPUInterface::setBankedMiscReg(), gem5::ArmISA::SelfDebug::setbSDD(), gem5::MipsISA::setCauseIP(), gem5::Iris::ThreadContext::setCCReg(), gem5::fastmodel::CortexA76TC::setCCRegFlat(), gem5::fastmodel::CortexR52TC::setCCRegFlat(), gem5::Iris::ThreadContext::setCCRegFlat(), gem5::ArchTimer::setCompareValue(), gem5::ArchTimer::setControl(), gem5::ArmISA::PMU::setControlReg(), gem5::ArmISA::PMU::setCounterTypeRegister(), gem5::ArmISA::PMU::setCounterValue(), gem5::trace::InstRecord::setData(), gem5::trace::InstRecord::setData(), gem5::StaticInst::setDestRegIdx(), gem5::ruby::ExpectedMap< RespType, DataType >::setExpectedCount(), gem5::trace::InstRecord::setFaulting(), gem5::SparcISA::ISA::setFSReg(), gem5::Request::setHtmAbortCause(), gem5::Shader::setHwReg(), gem5::RiscvISA::Interrupts::setIE(), gem5::ruby::AbstractCacheEntry::setInHtmReadSet(), gem5::ruby::AbstractCacheEntry::setInHtmWriteSet(), gem5::Request::setInstCount(), gem5::fastmodel::CortexR52TC::setIntReg(), gem5::Iris::ThreadContext::setIntReg(), gem5::fastmodel::CortexA76TC::setIntRegFlat(), gem5::Iris::ThreadContext::setIntRegFlat(), gem5::RiscvISA::Interrupts::setIP(), gem5::ArmISA::ArmStaticInst::setIWNextPC(), gem5::ruby::WriteMask::setMask(), gem5::ArmISA::SelfDebug::setMDBGen(), gem5::ArmISA::SelfDebug::setMDSCRvals(), gem5::CheckerCPU::setMemAccPredicate(), gem5::minor::ExecContext::setMemAccPredicate(), gem5::minor::MinorDynInst::setMemAccPredicate(), gem5::o3::DynInst::setMemAccPredicate(), gem5::SimpleExecContext::setMemAccPredicate(), gem5::SimpleThread::setMemAccPredicate(), gem5::ArmISA::DummyISADevice::setMiscReg(), gem5::ArmISA::ISA::setMiscReg(), gem5::ArmISA::PMU::setMiscReg(), gem5::CheckerCPU::setMiscReg(), gem5::CheckerThreadContext< TC >::setMiscReg(), gem5::GenericTimer::setMiscReg(), gem5::GenericTimerISA::setMiscReg(), gem5::Gicv3CPUInterface::setMiscReg(), gem5::Iris::ThreadContext::setMiscReg(), gem5::minor::ExecContext::setMiscReg(), gem5::MipsISA::ISA::setMiscReg(), gem5::MipsISA::ISA::setMiscReg(), gem5::o3::CPU::setMiscReg(), gem5::o3::DynInst::setMiscReg(), gem5::o3::ThreadContext::setMiscReg(), gem5::RiscvISA::ISA::setMiscReg(), gem5::SimpleExecContext::setMiscReg(), gem5::SimpleThread::setMiscReg(), gem5::SparcISA::ISA::setMiscReg(), gem5::X86ISA::ISA::setMiscReg(), gem5::ArmISA::ISA::setMiscRegNoEffect(), gem5::CheckerCPU::setMiscRegNoEffect(), gem5::CheckerThreadContext< TC >::setMiscRegNoEffect(), gem5::fastmodel::CortexR52TC::setMiscRegNoEffect(), gem5::Iris::ThreadContext::setMiscRegNoEffect(), gem5::MipsISA::ISA::setMiscRegNoEffect(), gem5::MipsISA::ISA::setMiscRegNoEffect(), gem5::o3::CPU::setMiscRegNoEffect(), gem5::o3::ThreadContext::setMiscRegNoEffect(), gem5::RiscvISA::ISA::setMiscRegNoEffect(), gem5::SimpleThread::setMiscRegNoEffect(), gem5::SparcISA::ISA::setMiscRegNoEffect(), gem5::X86ISA::ISA::setMiscRegNoEffect(), gem5::CheckerCPU::setMiscRegOperand(), gem5::minor::ExecContext::setMiscRegOperand(), gem5::o3::DynInst::setMiscRegOperand(), gem5::SimpleExecContext::setMiscRegOperand(), gem5::ArmISA::ISA::setMiscRegReset(), gem5::ArmISA::ArmStaticInst::setNextPC(), gem5::GenericISA::PCStateWithNext::setNPC(), gem5::X86ISA::PCState::setNPC(), gem5::ArchTimer::setOffset(), gem5::CheckerCPU::setPredicate(), gem5::minor::ExecContext::setPredicate(), gem5::minor::MinorDynInst::setPredicate(), gem5::o3::DynInst::setPredicate(), gem5::SimpleExecContext::setPredicate(), gem5::SimpleThread::setPredicate(), gem5::trace::InstRecord::setPredicate(), gem5::VecPredRegT< VecElem, NumElems, Packed, Const >::setRaw(), gem5::CheckerThreadContext< TC >::setReg(), gem5::CheckerThreadContext< TC >::setReg(), gem5::Iris::ThreadContext::setReg(), gem5::Iris::ThreadContext::setReg(), gem5::o3::CPU::setReg(), gem5::o3::CPU::setReg(), gem5::o3::PhysRegFile::setReg(), gem5::o3::PhysRegFile::setReg(), gem5::o3::ThreadContext::setReg(), gem5::o3::ThreadContext::setReg(), gem5::SimpleThread::setReg(), gem5::SimpleThread::setReg(), gem5::ThreadContext::setReg(), gem5::X86ISA::Interrupts::setReg(), gem5::MipsISA::ISA::setRegMask(), gem5::X86ISA::Interrupts::setRegNoEffect(), gem5::setRegNoEffectWithMask(), gem5::CheckerCPU::setRegOperand(), gem5::CheckerCPU::setRegOperand(), gem5::minor::ExecContext::setRegOperand(), gem5::minor::ExecContext::setRegOperand(), gem5::o3::DynInst::setRegOperand(), gem5::o3::DynInst::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::SimpleExecContext::setRegOperand(), gem5::MipsISA::setRegOtherThread(), gem5::MipsISA::setRegOtherThread(), gem5::setRegWithMask(), setRFlags(), gem5::StaticInst::setSrcRegIdx(), gem5::bitfield_backend::Signed< Storage, first, last >::setter(), gem5::bitfield_backend::Unsigned< Storage, first, last >::setter(), gem5::ArchTimer::setTimerValue(), gem5::setUintX(), gem5::ArmISA::PMU::CounterState::setValue(), gem5::sext(), gem5::sext(), gem5::GenericISA::SimplePCState< InstWidth >::SimplePCState(), gem5::DistIface::sizeParam(), gem5::ArmISA::ArmStaticInst::spsrWriteByInstr(), gem5::guest_abi::Result< Aapcs32, Composite, typename std::enable_if_t< IsAapcs32CompositeV< Composite > > >::store(), gem5::guest_abi::Result< Aapcs32, Integer, typename std::enable_if_t< std::is_integral_v< Integer > &&(sizeof(Integer)< sizeof(uint32_t))> >::store(), gem5::guest_abi::Result< Aapcs32Vfp, HA, typename std::enable_if_t< IsAapcs32HomogeneousAggregateV< HA > > >::store(), gem5::guest_abi::Result< Aapcs64, Composite, typename std::enable_if_t< IsAapcs64CompositeV< Composite > &&!IsAapcs64HxaV< Composite > > >::store(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< ArmISA::EmuFreebsd::BaseSyscallABI, ABI > > >::store(), gem5::guest_abi::Result< ABI, SyscallReturn, typename std::enable_if_t< std::is_base_of_v< SparcISA::SEWorkload::BaseSyscallABI, ABI > > >::store(), gem5::statistics::sum(), gem5::szext(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), TEST(), gem5::MipsISA::truncFP(), gem5::PortProxy::tryMemsetBlob(), gem5::unbcdize(), gem5::GenericISA::PCStateWithNext::upc(), gem5::GenericISA::UPCState< InstWidth >::UPCState(), gem5::statistics::ScalarPrint::update(), gem5::ArmISA::BrkPoint::updateControl(), gem5::ArmISA::WatchPoint::updateControl(), gem5::ArmISA::SelfDebug::updateDBGBCR(), gem5::ArmISA::SelfDebug::updateDBGWCR(), gem5::GPUDispatcher::updateInvCounter(), gem5::ArmISA::SelfDebug::updateOSLock(), gem5::HSAQueueEntry::updateOutstandingInvs(), gem5::HSAQueueEntry::updateOutstandingWbs(), gem5::GPUDispatcher::updateWbCounter(), gem5::PciMemBar::upper(), gem5::RegClass::valString(), gem5::RegClass::valString(), gem5::RegClassOps::valString(), gem5::TypedRegClassOps< ValueType >::valString(), gem5::statistics::ValueToString(), gem5::ArmISA::vfpFpToFixed(), gem5::ArmISA::vfpSFixedToFpD(), gem5::ArmISA::vfpSFixedToFpS(), gem5::ArmISA::vfpUFixedToFpD(), gem5::ArmISA::vfpUFixedToFpS(), gem5::HSAQueueEntry::wgId(), gem5::VegaISA::wholeQuadMode(), gem5::PciMemBar::wide(), gem5::ArmISA::PMU::SWIncrementEvent::write(), gem5::BaseSemihosting::InPlaceArg::write(), gem5::CopyEngine::write(), gem5::Gicv3Its::write(), gem5::IGbE::write(), gem5::PciIoBar::write(), gem5::PciMemBar::write(), gem5::PciMemUpperBar::write(), gem5::VncServer::write(), gem5::X86ISA::I8259::write(), gem5::X86ISA::Interrupts::write(), gem5::X86ISA::Speaker::write(), gem5::X86ISA::I8254::writeControl(), gem5::GPUExecContext::writeMiscReg(), gem5::AMDGPUVM::writeMMIO(), gem5::writeOutField(), gem5::ArmISA::misc_regs::writeRegister(), gem5::X86ISA::Cmos::writeRegister(), gem5::writeVal(), and gem5::o3::DynInst::~DynInst().

vcnt

gem5::X86ISA::vcnt

Definition at line 714 of file misc.hh.

vector

gem5::X86ISA::vector

Definition at line 48 of file intmessage.hh.

Referenced by gem5::Iob::generateIpi(), gem5::Iob::receiveDeviceInterrupt(), gem5::X86ISA::Interrupts::requestInterrupt(), gem5::Iob::serialize(), gem5::Iob::unserialize(), and gem5::Iob::writeIob().

vif

Bitfield<19> gem5::X86ISA::vif

Definition at line 575 of file misc.hh.

vip

Bitfield<20> gem5::X86ISA::vip

Definition at line 574 of file misc.hh.

vm

Bitfield<17> gem5::X86ISA::vm

Definition at line 577 of file misc.hh.

vme

Bitfield<0> gem5::X86ISA::vme

Definition at line 655 of file misc.hh.

w

Bitfield< 3 > gem5::X86ISA::w

Definition at line 150 of file pagetable.hh.

wc

Bitfield<10> gem5::X86ISA::wc

Definition at line 716 of file misc.hh.

wp

Bitfield<16> gem5::X86ISA::wp

Definition at line 613 of file misc.hh.

writable

Bitfield<12> gem5::X86ISA::writable

Definition at line 1029 of file misc.hh.

X

Bitfield<15,0> gem5::X86ISA::X

Definition at line 58 of file int.hh.

Referenced by gem5::ArmISA::addPACDA(), gem5::ArmISA::addPACDB(), gem5::ArmISA::addPACIA(), gem5::ArmISA::addPACIB(), gem5::ArmISA::authDA(), gem5::ArmISA::authDB(), gem5::ArmISA::authIA(), gem5::ArmISA::authIB(), gem5::branch_prediction::TAGEBase::handleAllocAndUReset(), and gem5::MatStore< X, Y >::xSize().

x

Bitfield< 6 > gem5::X86ISA::x

Definition at line 108 of file types.hh.

Referenced by gem5::X86ISA::TLB::TLB().

zf

Bitfield< 6 > gem5::X86ISA::zf

Definition at line 561 of file misc.hh.

zmm_hi256

Bitfield<6> gem5::X86ISA::zmm_hi256

Definition at line 673 of file misc.hh.