gem5 v24.0.0.0
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pcstate.hh File Reference
#include "arch/generic/pcstate.hh"
#include "arch/riscv/regs/vector.hh"
#include "enums/PrivilegeModeSet.hh"
#include "enums/RiscvType.hh"

Go to the source code of this file.

Classes

class  gem5::RiscvISA::PCState
 

Namespaces

namespace  gem5
 Copyright (c) 2024 - Pranith Kumar Copyright (c) 2020 Inria All rights reserved.
 
namespace  gem5::RiscvISA
 

Typedefs

using gem5::RiscvISA::RiscvType = enums::RiscvType
 
using gem5::RiscvISA::PrivilegeModeSet = enums::PrivilegeModeSet
 

Variables

constexpr enums::RiscvType gem5::RiscvISA::RV32 = enums::RV32
 
constexpr enums::RiscvType gem5::RiscvISA::RV64 = enums::RV64
 

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