process.cc File Reference

#include "arch/x86/process.hh"
#include <string>
#include <vector>
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/segment.hh"
#include "arch/x86/system.hh"
#include "arch/x86/types.hh"
#include "base/loader/elf_object.hh"
#include "base/loader/object_file.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/multi_level_page_table.hh"
#include "mem/page_table.hh"
#include "params/Process.hh"
#include "sim/aux_vector.hh"
#include "sim/process_impl.hh"
#include "sim/syscall_desc.hh"
#include "sim/syscall_return.hh"
#include "sim/system.hh"

Go to the source code of this file.

Typedefs
typedef MultiLevelPageTable< LongModePTE< 47, 39 >, LongModePTE< 38, 30 >, LongModePTE< 29, 21 >, LongModePTE< 20, 12 > >	ArchPageTable

Variables
static const int	ArgumentReg []
static const int NumArgumentRegs	M5_VAR_USED
static const int	ArgumentReg32 []

Typedef Documentation

ArchPageTable

typedef MultiLevelPageTable<LongModePTE<47, 39>, LongModePTE<38, 30>, LongModePTE<29, 21>, LongModePTE<20, 12> > ArchPageTable

Definition at line 106 of file process.cc.

Variable Documentation

ArgumentReg

const int ArgumentReg[]

static

Initial value:

= {
    INTREG_RDI,
    INTREG_RSI,
    INTREG_RDX,
    
    INTREG_R10W,
    
    INTREG_R8W,
    INTREG_R9W
}

Definition at line 73 of file process.cc.

Referenced by X86ISA::X86_64Process::getSyscallArg(), and X86ISA::I386Process::getSyscallArg().

ArgumentReg32

const int ArgumentReg32[]

static

Initial value:

= {
    INTREG_EBX,
    INTREG_ECX,
    INTREG_EDX,
    INTREG_ESI,
    INTREG_EDI,
    INTREG_EBP
}

Definition at line 87 of file process.cc.

M5_VAR_USED

static const int NumArgumentRegs32 M5_VAR_USED

static

Initial value:

=
    sizeof(ArgumentReg) / sizeof(const int)

Definition at line 84 of file process.cc.

Referenced by System::addFuncEvent(), ArmISA::ISA::assert32(), ArmISA::ISA::assert64(), AoutObject::buildImage(), EcoffObject::buildImage(), ArmISA::TLB::checkPermissions64(), VncServer::checkProtocolVersion(), SyscallDesc::doSyscall(), BPredUnit::drainSanityCheck(), ElfObject::ElfObject(), DRAMSim2Wrapper::enqueue(), HsailISA::LdaInst< DestDataType, AddrOperandType >::execute(), HsailISA::CbrInstBase< SRegOperand >::execute(), Minor::LSQ::SplitDataRequest::finish(), RubySystem::functionalWrite(), RubyPort::PioSlavePort::getAddrRanges(), MipsISA::Interrupts::getInterrupt(), ArmISA::Reset::getVector(), SimpleCache::handleResponse(), Cache::handleSnoop(), GarnetNetwork::init(), GPUCoalescer::insertRequest(), FALRU::invalidate(), ArmISA::ArmFault::invoke(), ArmISA::AbortFault< DataAbort >::invoke(), ArmISA::ArmFault::invoke64(), Minor::LSQ::SplitDataRequest::makeFragmentRequests(), Minor::Fetch1::minorTraceResponseLine(), Linux::openSpecialFile(), RoutingUnit::outportComputeXY(), TraceCPU::ElasticDataGen::printReadyList(), SkipFuncEvent::process(), BrigObject::processDirectives(), ComputeUnit::DataPort::processMemReqEvent(), LSQ< Impl >::pushRequest(), PciVirtIO::read(), Sinic::Device::read(), Wavefront::ready(), CacheMemory::recordCacheContents(), StubSlavePort::recvAtomic(), CoherentXBar::recvAtomicBackdoor(), RubyPort::MemSlavePort::recvFunctional(), ComputeUnit::DataPort::recvReqRetry(), ComputeUnit::SQCPort::recvReqRetry(), ComputeUnit::DTLBPort::recvReqRetry(), ComputeUnit::ITLBPort::recvReqRetry(), Cache::recvTimingReq(), RubyPort::PioSlavePort::recvTimingReq(), BaseCache::CpuSidePort::recvTimingReq(), ComputeUnit::DTLBPort::recvTimingResp(), ComputeUnit::ITLBPort::recvTimingResp(), CoherentXBar::recvTimingSnoopResp(), Stats::Group::regStats(), EmulationPageTable::remap(), TraceCPU::ElasticDataGen::GraphNode::removeDepOnInst(), Cache::sendMSHRQueuePacket(), ComputeUnit::LDSPort::sendTimingReq(), Fiber::start(), ComputeUnit::startWavefront(), TimingSimpleCPU::switchOut(), System::System(), MemTest::tick(), DefaultCommit< Impl >::tick(), Minor::LSQ::LSQRequest::tryToSuppressFault(), BaseCache::updateCompressionData(), ArmISA::VldSingleOp::VldSingleOp(), ArmISA::VstSingleOp::VstSingleOp(), PciVirtIO::write(), CopyEngine::write(), GicV2::writeDistributor(), and TCPIface::~TCPIface().