gem5
v19.0.0.0
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#include <tlb.hh>
Classes | |
class | Translation |
Public Types | |
enum | Mode { Read, Write, Execute } |
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typedef SimObjectParams | Params |
Public Member Functions | |
virtual void | demapPage (Addr vaddr, uint64_t asn)=0 |
virtual Fault | translateAtomic (const RequestPtr &req, ThreadContext *tc, Mode mode)=0 |
virtual void | translateTiming (const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode)=0 |
virtual Fault | translateFunctional (const RequestPtr &req, ThreadContext *tc, Mode mode) |
virtual Fault | finalizePhysical (const RequestPtr &req, ThreadContext *tc, Mode mode) const =0 |
Do post-translation physical address finalization. More... | |
virtual void | flushAll ()=0 |
Remove all entries from the TLB. More... | |
virtual void | takeOverFrom (BaseTLB *otlb)=0 |
Take over from an old tlb context. More... | |
virtual Port * | getTableWalkerPort () |
Get the table walker port if present. More... | |
void | memInvalidate () |
Invalidate the contents of memory buffers. More... | |
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const Params * | params () const |
SimObject (const Params *_params) | |
virtual | ~SimObject () |
virtual const std::string | name () const |
virtual void | init () |
init() is called after all C++ SimObjects have been created and all ports are connected. More... | |
virtual void | loadState (CheckpointIn &cp) |
loadState() is called on each SimObject when restoring from a checkpoint. More... | |
virtual void | initState () |
initState() is called on each SimObject when not restoring from a checkpoint. More... | |
virtual void | regProbePoints () |
Register probe points for this object. More... | |
virtual void | regProbeListeners () |
Register probe listeners for this object. More... | |
ProbeManager * | getProbeManager () |
Get the probe manager for this object. More... | |
virtual Port & | getPort (const std::string &if_name, PortID idx=InvalidPortID) |
Get a port with a given name and index. More... | |
virtual void | startup () |
startup() is the final initialization call before simulation. More... | |
DrainState | drain () override |
Provide a default implementation of the drain interface for objects that don't need draining. More... | |
virtual void | memWriteback () |
Write back dirty buffers to memory using functional writes. More... | |
void | serialize (CheckpointOut &cp) const override |
Serialize an object. More... | |
void | unserialize (CheckpointIn &cp) override |
Unserialize an object. More... | |
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EventManager (EventManager &em) | |
EventManager (EventManager *em) | |
EventManager (EventQueue *eq) | |
EventQueue * | eventQueue () const |
void | schedule (Event &event, Tick when) |
void | deschedule (Event &event) |
void | reschedule (Event &event, Tick when, bool always=false) |
void | schedule (Event *event, Tick when) |
void | deschedule (Event *event) |
void | reschedule (Event *event, Tick when, bool always=false) |
void | wakeupEventQueue (Tick when=(Tick) -1) |
void | setCurTick (Tick newVal) |
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Serializable () | |
virtual | ~Serializable () |
void | serializeSection (CheckpointOut &cp, const char *name) const |
Serialize an object into a new section. More... | |
void | serializeSection (CheckpointOut &cp, const std::string &name) const |
void | unserializeSection (CheckpointIn &cp, const char *name) |
Unserialize an a child object. More... | |
void | unserializeSection (CheckpointIn &cp, const std::string &name) |
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DrainState | drainState () const |
Return the current drain state of an object. More... | |
virtual void | notifyFork () |
Notify a child process of a fork. More... | |
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Group ()=delete | |
Group (const Group &)=delete | |
Group & | operator= (const Group &)=delete |
Group (Group *parent, const char *name=nullptr) | |
Construct a new statistics group. More... | |
virtual | ~Group () |
virtual void | regStats () |
Callback to set stat parameters. More... | |
virtual void | resetStats () |
Callback to reset stats. More... | |
virtual void | preDumpStats () |
Callback before stats are dumped. More... | |
void | addStat (Stats::Info *info) |
Register a stat with this group. More... | |
const std::map< std::string, Group * > & | getStatGroups () const |
Get all child groups associated with this object. More... | |
const std::vector< Info * > & | getStats () const |
Get all stats associated with this object. More... | |
void | addStatGroup (const char *name, Group *block) |
Add a stat block as a child of this block. More... | |
Protected Member Functions | |
BaseTLB (const Params *p) | |
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Drainable () | |
virtual | ~Drainable () |
virtual void | drainResume () |
Resume execution after a successful drain. More... | |
void | signalDrainDone () const |
Signal that an object is drained. More... | |
Additional Inherited Members | |
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static void | serializeAll (CheckpointOut &cp) |
Serialize all SimObjects in the system. More... | |
static SimObject * | find (const char *name) |
Find the SimObject with the given name and return a pointer to it. More... | |
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static const std::string & | currentSection () |
Get the fully-qualified name of the active section. More... | |
static void | serializeAll (const std::string &cpt_dir) |
static void | unserializeGlobals (CheckpointIn &cp) |
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static int | ckptCount = 0 |
static int | ckptMaxCount = 0 |
static int | ckptPrevCount = -1 |
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const SimObjectParams * | _params |
Cached copy of the object parameters. More... | |
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EventQueue * | eventq |
A pointer to this object's event queue. More... | |
enum BaseTLB::Mode |
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pure virtual |
Implemented in ArmISA::TLB, SparcISA::TLB, PowerISA::TLB, AlphaISA::TLB, MipsISA::TLB, RiscvISA::TLB, X86ISA::TLB, and Iris::TLB.
Referenced by SimpleThread::demapDataPage(), FullO3CPU< O3CPUImpl >::demapDataPage(), Minor::ExecContext::demapDataPage(), CheckerCPU::demapDataPage(), SimpleThread::demapInstPage(), FullO3CPU< O3CPUImpl >::demapInstPage(), Minor::ExecContext::demapInstPage(), CheckerCPU::demapInstPage(), SimpleThread::demapPage(), FullO3CPU< O3CPUImpl >::demapPage(), Minor::ExecContext::demapPage(), CheckerCPU::demapPage(), X86ISA::PageFault::invoke(), and BaseTLB::Translation::squashed().
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pure virtual |
Do post-translation physical address finalization.
This method is used by some architectures that need post-translation massaging of physical addresses. For example, X86 uses this to remap physical addresses in the APIC range to a range of physical memory not normally available to real x86 implementations.
req | Request to updated in-place. |
tc | Thread context that created the request. |
mode | Request type (read/write/execute). |
Implemented in ArmISA::TLB, SparcISA::TLB, PowerISA::TLB, AlphaISA::TLB, X86ISA::TLB, MipsISA::TLB, and RiscvISA::TLB.
Referenced by BaseKvmCPU::doMMIOAccess(), and translateFunctional().
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pure virtual |
Remove all entries from the TLB.
Implemented in ArmISA::TLB, PowerISA::TLB, SparcISA::TLB, MipsISA::TLB, AlphaISA::TLB, RiscvISA::TLB, X86ISA::TLB, and Iris::TLB.
Referenced by X86ISA::copyMiscRegs(), BaseCPU::flushTLBs(), memInvalidate(), mmapFunc(), and translateFunctional().
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inlinevirtual |
Get the table walker port if present.
This is used for migrating port connections during a CPU takeOverFrom() call. For architectures that do not have a table walker, NULL is returned, hence the use of a pointer rather than a reference.
Reimplemented in ArmISA::TLB, and X86ISA::TLB.
Definition at line 139 of file tlb.hh.
Referenced by BaseCPU::takeOverFrom().
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inlinevirtual |
Invalidate the contents of memory buffers.
When the switching to hardware virtualized CPU models, we need to make sure that we don't have any cached state in the system that might become stale when we return. This method is used to flush all such state back to main memory.
This does not cause any dirty state to be written back to memory.
Reimplemented from SimObject.
Definition at line 141 of file tlb.hh.
References flushAll().
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pure virtual |
Take over from an old tlb context.
Implemented in ArmISA::TLB, SparcISA::TLB, PowerISA::TLB, MipsISA::TLB, RiscvISA::TLB, AlphaISA::TLB, X86ISA::TLB, and Iris::TLB.
Referenced by BaseCPU::takeOverFrom(), and translateFunctional().
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pure virtual |
Implemented in ArmISA::TLB, SparcISA::TLB, PowerISA::TLB, AlphaISA::TLB, X86ISA::TLB, MipsISA::TLB, and RiscvISA::TLB.
Referenced by AtomicSimpleCPU::amoMem(), BaseCPU::mwaitAtomic(), AtomicSimpleCPU::readMem(), BaseTLB::Translation::squashed(), AtomicSimpleCPU::tick(), and AtomicSimpleCPU::writeMem().
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inlinevirtual |
Reimplemented in ArmISA::TLB.
Definition at line 98 of file tlb.hh.
References finalizePhysical(), flushAll(), panic, and takeOverFrom().
Referenced by CheckerCPU::readMem(), try_translate(), and CheckerCPU::writeMem().
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pure virtual |
Implemented in ArmISA::TLB, SparcISA::TLB, PowerISA::TLB, AlphaISA::TLB, X86ISA::TLB, MipsISA::TLB, and RiscvISA::TLB.
Referenced by TimingSimpleCPU::fetch(), TimingSimpleCPU::initiateMemAMO(), TimingSimpleCPU::initiateMemRead(), Minor::LSQ::SplitDataRequest::sendNextFragmentToTranslation(), BaseTLB::Translation::squashed(), Minor::LSQ::SingleDataRequest::startAddrTranslation(), QueuedPrefetcher::DeferredPacket::startTranslation(), and TimingSimpleCPU::writeMem().